- *
- * Create a new co-routine and add it to the list of co-routines that are
- * ready to run.
- *
- * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine
- * functions require special syntax - see the co-routine section of the WEB
- * documentation for more information.
- *
- * @param uxPriority The priority with respect to other co-routines at which
- * the co-routine will run.
- *
- * @param uxIndex Used to distinguish between different co-routines that
- * execute the same function. See the example below and the co-routine section
- * of the WEB documentation for further information.
- *
- * @return pdPASS if the co-routine was successfully created and added to a ready
- * list, otherwise an error code defined with ProjDefs.h.
- *
- * Example usage:
-
- // Co-routine to be created.
- void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- // This may not be necessary for const variables.
- static const char cLedToFlash[ 2 ] = { 5, 6 };
- static const portTickType xTimeToDelay[ 2 ] = { 200, 400 };
-
- // Must start every co-routine with a call to crSTART();
- crSTART( xHandle );
-
- for( ;; )
- {
- // This co-routine just delays for a fixed period, then toggles
- // an LED. Two co-routines are created using this function, so
- // the uxIndex parameter is used to tell the co-routine which
- // LED to flash and how long to delay. This assumes xQueue has
- // already been created.
- vParTestToggleLED( cLedToFlash[ uxIndex ] );
- crDELAY( xHandle, uxFlashRates[ uxIndex ] );
- }
-
- // Must end every co-routine with a call to crEND();
- crEND();
- }
-
- // Function that creates two co-routines.
- void vOtherFunction( void )
- {
- unsigned char ucParameterToPass;
- xTaskHandle xHandle;
-
- // Create two co-routines at priority 0. The first is given index 0
- // so (from the code above) toggles LED 5 every 200 ticks. The second
- // is given index 1 so toggles LED 6 every 400 ticks.
- for( uxIndex = 0; uxIndex < 2; uxIndex++ )
- {
- xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
- }
- }
-
- *
- * Run a co-routine.
- *
- * vCoRoutineSchedule() executes the highest priority co-routine that is able
- * to run. The co-routine will execute until it either blocks, yields or is
- * preempted by a task. Co-routines execute cooperatively so one
- * co-routine cannot be preempted by another, but can be preempted by a task.
- *
- * If an application comprises of both tasks and co-routines then
- * vCoRoutineSchedule should be called from the idle task (in an idle task
- * hook).
- *
- * Example usage:
-
- // This idle task hook will schedule a co-routine each time it is called.
- // The rest of the idle task will execute between co-routine calls.
- void vApplicationIdleHook( void )
- {
- vCoRoutineSchedule();
- }
-
- // Alternatively, if you do not require any other part of the idle task to
- // execute, the idle task hook can call vCoRoutineScheduler() within an
- // infinite loop.
- void vApplicationIdleHook( void )
- {
- for( ;; )
- {
- vCoRoutineSchedule();
- }
- }
-
- *
- * This macro MUST always be called at the start of a co-routine function.
- *
- * Example usage:
-
- // Co-routine to be created.
- void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static portLONG ulAVariable;
-
- // Must start every co-routine with a call to crSTART();
- crSTART( xHandle );
-
- for( ;; )
- {
- // Co-routine functionality goes here.
- }
-
- // Must end every co-routine with a call to crEND();
- crEND();
- }
- *
- * This macro MUST always be called at the end of a co-routine function.
- *
- * Example usage:
-
- // Co-routine to be created.
- void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static portLONG ulAVariable;
-
- // Must start every co-routine with a call to crSTART();
- crSTART( xHandle );
-
- for( ;; )
- {
- // Co-routine functionality goes here.
- }
-
- // Must end every co-routine with a call to crEND();
- crEND();
- }
- * \defgroup crSTART crSTART
- * \ingroup Tasks
- */
-#define crEND() }
-
-/*
- * These macros are intended for internal use by the co-routine implementation
- * only. The macros should not be used directly by application writers.
- */
-#define crSET_STATE0( xHandle ) ( ( corCRCB * )xHandle)->uxState = (__LINE__ * 2); return; case (__LINE__ * 2):
-#define crSET_STATE1( xHandle ) ( ( corCRCB * )xHandle)->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1):
-
-/**
- * croutine. h
- *
- *
- * Delay a co-routine for a fixed period of time.
- *
- * crDELAY can only be called from the co-routine function itself - not
- * from within a function called by the co-routine function. This is because
- * co-routines do not maintain their own stack.
- *
- * @param xHandle The handle of the co-routine to delay. This is the xHandle
- * parameter of the co-routine function.
- *
- * @param xTickToDelay The number of ticks that the co-routine should delay
- * for. The actual amount of time this equates to is defined by
- * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_RATE_MS
- * can be used to convert ticks to milliseconds.
- *
- * Example usage:
-
- // Co-routine to be created.
- void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- // This may not be necessary for const variables.
- // We are to delay for 200ms.
- static const xTickType xDelayTime = 200 / portTICK_RATE_MS;
-
- // Must start every co-routine with a call to crSTART();
- crSTART( xHandle );
-
- for( ;; )
- {
- // Delay for 200ms.
- crDELAY( xHandle, xDelayTime );
-
- // Do something here.
- }
-
- // Must end every co-routine with a call to crEND();
- crEND();
- }
- *
- * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
- * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
- *
- * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
- * xQueueSend() and xQueueReceive() can only be used from tasks.
- *
- * crQUEUE_SEND can only be called from the co-routine function itself - not
- * from within a function called by the co-routine function. This is because
- * co-routines do not maintain their own stack.
- *
- * See the co-routine section of the WEB documentation for information on
- * passing data between tasks and co-routines and between ISR's and
- * co-routines.
- *
- * @param xHandle The handle of the calling co-routine. This is the xHandle
- * parameter of the co-routine function.
- *
- * @param pxQueue The handle of the queue on which the data will be posted.
- * The handle is obtained as the return value when the queue is created using
- * the xQueueCreate() API function.
- *
- * @param pvItemToQueue A pointer to the data being posted onto the queue.
- * The number of bytes of each queued item is specified when the queue is
- * created. This number of bytes is copied from pvItemToQueue into the queue
- * itself.
- *
- * @param xTickToDelay The number of ticks that the co-routine should block
- * to wait for space to become available on the queue, should space not be
- * available immediately. The actual amount of time this equates to is defined
- * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant
- * portTICK_RATE_MS can be used to convert ticks to milliseconds (see example
- * below).
- *
- * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
- * data was successfully posted onto the queue, otherwise it will be set to an
- * error defined within ProjDefs.h.
- *
- * Example usage:
-
- // Co-routine function that blocks for a fixed period then posts a number onto
- // a queue.
- static void prvCoRoutineFlashTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static portBASE_TYPE xNumberToPost = 0;
- static portBASE_TYPE xResult;
-
- // Co-routines must begin with a call to crSTART().
- crSTART( xHandle );
-
- for( ;; )
- {
- // This assumes the queue has already been created.
- crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
-
- if( xResult != pdPASS )
- {
- // The message was not posted!
- }
-
- // Increment the number to be posted onto the queue.
- xNumberToPost++;
-
- // Delay for 100 ticks.
- crDELAY( xHandle, 100 );
- }
-
- // Co-routines must end with a call to crEND().
- crEND();
- }
- *
- * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
- * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
- *
- * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
- * xQueueSend() and xQueueReceive() can only be used from tasks.
- *
- * crQUEUE_RECEIVE can only be called from the co-routine function itself - not
- * from within a function called by the co-routine function. This is because
- * co-routines do not maintain their own stack.
- *
- * See the co-routine section of the WEB documentation for information on
- * passing data between tasks and co-routines and between ISR's and
- * co-routines.
- *
- * @param xHandle The handle of the calling co-routine. This is the xHandle
- * parameter of the co-routine function.
- *
- * @param pxQueue The handle of the queue from which the data will be received.
- * The handle is obtained as the return value when the queue is created using
- * the xQueueCreate() API function.
- *
- * @param pvBuffer The buffer into which the received item is to be copied.
- * The number of bytes of each queued item is specified when the queue is
- * created. This number of bytes is copied into pvBuffer.
- *
- * @param xTickToDelay The number of ticks that the co-routine should block
- * to wait for data to become available from the queue, should data not be
- * available immediately. The actual amount of time this equates to is defined
- * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant
- * portTICK_RATE_MS can be used to convert ticks to milliseconds (see the
- * crQUEUE_SEND example).
- *
- * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
- * data was successfully retrieved from the queue, otherwise it will be set to
- * an error code as defined within ProjDefs.h.
- *
- * Example usage:
-
- // A co-routine receives the number of an LED to flash from a queue. It
- // blocks on the queue until the number is received.
- static void prvCoRoutineFlashWorkTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static portBASE_TYPE xResult;
- static unsigned portBASE_TYPE uxLEDToFlash;
-
- // All co-routines must start with a call to crSTART().
- crSTART( xHandle );
-
- for( ;; )
- {
- // Wait for data to become available on the queue.
- crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
-
- if( xResult == pdPASS )
- {
- // We received the LED to flash - flash it!
- vParTestToggleLED( uxLEDToFlash );
- }
- }
-
- crEND();
- }
- *
- * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
- * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
- * functions used by tasks.
- *
- * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
- * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
- * xQueueReceiveFromISR() can only be used to pass data between a task and and
- * ISR.
- *
- * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue
- * that is being used from within a co-routine.
- *
- * See the co-routine section of the WEB documentation for information on
- * passing data between tasks and co-routines and between ISR's and
- * co-routines.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue. The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto
- * the same queue multiple times from a single interrupt. The first call
- * should always pass in pdFALSE. Subsequent calls should pass in
- * the value returned from the previous call.
- *
- * @return pdTRUE if a co-routine was woken by posting onto the queue. This is
- * used by the ISR to determine if a context switch may be required following
- * the ISR.
- *
- * Example usage:
-
- // A co-routine that blocks on a queue waiting for characters to be received.
- static void vReceivingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- portCHAR cRxedChar;
- portBASE_TYPE xResult;
-
- // All co-routines must start with a call to crSTART().
- crSTART( xHandle );
-
- for( ;; )
- {
- // Wait for data to become available on the queue. This assumes the
- // queue xCommsRxQueue has already been created!
- crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
-
- // Was a character received?
- if( xResult == pdPASS )
- {
- // Process the character here.
- }
- }
-
- // All co-routines must end with a call to crEND().
- crEND();
- }
-
- // An ISR that uses a queue to send characters received on a serial port to
- // a co-routine.
- void vUART_ISR( void )
- {
- portCHAR cRxedChar;
- portBASE_TYPE xCRWokenByPost = pdFALSE;
-
- // We loop around reading characters until there are none left in the UART.
- while( UART_RX_REG_NOT_EMPTY() )
- {
- // Obtain the character from the UART.
- cRxedChar = UART_RX_REG;
-
- // Post the character onto a queue. xCRWokenByPost will be pdFALSE
- // the first time around the loop. If the post causes a co-routine
- // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
- // In this manner we can ensure that if more than one co-routine is
- // blocked on the queue only one is woken by this ISR no matter how
- // many characters are posted to the queue.
- xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
- }
- }
- *
- * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
- * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
- * functions used by tasks.
- *
- * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
- * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
- * xQueueReceiveFromISR() can only be used to pass data between a task and and
- * ISR.
- *
- * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data
- * from a queue that is being used from within a co-routine (a co-routine
- * posted to the queue).
- *
- * See the co-routine section of the WEB documentation for information on
- * passing data between tasks and co-routines and between ISR's and
- * co-routines.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvBuffer A pointer to a buffer into which the received item will be
- * placed. The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from the queue into
- * pvBuffer.
- *
- * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become
- * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a
- * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise
- * *pxCoRoutineWoken will remain unchanged.
- *
- * @return pdTRUE an item was successfully received from the queue, otherwise
- * pdFALSE.
- *
- * Example usage:
-
- // A co-routine that posts a character to a queue then blocks for a fixed
- // period. The character is incremented each time.
- static void vSendingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // cChar holds its value while this co-routine is blocked and must therefore
- // be declared static.
- static portCHAR cCharToTx = 'a';
- portBASE_TYPE xResult;
-
- // All co-routines must start with a call to crSTART().
- crSTART( xHandle );
-
- for( ;; )
- {
- // Send the next character to the queue.
- crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
-
- if( xResult == pdPASS )
- {
- // The character was successfully posted to the queue.
- }
- else
- {
- // Could not post the character to the queue.
- }
-
- // Enable the UART Tx interrupt to cause an interrupt in this
- // hypothetical UART. The interrupt will obtain the character
- // from the queue and send it.
- ENABLE_RX_INTERRUPT();
-
- // Increment to the next character then block for a fixed period.
- // cCharToTx will maintain its value across the delay as it is
- // declared static.
- cCharToTx++;
- if( cCharToTx > 'x' )
- {
- cCharToTx = 'a';
- }
- crDELAY( 100 );
- }
-
- // All co-routines must end with a call to crEND().
- crEND();
- }
-
- // An ISR that uses a queue to receive characters to send on a UART.
- void vUART_ISR( void )
- {
- portCHAR cCharToTx;
- portBASE_TYPE xCRWokenByPost = pdFALSE;
-
- while( UART_TX_REG_EMPTY() )
- {
- // Are there any characters in the queue waiting to be sent?
- // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
- // is woken by the post - ensuring that only a single co-routine is
- // woken no matter how many times we go around this loop.
- if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
- {
- SEND_CHARACTER( cCharToTx );
- }
- }
- }
- * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR
- * \ingroup Tasks
- */
-#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( pxQueue, pvBuffer, pxCoRoutineWoken )
-
-/*
- * This function is intended for internal use by the co-routine macros only.
- * The macro nature of the co-routine implementation requires that the
- * prototype appears here. The function should not be used by application
- * writers.
- *
- * Removes the current co-routine from its ready list and places it in the
- * appropriate delayed list.
- */
-void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList *pxEventList );
-
-/*
- * This function is intended for internal use by the queue implementation only.
- * The function should not be used by application writers.
- *
- * Removes the highest priority co-routine from the event list and places it in
- * the pending ready list.
- */
-signed portBASE_TYPE xCoRoutineRemoveFromEventList( const xList *pxEventList );
-
-
-#endif /* CO_ROUTINE_H */
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/list.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/list.h
deleted file mode 100644
index f3702c14..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/list.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry.
-
- This file is part of the FreeRTOS.org distribution.
-
- FreeRTOS.org is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- FreeRTOS.org is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with FreeRTOS.org; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes FreeRTOS.org, without being obliged to provide
- the source code for any proprietary components. See the licensing section
- of http://www.FreeRTOS.org for full details of how and when the exception
- can be applied.
-
- ***************************************************************************
- See http://www.FreeRTOS.org for documentation, latest information, license
- and contact details. Please ensure to read the configuration and relevant
- port sections of the online documentation.
-
- Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
- with commercial development and support options.
- ***************************************************************************
-*/
-
-/*
- * This is the list implementation used by the scheduler. While it is tailored
- * heavily for the schedulers needs, it is also available for use by
- * application code.
- *
- * xLists can only store pointers to xListItems. Each xListItem contains a
- * numeric value (xItemValue). Most of the time the lists are sorted in
- * descending item value order.
- *
- * Lists are created already containing one list item. The value of this
- * item is the maximum possible that can be stored, it is therefore always at
- * the end of the list and acts as a marker. The list member pxHead always
- * points to this marker - even though it is at the tail of the list. This
- * is because the tail contains a wrap back pointer to the true head of
- * the list.
- *
- * In addition to it's value, each list item contains a pointer to the next
- * item in the list (pxNext), a pointer to the list it is in (pxContainer)
- * and a pointer to back to the object that contains it. These later two
- * pointers are included for efficiency of list manipulation. There is
- * effectively a two way link between the object containing the list item and
- * the list item itself.
- *
- *
- * \page ListIntroduction List Implementation
- * \ingroup FreeRTOSIntro
- */
-
-/*
- Changes from V4.3.1
-
- + Included local const within listGET_OWNER_OF_NEXT_ENTRY() to assist
- compiler with optimisation. Thanks B.R.
-*/
-
-#ifndef LIST_H
-#define LIST_H
-
-/*
- * Definition of the only type of object that a list can contain.
- */
-struct xLIST_ITEM
-{
- portTickType xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */
- volatile struct xLIST_ITEM * pxNext; /*< Pointer to the next xListItem in the list. */
- volatile struct xLIST_ITEM * pxPrevious;/*< Pointer to the previous xListItem in the list. */
- void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */
- void * pvContainer; /*< Pointer to the list in which this list item is placed (if any). */
-};
-typedef struct xLIST_ITEM xListItem; /* For some reason lint wants this as two separate definitions. */
-
-struct xMINI_LIST_ITEM
-{
- portTickType xItemValue;
- volatile struct xLIST_ITEM *pxNext;
- volatile struct xLIST_ITEM *pxPrevious;
-};
-typedef struct xMINI_LIST_ITEM xMiniListItem;
-
-/*
- * Definition of the type of queue used by the scheduler.
- */
-typedef struct xLIST
-{
- volatile unsigned portBASE_TYPE uxNumberOfItems;
- volatile xListItem * pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to pvListGetOwnerOfNextEntry (). */
- volatile xMiniListItem xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */
-} xList;
-
-/*
- * Access macro to set the owner of a list item. The owner of a list item
- * is the object (usually a TCB) that contains the list item.
- *
- * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
- * \ingroup LinkedList
- */
-#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( pxListItem )->pvOwner = ( void * ) pxOwner
-
-/*
- * Access macro to set the value of the list item. In most cases the value is
- * used to sort the list in descending order.
- *
- * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE
- * \ingroup LinkedList
- */
-#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( pxListItem )->xItemValue = xValue
-
-/*
- * Access macro the retrieve the value of the list item. The value can
- * represent anything - for example a the priority of a task, or the time at
- * which a task should be unblocked.
- *
- * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
- * \ingroup LinkedList
- */
-#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue )
-
-/*
- * Access macro to determine if a list contains any items. The macro will
- * only have the value true if the list is empty.
- *
- * \page listLIST_IS_EMPTY listLIST_IS_EMPTY
- * \ingroup LinkedList
- */
-#define listLIST_IS_EMPTY( pxList ) ( ( pxList )->uxNumberOfItems == ( unsigned portBASE_TYPE ) 0 )
-
-/*
- * Access macro to return the number of items in the list.
- */
-#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems )
-
-/*
- * Access function to obtain the owner of the next entry in a list.
- *
- * The list member pxIndex is used to walk through a list. Calling
- * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list
- * and returns that entries pxOwner parameter. Using multiple calls to this
- * function it is therefore possible to move through every item contained in
- * a list.
- *
- * The pxOwner parameter of a list item is a pointer to the object that owns
- * the list item. In the scheduler this is normally a task control block.
- * The pxOwner parameter effectively creates a two way link between the list
- * item and its owner.
- *
- * @param pxList The list from which the next item owner is to be returned.
- *
- * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY
- * \ingroup LinkedList
- */
-#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \
-{ \
-xList * const pxConstList = pxList; \
- /* Increment the index to the next item and return the item, ensuring */ \
- /* we don't return the marker used at the end of the list. */ \
- ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \
- if( ( pxConstList )->pxIndex == ( xListItem * ) &( ( pxConstList )->xListEnd ) ) \
- { \
- ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \
- } \
- pxTCB = ( pxConstList )->pxIndex->pvOwner; \
-}
-
-
-/*
- * Access function to obtain the owner of the first entry in a list. Lists
- * are normally sorted in ascending item value order.
- *
- * This function returns the pxOwner member of the first item in the list.
- * The pxOwner parameter of a list item is a pointer to the object that owns
- * the list item. In the scheduler this is normally a task control block.
- * The pxOwner parameter effectively creates a two way link between the list
- * item and its owner.
- *
- * @param pxList The list from which the owner of the head item is to be
- * returned.
- *
- * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY
- * \ingroup LinkedList
- */
-#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( ( pxList->uxNumberOfItems != ( unsigned portBASE_TYPE ) 0 ) ? ( (&( pxList->xListEnd ))->pxNext->pvOwner ) : ( NULL ) )
-
-/*
- * Check to see if a list item is within a list. The list item maintains a
- * "container" pointer that points to the list it is in. All this macro does
- * is check to see if the container and the list match.
- *
- * @param pxList The list we want to know if the list item is within.
- * @param pxListItem The list item we want to know if is in the list.
- * @return pdTRUE is the list item is in the list, otherwise pdFALSE.
- * pointer against
- */
-#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( pxListItem )->pvContainer == ( void * ) pxList )
-
-/*
- * Must be called before a list is used! This initialises all the members
- * of the list structure and inserts the xListEnd item into the list as a
- * marker to the back of the list.
- *
- * @param pxList Pointer to the list being initialised.
- *
- * \page vListInitialise vListInitialise
- * \ingroup LinkedList
- */
-void vListInitialise( xList *pxList );
-
-/*
- * Must be called before a list item is used. This sets the list container to
- * null so the item does not think that it is already contained in a list.
- *
- * @param pxItem Pointer to the list item being initialised.
- *
- * \page vListInitialiseItem vListInitialiseItem
- * \ingroup LinkedList
- */
-void vListInitialiseItem( xListItem *pxItem );
-
-/*
- * Insert a list item into a list. The item will be inserted into the list in
- * a position determined by its item value (descending item value order).
- *
- * @param pxList The list into which the item is to be inserted.
- *
- * @param pxNewListItem The item to that is to be placed in the list.
- *
- * \page vListInsert vListInsert
- * \ingroup LinkedList
- */
-void vListInsert( xList *pxList, xListItem *pxNewListItem );
-
-/*
- * Insert a list item into a list. The item will be inserted in a position
- * such that it will be the last item within the list returned by multiple
- * calls to listGET_OWNER_OF_NEXT_ENTRY.
- *
- * The list member pvIndex is used to walk through a list. Calling
- * listGET_OWNER_OF_NEXT_ENTRY increments pvIndex to the next item in the list.
- * Placing an item in a list using vListInsertEnd effectively places the item
- * in the list position pointed to by pvIndex. This means that every other
- * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before
- * the pvIndex parameter again points to the item being inserted.
- *
- * @param pxList The list into which the item is to be inserted.
- *
- * @param pxNewListItem The list item to be inserted into the list.
- *
- * \page vListInsertEnd vListInsertEnd
- * \ingroup LinkedList
- */
-void vListInsertEnd( xList *pxList, xListItem *pxNewListItem );
-
-/*
- * Remove an item from a list. The list item has a pointer to the list that
- * it is in, so only the list item need be passed into the function.
- *
- * @param vListRemove The item to be removed. The item will remove itself from
- * the list pointed to by it's pxContainer parameter.
- *
- * \page vListRemove vListRemove
- * \ingroup LinkedList
- */
-void vListRemove( xListItem *pxItemToRemove );
-
-
-
-#endif
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/portable.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/portable.h
deleted file mode 100644
index 80bac44a..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/portable.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry.
-
- This file is part of the FreeRTOS.org distribution.
-
- FreeRTOS.org is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- FreeRTOS.org is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with FreeRTOS.org; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes FreeRTOS.org, without being obliged to provide
- the source code for any proprietary components. See the licensing section
- of http:www.FreeRTOS.org for full details of how and when the exception
- can be applied.
-
- ***************************************************************************
- See http:www.FreeRTOS.org for documentation, latest information, license
- and contact details. Please ensure to read the configuration and relevant
- port sections of the online documentation.
-
- Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
- with commercial development and support options.
- ***************************************************************************
-*/
-
-/*-----------------------------------------------------------
- * Portable layer API. Each function must be defined for each port.
- *----------------------------------------------------------*/
-
-#ifndef PORTABLE_H
-#define PORTABLE_H
-
-/* Include the macro file relevant to the port being used. */
-
-#ifdef SAM7_GCC
- #include "FreeRTOS/portable/GCC/ARM7_AT91SAM7S/portmacro.h"
-#endif
-
-/*
- * Setup the stack of a new task so it is ready to be placed under the
- * scheduler control. The registers have to be placed on the stack in
- * the order that the port expects to find them.
- */
-portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters );
-
-/*
- * Map to the memory management routines required for the port.
- */
-void *pvPortMalloc( size_t xSize );
-void vPortFree( void *pv );
-void vPortInitialiseBlocks( void );
-
-/*
- * Setup the hardware ready for the scheduler to take control. This generally
- * sets up a tick interrupt and sets timers for the correct tick frequency.
- */
-portBASE_TYPE xPortStartScheduler( void );
-
-/*
- * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
- * the hardware is left in its original condition after the scheduler stops
- * executing.
- */
-void vPortEndScheduler( void );
-
-#endif /* PORTABLE_H */
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/projdefs.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/projdefs.h
deleted file mode 100644
index 37a66222..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/projdefs.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry.
-
- This file is part of the FreeRTOS.org distribution.
-
- FreeRTOS.org is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- FreeRTOS.org is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with FreeRTOS.org; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes FreeRTOS.org, without being obliged to provide
- the source code for any proprietary components. See the licensing section
- of http://www.FreeRTOS.org for full details of how and when the exception
- can be applied.
-
- ***************************************************************************
- See http://www.FreeRTOS.org for documentation, latest information, license
- and contact details. Please ensure to read the configuration and relevant
- port sections of the online documentation.
-
- Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
- with commercial development and support options.
- ***************************************************************************
-*/
-
-#ifndef PROJDEFS_H
-#define PROJDEFS_H
-
-/* Defines to prototype to which task functions must conform. */
-typedef void (*pdTASK_CODE)( void * );
-
-#define pdTRUE ( 1 )
-#define pdFALSE ( 0 )
-
-#define pdPASS ( 1 )
-#define pdFAIL ( 0 )
-#define errQUEUE_EMPTY ( 0 )
-#define errQUEUE_FULL ( 0 )
-
-/* Error definitions. */
-#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 )
-#define errNO_TASK_TO_RUN ( -2 )
-#define errQUEUE_BLOCKED ( -4 )
-#define errQUEUE_YIELD ( -5 )
-
-#endif /* PROJDEFS_H */
-
-
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/queue.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/queue.h
deleted file mode 100644
index 4a6c9a66..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/queue.h
+++ /dev/null
@@ -1,474 +0,0 @@
-/*
- FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry.
-
- This file is part of the FreeRTOS.org distribution.
-
- FreeRTOS.org is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- FreeRTOS.org is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with FreeRTOS.org; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes FreeRTOS.org, without being obliged to provide
- the source code for any proprietary components. See the licensing section
- of http://www.FreeRTOS.org for full details of how and when the exception
- can be applied.
-
- ***************************************************************************
- See http://www.FreeRTOS.org for documentation, latest information, license
- and contact details. Please ensure to read the configuration and relevant
- port sections of the online documentation.
-
- Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
- with commercial development and support options.
- ***************************************************************************
-*/
-
-#ifndef QUEUE_H
-#define QUEUE_H
-
-typedef void * xQueueHandle;
-
-/**
- * queue. h
- *
- *
- * Creates a new queue instance. This allocates the storage required by the
- * new queue and returns a handle for the queue.
- *
- * @param uxQueueLength The maximum number of items that the queue can contain.
- *
- * @param uxItemSize The number of bytes each item in the queue will require.
- * Items are queued by copy, not by reference, so this is the number of bytes
- * that will be copied for each posted item. Each item on the queue must be
- * the same size.
- *
- * @return If the queue is successfully create then a handle to the newly
- * created queue is returned. If the queue cannot be created then 0 is
- * returned.
- *
- * Example usage:
-
- struct AMessage
- {
- portCHAR ucMessageID;
- portCHAR ucData[ 20 ];
- };
-
- void vATask( void *pvParameters )
- {
- xQueueHandle xQueue1, xQueue2;
-
- // Create a queue capable of containing 10 unsigned long values.
- xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );
- if( xQueue1 == 0 )
- {
- // Queue was not created and must not be used.
- }
-
- // Create a queue capable of containing 10 pointers to AMessage structures.
- // These should be passed by pointer as they contain a lot of data.
- xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
- if( xQueue2 == 0 )
- {
- // Queue was not created and must not be used.
- }
-
- // ... Rest of task code.
- }
-
- *
- * Post an item on a queue. The item is queued by copy, not by reference.
- * This function must not be called from an interrupt service routine.
- * See xQueueSendFromISR () for an alternative which may be used in an ISR.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue. The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for space to become available on the queue, should it already
- * be full. The call will return immediately if this is set to 0. The
- * time is defined in tick periods so the constant portTICK_RATE_MS
- * should be used to convert to real time if this is required.
- *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
- *
- * Example usage:
-
- struct AMessage
- {
- portCHAR ucMessageID;
- portCHAR ucData[ 20 ];
- } xMessage;
-
- unsigned portLONG ulVar = 10UL;
-
- void vATask( void *pvParameters )
- {
- xQueueHandle xQueue1, xQueue2;
- struct AMessage *pxMessage;
-
- // Create a queue capable of containing 10 unsigned long values.
- xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );
-
- // Create a queue capable of containing 10 pointers to AMessage structures.
- // These should be passed by pointer as they contain a lot of data.
- xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
-
- // ...
-
- if( xQueue1 != 0 )
- {
- // Send an unsigned long. Wait for 10 ticks for space to become
- // available if necessary.
- if( xQueueSend( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS )
- {
- // Failed to post the message, even after 10 ticks.
- }
- }
-
- if( xQueue2 != 0 )
- {
- // Send a pointer to a struct AMessage object. Don't block if the
- // queue is already full.
- pxMessage = & xMessage;
- xQueueSend( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 );
- }
-
- // ... Rest of task code.
- }
-
- *
- * Receive an item from a queue. The item is received by copy so a buffer of
- * adequate size must be provided. The number of bytes copied into the buffer
- * was defined when the queue was created.
- *
- * This function must not be used in an interrupt service routine. See
- * xQueueReceiveFromISR for an alternative that can.
- *
- * @param pxQueue The handle to the queue from which the item is to be
- * received.
- *
- * @param pvBuffer Pointer to the buffer into which the received item will
- * be copied.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for an item to receive should the queue be empty at the time
- * of the call. The time is defined in tick periods so the constant
- * portTICK_RATE_MS should be used to convert to real time if this is required.
- *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
- *
- * Example usage:
-
- struct AMessage
- {
- portCHAR ucMessageID;
- portCHAR ucData[ 20 ];
- } xMessage;
-
- xQueueHandle xQueue;
-
- // Task to create a queue and post a value.
- void vATask( void *pvParameters )
- {
- struct AMessage *pxMessage;
-
- // Create a queue capable of containing 10 pointers to AMessage structures.
- // These should be passed by pointer as they contain a lot of data.
- xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
- if( xQueue == 0 )
- {
- // Failed to create the queue.
- }
-
- // ...
-
- // Send a pointer to a struct AMessage object. Don't block if the
- // queue is already full.
- pxMessage = & xMessage;
- xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 );
-
- // ... Rest of task code.
- }
-
- // Task to receive from the queue.
- void vADifferentTask( void *pvParameters )
- {
- struct AMessage *pxRxedMessage;
-
- if( xQueue != 0 )
- {
- // Receive a message on the created queue. Block for 10 ticks if a
- // message is not immediately available.
- if( xQueueReceive( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) )
- {
- // pcRxedMessage now points to the struct AMessage variable posted
- // by vATask.
- }
- }
-
- // ... Rest of task code.
- }
-
- *
- * Return the number of messages stored in a queue.
- *
- * @param xQueue A handle to the queue being queried.
- *
- * @return The number of messages available in the queue.
- *
- * \page uxQueueMessagesWaiting uxQueueMessagesWaiting
- * \ingroup QueueManagement
- */
-unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle xQueue );
-
-/**
- * queue. h
- *
void vQueueDelete( xQueueHandle xQueue );
- *
- * Delete a queue - freeing all the memory allocated for storing of items
- * placed on the queue.
- *
- * @param xQueue A handle to the queue to be deleted.
- *
- * \page vQueueDelete vQueueDelete
- * \ingroup QueueManagement
- */
-void vQueueDelete( xQueueHandle xQueue );
-
-/**
- * queue. h
- *
- *
- * Post an item on a queue. It is safe to use this function from within an
- * interrupt service routine.
- *
- * Items are queued by copy not reference so it is preferable to only
- * queue small items, especially when called from an ISR. In most cases
- * it would be preferable to store a pointer to the item being queued.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue. The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param cTaskPreviouslyWoken This is included so an ISR can post onto
- * the same queue multiple times from a single interrupt. The first call
- * should always pass in pdFALSE. Subsequent calls should pass in
- * the value returned from the previous call. See the file serial .c in the
- * PC port for a good example of this mechanism.
- *
- * @return pdTRUE if a task was woken by posting onto the queue. This is
- * used by the ISR to determine if a context switch may be required following
- * the ISR.
- *
- * Example usage for buffered IO (where the ISR can obtain more than one value
- * per call):
-
- void vBufferISR( void )
- {
- portCHAR cIn;
- portBASE_TYPE xTaskWokenByPost;
-
- // We have not woken a task at the start of the ISR.
- cTaskWokenByPost = pdFALSE;
-
- // Loop until the buffer is empty.
- do
- {
- // Obtain a byte from the buffer.
- cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
-
- // Post the byte. The first time round the loop cTaskWokenByPost
- // will be pdFALSE. If the queue send causes a task to wake we do
- // not want the task to run until we have finished the ISR, so
- // xQueueSendFromISR does not cause a context switch. Also we
- // don't want subsequent posts to wake any other tasks, so we store
- // the return value back into cTaskWokenByPost so xQueueSendFromISR
- // knows not to wake any task the next iteration of the loop.
- xTaskWokenByPost = xQueueSendFromISR( xRxQueue, &cIn, cTaskWokenByPost );
-
- } while( portINPUT_BYTE( BUFFER_COUNT ) );
-
- // Now the buffer is empty we can switch context if necessary.
- if( cTaskWokenByPost )
- {
- taskYIELD ();
- }
- }
-
- *
- * Receive an item from a queue. It is safe to use this function from within an
- * interrupt service routine.
- *
- * @param pxQueue The handle to the queue from which the item is to be
- * received.
- *
- * @param pvBuffer Pointer to the buffer into which the received item will
- * be copied.
- *
- * @param pxTaskWoken A task may be blocked waiting for space to become
- * available on the queue. If xQueueReceiveFromISR causes such a task to
- * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
- * remain unchanged.
- *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
- *
- * Example usage:
-
-
- xQueueHandle xQueue;
-
- // Function to create a queue and post some values.
- void vAFunction( void *pvParameters )
- {
- portCHAR cValueToPost;
- const portTickType xBlockTime = ( portTickType )0xff;
-
- // Create a queue capable of containing 10 characters.
- xQueue = xQueueCreate( 10, sizeof( portCHAR ) );
- if( xQueue == 0 )
- {
- // Failed to create the queue.
- }
-
- // ...
-
- // Post some characters that will be used within an ISR. If the queue
- // is full then this task will block for xBlockTime ticks.
- cValueToPost = 'a';
- xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );
- cValueToPost = 'b';
- xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );
-
- // ... keep posting characters ... this task may block when the queue
- // becomes full.
-
- cValueToPost = 'c';
- xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );
- }
-
- // ISR that outputs all the characters received on the queue.
- void vISR_Routine( void )
- {
- portBASE_TYPE xTaskWokenByReceive = pdFALSE;
- portCHAR cRxedChar;
-
- while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
- {
- // A character was received. Output the character now.
- vOutputCharacter( cRxedChar );
-
- // If removing the character from the queue woke the task that was
- // posting onto the queue cTaskWokenByReceive will have been set to
- // pdTRUE. No matter how many times this loop iterates only one
- // task will be woken.
- }
-
- if( cTaskWokenByPost != ( portCHAR ) pdFALSE;
- {
- taskYIELD ();
- }
- }
-
- * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR
- * \ingroup QueueManagement
- */
-signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken );
-
-
-/*
- * The functions defined above are for passing data to and from tasks. The
- * functions below are the equivalents for passing data to and from
- * co-rtoutines.
- *
- * These functions are called from the co-routine macro implementation and
- * should not be called directly from application code. Instead use the macro
- * wrappers defined within croutine.h.
- */
-signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken );
-signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken );
-signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait );
-signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait );
-
-#endif
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/semphr.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/semphr.h
deleted file mode 100644
index bae09c74..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/semphr.h
+++ /dev/null
@@ -1,292 +0,0 @@
-/*
- FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry.
-
- This file is part of the FreeRTOS.org distribution.
-
- FreeRTOS.org is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- FreeRTOS.org is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with FreeRTOS.org; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes FreeRTOS.org, without being obliged to provide
- the source code for any proprietary components. See the licensing section
- of http://www.FreeRTOS.org for full details of how and when the exception
- can be applied.
-
- ***************************************************************************
- See http://www.FreeRTOS.org for documentation, latest information, license
- and contact details. Please ensure to read the configuration and relevant
- port sections of the online documentation.
-
- Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
- with commercial development and support options.
- ***************************************************************************
-*/
-
-#include "queue.h"
-
-#ifndef SEMAPHORE_H
-#define SEMAPHORE_H
-
-typedef xQueueHandle xSemaphoreHandle;
-
-#define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( unsigned portCHAR ) 1 )
-#define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( unsigned portCHAR ) 0 )
-#define semGIVE_BLOCK_TIME ( ( portTickType ) 0 )
-
-
-/**
- * semphr. h
- *
- *
- * Macro that implements a semaphore by using the existing queue mechanism.
- * The queue length is 1 as this is a binary semaphore. The data size is 0
- * as we don't want to actually store any data - we just want to know if the
- * queue is empty or full.
- *
- * @param xSemaphore Handle to the created semaphore. Should be of type xSemaphoreHandle.
- *
- * Example usage:
-
- xSemaphoreHandle xSemaphore;
-
- void vATask( void * pvParameters )
- {
- // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
- // This is a macro so pass the variable in directly.
- vSemaphoreCreateBinary( xSemaphore );
-
- if( xSemaphore != NULL )
- {
- // The semaphore was created successfully.
- // The semaphore can now be used.
- }
- }
-
- * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary
- * \ingroup Semaphores
- */
-#define vSemaphoreCreateBinary( xSemaphore ) { \
- xSemaphore = xQueueCreate( ( unsigned portCHAR ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH ); \
- if( xSemaphore != NULL ) \
- { \
- xSemaphoreGive( xSemaphore ); \
- } \
- }
-
-/**
- * semphr. h
- * xSemaphoreTake(
- * xSemaphoreHandle xSemaphore,
- * portTickType xBlockTime
- * )
- *
- * Macro to obtain a semaphore. The semaphore must of been created using
- * vSemaphoreCreateBinary ().
- *
- * @param xSemaphore A handle to the semaphore being obtained. This is the
- * handle returned by vSemaphoreCreateBinary ();
- *
- * @param xBlockTime The time in ticks to wait for the semaphore to become
- * available. The macro portTICK_RATE_MS can be used to convert this to a
- * real time. A block time of zero can be used to poll the semaphore.
- *
- * @return pdTRUE if the semaphore was obtained. pdFALSE if xBlockTime
- * expired without the semaphore becoming available.
- *
- * Example usage:
-
- xSemaphoreHandle xSemaphore = NULL;
-
- // A task that creates a semaphore.
- void vATask( void * pvParameters )
- {
- // Create the semaphore to guard a shared resource.
- vSemaphoreCreateBinary( xSemaphore );
- }
-
- // A task that uses the semaphore.
- void vAnotherTask( void * pvParameters )
- {
- // ... Do other things.
-
- if( xSemaphore != NULL )
- {
- // See if we can obtain the semaphore. If the semaphore is not available
- // wait 10 ticks to see if it becomes free.
- if( xSemaphoreTake( xSemaphore, ( portTickType ) 10 ) == pdTRUE )
- {
- // We were able to obtain the semaphore and can now access the
- // shared resource.
-
- // ...
-
- // We have finished accessing the shared resource. Release the
- // semaphore.
- xSemaphoreGive( xSemaphore );
- }
- else
- {
- // We could not obtain the semaphore and can therefore not access
- // the shared resource safely.
- }
- }
- }
-
- *
- * Macro to release a semaphore. The semaphore must of been created using
- * vSemaphoreCreateBinary (), and obtained using sSemaphoreTake ().
- *
- * This must not be used from an ISR. See xSemaphoreGiveFromISR () for
- * an alternative which can be used from an ISR.
- *
- * @param xSemaphore A handle to the semaphore being released. This is the
- * handle returned by vSemaphoreCreateBinary ();
- *
- * @return pdTRUE if the semaphore was released. pdFALSE if an error occurred.
- * Semaphores are implemented using queues. An error can occur if there is
- * no space on the queue to post a message - indicating that the
- * semaphore was not first obtained correctly.
- *
- * Example usage:
-
- xSemaphoreHandle xSemaphore = NULL;
-
- void vATask( void * pvParameters )
- {
- // Create the semaphore to guard a shared resource.
- vSemaphoreCreateBinary( xSemaphore );
-
- if( xSemaphore != NULL )
- {
- if( xSemaphoreGive( xSemaphore ) != pdTRUE )
- {
- // We would expect this call to fail because we cannot give
- // a semaphore without first "taking" it!
- }
-
- // Obtain the semaphore - don't block if the semaphore is not
- // immediately available.
- if( xSemaphoreTake( xSemaphore, ( portTickType ) 0 ) )
- {
- // We now have the semaphore and can access the shared resource.
-
- // ...
-
- // We have finished accessing the shared resource so can free the
- // semaphore.
- if( xSemaphoreGive( xSemaphore ) != pdTRUE )
- {
- // We would not expect this call to fail because we must have
- // obtained the semaphore to get here.
- }
- }
- }
- }
-
- *
- * Macro to release a semaphore. The semaphore must of been created using
- * vSemaphoreCreateBinary (), and obtained using xSemaphoreTake ().
- *
- * This macro can be used from an ISR.
- *
- * @param xSemaphore A handle to the semaphore being released. This is the
- * handle returned by vSemaphoreCreateBinary ();
- *
- * @param sTaskPreviouslyWoken This is included so an ISR can make multiple calls
- * to xSemaphoreGiveFromISR () from a single interrupt. The first call
- * should always pass in pdFALSE. Subsequent calls should pass in
- * the value returned from the previous call. See the file serial .c in the
- * PC port for a good example of using xSemaphoreGiveFromISR ().
- *
- * @return pdTRUE if a task was woken by releasing the semaphore. This is
- * used by the ISR to determine if a context switch may be required following
- * the ISR.
- *
- * Example usage:
-
- #define LONG_TIME 0xffff
- #define TICKS_TO_WAIT 10
- xSemaphoreHandle xSemaphore = NULL;
-
- // Repetitive task.
- void vATask( void * pvParameters )
- {
- for( ;; )
- {
- // We want this task to run every 10 ticks or a timer. The semaphore
- // was created before this task was started
-
- // Block waiting for the semaphore to become available.
- if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
- {
- // It is time to execute.
-
- // ...
-
- // We have finished our task. Return to the top of the loop where
- // we will block on the semaphore until it is time to execute
- // again.
- }
- }
- }
-
- // Timer ISR
- void vTimerISR( void * pvParameters )
- {
- static unsigned portCHAR ucLocalTickCount = 0;
-
- // A timer tick has occurred.
-
- // ... Do other time functions.
-
- // Is it time for vATask () to run?
- ucLocalTickCount++;
- if( ucLocalTickCount >= TICKS_TO_WAIT )
- {
- // Unblock the task by releasing the semaphore.
- xSemaphoreGive( xSemaphore );
-
- // Reset the count so we release the semaphore again in 10 ticks time.
- ucLocalTickCount = 0;
- }
- }
-
- * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR
- * \ingroup Semaphores
- */
-#define xSemaphoreGiveFromISR( xSemaphore, xTaskPreviouslyWoken ) xQueueSendFromISR( ( xQueueHandle ) xSemaphore, NULL, xTaskPreviouslyWoken )
-
-
-#endif
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/task.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/task.h
deleted file mode 100644
index 5103f3c2..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/task.h
+++ /dev/null
@@ -1,970 +0,0 @@
-/*
- FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry.
-
- This file is part of the FreeRTOS.org distribution.
-
- FreeRTOS.org is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- FreeRTOS.org is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with FreeRTOS.org; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes FreeRTOS.org, without being obliged to provide
- the source code for any proprietary components. See the licensing section
- of http://www.FreeRTOS.org for full details of how and when the exception
- can be applied.
-
- ***************************************************************************
- See http://www.FreeRTOS.org for documentation, latest information, license
- and contact details. Please ensure to read the configuration and relevant
- port sections of the online documentation.
-
- Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
- with commercial development and support options.
- ***************************************************************************
-*/
-
-/*
-Changes since V4.3.1:
-
- + Added xTaskGetSchedulerState() function.
-*/
-
-#ifndef TASK_H
-#define TASK_H
-
-#include "portable.h"
-#include "list.h"
-
-/*-----------------------------------------------------------
- * MACROS AND DEFINITIONS
- *----------------------------------------------------------*/
-
-#define tskKERNEL_VERSION_NUMBER "V4.4.0"
-
-/**
- * task. h
- *
- * Type by which tasks are referenced. For example, a call to xTaskCreate
- * returns (via a pointer parameter) an xTaskHandle variable that can then
- * be used as a parameter to vTaskDelete to delete the task.
- *
- * \page xTaskHandle xTaskHandle
- * \ingroup Tasks
- */
-typedef void * xTaskHandle;
-
-/*
- * Used internally only.
- */
-typedef struct xTIME_OUT
-{
- portBASE_TYPE xOverflowCount;
- portTickType xTimeOnEntering;
-} xTimeOutType;
-
-/*
- * Defines the priority used by the idle task. This must not be modified.
- *
- * \ingroup TaskUtils
- */
-#define tskIDLE_PRIORITY ( ( unsigned portBASE_TYPE ) 0 )
-
-/**
- * task. h
- *
- * Macro for forcing a context switch.
- *
- * \page taskYIELD taskYIELD
- * \ingroup SchedulerControl
- */
-#define taskYIELD() portYIELD()
-
-/**
- * task. h
- *
- * Macro to mark the start of a critical code region. Preemptive context
- * switches cannot occur when in a critical region.
- *
- * NOTE: This may alter the stack (depending on the portable implementation)
- * so must be used with care!
- *
- * \page taskENTER_CRITICAL taskENTER_CRITICAL
- * \ingroup SchedulerControl
- */
-#define taskENTER_CRITICAL() portENTER_CRITICAL()
-
-/**
- * task. h
- *
- * Macro to mark the end of a critical code region. Preemptive context
- * switches cannot occur when in a critical region.
- *
- * NOTE: This may alter the stack (depending on the portable implementation)
- * so must be used with care!
- *
- * \page taskEXIT_CRITICAL taskEXIT_CRITICAL
- * \ingroup SchedulerControl
- */
-#define taskEXIT_CRITICAL() portEXIT_CRITICAL()
-
-/**
- * task. h
- *
- * Macro to disable all maskable interrupts.
- *
- * \page taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS
- * \ingroup SchedulerControl
- */
-#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS()
-
-/**
- * task. h
- *
- * Macro to enable microcontroller interrupts.
- *
- * \page taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS
- * \ingroup SchedulerControl
- */
-#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS()
-
-/* Definitions returned by xTaskGetSchedulerState(). */
-#define taskSCHEDULER_NOT_STARTED 0
-#define taskSCHEDULER_RUNNING 1
-#define taskSCHEDULER_SUSPENDED 2
-
-/*-----------------------------------------------------------
- * TASK CREATION API
- *----------------------------------------------------------*/
-
-/**
- * task. h
- *
- *
- * Create a new task and add it to the list of tasks that are ready to run.
- *
- * @param pvTaskCode Pointer to the task entry function. Tasks
- * must be implemented to never return (i.e. continuous loop).
- *
- * @param pcName A descriptive name for the task. This is mainly used to
- * facilitate debugging. Max length defined by tskMAX_TASK_NAME_LEN - default
- * is 16.
- *
- * @param usStackDepth The size of the task stack specified as the number of
- * variables the stack can hold - not the number of bytes. For example, if
- * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes
- * will be allocated for stack storage.
- *
- * @param pvParameters Pointer that will be used as the parameter for the task
- * being created.
- *
- * @param uxPriority The priority at which the task should run.
- *
- * @param pvCreatedTask Used to pass back a handle by which the created task
- * can be referenced.
- *
- * @return pdPASS if the task was successfully created and added to a ready
- * list, otherwise an error code defined in the file errors. h
- *
- * Example usage:
-
- // Task to be created.
- void vTaskCode( void * pvParameters )
- {
- for( ;; )
- {
- // Task code goes here.
- }
- }
-
- // Function that creates a task.
- void vOtherFunction( void )
- {
- unsigned char ucParameterToPass;
- xTaskHandle xHandle;
-
- // Create the task, storing the handle.
- xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
-
- // Use the handle to delete the task.
- vTaskDelete( xHandle );
- }
-
- *
- * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Remove a task from the RTOS real time kernels management. The task being
- * deleted will be removed from all ready, blocked, suspended and event lists.
- *
- * NOTE: The idle task is responsible for freeing the kernel allocated
- * memory from tasks that have been deleted. It is therefore important that
- * the idle task is not starved of microcontroller processing time if your
- * application makes any calls to vTaskDelete (). Memory allocated by the
- * task code is not automatically freed, and should be freed before the task
- * is deleted.
- *
- * See the demo application file death.c for sample code that utilises
- * vTaskDelete ().
- *
- * @param pxTask The handle of the task to be deleted. Passing NULL will
- * cause the calling task to be deleted.
- *
- * Example usage:
-
- void vOtherFunction( void )
- {
- xTaskHandle xHandle;
-
- // Create the task, storing the handle.
- xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-
- // Use the handle to delete the task.
- vTaskDelete( xHandle );
- }
-
- *
- * Delay a task for a given number of ticks. The actual time that the
- * task remains blocked depends on the tick rate. The constant
- * portTICK_RATE_MS can be used to calculate real time from the tick
- * rate - with the resolution of one tick period.
- *
- * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * @param xTicksToDelay The amount of time, in tick periods, that
- * the calling task should block.
- *
- * Example usage:
-
- // Wait 10 ticks before performing an action.
- // NOTE:
- // This is for demonstration only and would be better achieved
- // using vTaskDelayUntil ().
- void vTaskFunction( void * pvParameters )
- {
- portTickType xDelay, xNextTime;
-
- // Calc the time at which we want to perform the action
- // next.
- xNextTime = xTaskGetTickCount () + ( portTickType ) 10;
-
- for( ;; )
- {
- xDelay = xNextTime - xTaskGetTickCount ();
- xNextTime += ( portTickType ) 10;
-
- // Guard against overflow
- if( xDelay <= ( portTickType ) 10 )
- {
- vTaskDelay( xDelay );
- }
-
- // Perform action here.
- }
- }
-
- *
- * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Delay a task until a specified time. This function can be used by cyclical
- * tasks to ensure a constant execution frequency.
- *
- * This function differs from vTaskDelay () in one important aspect: vTaskDelay () will
- * cause a task to block for the specified number of ticks from the time vTaskDelay () is
- * called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed
- * execution frequency as the time between a task starting to execute and that task
- * calling vTaskDelay () may not be fixed [the task may take a different path though the
- * code between calls, or may get interrupted or preempted a different number of times
- * each time it executes].
- *
- * Whereas vTaskDelay () specifies a wake time relative to the time at which the function
- * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to
- * unblock.
- *
- * The constant portTICK_RATE_MS can be used to calculate real time from the tick
- * rate - with the resolution of one tick period.
- *
- * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the
- * task was last unblocked. The variable must be initialised with the current time
- * prior to its first use (see the example below). Following this the variable is
- * automatically updated within vTaskDelayUntil ().
- *
- * @param xTimeIncrement The cycle time period. The task will be unblocked at
- * time *pxPreviousWakeTime + xTimeIncrement. Calling vTaskDelayUntil with the
- * same xTimeIncrement parameter value will cause the task to execute with
- * a fixed interface period.
- *
- * Example usage:
-
- // Perform an action every 10 ticks.
- void vTaskFunction( void * pvParameters )
- {
- portTickType xLastWakeTime;
- const portTickType xFrequency = 10;
-
- // Initialise the xLastWakeTime variable with the current time.
- xLastWakeTime = xTaskGetTickCount ();
- for( ;; )
- {
- // Wait for the next cycle.
- vTaskDelayUntil( &xLastWakeTime, xFrequency );
-
- // Perform action here.
- }
- }
-
- *
- * INCLUDE_xTaskPriorityGet must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Obtain the priority of any task.
- *
- * @param pxTask Handle of the task to be queried. Passing a NULL
- * handle results in the priority of the calling task being returned.
- *
- * @return The priority of pxTask.
- *
- * Example usage:
-
- void vAFunction( void )
- {
- xTaskHandle xHandle;
-
- // Create a task, storing the handle.
- xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-
- // ...
-
- // Use the handle to obtain the priority of the created task.
- // It was created with tskIDLE_PRIORITY, but may have changed
- // it itself.
- if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
- {
- // The task has changed it's priority.
- }
-
- // ...
-
- // Is our priority higher than the created task?
- if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
- {
- // Our priority (obtained using NULL handle) is higher.
- }
- }
-
- *
- * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Set the priority of any task.
- *
- * A context switch will occur before the function returns if the priority
- * being set is higher than the currently executing task.
- *
- * @param pxTask Handle to the task for which the priority is being set.
- * Passing a NULL handle results in the priority of the calling task being set.
- *
- * @param uxNewPriority The priority to which the task will be set.
- *
- * Example usage:
-
- void vAFunction( void )
- {
- xTaskHandle xHandle;
-
- // Create a task, storing the handle.
- xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-
- // ...
-
- // Use the handle to raise the priority of the created task.
- vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
-
- // ...
-
- // Use a NULL handle to raise our priority to the same value.
- vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
- }
-
- *
- * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Suspend any task. When suspended a task will never get any microcontroller
- * processing time, no matter what its priority.
- *
- * Calls to vTaskSuspend are not accumulative -
- * i.e. calling vTaskSuspend () twice on the same task still only requires one
- * call to vTaskResume () to ready the suspended task.
- *
- * @param pxTaskToSuspend Handle to the task being suspended. Passing a NULL
- * handle will cause the calling task to be suspended.
- *
- * Example usage:
-
- void vAFunction( void )
- {
- xTaskHandle xHandle;
-
- // Create a task, storing the handle.
- xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-
- // ...
-
- // Use the handle to suspend the created task.
- vTaskSuspend( xHandle );
-
- // ...
-
- // The created task will not run during this period, unless
- // another task calls vTaskResume( xHandle ).
-
- //...
-
-
- // Suspend ourselves.
- vTaskSuspend( NULL );
-
- // We cannot get here unless another task calls vTaskResume
- // with our handle as the parameter.
- }
-
- *
- * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Resumes a suspended task.
- *
- * A task that has been suspended by one of more calls to vTaskSuspend ()
- * will be made available for running again by a single call to
- * vTaskResume ().
- *
- * @param pxTaskToResume Handle to the task being readied.
- *
- * Example usage:
-
- void vAFunction( void )
- {
- xTaskHandle xHandle;
-
- // Create a task, storing the handle.
- xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-
- // ...
-
- // Use the handle to suspend the created task.
- vTaskSuspend( xHandle );
-
- // ...
-
- // The created task will not run during this period, unless
- // another task calls vTaskResume( xHandle ).
-
- //...
-
-
- // Resume the suspended task ourselves.
- vTaskResume( xHandle );
-
- // The created task will once again get microcontroller processing
- // time in accordance with it priority within the system.
- }
-
- *
- * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be
- * available. See the configuration section for more information.
- *
- * An implementation of vTaskResume() that can be called from within an ISR.
- *
- * A task that has been suspended by one of more calls to vTaskSuspend ()
- * will be made available for running again by a single call to
- * xTaskResumeFromISR ().
- *
- * @param pxTaskToResume Handle to the task being readied.
- *
- * \defgroup vTaskResumeFromISR vTaskResumeFromISR
- * \ingroup TaskCtrl
- */
-portBASE_TYPE xTaskResumeFromISR( xTaskHandle pxTaskToResume );
-
-/*-----------------------------------------------------------
- * SCHEDULER CONTROL
- *----------------------------------------------------------*/
-
-/**
- * task. h
- *
void vTaskStartScheduler( void );
- *
- * Starts the real time kernel tick processing. After calling the kernel
- * has control over which tasks are executed and when. This function
- * does not return until an executing task calls vTaskEndScheduler ().
- *
- * At least one task should be created via a call to xTaskCreate ()
- * before calling vTaskStartScheduler (). The idle task is created
- * automatically when the first application task is created.
- *
- * See the demo application file main.c for an example of creating
- * tasks and starting the kernel.
- *
- * Example usage:
-
- void vAFunction( void )
- {
- // Create at least one task before starting the kernel.
- xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
-
- // Start the real time kernel with preemption.
- vTaskStartScheduler ();
-
- // Will not get here unless a task calls vTaskEndScheduler ()
- }
-
- *
- * Stops the real time kernel tick. All created tasks will be automatically
- * deleted and multitasking (either preemptive or cooperative) will
- * stop. Execution then resumes from the point where vTaskStartScheduler ()
- * was called, as if vTaskStartScheduler () had just returned.
- *
- * See the demo application file main. c in the demo/PC directory for an
- * example that uses vTaskEndScheduler ().
- *
- * vTaskEndScheduler () requires an exit function to be defined within the
- * portable layer (see vPortEndScheduler () in port. c for the PC port). This
- * performs hardware specific operations such as stopping the kernel tick.
- *
- * vTaskEndScheduler () will cause all of the resources allocated by the
- * kernel to be freed - but will not free resources allocated by application
- * tasks.
- *
- * Example usage:
-
- void vTaskCode( void * pvParameters )
- {
- for( ;; )
- {
- // Task code goes here.
-
- // At some point we want to end the real time kernel processing
- // so call ...
- vTaskEndScheduler ();
- }
- }
-
- void vAFunction( void )
- {
- // Create at least one task before starting the kernel.
- xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
-
- // Start the real time kernel with preemption.
- vTaskStartScheduler ();
-
- // Will only get here when the vTaskCode () task has called
- // vTaskEndScheduler (). When we get here we are back to single task
- // execution.
- }
-
- *
- * Suspends all real time kernel activity while keeping interrupts (including the
- * kernel tick) enabled.
- *
- * After calling vTaskSuspendAll () the calling task will continue to execute
- * without risk of being swapped out until a call to xTaskResumeAll () has been
- * made.
- *
- * Example usage:
-
- void vTask1( void * pvParameters )
- {
- for( ;; )
- {
- // Task code goes here.
-
- // ...
-
- // At some point the task wants to perform a long operation during
- // which it does not want to get swapped out. It cannot use
- // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
- // operation may cause interrupts to be missed - including the
- // ticks.
-
- // Prevent the real time kernel swapping out the task.
- vTaskSuspendAll ();
-
- // Perform the operation here. There is no need to use critical
- // sections as we have all the microcontroller processing time.
- // During this time interrupts will still operate and the kernel
- // tick count will be maintained.
-
- // ...
-
- // The operation is complete. Restart the kernel.
- xTaskResumeAll ();
- }
- }
-
- *
- * Resumes real time kernel activity following a call to vTaskSuspendAll ().
- * After a call to vTaskSuspendAll () the kernel will take control of which
- * task is executing at any time.
- *
- * @return If resuming the scheduler caused a context switch then pdTRUE is
- * returned, otherwise pdFALSE is returned.
- *
- * Example usage:
-
- void vTask1( void * pvParameters )
- {
- for( ;; )
- {
- // Task code goes here.
-
- // ...
-
- // At some point the task wants to perform a long operation during
- // which it does not want to get swapped out. It cannot use
- // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
- // operation may cause interrupts to be missed - including the
- // ticks.
-
- // Prevent the real time kernel swapping out the task.
- vTaskSuspendAll ();
-
- // Perform the operation here. There is no need to use critical
- // sections as we have all the microcontroller processing time.
- // During this time interrupts will still operate and the real
- // time kernel tick count will be maintained.
-
- // ...
-
- // The operation is complete. Restart the kernel. We want to force
- // a context switch - but there is no point if resuming the scheduler
- // caused a context switch already.
- if( !xTaskResumeAll () )
- {
- taskYIELD ();
- }
- }
- }
-
- *
- * @return The number of tasks that the real time kernel is currently managing.
- * This includes all ready, blocked and suspended tasks. A task that
- * has been deleted but not yet freed by the idle task will also be
- * included in the count.
- *
- * \page uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks
- * \ingroup TaskUtils
- */
-unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void );
-
-/**
- * task. h
- *
void vTaskList( portCHAR *pcWriteBuffer );
- *
- * configUSE_TRACE_FACILITY, INCLUDE_vTaskDelete and INCLUDE_vTaskSuspend
- * must all be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * NOTE: This function will disable interrupts for its duration. It is
- * not intended for normal application runtime use but as a debug aid.
- *
- * Lists all the current tasks, along with their current state and stack
- * usage high water mark.
- *
- * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
- * suspended ('S').
- *
- * @param pcWriteBuffer A buffer into which the above mentioned details
- * will be written, in ascii form. This buffer is assumed to be large
- * enough to contain the generated report. Approximately 40 bytes per
- * task should be sufficient.
- *
- * \page vTaskList vTaskList
- * \ingroup TaskUtils
- */
-void vTaskList( signed portCHAR *pcWriteBuffer );
-
-/**
- * task. h
- *
- *
- * Starts a real time kernel activity trace. The trace logs the identity of
- * which task is running when.
- *
- * The trace file is stored in binary format. A separate DOS utility called
- * convtrce.exe is used to convert this into a tab delimited text file which
- * can be viewed and plotted in a spread sheet.
- *
- * @param pcBuffer The buffer into which the trace will be written.
- *
- * @param ulBufferSize The size of pcBuffer in bytes. The trace will continue
- * until either the buffer in full, or ulTaskEndTrace () is called.
- *
- * \page vTaskStartTrace vTaskStartTrace
- * \ingroup TaskUtils
- */
-void vTaskStartTrace( signed portCHAR * pcBuffer, unsigned portLONG ulBufferSize );
-
-/**
- * task. h
- *
unsigned portLONG ulTaskEndTrace( void );
- *
- * Stops a kernel activity trace. See vTaskStartTrace ().
- *
- * @return The number of bytes that have been written into the trace buffer.
- *
- * \page usTaskEndTrace usTaskEndTrace
- * \ingroup TaskUtils
- */
-unsigned portLONG ulTaskEndTrace( void );
-
-
-/*-----------------------------------------------------------
- * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
- *----------------------------------------------------------*/
-
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY
- * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
- * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * Called from the real time kernel tick (either preemptive or cooperative),
- * this increments the tick count and checks if any tasks that are blocked
- * for a finite period required removing from a blocked list and placing on
- * a ready list.
- */
-inline void vTaskIncrementTick( void );
-
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN
- * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
- *
- * Removes the calling task from the ready list and places it both
- * on the list of tasks waiting for a particular event, and the
- * list of delayed tasks. The task will be removed from both lists
- * and replaced on the ready list should either the event occur (and
- * there be no higher priority tasks waiting on the same event) or
- * the delay period expires.
- *
- * @param pxEventList The list containing tasks that are blocked waiting
- * for the event to occur.
- *
- * @param xTicksToWait The maximum amount of time that the task should wait
- * for the event to occur. This is specified in kernel ticks,the constant
- * portTICK_RATE_MS can be used to convert kernel ticks into a real time
- * period.
- */
-void vTaskPlaceOnEventList( xList *pxEventList, portTickType xTicksToWait );
-
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN
- * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
- *
- * Removes a task from both the specified event list and the list of blocked
- * tasks, and places it on a ready queue.
- *
- * xTaskRemoveFromEventList () will be called if either an event occurs to
- * unblock a task, or the block timeout period expires.
- *
- * @return pdTRUE if the task being removed has a higher priority than the task
- * making the call, otherwise pdFALSE.
- */
-signed portBASE_TYPE xTaskRemoveFromEventList( const xList *pxEventList );
-
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN
- * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * INCLUDE_vTaskCleanUpResources and INCLUDE_vTaskSuspend must be defined as 1
- * for this function to be available.
- * See the configuration section for more information.
- *
- * Empties the ready and delayed queues of task control blocks, freeing the
- * memory allocated for the task control block and task stacks as it goes.
- */
-void vTaskCleanUpResources( void );
-
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY
- * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
- * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * Sets the pointer to the current TCB to the TCB of the highest priority task
- * that is ready to run.
- */
-inline void vTaskSwitchContext( void );
-
-/*
- * Return the handle of the calling task.
- */
-xTaskHandle xTaskGetCurrentTaskHandle( void );
-
-/*
- * Capture the current time status for future reference.
- */
-void vTaskSetTimeOutState( xTimeOutType *pxTimeOut );
-
-/*
- * Compare the time status now with that previously captured to see if the
- * timeout has expired.
- */
-portBASE_TYPE xTaskCheckForTimeOut( xTimeOutType *pxTimeOut, portTickType * const pxTicksToWait );
-
-/*
- * Shortcut used by the queue implementation to prevent unnecessary call to
- * taskYIELD();
- */
-void vTaskMissedYield( void );
-
-/*
- * Returns the scheduler state as taskSCHEDULER_RUNNING,
- * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.
- */
-portBASE_TYPE xTaskGetSchedulerState( void );
-
-#endif /* TASK_H */
-
-
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/list.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/list.c
deleted file mode 100644
index 3faa8b4e..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/list.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry.
-
- This file is part of the FreeRTOS.org distribution.
-
- FreeRTOS.org is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- FreeRTOS.org is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with FreeRTOS.org; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes FreeRTOS.org, without being obliged to provide
- the source code for any proprietary components. See the licensing section
- of http://www.FreeRTOS.org for full details of how and when the exception
- can be applied.
-
- ***************************************************************************
- See http://www.FreeRTOS.org for documentation, latest information, license
- and contact details. Please ensure to read the configuration and relevant
- port sections of the online documentation.
-
- Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
- with commercial development and support options.
- ***************************************************************************
-*/
-
-/*
-Changes from V1.2.0
-
- + Removed the volatile modifier from the function parameters. This was
- only ever included to prevent compiler warnings. Now warnings are
- removed by casting parameters where the calls are made.
-
- + prvListGetOwnerOfNextEntry() and prvListGetOwnerOfHeadEntry() have been
- removed from the c file and added as macros to the h file.
-
- + uxNumberOfItems has been added to the list structure. This removes the
- need for a pointer comparison when checking if a list is empty, and so
- is slightly faster.
-
- + Removed the NULL check in vListRemove(). This makes the call faster but
- necessitates any application code utilising the list implementation to
- ensure NULL pointers are not passed.
-
-Changes from V2.0.0
-
- + Double linked the lists to allow faster removal item removal.
-
-Changes from V2.6.1
-
- + Make use of the new portBASE_TYPE definition where ever appropriate.
-
-Changes from V3.0.0
-
- + API changes as described on the FreeRTOS.org WEB site.
-
-Changes from V3.2.4
-
- + Removed the pxHead member of the xList structure. This always pointed
- to the same place so has been removed to free a few bytes of RAM.
-
- + Introduced the xMiniListItem structure that does not include the
- xListItem members that are not required by the xListEnd member of a list.
- Again this was done to reduce RAM usage.
-
- + Changed the volatile definitions of some structure members to clean up
- the code where the list structures are used.
-
-Changes from V4.0.4
-
- + Optimised vListInsert() in the case when the wake time is the maximum
- tick count value.
-*/
-
-#include
-#include "FreeRTOS.h"
-#include "list.h"
-
-/*-----------------------------------------------------------
- * PUBLIC LIST API documented in list.h
- *----------------------------------------------------------*/
-
-void vListInitialise( xList *pxList )
-{
- /* The list structure contains a list item which is used to mark the
- end of the list. To initialise the list the list end is inserted
- as the only list entry. */
- pxList->pxIndex = ( xListItem * ) &( pxList->xListEnd );
-
- /* The list end value is the highest possible value in the list to
- ensure it remains at the end of the list. */
- pxList->xListEnd.xItemValue = portMAX_DELAY;
-
- /* The list end next and previous pointers point to itself so we know
- when the list is empty. */
- pxList->xListEnd.pxNext = ( xListItem * ) &( pxList->xListEnd );
- pxList->xListEnd.pxPrevious = ( xListItem * ) &( pxList->xListEnd );
-
- pxList->uxNumberOfItems = 0;
-}
-/*-----------------------------------------------------------*/
-
-void vListInitialiseItem( xListItem *pxItem )
-{
- /* Make sure the list item is not recorded as being on a list. */
- pxItem->pvContainer = NULL;
-}
-/*-----------------------------------------------------------*/
-
-void vListInsertEnd( xList *pxList, xListItem *pxNewListItem )
-{
-volatile xListItem * pxIndex;
-
- /* Insert a new list item into pxList, but rather than sort the list,
- makes the new list item the last item to be removed by a call to
- pvListGetOwnerOfNextEntry. This means it has to be the item pointed to by
- the pxIndex member. */
- pxIndex = pxList->pxIndex;
-
- pxNewListItem->pxNext = pxIndex->pxNext;
- pxNewListItem->pxPrevious = pxList->pxIndex;
- pxIndex->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem;
- pxIndex->pxNext = ( volatile xListItem * ) pxNewListItem;
- pxList->pxIndex = ( volatile xListItem * ) pxNewListItem;
-
- /* Remember which list the item is in. */
- pxNewListItem->pvContainer = ( void * ) pxList;
-
- ( pxList->uxNumberOfItems )++;
-}
-/*-----------------------------------------------------------*/
-
-void vListInsert( xList *pxList, xListItem *pxNewListItem )
-{
-volatile xListItem *pxIterator;
-portTickType xValueOfInsertion;
-
- /* Insert the new list item into the list, sorted in ulListItem order. */
- xValueOfInsertion = pxNewListItem->xItemValue;
-
- /* If the list already contains a list item with the same item value then
- the new list item should be placed after it. This ensures that TCB's which
- are stored in ready lists (all of which have the same ulListItem value)
- get an equal share of the CPU. However, if the xItemValue is the same as
- the back marker the iteration loop below will not end. This means we need
- to guard against this by checking the value first and modifying the
- algorithm slightly if necessary. */
- if( xValueOfInsertion == portMAX_DELAY )
- {
- pxIterator = pxList->xListEnd.pxPrevious;
- }
- else
- {
- for( pxIterator = ( xListItem * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext )
- {
- /* There is nothing to do here, we are just iterating to the
- wanted insertion position. */
- }
- }
-
- pxNewListItem->pxNext = pxIterator->pxNext;
- pxNewListItem->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem;
- pxNewListItem->pxPrevious = pxIterator;
- pxIterator->pxNext = ( volatile xListItem * ) pxNewListItem;
-
- /* Remember which list the item is in. This allows fast removal of the
- item later. */
- pxNewListItem->pvContainer = ( void * ) pxList;
-
- ( pxList->uxNumberOfItems )++;
-}
-/*-----------------------------------------------------------*/
-
-void vListRemove( xListItem *pxItemToRemove )
-{
-xList * pxList;
-
- pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
- pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
-
- /* The list item knows which list it is in. Obtain the list from the list
- item. */
- pxList = ( xList * ) pxItemToRemove->pvContainer;
-
- /* Make sure the index is left pointing to a valid item. */
- if( pxList->pxIndex == pxItemToRemove )
- {
- pxList->pxIndex = pxItemToRemove->pxPrevious;
- }
-
- pxItemToRemove->pvContainer = NULL;
- ( pxList->uxNumberOfItems )--;
-}
-/*-----------------------------------------------------------*/
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/GCC/ARM7_AT91SAM7S/port.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/GCC/ARM7_AT91SAM7S/port.c
deleted file mode 100644
index 797cb507..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/GCC/ARM7_AT91SAM7S/port.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * MODBUS Library: SAM7X Port
- * Copyright (c) 2007 Christian Walter
- * All rights reserved.
- *
- * $Id$
- */
-/*
- * FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry.
- *
- * This file is part of the FreeRTOS.org distribution.
- *
- * FreeRTOS.org is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * FreeRTOS.org is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with FreeRTOS.org; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * A special exception to the GPL can be applied should you wish to distribute
- * a combined work that includes FreeRTOS.org, without being obliged to provide
- * the source code for any proprietary components. See the licensing section
- * of http://www.FreeRTOS.org for full details of how and when the exception
- * can be applied.
- *
- ****************************************************************************
- * See http://www.FreeRTOS.org for documentation, latest information, license
- * and contact details. Please ensure to read the configuration and relevant
- * port sections of the online documentation.
- *
- * Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
- * with commercial development and support options.
- ***************************************************************************
- */
-
-/* ----------------------- System includes ----------------------------------*/
-#include
-
-/* ----------------------- FreeRTOS includes --------------------------------*/
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* ----------------------- Platform includes --------------------------------*/
-#include "AT91SAM7X256.h"
-#include "lib_AT91SAM7X256.h"
-
-/* ----------------------- Defines ------------------------------------------*/
-#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f )
-#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 )
-#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )
-#define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 )
-
-/*
-#define portPRESCALE_VALUE 0x00
-#define portINTERRUPT_ON_MATCH ( ( unsigned portLONG ) 0x01 )
-#define portRESET_COUNT_ON_MATCH ( ( unsigned portLONG ) 0x02 )
-
-#define portPIT_CLOCK_DIVISOR ( ( unsigned portLONG ) 16 )
-#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_RATE_MS )
-
-#define portINT_LEVEL_SENSITIVE 0
-#define portPIT_ENABLE ( ( unsigned portSHORT ) 0x1 << 24 )
-#define portPIT_INT_ENABLE ( ( unsigned portSHORT ) 0x1 << 25 )
-*/
-
-/* ----------------------- Type definitions ---------------------------------*/
-
-/* ----------------------- Static variables ---------------------------------*/
-
-/* ----------------------- Function prototypes ------------------------------*/
-extern void vPortISRStartFirstTask( void );
-extern void vNonPreemptiveTick ( void );
-extern void vPreemptiveTick( void );
-
-/* ----------------------- Static functions ---------------------------------*/
-static void prvSetupTimerInterrupt( void );
-
-/* ----------------------- Start implementation -----------------------------*/
-
-portSTACK_TYPE *
-pxPortInitialiseStack( portSTACK_TYPE * pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
-{
- portSTACK_TYPE *pxOriginalTOS;
-
- pxOriginalTOS = pxTopOfStack;
- /* Setup the initial stack of the task. The stack is set exactly as
- * expected by the portRESTORE_CONTEXT() macro.
- */
-
- /* First on the stack is the return address - which in this case is the
- * start of the task. The offset is added to make the return address appear
- * as it would within an IRQ ISR.
- */
- *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE;
- pxTopOfStack--;
-
- *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */
- pxTopOfStack--;
- *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
- pxTopOfStack--;
- *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */
- pxTopOfStack--;
- *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */
- pxTopOfStack--;
- *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */
- pxTopOfStack--;
- *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */
- pxTopOfStack--;
- *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */
- pxTopOfStack--;
- *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */
- pxTopOfStack--;
- *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */
- pxTopOfStack--;
- *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */
- pxTopOfStack--;
- *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */
- pxTopOfStack--;
- *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */
- pxTopOfStack--;
- *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */
- pxTopOfStack--;
- *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */
- pxTopOfStack--;
-
- /* When the task starts is will expect to find the function parameter in
- * R0.
- */
- *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
- pxTopOfStack--;
-
- /* The last thing onto the stack is the status register, which is set for
- * system mode, with interrupts enabled.
- */
- *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;
-
-#ifdef THUMB_INTERWORK
- {
- /* We want the task to start in thumb mode. */
- *pxTopOfStack |= portTHUMB_MODE_BIT;
- }
-#endif
-
- pxTopOfStack--;
-
- /* Some optimisation levels use the stack differently to others. This
- * means the interrupt flags cannot always be stored on the stack and will
- * instead be stored in a variable, which is then saved as part of the
- * tasks context.
- */
- *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
-
- return pxTopOfStack;
-}
-
-portBASE_TYPE
-xPortStartScheduler( void )
-{
- /* Start the timer that generates the tick ISR. Interrupts are disabled
- * here already.
- */
- prvSetupTimerInterrupt( );
-
- /* Start the first task. */
- vPortISRStartFirstTask( );
-
- /* Should not get here! */
- return 0;
-}
-
-void
-vPortEndScheduler( void )
-{
-}
-
-/*
- * Setup the timer 0 to generate the tick interrupts at the required frequency.
- */
-static void
-prvSetupTimerInterrupt( void )
-{
- /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends
- * on whether the preemptive or cooperative scheduler is being used.
- */
-#if configUSE_PREEMPTION == 0
- AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST,
- AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL,
- ( void ( * )( void ) )vNonPreemptiveTick );
-#else
- AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST,
- AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL,
- ( void ( * )( void ) )vPreemptiveTick );
-
-#endif
-
- /* Configure the PIT period. */
- AT91F_PITInit( AT91C_BASE_PITC, portTICK_RATE_MS * 1000U, configCPU_CLOCK_HZ / 1000000U );
- AT91F_PITEnableInt( AT91C_BASE_PITC );
- AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_SYS );
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/GCC/ARM7_AT91SAM7S/portISR.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/GCC/ARM7_AT91SAM7S/portISR.c
deleted file mode 100644
index a9649127..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/GCC/ARM7_AT91SAM7S/portISR.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * MODBUS Library: SAM7X Port
- * Copyright (c) 2007 Christian Walter
- * All rights reserved.
- *
- * $Id$
- */
-/*
- * FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry.
- *
- * This file is part of the FreeRTOS.org distribution.
- *
- * FreeRTOS.org is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * FreeRTOS.org is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with FreeRTOS.org; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * A special exception to the GPL can be applied should you wish to distribute
- * a combined work that includes FreeRTOS.org, without being obliged to provide
- * the source code for any proprietary components. See the licensing section
- * of http://www.FreeRTOS.org for full details of how and when the exception
- * can be applied.
- *
- ****************************************************************************
- * See http://www.FreeRTOS.org for documentation, latest information, license
- * and contact details. Please ensure to read the configuration and relevant
- * port sections of the online documentation.
- *
- * Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
- * with commercial development and support options.
- ***************************************************************************
- */
-
-/* ----------------------- System includes ----------------------------------*/
-#include
-
-/* ----------------------- FreeRTOS includes --------------------------------*/
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* ----------------------- Platform includes --------------------------------*/
-#include "AT91SAM7X256.h"
-#include "lib_AT91SAM7X256.h"
-
-/* ----------------------- Defines ------------------------------------------*/
-#define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 )
-#define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )
-#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )
-volatile unsigned portLONG ulCriticalNesting = 9999UL;
-
-/* ----------------------- Type definitions ---------------------------------*/
-
-/* ----------------------- Static variables ---------------------------------*/
-
-/* ----------------------- Function prototypes ------------------------------*/
-void vPortDisableInterruptsFromThumb( void ) __attribute__ ( ( naked ) );
-void vPortEnableInterruptsFromThumb( void ) __attribute__ ( ( naked ) );
-void vNonPreemptiveTick( void ) __attribute__ ( ( interrupt( "IRQ" ) ) );
-void vPreemptiveTick( void ) __attribute__ ( ( naked ) );
-void vPortYieldProcessor( void ) __attribute__ ( ( interrupt( "SWI" ), naked ) );
-
-void vPortISRStartFirstTask( void );
-
-/* ----------------------- Static functions ---------------------------------*/
-
-/* ----------------------- Start implementation -----------------------------*/
-
-void
-vPortISRStartFirstTask( void )
-{
- /* Simply start the scheduler. This is included here as it can only be
- * called from ARM mode.
- */
- portRESTORE_CONTEXT( );
-}
-
-/*
- * Called by portYIELD() or taskYIELD() to manually force a context switch.
- *
- * When a context switch is performed from the task level the saved task
- * context is made to look as if it occurred from within the tick ISR. This
- * way the same restore context function can be used when restoring the context
- * saved from the ISR or that saved from a call to vPortYieldProcessor.
- */
-void
-vPortYieldProcessor( void )
-{
- /* Within an IRQ ISR the link register has an offset from the true return
- * address, but an SWI ISR does not. Add the offset manually so the same
- * ISR return code can be used in both cases.
- */
- asm volatile ( "ADD LR, LR, #4" );
-
- /* Perform the context switch. First save the context of the current task. */
- portSAVE_CONTEXT( );
-
- /* Find the highest priority task that is ready to run. */
- vTaskSwitchContext( );
-
- /* Restore the context of the new task. */
- portRESTORE_CONTEXT( );
-}
-
-/*
- * The ISR used for the scheduler tick depends on whether the cooperative or
- * the preemptive scheduler is being used.
- */
-#if configUSE_PREEMPTION == 0
-
-
-
-void
-vNonPreemptiveTick( void )
-{
- unsigned portLONG ulDummy;
-
- /* Increment the tick count - which may wake some tasks but as the
- * preemptive scheduler is not being used any woken task is not given
- * processor time no matter what its priority.
- */
- vTaskIncrementTick( );
-
- /* Clear the PIT interrupt. */
- AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;
-}
-#else
-void
-vPreemptiveTick( void )
-{
- /* Save the context of the current task. */
- portSAVE_CONTEXT( );
-
- /* Increment the tick count - this may wake a task. */
- vTaskIncrementTick( );
-
- /* Find the highest priority task that is ready to run. */
- vTaskSwitchContext( );
-
- /* End the interrupt in the AIC. */
- AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;;
-
- portRESTORE_CONTEXT( );
-}
-#endif
-
-/*
- * The interrupt management utilities can only be called from ARM mode. When
- * THUMB_INTERWORK is defined the utilities are defined as functions here to
- * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
- * the utilities are defined as macros in portmacro.h - as per other ports.
- */
-void
-vPortDisableInterruptsFromThumb( void )
-{
- asm volatile ( "STMDB SP!, {R0}\n\t" /* Push R0. */
- "MRS R0, CPSR\n\t" /* Get CPSR. */
- "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
- "MSR CPSR, R0\n\t" /* Write back modified value. */
- "LDMIA SP!, {R0}\n\t" /* Pop R0. */
- "BX R14" ); /* Return back to thumb. */
-}
-
-void
-vPortEnableInterruptsFromThumb( void )
-{
- asm volatile ( "STMDB SP!, {R0}\n\t" /* Push R0. */
- "MRS R0, CPSR\n\t" /* Get CPSR. */
- "BIC R0, R0, #0xC0\n\t" /* Enable IRQ, FIQ. */
- "MSR CPSR, R0\n\t" /* Write back modified value. */
- "LDMIA SP!, {R0}\n\t" /* Pop R0. */
- "BX R14" ); /* Return back to thumb. */
-}
-
-/* The code generated by the GCC compiler uses the stack in different ways at
- * different optimisation levels. The interrupt flags can therefore not always
- * be saved to the stack. Instead the critical section nesting level is stored
- * in a variable, which is then saved as part of the stack context.
- */
-void
-vPortEnterCritical( void )
-{
- /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
- asm volatile ( "STMDB SP!, {R0}\n\t" /* Push R0. */
- "MRS R0, CPSR\n\t" /* Get CPSR. */
- "ORR R0, R0, #0xC0\n\t" /* Disable IRQ, FIQ. */
- "MSR CPSR, R0\n\t" /* Write back modified value. */
- "LDMIA SP!, {R0}" ); /* Pop R0. */
-
- /* Now interrupts are disabled ulCriticalNesting can be accessed
- * directly. Increment ulCriticalNesting to keep a count of how many times
- * portENTER_CRITICAL() has been called.
- */
- ulCriticalNesting++;
-}
-
-void
-vPortExitCritical( void )
-{
- if( ulCriticalNesting > portNO_CRITICAL_NESTING )
- {
- /* Decrement the nesting count as we are leaving a critical section. */
- ulCriticalNesting--;
-
- /* If the nesting level has reached zero then interrupts should be
- re-enabled. */
- if( ulCriticalNesting == portNO_CRITICAL_NESTING )
- {
- /* Enable interrupts as per portEXIT_CRITICAL(). */
- asm volatile ( "STMDB SP!, {R0}\n\t" /* Push R0. */
- "MRS R0, CPSR\n\t" /* Get CPSR. */
- "BIC R0, R0, #0xC0\n\t" /* Enable IRQ, FIQ. */
- "MSR CPSR, R0\n\t" /* Write back modified value. */
- "LDMIA SP!, {R0}" ); /* Pop R0. */
- }
- }
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/GCC/ARM7_AT91SAM7S/portmacro.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/GCC/ARM7_AT91SAM7S/portmacro.h
deleted file mode 100644
index 43593c56..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/GCC/ARM7_AT91SAM7S/portmacro.h
+++ /dev/null
@@ -1,230 +0,0 @@
-/*
- * MODBUS Library: SAM7X Port
- * Copyright (c) 2007 Christian Walter
- * All rights reserved.
- *
- * $Id$
- */
-/*
- * FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry.
- *
- * This file is part of the FreeRTOS.org distribution.
- *
- * FreeRTOS.org is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * FreeRTOS.org is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with FreeRTOS.org; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * A special exception to the GPL can be applied should you wish to distribute
- * a combined work that includes FreeRTOS.org, without being obliged to provide
- * the source code for any proprietary components. See the licensing section
- * of http://www.FreeRTOS.org for full details of how and when the exception
- * can be applied.
- *
- ****************************************************************************
- * See http://www.FreeRTOS.org for documentation, latest information, license
- * and contact details. Please ensure to read the configuration and relevant
- * port sections of the online documentation.
- *
- * Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
- * with commercial development and support options.
- ***************************************************************************
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/* ----------------------- Defines (Type definitions) -----------------------*/
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
-#define portSTACK_TYPE unsigned portLONG
-#define portBASE_TYPE portLONG
-
-#if( configUSE_16_BIT_TICKS == 1 )
-typedef unsigned portSHORT portTickType;
-#define portMAX_DELAY ( portTickType ) 0xffff
-#else
-typedef unsigned portLONG portTickType;
-#define portMAX_DELAY ( portTickType ) 0xffffffff
-#endif
-
-/* ----------------------- Defines (Architecture specific) ------------------*/
-
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT 4
-#define portNOP() asm volatile ( "NOP" );
-
-/*
- * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
- * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
- * are included here for efficiency. An attempt to call one from
- * THUMB mode code will result in a compile time error.
- */
-#define portRESTORE_CONTEXT() do { \
- extern volatile void * volatile pxCurrentTCB; \
- extern volatile unsigned portLONG ulCriticalNesting; \
- \
- /* Set the LR to the task stack. */ \
- asm volatile ( \
- "LDR R0, =pxCurrentTCB\n\t" \
- "LDR R0, [R0]\n\t" \
- "LDR LR, [R0]\n\t" \
- \
- /* The critical nesting depth is the first item on the stack. */ \
- /* Load it into the ulCriticalNesting variable. */ \
- "LDR R0, =ulCriticalNesting\n\t" \
- "LDMFD LR!, {R1}\n\t" \
- "STR R1, [R0]\n\t" \
- \
- /* Get the SPSR from the stack. */ \
- "LDMFD LR!, {R0}\n\t" \
- "MSR SPSR, R0\n\t" \
- \
- /* Restore all system mode registers for the task. */ \
- "LDMFD LR, {R0-R14}^\n\t" \
- "NOP\n\t" \
- \
- /* Restore the return address. */ \
- "LDR LR, [LR, #+60]\n\t" \
- \
- /* And return - correcting the offset in the LR to obtain the */ \
- /* correct address. */ \
- "SUBS PC, LR, #4\n\t" \
- ); \
- ( void ) ulCriticalNesting; \
- ( void ) pxCurrentTCB; \
-} while( 0 )
-
-#define portSAVE_CONTEXT() do { \
- extern volatile void * volatile pxCurrentTCB; \
- extern volatile unsigned portLONG ulCriticalNesting; \
- \
- /* Push R0 as we are going to use the register. */ \
- asm volatile ( \
- "STMDB SP!, {R0}\n\t" \
- \
- /* Set R0 to point to the task stack pointer. */ \
- "STMDB SP,{SP}^\n\t" \
- "NOP\n\t" \
- "SUB SP, SP, #4\n\t" \
- "LDMIA SP!,{R0}\n\t" \
- \
- /* Push the return address onto the stack. */ \
- "STMDB R0!, {LR}\n\t" \
- \
- /* Now we have saved LR we can use it instead of R0. */ \
- "MOV LR, R0\n\t" \
- \
- /* Pop R0 so we can save it onto the system mode stack. */ \
- "LDMIA SP!, {R0}\n\t" \
- \
- /* Push all the system mode registers onto the task stack. */ \
- "STMDB LR,{R0-LR}^\n\t" \
- "NOP\n\t" \
- "SUB LR, LR, #60\n\t" \
- \
- /* Push the SPSR onto the task stack. */ \
- "MRS R0, SPSR\n\t" \
- "STMDB LR!, {R0}\n\t" \
- \
- "LDR R0, =ulCriticalNesting\n\t" \
- "LDR R0, [R0]\n\t" \
- "STMDB LR!, {R0}\n\t" \
- \
- /* Store the new top of stack for the task. */ \
- "LDR R0, =pxCurrentTCB\n\t" \
- "LDR R0, [R0]\n\t" \
- "STR LR, [R0]\n\t" \
- ); \
- ( void ) ulCriticalNesting; \
- ( void ) pxCurrentTCB; \
-} while( 0 )
-
-#define portENTER_SWITCHING_ISR() do { \
- /* Save the context of the interrupted task. */ \
- portSAVE_CONTEXT(); \
- \
- /* We don't know the stack requirements for the ISR, so the frame */ \
- /* pointer will be set to the top of the task stack, and the stack*/ \
- /* pointer left where it is. The IRQ stack will get used for any */ \
- /* functions calls made by this ISR. */ \
- asm volatile ( "SUB R11, LR, #4" ); \
- {
-
-#define portEXIT_SWITCHING_ISR( SwitchRequired ) \
- /* If a switch is required then we just need to call */ \
- /* vTaskSwitchContext() as the context has already been */ \
- /* saved. */ \
- if( SwitchRequired ) \
- { \
- vTaskSwitchContext(); \
- } \
- } \
- /* Restore the context of which ever task is now the highest */ \
- /* priority that is ready to run. */ \
- portRESTORE_CONTEXT(); \
-} while( 0 )
-
-#define portYIELD() asm volatile ( "SWI" );
-
-/*
- * The interrupt management utilities can only be called from ARM mode. When
- * THUMB_INTERWORK is defined the utilities are defined as functions in
- * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not
- * defined then the utilities are defined as macros here - as per other ports.
- */
-#ifdef THUMB_INTERWORK
-
-extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ( ( naked ) );
-extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ( ( naked ) );
-
-#define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
-#define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
-
-#else
-
-#define portDISABLE_INTERRUPTS() do { \
- asm volatile ( \
- "STMDB SP!, {R0}\n\t" /* Push R0. */ \
- "MRS R0, CPSR\n\t" /* Get CPSR. */ \
- "ORR R0, R0, #0xC0\n\t" /* Disable IRQ, FIQ. */ \
- "MSR CPSR, R0\n\t" /* Write back modified value. */ \
- "LDMIA SP!, {R0}" ); /* Pop R0. */ \
-} while( 0 )
-
-#define portENABLE_INTERRUPTS() do { \
- asm volatile ( \
- "STMDB SP!, {R0}\n\t" /* Push R0. */ \
- "MRS R0, CPSR\n\t" /* Get CPSR. */ \
- "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \
- "MSR CPSR, R0\n\t" /* Write back modified value. */ \
- "LDMIA SP!, {R0}" ); /* Pop R0. */ \
-} while( 0 )
-#endif
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portENTER_CRITICAL() vPortEnterCritical();
-#define portEXIT_CRITICAL() vPortExitCritical();
-
-/* ----------------------- Defines (Other) ----------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#endif
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/MemMang/heap_1.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/MemMang/heap_1.c
deleted file mode 100644
index 57a7e4e0..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/MemMang/heap_1.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry.
-
- This file is part of the FreeRTOS.org distribution.
-
- FreeRTOS.org is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- FreeRTOS.org is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with FreeRTOS.org; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes FreeRTOS.org, without being obliged to provide
- the source code for any proprietary components. See the licensing section
- of http://www.FreeRTOS.org for full details of how and when the exception
- can be applied.
-
- ***************************************************************************
- See http://www.FreeRTOS.org for documentation, latest information, license
- and contact details. Please ensure to read the configuration and relevant
- port sections of the online documentation.
-
- Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
- with commercial development and support options.
- ***************************************************************************
-*/
-
-/*
-
-Changes between V2.5.1 and V2.5.1
-
- + The memory pool has been defined within a struct to ensure correct memory
- alignment on 32bit systems.
-
-Changes between V2.6.1 and V3.0.0
-
- + An overflow check has been added to ensure the next free byte variable
- does not wrap around.
-*/
-
-
-/*
- * The simplest possible implementation of pvPortMalloc(). Note that this
- * implementation does NOT allow allocated memory to be freed again.
- *
- * See heap_2.c and heap_3.c for alternative implementations, and the memory
- * management pages of http://www.FreeRTOS.org for more information.
- */
-#include
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Setup the correct byte alignment mask for the defined byte alignment. */
-
-#if portBYTE_ALIGNMENT == 8
- #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0007 )
-#endif
-
-#if portBYTE_ALIGNMENT == 4
- #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 )
-#endif
-
-#if portBYTE_ALIGNMENT == 2
- #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 )
-#endif
-
-#if portBYTE_ALIGNMENT == 1
- #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 )
-#endif
-
-#ifndef heapBYTE_ALIGNMENT_MASK
- #error "Invalid portBYTE_ALIGNMENT definition"
-#endif
-
-/* Allocate the memory for the heap. The struct is used to force byte
-alignment without using any non-portable code. */
-static struct xRTOS_HEAP
-{
- unsigned portLONG ulDummy;
- unsigned portCHAR ucHeap[ configTOTAL_HEAP_SIZE ];
-} xHeap;
-
-static size_t xNextFreeByte = ( size_t ) 0;
-/*-----------------------------------------------------------*/
-
-void *pvPortMalloc( size_t xWantedSize )
-{
-void *pvReturn = NULL;
-
- /* Ensure that blocks are always aligned to the required number of bytes. */
- #if portBYTE_ALIGNMENT != 1
- if( xWantedSize & heapBYTE_ALIGNMENT_MASK )
- {
- /* Byte alignment required. */
- xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) );
- }
- #endif
-
- vTaskSuspendAll();
- {
- /* Check there is enough room left for the allocation. */
- if( ( ( xNextFreeByte + xWantedSize ) < configTOTAL_HEAP_SIZE ) &&
- ( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) )/* Check for overflow. */
- {
- /* Return the next free byte then increment the index past this
- block. */
- pvReturn = &( xHeap.ucHeap[ xNextFreeByte ] );
- xNextFreeByte += xWantedSize;
- }
- }
- xTaskResumeAll();
-
- return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void *pv )
-{
- /* Memory cannot be freed using this scheme. See heap_2.c and heap_3.c
- for alternative implementations, and the memory management pages of
- http://www.FreeRTOS.org for more information. */
- ( void ) pv;
-}
-/*-----------------------------------------------------------*/
-
-void vPortInitialiseBlocks( void )
-{
- /* Only required when static memory is not cleared. */
- xNextFreeByte = ( size_t ) 0;
-}
-
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/MemMang/heap_2.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/MemMang/heap_2.c
deleted file mode 100644
index f733e7dd..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/MemMang/heap_2.c
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry.
-
- This file is part of the FreeRTOS.org distribution.
-
- FreeRTOS.org is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- FreeRTOS.org is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with FreeRTOS.org; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes FreeRTOS.org, without being obliged to provide
- the source code for any proprietary components. See the licensing section
- of http://www.FreeRTOS.org for full details of how and when the exception
- can be applied.
-
- ***************************************************************************
- See http://www.FreeRTOS.org for documentation, latest information, license
- and contact details. Please ensure to read the configuration and relevant
- port sections of the online documentation.
-
- Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
- with commercial development and support options.
- ***************************************************************************
-*/
-
-/*
- * A sample implementation of pvPortMalloc() and vPortFree() that permits
- * allocated blocks to be freed, but does not combine adjacent free blocks
- * into a single larger block.
- *
- * See heap_1.c and heap_3.c for alternative implementations, and the memory
- * management pages of http://www.FreeRTOS.org for more information.
- */
-#include
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Setup the correct byte alignment mask for the defined byte alignment. */
-
-#if portBYTE_ALIGNMENT == 8
- #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0007 )
-#endif
-
-#if portBYTE_ALIGNMENT == 4
- #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 )
-#endif
-
-#if portBYTE_ALIGNMENT == 2
- #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 )
-#endif
-
-#if portBYTE_ALIGNMENT == 1
- #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 )
-#endif
-
-#ifndef heapBYTE_ALIGNMENT_MASK
- #error "Invalid portBYTE_ALIGNMENT definition"
-#endif
-
-/* Allocate the memory for the heap. The struct is used to force byte
-alignment without using any non-portable code. */
-static struct xRTOS_HEAP
-{
- unsigned portLONG ulDummy;
- unsigned portCHAR ucHeap[ configTOTAL_HEAP_SIZE ];
-} xHeap;
-
-/* Define the linked list structure. This is used to link free blocks in order
-of their size. */
-typedef struct A_BLOCK_LINK
-{
- struct A_BLOCK_LINK *pxNextFreeBlock; /*<< The next free block in the list. */
- size_t xBlockSize; /*<< The size of the free block. */
-} xBlockLink;
-
-
-static const unsigned portSHORT heapSTRUCT_SIZE = ( sizeof( xBlockLink ) + ( sizeof( xBlockLink ) % portBYTE_ALIGNMENT ) );
-#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) )
-
-/* Create a couple of list links to mark the start and end of the list. */
-static xBlockLink xStart, xEnd;
-
-/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */
-
-/*
- * Insert a block into the list of free blocks - which is ordered by size of
- * the block. Small blocks at the start of the list and large blocks at the end
- * of the list.
- */
-#define prvInsertBlockIntoFreeList( pxBlockToInsert ) \
-{ \
-xBlockLink *pxIterator; \
-size_t xBlockSize; \
- \
- xBlockSize = pxBlockToInsert->xBlockSize; \
- \
- /* Iterate through the list until a block is found that has a larger size */ \
- /* than the block we are inserting. */ \
- for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock ) \
- { \
- /* There is nothing to do here - just iterate to the correct position. */ \
- } \
- \
- /* Update the list to include the block being inserted in the correct */ \
- /* position. */ \
- pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; \
- pxIterator->pxNextFreeBlock = pxBlockToInsert; \
-}
-/*-----------------------------------------------------------*/
-
-#define prvHeapInit() \
-{ \
-xBlockLink *pxFirstFreeBlock; \
- \
- /* xStart is used to hold a pointer to the first item in the list of free */ \
- /* blocks. The void cast is used to prevent compiler warnings. */ \
- xStart.pxNextFreeBlock = ( void * ) xHeap.ucHeap; \
- xStart.xBlockSize = ( size_t ) 0; \
- \
- /* xEnd is used to mark the end of the list of free blocks. */ \
- xEnd.xBlockSize = configTOTAL_HEAP_SIZE; \
- xEnd.pxNextFreeBlock = NULL; \
- \
- /* To start with there is a single free block that is sized to take up the \
- entire heap space. */ \
- pxFirstFreeBlock = ( void * ) xHeap.ucHeap; \
- pxFirstFreeBlock->xBlockSize = configTOTAL_HEAP_SIZE; \
- pxFirstFreeBlock->pxNextFreeBlock = &xEnd; \
-}
-/*-----------------------------------------------------------*/
-
-void *pvPortMalloc( size_t xWantedSize )
-{
-xBlockLink *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
-static portBASE_TYPE xHeapHasBeenInitialised = pdFALSE;
-void *pvReturn = NULL;
-
- vTaskSuspendAll();
- {
- /* If this is the first call to malloc then the heap will require
- initialisation to setup the list of free blocks. */
- if( xHeapHasBeenInitialised == pdFALSE )
- {
- prvHeapInit();
- xHeapHasBeenInitialised = pdTRUE;
- }
-
- /* The wanted size is increased so it can contain a xBlockLink
- structure in addition to the requested amount of bytes. */
- if( xWantedSize > 0 )
- {
- xWantedSize += heapSTRUCT_SIZE;
-
- /* Ensure that blocks are always aligned to the required number of bytes. */
- if( xWantedSize & heapBYTE_ALIGNMENT_MASK )
- {
- /* Byte alignment required. */
- xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) );
- }
- }
-
- if( ( xWantedSize > 0 ) && ( xWantedSize < configTOTAL_HEAP_SIZE ) )
- {
- /* Blocks are stored in byte order - traverse the list from the start
- (smallest) block until one of adequate size is found. */
- pxPreviousBlock = &xStart;
- pxBlock = xStart.pxNextFreeBlock;
- while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock ) )
- {
- pxPreviousBlock = pxBlock;
- pxBlock = pxBlock->pxNextFreeBlock;
- }
-
- /* If we found the end marker then a block of adequate size was not found. */
- if( pxBlock != &xEnd )
- {
- /* Return the memory space - jumping over the xBlockLink structure
- at its start. */
- pvReturn = ( void * ) ( ( ( unsigned portCHAR * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE );
-
- /* This block is being returned for use so must be taken our of the
- list of free blocks. */
- pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
-
- /* If the block is larger than required it can be split into two. */
- if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
- {
- /* This block is to be split into two. Create a new block
- following the number of bytes requested. The void cast is
- used to prevent byte alignment warnings from the compiler. */
- pxNewBlockLink = ( void * ) ( ( ( unsigned portCHAR * ) pxBlock ) + xWantedSize );
-
- /* Calculate the sizes of two blocks split from the single
- block. */
- pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
- pxBlock->xBlockSize = xWantedSize;
-
- /* Insert the new block into the list of free blocks. */
- prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
- }
- }
- }
- }
- xTaskResumeAll();
-
- return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void *pv )
-{
-unsigned portCHAR *puc = ( unsigned portCHAR * ) pv;
-xBlockLink *pxLink;
-
- if( pv )
- {
- /* The memory being freed will have an xBlockLink structure immediately
- before it. */
- puc -= heapSTRUCT_SIZE;
-
- /* This casting is to keep the compiler from issuing warnings. */
- pxLink = ( void * ) puc;
-
- vTaskSuspendAll();
- {
- /* Add this block to the list of free blocks. */
- prvInsertBlockIntoFreeList( ( ( xBlockLink * ) pxLink ) );
- }
- xTaskResumeAll();
- }
-}
-/*-----------------------------------------------------------*/
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/MemMang/heap_3.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/MemMang/heap_3.c
deleted file mode 100644
index c32f883b..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/MemMang/heap_3.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry.
-
- This file is part of the FreeRTOS.org distribution.
-
- FreeRTOS.org is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- FreeRTOS.org is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with FreeRTOS.org; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes FreeRTOS.org, without being obliged to provide
- the source code for any proprietary components. See the licensing section
- of http://www.FreeRTOS.org for full details of how and when the exception
- can be applied.
-
- ***************************************************************************
- See http://www.FreeRTOS.org for documentation, latest information, license
- and contact details. Please ensure to read the configuration and relevant
- port sections of the online documentation.
-
- Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
- with commercial development and support options.
- ***************************************************************************
-*/
-
-
-/*
- * Implementation of pvPortMalloc() and vPortFree() that relies on the
- * compilers own malloc() and free() implementations.
- *
- * This file can only be used if the linker is configured to to generate
- * a heap memory area.
- *
- * See heap_2.c and heap_1.c for alternative implementations, and the memory
- * management pages of http://www.FreeRTOS.org for more information.
- */
-
-#include
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-/*-----------------------------------------------------------*/
-
-void *pvPortMalloc( size_t xWantedSize )
-{
-void *pvReturn;
-
- vTaskSuspendAll();
- {
- pvReturn = malloc( xWantedSize );
- }
- xTaskResumeAll();
-
- return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void *pv )
-{
- if( pv )
- {
- vTaskSuspendAll();
- {
- free( pv );
- }
- xTaskResumeAll();
- }
-}
-
-
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/queue.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/queue.c
deleted file mode 100644
index ab0c13ae..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/queue.c
+++ /dev/null
@@ -1,930 +0,0 @@
-/*
- FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry.
-
- This file is part of the FreeRTOS.org distribution.
-
- FreeRTOS.org is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- FreeRTOS.org is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with FreeRTOS.org; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes FreeRTOS.org, without being obliged to provide
- the source code for any proprietary components. See the licensing section
- of http://www.FreeRTOS.org for full details of how and when the exception
- can be applied.
-
- ***************************************************************************
- See http://www.FreeRTOS.org for documentation, latest information, license
- and contact details. Please ensure to read the configuration and relevant
- port sections of the online documentation.
-
- Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
- with commercial development and support options.
- ***************************************************************************
-*/
-
-/*
-Changes from V1.01
-
- + More use of 8bit data types.
- + Function name prefixes changed where the data type returned has changed.
-
-Changed from V2.0.0
-
- + Added the queue locking mechanism and make more use of the scheduler
- suspension feature to minimise the time interrupts have to be disabled
- when accessing a queue.
-
-Changed from V2.2.0
-
- + Explicit use of 'signed' qualifier on portCHAR types added.
-
-Changes from V3.0.0
-
- + API changes as described on the FreeRTOS.org WEB site.
-
-Changes from V3.2.3
-
- + Added the queue functions that can be used from co-routines.
-
-Changes from V4.0.5
-
- + Added a loop within xQueueSend() and xQueueReceive() to prevent the
- functions exiting when a block time remains and the function has
- not completed.
-
-Changes from V4.1.2:
-
- + BUG FIX: Removed the call to prvIsQueueEmpty from within xQueueCRReceive
- as it exited with interrupts enabled. Thanks Paul Katz.
-
-Changes from V4.1.3:
-
- + Modified xQueueSend() and xQueueReceive() to handle the (very unlikely)
- case whereby a task unblocking due to a temporal event can remove/send an
- item from/to a queue when a higher priority task is still blocked on the
- queue. This modification is a result of the SafeRTOS testing.
-*/
-
-#include
-#include
-#include "FreeRTOS.h"
-#include "task.h"
-#include "croutine.h"
-
-/*-----------------------------------------------------------
- * PUBLIC LIST API documented in list.h
- *----------------------------------------------------------*/
-
-/* Constants used with the cRxLock and cTxLock structure members. */
-#define queueUNLOCKED ( ( signed portBASE_TYPE ) -1 )
-#define queueERRONEOUS_UNBLOCK ( -1 )
-
-/*
- * Definition of the queue used by the scheduler.
- * Items are queued by copy, not reference.
- */
-typedef struct QueueDefinition
-{
- signed portCHAR *pcHead; /*< Points to the beginning of the queue storage area. */
- signed portCHAR *pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
-
- signed portCHAR *pcWriteTo; /*< Points to the free next place in the storage area. */
- signed portCHAR *pcReadFrom; /*< Points to the last place that a queued item was read from. */
-
- xList xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */
- xList xTasksWaitingToReceive; /*< List of tasks that are blocked waiting to read from this queue. Stored in priority order. */
-
- unsigned portBASE_TYPE uxMessagesWaiting;/*< The number of items currently in the queue. */
- unsigned portBASE_TYPE uxLength; /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */
- unsigned portBASE_TYPE uxItemSize; /*< The size of each items that the queue will hold. */
-
- signed portBASE_TYPE xRxLock; /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */
- signed portBASE_TYPE xTxLock; /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */
-} xQUEUE;
-/*-----------------------------------------------------------*/
-
-/*
- * Inside this file xQueueHandle is a pointer to a xQUEUE structure.
- * To keep the definition private the API header file defines it as a
- * pointer to void.
- */
-typedef xQUEUE * xQueueHandle;
-
-/*
- * Prototypes for public functions are included here so we don't have to
- * include the API header file (as it defines xQueueHandle differently). These
- * functions are documented in the API header file.
- */
-xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize );
-signed portBASE_TYPE xQueueSend( xQueueHandle xQueue, const void * pvItemToQueue, portTickType xTicksToWait );
-unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle pxQueue );
-void vQueueDelete( xQueueHandle xQueue );
-signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken );
-signed portBASE_TYPE xQueueReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait );
-signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken );
-
-#if configUSE_CO_ROUTINES == 1
- signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken );
- signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken );
- signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait );
- signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait );
-#endif
-
-/*
- * Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not
- * prevent an ISR from adding or removing items to the queue, but does prevent
- * an ISR from removing tasks from the queue event lists. If an ISR finds a
- * queue is locked it will instead increment the appropriate queue lock count
- * to indicate that a task may require unblocking. When the queue in unlocked
- * these lock counts are inspected, and the appropriate action taken.
- */
-static void prvUnlockQueue( xQueueHandle pxQueue );
-
-/*
- * Uses a critical section to determine if there is any data in a queue.
- *
- * @return pdTRUE if the queue contains no items, otherwise pdFALSE.
- */
-static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue );
-
-/*
- * Uses a critical section to determine if there is any space in a queue.
- *
- * @return pdTRUE if there is no space, otherwise pdFALSE;
- */
-static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue );
-
-/*
- * Macro that copies an item into the queue. This is done by copying the item
- * byte for byte, not by reference. Updates the queue state to ensure it's
- * integrity after the copy.
- */
-#define prvCopyQueueData( pxQueue, pvItemToQueue ) \
-{ \
- memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( unsigned ) pxQueue->uxItemSize ); \
- ++( pxQueue->uxMessagesWaiting ); \
- pxQueue->pcWriteTo += pxQueue->uxItemSize; \
- if( pxQueue->pcWriteTo >= pxQueue->pcTail ) \
- { \
- pxQueue->pcWriteTo = pxQueue->pcHead; \
- } \
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Macro to mark a queue as locked. Locking a queue prevents an ISR from
- * accessing the queue event lists.
- */
-#define prvLockQueue( pxQueue ) \
-{ \
- taskENTER_CRITICAL(); \
- ++( pxQueue->xRxLock ); \
- ++( pxQueue->xTxLock ); \
- taskEXIT_CRITICAL(); \
-}
-/*-----------------------------------------------------------*/
-
-
-/*-----------------------------------------------------------
- * PUBLIC QUEUE MANAGEMENT API documented in queue.h
- *----------------------------------------------------------*/
-
-xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize )
-{
-xQUEUE *pxNewQueue;
-size_t xQueueSizeInBytes;
-
- /* Allocate the new queue structure. */
- if( uxQueueLength > ( unsigned portBASE_TYPE ) 0 )
- {
- pxNewQueue = ( xQUEUE * ) pvPortMalloc( sizeof( xQUEUE ) );
- if( pxNewQueue != NULL )
- {
- /* Create the list of pointers to queue items. The queue is one byte
- longer than asked for to make wrap checking easier/faster. */
- xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ) + ( size_t ) 1;
-
- pxNewQueue->pcHead = ( signed portCHAR * ) pvPortMalloc( xQueueSizeInBytes );
- if( pxNewQueue->pcHead != NULL )
- {
- /* Initialise the queue members as described above where the
- queue type is defined. */
- pxNewQueue->pcTail = pxNewQueue->pcHead + ( uxQueueLength * uxItemSize );
- pxNewQueue->uxMessagesWaiting = 0;
- pxNewQueue->pcWriteTo = pxNewQueue->pcHead;
- pxNewQueue->pcReadFrom = pxNewQueue->pcHead + ( ( uxQueueLength - 1 ) * uxItemSize );
- pxNewQueue->uxLength = uxQueueLength;
- pxNewQueue->uxItemSize = uxItemSize;
- pxNewQueue->xRxLock = queueUNLOCKED;
- pxNewQueue->xTxLock = queueUNLOCKED;
-
- /* Likewise ensure the event queues start with the correct state. */
- vListInitialise( &( pxNewQueue->xTasksWaitingToSend ) );
- vListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) );
-
- return pxNewQueue;
- }
- else
- {
- vPortFree( pxNewQueue );
- }
- }
- }
-
- /* Will only reach here if we could not allocate enough memory or no memory
- was required. */
- return NULL;
-}
-/*-----------------------------------------------------------*/
-
-signed portBASE_TYPE xQueueSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait )
-{
-signed portBASE_TYPE xReturn = pdPASS;
-xTimeOutType xTimeOut;
-
- /* Make sure other tasks do not access the queue. */
- vTaskSuspendAll();
-
- /* Capture the current time status for future reference. */
- vTaskSetTimeOutState( &xTimeOut );
-
- /* It is important that this is the only thread/ISR that modifies the
- ready or delayed lists until xTaskResumeAll() is called. Places where
- the ready/delayed lists are modified include:
-
- + vTaskDelay() - Nothing can call vTaskDelay as the scheduler is
- suspended, vTaskDelay() cannot be called from an ISR.
- + vTaskPrioritySet() - Has a critical section around the access.
- + vTaskSwitchContext() - This will not get executed while the scheduler
- is suspended.
- + prvCheckDelayedTasks() - This will not get executed while the
- scheduler is suspended.
- + xTaskCreate() - Has a critical section around the access.
- + vTaskResume() - Has a critical section around the access.
- + xTaskResumeAll() - Has a critical section around the access.
- + xTaskRemoveFromEventList - Checks to see if the scheduler is
- suspended. If so then the TCB being removed from the event is
- removed from the event and added to the xPendingReadyList.
- */
-
- /* Make sure interrupts do not access the queue event list. */
- prvLockQueue( pxQueue );
-
- /* It is important that interrupts to not access the event list of the
- queue being modified here. Places where the event list is modified
- include:
-
- + xQueueSendFromISR(). This checks the lock on the queue to see if
- it has access. If the queue is locked then the Tx lock count is
- incremented to signify that a task waiting for data can be made ready
- once the queue lock is removed. If the queue is not locked then
- a task can be moved from the event list, but will not be removed
- from the delayed list or placed in the ready list until the scheduler
- is unlocked.
-
- + xQueueReceiveFromISR(). As per xQueueSendFromISR().
- */
-
- /* If the queue is already full we may have to block. */
- do
- {
- if( prvIsQueueFull( pxQueue ) )
- {
- /* The queue is full - do we want to block or just leave without
- posting? */
- if( xTicksToWait > ( portTickType ) 0 )
- {
- /* We are going to place ourselves on the xTasksWaitingToSend event
- list, and will get woken should the delay expire, or space become
- available on the queue.
-
- As detailed above we do not require mutual exclusion on the event
- list as nothing else can modify it or the ready lists while we
- have the scheduler suspended and queue locked.
-
- It is possible that an ISR has removed data from the queue since we
- checked if any was available. If this is the case then the data
- will have been copied from the queue, and the queue variables
- updated, but the event list will not yet have been checked to see if
- anything is waiting as the queue is locked. */
- vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
-
- /* Force a context switch now as we are blocked. We can do
- this from within a critical section as the task we are
- switching to has its own context. When we return here (i.e. we
- unblock) we will leave the critical section as normal.
-
- It is possible that an ISR has caused an event on an unrelated and
- unlocked queue. If this was the case then the event list for that
- queue will have been updated but the ready lists left unchanged -
- instead the readied task will have been added to the pending ready
- list. */
- taskENTER_CRITICAL();
- {
- /* We can safely unlock the queue and scheduler here as
- interrupts are disabled. We must not yield with anything
- locked, but we can yield from within a critical section.
-
- Tasks that have been placed on the pending ready list cannot
- be tasks that are waiting for events on this queue. See
- in comment xTaskRemoveFromEventList(). */
- prvUnlockQueue( pxQueue );
-
- /* Resuming the scheduler may cause a yield. If so then there
- is no point yielding again here. */
- if( !xTaskResumeAll() )
- {
- taskYIELD();
- }
-
- /* We want to check to see if the queue is still full
- before leaving the critical section. This is to prevent
- this task placing an item into the queue due to an
- interrupt making space on the queue between critical
- sections (when there might be a higher priority task
- blocked on the queue that cannot run yet because the
- scheduler gets suspended). */
- if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
- {
- /* We unblocked but there is no space in the queue,
- we probably timed out. */
- xReturn = errQUEUE_FULL;
- }
-
- /* Before leaving the critical section we have to ensure
- exclusive access again. */
- vTaskSuspendAll();
- prvLockQueue( pxQueue );
- }
- taskEXIT_CRITICAL();
- }
- }
-
- /* If xReturn is errQUEUE_FULL then we unblocked when the queue
- was still full. Don't check it again now as it is possible that
- an interrupt has removed an item from the queue since we left the
- critical section and we don't want to write to the queue in case
- there is a task of higher priority blocked waiting for space to
- be available on the queue. If this is the case the higher priority
- task will execute when the scheduler is unsupended. */
- if( xReturn != errQUEUE_FULL )
- {
- /* When we are here it is possible that we unblocked as space became
- available on the queue. It is also possible that an ISR posted to the
- queue since we left the critical section, so it may be that again there
- is no space. This would only happen if a task and ISR post onto the
- same queue. */
- taskENTER_CRITICAL();
- {
- if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
- {
- /* There is room in the queue, copy the data into the queue. */
- prvCopyQueueData( pxQueue, pvItemToQueue );
- xReturn = pdPASS;
-
- /* Update the TxLock count so prvUnlockQueue knows to check for
- tasks waiting for data to become available in the queue. */
- ++( pxQueue->xTxLock );
- }
- else
- {
- xReturn = errQUEUE_FULL;
- }
- }
- taskEXIT_CRITICAL();
- }
-
- if( xReturn == errQUEUE_FULL )
- {
- if( xTicksToWait > 0 )
- {
- if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
- {
- xReturn = queueERRONEOUS_UNBLOCK;
- }
- }
- }
- }
- while( xReturn == queueERRONEOUS_UNBLOCK );
-
- prvUnlockQueue( pxQueue );
- xTaskResumeAll();
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken )
-{
- /* Similar to xQueueSend, except we don't block if there is no room in the
- queue. Also we don't directly wake a task that was blocked on a queue
- read, instead we return a flag to say whether a context switch is required
- or not (i.e. has a task with a higher priority than us been woken by this
- post). */
- if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
- {
- prvCopyQueueData( pxQueue, pvItemToQueue );
-
- /* If the queue is locked we do not alter the event list. This will
- be done when the queue is unlocked later. */
- if( pxQueue->xTxLock == queueUNLOCKED )
- {
- /* We only want to wake one task per ISR, so check that a task has
- not already been woken. */
- if( !xTaskPreviouslyWoken )
- {
- if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) )
- {
- if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
- {
- /* The task waiting has a higher priority so record that a
- context switch is required. */
- return pdTRUE;
- }
- }
- }
- }
- else
- {
- /* Increment the lock count so the task that unlocks the queue
- knows that data was posted while it was locked. */
- ++( pxQueue->xTxLock );
- }
- }
-
- return xTaskPreviouslyWoken;
-}
-/*-----------------------------------------------------------*/
-
-signed portBASE_TYPE xQueueReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait )
-{
-signed portBASE_TYPE xReturn = pdTRUE;
-xTimeOutType xTimeOut;
-
- /* This function is very similar to xQueueSend(). See comments within
- xQueueSend() for a more detailed explanation.
-
- Make sure other tasks do not access the queue. */
- vTaskSuspendAll();
-
- /* Capture the current time status for future reference. */
- vTaskSetTimeOutState( &xTimeOut );
-
- /* Make sure interrupts do not access the queue. */
- prvLockQueue( pxQueue );
-
- do
- {
- /* If there are no messages in the queue we may have to block. */
- if( prvIsQueueEmpty( pxQueue ) )
- {
- /* There are no messages in the queue, do we want to block or just
- leave with nothing? */
- if( xTicksToWait > ( portTickType ) 0 )
- {
- vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
- taskENTER_CRITICAL();
- {
- prvUnlockQueue( pxQueue );
- if( !xTaskResumeAll() )
- {
- taskYIELD();
- }
-
- if( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 )
- {
- /* We unblocked but the queue is empty. We probably
- timed out. */
- xReturn = errQUEUE_EMPTY;
- }
-
- vTaskSuspendAll();
- prvLockQueue( pxQueue );
- }
- taskEXIT_CRITICAL();
- }
- }
-
- if( xReturn != errQUEUE_EMPTY )
- {
- taskENTER_CRITICAL();
- {
- if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 )
- {
- pxQueue->pcReadFrom += pxQueue->uxItemSize;
- if( pxQueue->pcReadFrom >= pxQueue->pcTail )
- {
- pxQueue->pcReadFrom = pxQueue->pcHead;
- }
- --( pxQueue->uxMessagesWaiting );
- memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
-
- /* Increment the lock count so prvUnlockQueue knows to check for
- tasks waiting for space to become available on the queue. */
- ++( pxQueue->xRxLock );
- xReturn = pdPASS;
- }
- else
- {
- xReturn = errQUEUE_EMPTY;
- }
- }
- taskEXIT_CRITICAL();
- }
-
- if( xReturn == errQUEUE_EMPTY )
- {
- if( xTicksToWait > 0 )
- {
- if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
- {
- xReturn = queueERRONEOUS_UNBLOCK;
- }
- }
- }
- } while( xReturn == queueERRONEOUS_UNBLOCK );
-
- /* We no longer require exclusive access to the queue. */
- prvUnlockQueue( pxQueue );
- xTaskResumeAll();
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken )
-{
-signed portBASE_TYPE xReturn;
-
- /* We cannot block from an ISR, so check there is data available. */
- if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 )
- {
- /* Copy the data from the queue. */
- pxQueue->pcReadFrom += pxQueue->uxItemSize;
- if( pxQueue->pcReadFrom >= pxQueue->pcTail )
- {
- pxQueue->pcReadFrom = pxQueue->pcHead;
- }
- --( pxQueue->uxMessagesWaiting );
- memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
-
- /* If the queue is locked we will not modify the event list. Instead
- we update the lock count so the task that unlocks the queue will know
- that an ISR has removed data while the queue was locked. */
- if( pxQueue->xRxLock == queueUNLOCKED )
- {
- /* We only want to wake one task per ISR, so check that a task has
- not already been woken. */
- if( !( *pxTaskWoken ) )
- {
- if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) )
- {
- if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
- {
- /* The task waiting has a higher priority than us so
- force a context switch. */
- *pxTaskWoken = pdTRUE;
- }
- }
- }
- }
- else
- {
- /* Increment the lock count so the task that unlocks the queue
- knows that data was removed while it was locked. */
- ++( pxQueue->xRxLock );
- }
-
- xReturn = pdPASS;
- }
- else
- {
- xReturn = pdFAIL;
- }
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle pxQueue )
-{
-unsigned portBASE_TYPE uxReturn;
-
- taskENTER_CRITICAL();
- uxReturn = pxQueue->uxMessagesWaiting;
- taskEXIT_CRITICAL();
-
- return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vQueueDelete( xQueueHandle pxQueue )
-{
- vPortFree( pxQueue->pcHead );
- vPortFree( pxQueue );
-}
-/*-----------------------------------------------------------*/
-
-static void prvUnlockQueue( xQueueHandle pxQueue )
-{
- /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */
-
- /* The lock counts contains the number of extra data items placed or
- removed from the queue while the queue was locked. When a queue is
- locked items can be added or removed, but the event lists cannot be
- updated. */
- taskENTER_CRITICAL();
- {
- --( pxQueue->xTxLock );
-
- /* See if data was added to the queue while it was locked. */
- if( pxQueue->xTxLock > queueUNLOCKED )
- {
- pxQueue->xTxLock = queueUNLOCKED;
-
- /* Data was posted while the queue was locked. Are any tasks
- blocked waiting for data to become available? */
- if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) )
- {
- /* Tasks that are removed from the event list will get added to
- the pending ready list as the scheduler is still suspended. */
- if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
- {
- /* The task waiting has a higher priority so record that a
- context switch is required. */
- vTaskMissedYield();
- }
- }
- }
- }
- taskEXIT_CRITICAL();
-
- /* Do the same for the Rx lock. */
- taskENTER_CRITICAL();
- {
- --( pxQueue->xRxLock );
-
- if( pxQueue->xRxLock > queueUNLOCKED )
- {
- pxQueue->xRxLock = queueUNLOCKED;
-
- if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) )
- {
- if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
- {
- vTaskMissedYield();
- }
- }
- }
- }
- taskEXIT_CRITICAL();
-}
-/*-----------------------------------------------------------*/
-
-static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue )
-{
-signed portBASE_TYPE xReturn;
-
- taskENTER_CRITICAL();
- xReturn = ( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 );
- taskEXIT_CRITICAL();
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue )
-{
-signed portBASE_TYPE xReturn;
-
- taskENTER_CRITICAL();
- xReturn = ( pxQueue->uxMessagesWaiting == pxQueue->uxLength );
- taskEXIT_CRITICAL();
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if configUSE_CO_ROUTINES == 1
-signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait )
-{
-signed portBASE_TYPE xReturn;
-
- /* If the queue is already full we may have to block. A critical section
- is required to prevent an interrupt removing something from the queue
- between the check to see if the queue is full and blocking on the queue. */
- portDISABLE_INTERRUPTS();
- {
- if( prvIsQueueFull( pxQueue ) )
- {
- /* The queue is full - do we want to block or just leave without
- posting? */
- if( xTicksToWait > ( portTickType ) 0 )
- {
- /* As this is called from a coroutine we cannot block directly, but
- return indicating that we need to block. */
- vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );
- portENABLE_INTERRUPTS();
- return errQUEUE_BLOCKED;
- }
- else
- {
- portENABLE_INTERRUPTS();
- return errQUEUE_FULL;
- }
- }
- }
- portENABLE_INTERRUPTS();
-
- portNOP();
-
- portDISABLE_INTERRUPTS();
- {
- if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
- {
- /* There is room in the queue, copy the data into the queue. */
- prvCopyQueueData( pxQueue, pvItemToQueue );
- xReturn = pdPASS;
-
- /* Were any co-routines waiting for data to become available? */
- if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) )
- {
- /* In this instance the co-routine could be placed directly
- into the ready list as we are within a critical section.
- Instead the same pending ready list mechansim is used as if
- the event were caused from within an interrupt. */
- if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
- {
- /* The co-routine waiting has a higher priority so record
- that a yield might be appropriate. */
- xReturn = errQUEUE_YIELD;
- }
- }
- }
- else
- {
- xReturn = errQUEUE_FULL;
- }
- }
- portENABLE_INTERRUPTS();
-
- return xReturn;
-}
-#endif
-/*-----------------------------------------------------------*/
-
-#if configUSE_CO_ROUTINES == 1
-signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait )
-{
-signed portBASE_TYPE xReturn;
-
- /* If the queue is already empty we may have to block. A critical section
- is required to prevent an interrupt adding something to the queue
- between the check to see if the queue is empty and blocking on the queue. */
- portDISABLE_INTERRUPTS();
- {
- if( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 )
- {
- /* There are no messages in the queue, do we want to block or just
- leave with nothing? */
- if( xTicksToWait > ( portTickType ) 0 )
- {
- /* As this is a co-routine we cannot block directly, but return
- indicating that we need to block. */
- vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );
- portENABLE_INTERRUPTS();
- return errQUEUE_BLOCKED;
- }
- else
- {
- portENABLE_INTERRUPTS();
- return errQUEUE_FULL;
- }
- }
- }
- portENABLE_INTERRUPTS();
-
- portNOP();
-
- portDISABLE_INTERRUPTS();
- {
- if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 )
- {
- /* Data is available from the queue. */
- pxQueue->pcReadFrom += pxQueue->uxItemSize;
- if( pxQueue->pcReadFrom >= pxQueue->pcTail )
- {
- pxQueue->pcReadFrom = pxQueue->pcHead;
- }
- --( pxQueue->uxMessagesWaiting );
- memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
-
- xReturn = pdPASS;
-
- /* Were any co-routines waiting for space to become available? */
- if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) )
- {
- /* In this instance the co-routine could be placed directly
- into the ready list as we are within a critical section.
- Instead the same pending ready list mechansim is used as if
- the event were caused from within an interrupt. */
- if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
- {
- xReturn = errQUEUE_YIELD;
- }
- }
- }
- else
- {
- xReturn = pdFAIL;
- }
- }
- portENABLE_INTERRUPTS();
-
- return xReturn;
-}
-#endif
-/*-----------------------------------------------------------*/
-
-
-
-#if configUSE_CO_ROUTINES == 1
-signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken )
-{
- /* Cannot block within an ISR so if there is no space on the queue then
- exit without doing anything. */
- if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
- {
- prvCopyQueueData( pxQueue, pvItemToQueue );
-
- /* We only want to wake one co-routine per ISR, so check that a
- co-routine has not already been woken. */
- if( !xCoRoutinePreviouslyWoken )
- {
- if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) )
- {
- if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
- {
- return pdTRUE;
- }
- }
- }
- }
-
- return xCoRoutinePreviouslyWoken;
-}
-#endif
-/*-----------------------------------------------------------*/
-
-#if configUSE_CO_ROUTINES == 1
-signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxCoRoutineWoken )
-{
-signed portBASE_TYPE xReturn;
-
- /* We cannot block from an ISR, so check there is data available. If
- not then just leave without doing anything. */
- if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 )
- {
- /* Copy the data from the queue. */
- pxQueue->pcReadFrom += pxQueue->uxItemSize;
- if( pxQueue->pcReadFrom >= pxQueue->pcTail )
- {
- pxQueue->pcReadFrom = pxQueue->pcHead;
- }
- --( pxQueue->uxMessagesWaiting );
- memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
-
- if( !( *pxCoRoutineWoken ) )
- {
- if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) )
- {
- if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
- {
- *pxCoRoutineWoken = pdTRUE;
- }
- }
- }
-
- xReturn = pdPASS;
- }
- else
- {
- xReturn = pdFAIL;
- }
-
- return xReturn;
-}
-#endif
-/*-----------------------------------------------------------*/
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/tasks.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/tasks.c
deleted file mode 100644
index 3f2f0672..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/tasks.c
+++ /dev/null
@@ -1,1936 +0,0 @@
-/*
- FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry.
-
- This file is part of the FreeRTOS.org distribution.
-
- FreeRTOS.org is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- FreeRTOS.org is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with FreeRTOS.org; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes FreeRTOS.org, without being obliged to provide
- the source code for any proprietary components. See the licensing section
- of http://www.FreeRTOS.org for full details of how and when the exception
- can be applied.
-
- ***************************************************************************
- See http://www.FreeRTOS.org for documentation, latest information, license
- and contact details. Please ensure to read the configuration and relevant
- port sections of the online documentation.
-
- Also see http://www.SafeRTOS.com for an IEC 61508 compliant version, along
- with development and support options.
- ***************************************************************************
-*/
-
-/*
-Changes from V1.00:
-
- + Call to portRESTORE_CONTEXT has been removed. The first context
- switch is now performed within sPortStartScheduler().
-
-Changes from V1.01:
-
- + More use of 8bit data types.
- + Function name prefixes changed where the data type returned has changed.
- + configUSE_TRACE_FACILITY is no longer defined by default.
-
-Changes from V1.2.0
-
- + Introduced ucTopReadyPriority. This tracks the highest priority ready
- queue that contains a valid TCB and thus makes the context switch
- slightly faster.
-
- + prvAddTaskToReadyQueue() has been made a macro.
-
-Changes from V1.2.6
-
- + Added conditional compilation directives.
- + Extended API.
- + Rearranged function order.
- + Creating a task now causes a context switch if the task being created
- has a higher priority than the calling task - assuming the kernel is
- running.
- + vTaskDelete() now only causes a context switch if the calling task is
- the task being deleted.
-
-Changes from V2.0.0
-
- + Allow the type of the tick count to be 16 or 32 bits.
- + Introduce xPendingReadyList feature to allow the time interrupts have to
- be disabled to be minimised.
- + Remove the #if( INCLUDE_vTaskSuspendAll ) statements. vTaskSuspendAll()
- is now always included as it is used by the scheduler itself.
-
-Changes from V2.1.0
-
- + Bug fix - pxCurrentTCB is now initialised before the call to
- prvInitializeTaskLists(). Previously pxCurrentTCB could be accessed
- while null.
-
-Changed from V2.1.1
-
- + Change to where lStackSize is declared within sTaskCreate() to prevent
- compiler warnings with 8051 port.
-
-Changes from V2.2.0
-
- + Explicit use of 'signed' qualifier on portCHAR types added.
- + Changed odd calculation of initial pxTopOfStack value when
- portSTACK_GROWTH < 0.
- + Removed pcVersionNumber definition.
-
-Changes from V2.5.3
-
- + cTaskResumeAll() modified to ensure it can be called prior to the task
- lists being initialised.
-
-Changes from V2.5.5
-
- + Added API function vTaskDelayUntil().
- + Added INCLUDE_vTaskDelay conditional compilation.
-
-Changes from V2.6.0
-
- + Updated the vWriteTraceToBuffer macro to always be 4 byte aligned so it
- can be used on ARM architectures.
- + tskMAX_TASK_NAME_LEN definition replaced with the port specific
- configMAX_TASK_NAME_LEN definition.
- + Removed the call to strcpy when copying across the task name into the
- TCB.
- + Added ucTasksDeleted variable to prevent vTaskSuspendAll() being called
- too often in the idle task.
-
-Changes between V3.0.0 and V2.6.1
-
- + When resuming the scheduler a yield is performed if either a tick has
- been missed, or a task is moved from the pending ready list into a ready
- list. Previously a yield was not performed on this second condition.
- + Introduced the type portBASE_TYPE. This necessitates several API
- changes.
- + Removed the sUsingPreemption variable. The constant defined in
- portmacro.h is now used directly.
- + The idle task can now include an optional hook function - and no longer
- completes its time slice if other tasks with equal priority to it are
- ready to run.
- + See the FreeRTOS.org documentation for more information on V2.x.x to
- V3.x.x modifications.
-
-Changes from V3.1.1
-
- + Modified vTaskPrioritySet() and vTaskResume() to allow these functions to
- be called while the scheduler is suspended.
- + Corrected the task ordering within event lists.
-
-Changes from V3.2.0
-
- + Added function xTaskGetCurrentTaskHandle().
-
-Changes from V3.2.4
-
- + Changed the volatile declarations on some variables to reflect the
- changes to the list definitions.
- + Changed the order of the TCB definition so there is commonality between
- the task control block and a co-routine control block.
- + Allow the scheduler to be started even if no tasks other than the idle
- task has been created. This allows co-routines to run even when no tasks
- have been created.
- + The need for a context switch is now signalled if a task woken by an
- event has a priority greater or equal to the currently running task.
- Previously this was only greater than.
-
-Changes from V4.0.0
-
- + Added the xMissedYield handling.
-
-Changes from V4.0.1
-
- + The function vTaskList() now suspends the scheduler rather than disabling
- interrupts during the creation of the task list.
- + Allow a task to delete itself by passing in its own handle. Previously
- this could only be done by passing in NULL.
- + The tick hook function is now called only within a tick isr. Previously
- it was also called when the tick function was called during the scheduler
- unlocking process.
-
-Changes from V4.0.3
-
- + Extra checks have been placed in vTaskPrioritySet() to avoid unnecessary
- yields.
-
-Changed from V4.0.4
-
- + Bug fix: The 'value' of the event list item is updated when the priority
- of a task is changed. Previously only the priority of the TCB itself was
- changed.
- + When resuming a task a check is first made to see if the task is actually
- suspended.
- + vTaskPrioritySet() and vTaskResume() no longer use the event list item.
- This has not been necessary since V4.0.1 when the xMissedYield handling
- was added.
- + Implement xTaskResumeFromISR().
-
-Changes from V4.0.5
-
- + Added utility functions and xOverflowCount variable to facilitate the
- queue.c changes.
-
-Changes from V4.1.2
-
- + Tasks that block on events with a timeout of portMAX_DELAY are now
- blocked indefinitely if configINCLUDE_vTaskSuspend is defined.
- Previously portMAX_DELAY was just the longest block time possible.
-
-Changes from V4.1.3
-
- + Very small change made to xTaskCheckForTimeout() as a result of the
- SafeRTOS testing. This corrects the case where the function can return an
- invalid value - but only in an extremely unlikely scenario.
-
-Changes since V4.3.1:
-
- + Added xTaskGetSchedulerState() function.
- + Added prvIsTaskSuspended() to take into account the Occurrence of
- vTaskResume() or vTaskResumeFromISR() being called passing in the
- handle of a task that appears in the Suspended list only because it
- is blocked on an event without a timeout being specified.
- + Updated xTaskCheckForTimeout() to take into account that tasks blocked
- using the Suspended list should never time out.
-*/
-
-#include
-#include
-#include
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-/*
- * Macro to define the amount of stack available to the idle task.
- */
-#define tskIDLE_STACK_SIZE configMINIMAL_STACK_SIZE
-
-
-/*
- * Default a definitions for backwards compatibility with old
- * portmacro.h files.
- */
-#ifndef configMAX_TASK_NAME_LEN
- #define configMAX_TASK_NAME_LEN 16
-#endif
-
-#ifndef INCLUDE_xTaskGetCurrentTaskHandle
- #define INCLUDE_xTaskGetCurrentTaskHandle 0
-#endif
-
-#ifndef configIDLE_SHOULD_YIELD
- #define configIDLE_SHOULD_YIELD 1
-#endif
-
-#if configMAX_TASK_NAME_LEN < 1
- #undef configMAX_TASK_NAME_LEN
- #define configMAX_TASK_NAME_LEN 1
-#endif
-
-#ifndef INCLUDE_xTaskResumeFromISR
- #define INCLUDE_xTaskResumeFromISR 1
-#endif
-
-#ifndef INCLUDE_xTaskGetSchedulerState
- #define INCLUDE_xTaskGetSchedulerState 0
-#endif
-
-/*
- * Task control block. A task control block (TCB) is allocated to each task,
- * and stores the context of the task.
- */
-typedef struct tskTaskControlBlock
-{
- volatile portSTACK_TYPE *pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE STRUCT. */
- xListItem xGenericListItem; /*< List item used to place the TCB in ready and blocked queues. */
- xListItem xEventListItem; /*< List item used to place the TCB in event lists. */
- unsigned portBASE_TYPE uxPriority; /*< The priority of the task where 0 is the lowest priority. */
- portSTACK_TYPE *pxStack; /*< Points to the start of the stack. */
- unsigned portBASE_TYPE uxTCBNumber; /*< This is used for tracing the scheduler and making debugging easier only. */
- signed portCHAR pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created. Facilitates debugging only. */
- unsigned portSHORT usStackDepth; /*< Total depth of the stack (when empty). This is defined as the number of variables the stack can hold, not the number of bytes. */
-} tskTCB;
-
-/*lint -e956 */
-
-tskTCB * volatile pxCurrentTCB = NULL;
-
-/* Lists for ready and blocked tasks. --------------------*/
-
-static xList pxReadyTasksLists[ configMAX_PRIORITIES ]; /*< Prioritised ready tasks. */
-static xList xDelayedTaskList1; /*< Delayed tasks. */
-static xList xDelayedTaskList2; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
-static xList * volatile pxDelayedTaskList; /*< Points to the delayed task list currently being used. */
-static xList * volatile pxOverflowDelayedTaskList; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
-static xList xPendingReadyList; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready queue when the scheduler is resumed. */
-
-#if ( INCLUDE_vTaskDelete == 1 )
-
- static volatile xList xTasksWaitingTermination; /*< Tasks that have been deleted - but the their memory not yet freed. */
- static volatile unsigned portBASE_TYPE uxTasksDeleted = ( unsigned portBASE_TYPE ) 0;
-
-#endif
-
-#if ( INCLUDE_vTaskSuspend == 1 )
-
- static xList xSuspendedTaskList; /*< Tasks that are currently suspended. */
-
-#endif
-
-/* File private variables. --------------------------------*/
-static volatile unsigned portBASE_TYPE uxCurrentNumberOfTasks = ( unsigned portBASE_TYPE ) 0;
-static volatile portTickType xTickCount = ( portTickType ) 0;
-static unsigned portBASE_TYPE uxTopUsedPriority = tskIDLE_PRIORITY;
-static volatile unsigned portBASE_TYPE uxTopReadyPriority = tskIDLE_PRIORITY;
-static volatile signed portBASE_TYPE xSchedulerRunning = pdFALSE;
-static volatile unsigned portBASE_TYPE uxSchedulerSuspended = ( unsigned portBASE_TYPE ) pdFALSE;
-static volatile unsigned portBASE_TYPE uxMissedTicks = ( unsigned portBASE_TYPE ) 0;
-static volatile portBASE_TYPE xMissedYield = ( portBASE_TYPE ) pdFALSE;
-static volatile portBASE_TYPE xNumOfOverflows = ( portBASE_TYPE ) 0;
-/* Debugging and trace facilities private variables and macros. ------------*/
-
-/*
- * The value used to fill the stack of a task when the task is created. This
- * is used purely for checking the high water mark for tasks.
- */
-#define tskSTACK_FILL_BYTE ( 0xa5 )
-
-/*
- * Macros used by vListTask to indicate which state a task is in.
- */
-#define tskBLOCKED_CHAR ( ( signed portCHAR ) 'B' )
-#define tskREADY_CHAR ( ( signed portCHAR ) 'R' )
-#define tskDELETED_CHAR ( ( signed portCHAR ) 'D' )
-#define tskSUSPENDED_CHAR ( ( signed portCHAR ) 'S' )
-
-/*
- * Macros and private variables used by the trace facility.
- */
-#if ( configUSE_TRACE_FACILITY == 1 )
-
- #define tskSIZE_OF_EACH_TRACE_LINE ( ( unsigned portLONG ) ( sizeof( unsigned portLONG ) + sizeof( unsigned portLONG ) ) )
- static volatile signed portCHAR * volatile pcTraceBuffer;
- static signed portCHAR *pcTraceBufferStart;
- static signed portCHAR *pcTraceBufferEnd;
- static signed portBASE_TYPE xTracing = pdFALSE;
-
-#endif
-
-/*
- * Macro that writes a trace of scheduler activity to a buffer. This trace
- * shows which task is running when and is very useful as a debugging tool.
- * As this macro is called each context switch it is a good idea to undefine
- * it if not using the facility.
- */
-#if ( configUSE_TRACE_FACILITY == 1 )
-
- #define vWriteTraceToBuffer() \
- { \
- if( xTracing ) \
- { \
- static unsigned portBASE_TYPE uxPreviousTask = 255; \
- \
- if( uxPreviousTask != pxCurrentTCB->uxTCBNumber ) \
- { \
- if( ( pcTraceBuffer + tskSIZE_OF_EACH_TRACE_LINE ) < pcTraceBufferEnd ) \
- { \
- uxPreviousTask = pxCurrentTCB->uxTCBNumber; \
- *( unsigned portLONG * ) pcTraceBuffer = ( unsigned portLONG ) xTickCount; \
- pcTraceBuffer += sizeof( unsigned portLONG ); \
- *( unsigned portLONG * ) pcTraceBuffer = ( unsigned portLONG ) uxPreviousTask; \
- pcTraceBuffer += sizeof( unsigned portLONG ); \
- } \
- else \
- { \
- xTracing = pdFALSE; \
- } \
- } \
- } \
- }
-
-#else
-
- #define vWriteTraceToBuffer()
-
-#endif
-
-
-/*
- * Place the task represented by pxTCB into the appropriate ready queue for
- * the task. It is inserted at the end of the list. One quirk of this is
- * that if the task being inserted is at the same priority as the currently
- * executing task, then it will only be rescheduled after the currently
- * executing task has been rescheduled.
- */
-#define prvAddTaskToReadyQueue( pxTCB ) \
-{ \
- if( pxTCB->uxPriority > uxTopReadyPriority ) \
- { \
- uxTopReadyPriority = pxTCB->uxPriority; \
- } \
- vListInsertEnd( ( xList * ) &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xGenericListItem ) ); \
-}
-
-/*
- * Macro that looks at the list of tasks that are currently delayed to see if
- * any require waking.
- *
- * Tasks are stored in the queue in the order of their wake time - meaning
- * once one tasks has been found whose timer has not expired we need not look
- * any further down the list.
- */
-#define prvCheckDelayedTasks() \
-{ \
-register tskTCB *pxTCB; \
- \
- while( ( pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ) ) != NULL ) \
- { \
- if( xTickCount < listGET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ) ) ) \
- { \
- break; \
- } \
- vListRemove( &( pxTCB->xGenericListItem ) ); \
- /* Is the task waiting on an event also? */ \
- if( pxTCB->xEventListItem.pvContainer ) \
- { \
- vListRemove( &( pxTCB->xEventListItem ) ); \
- } \
- prvAddTaskToReadyQueue( pxTCB ); \
- } \
-}
-
-/*
- * Several functions take an xTaskHandle parameter that can optionally be NULL,
- * where NULL is used to indicate that the handle of the currently executing
- * task should be used in place of the parameter. This macro simply checks to
- * see if the parameter is NULL and returns a pointer to the appropriate TCB.
- */
-#define prvGetTCBFromHandle( pxHandle ) ( ( pxHandle == NULL ) ? ( tskTCB * ) pxCurrentTCB : ( tskTCB * ) pxHandle )
-
-
-/* File private functions. --------------------------------*/
-
-/*
- * Utility to ready a TCB for a given task. Mainly just copies the parameters
- * into the TCB structure.
- */
-static void prvInitialiseTCBVariables( tskTCB *pxTCB, unsigned portSHORT usStackDepth, const signed portCHAR * const pcName, unsigned portBASE_TYPE uxPriority );
-
-/*
- * Utility to ready all the lists used by the scheduler. This is called
- * automatically upon the creation of the first task.
- */
-static void prvInitialiseTaskLists( void );
-
-/*
- * The idle task, which as all tasks is implemented as a never ending loop.
- * The idle task is automatically created and added to the ready lists upon
- * creation of the first user task.
- *
- * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific
- * language extensions. The equivalent prototype for this function is:
- *
- * void prvIdleTask( void *pvParameters );
- *
- */
-static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );
-
-/*
- * Utility to free all memory allocated by the scheduler to hold a TCB,
- * including the stack pointed to by the TCB.
- *
- * This does not free memory allocated by the task itself (i.e. memory
- * allocated by calls to pvPortMalloc from within the tasks application code).
- */
-#if ( ( INCLUDE_vTaskDelete == 1 ) || ( INCLUDE_vTaskCleanUpResources == 1 ) )
- static void prvDeleteTCB( tskTCB *pxTCB );
-#endif
-
-/*
- * Used only by the idle task. This checks to see if anything has been placed
- * in the list of tasks waiting to be deleted. If so the task is cleaned up
- * and its TCB deleted.
- */
-static void prvCheckTasksWaitingTermination( void );
-
-/*
- * Allocates memory from the heap for a TCB and associated stack. Checks the
- * allocation was successful.
- */
-static tskTCB *prvAllocateTCBAndStack( unsigned portSHORT usStackDepth );
-
-/*
- * Called from vTaskList. vListTasks details all the tasks currently under
- * control of the scheduler. The tasks may be in one of a number of lists.
- * prvListTaskWithinSingleList accepts a list and details the tasks from
- * within just that list.
- *
- * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM
- * NORMAL APPLICATION CODE.
- */
-#if ( configUSE_TRACE_FACILITY == 1 )
-
- static void prvListTaskWithinSingleList( signed portCHAR *pcWriteBuffer, xList *pxList, signed portCHAR cStatus );
-
-#endif
-
-/*
- * When a task is created, the stack of the task is filled with a known value.
- * This function determines the 'high water mark' of the task stack by
- * determining how much of the stack remains at the original preset value.
- */
-#if ( configUSE_TRACE_FACILITY == 1 )
-
- unsigned portSHORT usTaskCheckFreeStackSpace( const unsigned portCHAR *pucStackByte );
-
-#endif
-
-/*
- * Checks that a task being resumed (unsuspended) is actually in the Suspended
- * state.
- */
-#if ( INCLUDE_vTaskSuspend == 1 )
-
- static portBASE_TYPE prvIsTaskSuspended( const tskTCB * const pxTCB );
-
-#endif
-
-/*lint +e956 */
-
-
-
-
-
-/*-----------------------------------------------------------
- * TASK CREATION API documented in task.h
- *----------------------------------------------------------*/
-
-signed portBASE_TYPE xTaskCreate( pdTASK_CODE pvTaskCode, const signed portCHAR * const pcName, unsigned portSHORT usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask )
-{
-signed portBASE_TYPE xReturn;
-tskTCB * pxNewTCB;
-static unsigned portBASE_TYPE uxTaskNumber = 0; /*lint !e956 Static is deliberate - this is guarded before use. */
-
- /* Allocate the memory required by the TCB and stack for the new task.
- checking that the allocation was successful. */
- pxNewTCB = prvAllocateTCBAndStack( usStackDepth );
-
- if( pxNewTCB != NULL )
- {
- portSTACK_TYPE *pxTopOfStack;
-
- /* Setup the newly allocated TCB with the initial state of the task. */
- prvInitialiseTCBVariables( pxNewTCB, usStackDepth, pcName, uxPriority );
-
- /* Calculate the top of stack address. This depends on whether the
- stack grows from high memory to low (as per the 80x86) or visa versa.
- portSTACK_GROWTH is used to make the result positive or negative as
- required by the port. */
- #if portSTACK_GROWTH < 0
- {
- pxTopOfStack = pxNewTCB->pxStack + ( pxNewTCB->usStackDepth - 1 );
- }
- #else
- {
- pxTopOfStack = pxNewTCB->pxStack;
- }
- #endif
-
- /* Initialize the TCB stack to look as if the task was already running,
- but had been interrupted by the scheduler. The return address is set
- to the start of the task function. Once the stack has been initialised
- the top of stack variable is updated. */
- pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pvTaskCode, pvParameters );
-
- /* We are going to manipulate the task queues to add this task to a
- ready list, so must make sure no interrupts occur. */
- portENTER_CRITICAL();
- {
- uxCurrentNumberOfTasks++;
- if( uxCurrentNumberOfTasks == ( unsigned portBASE_TYPE ) 1 )
- {
- /* As this is the first task it must also be the current task. */
- pxCurrentTCB = pxNewTCB;
-
- /* This is the first task to be created so do the preliminary
- initialisation required. We will not recover if this call
- fails, but we will report the failure. */
- prvInitialiseTaskLists();
- }
- else
- {
- /* If the scheduler is not already running, make this task the
- current task if it is the highest priority task to be created
- so far. */
- if( xSchedulerRunning == pdFALSE )
- {
- if( pxCurrentTCB->uxPriority <= uxPriority )
- {
- pxCurrentTCB = pxNewTCB;
- }
- }
- }
-
- /* Remember the top priority to make context switching faster. Use
- the priority in pxNewTCB as this has been capped to a valid value. */
- if( pxNewTCB->uxPriority > uxTopUsedPriority )
- {
- uxTopUsedPriority = pxNewTCB->uxPriority;
- }
-
- /* Add a counter into the TCB for tracing only. */
- pxNewTCB->uxTCBNumber = uxTaskNumber;
- uxTaskNumber++;
-
- prvAddTaskToReadyQueue( pxNewTCB );
-
- xReturn = pdPASS;
- }
- portEXIT_CRITICAL();
- }
- else
- {
- xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
- }
-
- if( xReturn == pdPASS )
- {
- if( ( void * ) pxCreatedTask != NULL )
- {
- /* Pass the TCB out - in an anonymous way. The calling function/
- task can use this as a handle to delete the task later if
- required.*/
- *pxCreatedTask = ( xTaskHandle ) pxNewTCB;
- }
-
- if( xSchedulerRunning != pdFALSE )
- {
- /* If the created task is of a higher priority than the current task
- then it should run now. */
- if( pxCurrentTCB->uxPriority < uxPriority )
- {
- taskYIELD();
- }
- }
- }
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskDelete == 1 )
-
- void vTaskDelete( xTaskHandle pxTaskToDelete )
- {
- tskTCB *pxTCB;
-
- taskENTER_CRITICAL();
- {
- /* Ensure a yield is performed if the current task is being
- deleted. */
- if( pxTaskToDelete == pxCurrentTCB )
- {
- pxTaskToDelete = NULL;
- }
-
- /* If null is passed in here then we are deleting ourselves. */
- pxTCB = prvGetTCBFromHandle( pxTaskToDelete );
-
- /* Remove task from the ready list and place in the termination list.
- This will stop the task from be scheduled. The idle task will check
- the termination list and free up any memory allocated by the
- scheduler for the TCB and stack. */
- vListRemove( &( pxTCB->xGenericListItem ) );
-
- /* Is the task waiting on an event also? */
- if( pxTCB->xEventListItem.pvContainer )
- {
- vListRemove( &( pxTCB->xEventListItem ) );
- }
-
- vListInsertEnd( ( xList * ) &xTasksWaitingTermination, &( pxTCB->xGenericListItem ) );
-
- /* Increment the ucTasksDeleted variable so the idle task knows
- there is a task that has been deleted and that it should therefore
- check the xTasksWaitingTermination list. */
- ++uxTasksDeleted;
- }
- taskEXIT_CRITICAL();
-
- /* Force a reschedule if we have just deleted the current task. */
- if( xSchedulerRunning != pdFALSE )
- {
- if( ( void * ) pxTaskToDelete == NULL )
- {
- taskYIELD();
- }
- }
- }
-
-#endif
-
-
-
-
-
-
-/*-----------------------------------------------------------
- * TASK CONTROL API documented in task.h
- *----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskDelayUntil == 1 )
-
- void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement )
- {
- portTickType xTimeToWake;
- portBASE_TYPE xAlreadyYielded, xShouldDelay = pdFALSE;
-
- vTaskSuspendAll();
- {
- /* Generate the tick time at which the task wants to wake. */
- xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
-
- if( xTickCount < *pxPreviousWakeTime )
- {
- /* The tick count has overflowed since this function was
- lasted called. In this case the only time we should ever
- actually delay is if the wake time has also overflowed,
- and the wake time is greater than the tick time. When this
- is the case it is as if neither time had overflowed. */
- if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xTickCount ) )
- {
- xShouldDelay = pdTRUE;
- }
- }
- else
- {
- /* The tick time has not overflowed. In this case we will
- delay if either the wake time has overflowed, and/or the
- tick time is less than the wake time. */
- if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xTickCount ) )
- {
- xShouldDelay = pdTRUE;
- }
- }
-
- /* Update the wake time ready for the next call. */
- *pxPreviousWakeTime = xTimeToWake;
-
- if( xShouldDelay )
- {
- /* We must remove ourselves from the ready list before adding
- ourselves to the blocked list as the same list item is used for
- both lists. */
- vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );
-
- /* The list item will be inserted in wake time order. */
- listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake );
-
- if( xTimeToWake < xTickCount )
- {
- /* Wake time has overflowed. Place this item in the
- overflow list. */
- vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );
- }
- else
- {
- /* The wake time has not overflowed, so we can use the
- current block list. */
- vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );
- }
- }
- }
- xAlreadyYielded = xTaskResumeAll();
-
- /* Force a reschedule if xTaskResumeAll has not already done so, we may
- have put ourselves to sleep. */
- if( !xAlreadyYielded )
- {
- taskYIELD();
- }
- }
-
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskDelay == 1 )
-
- void vTaskDelay( portTickType xTicksToDelay )
- {
- portTickType xTimeToWake;
- signed portBASE_TYPE xAlreadyYielded = pdFALSE;
-
- /* A delay time of zero just forces a reschedule. */
- if( xTicksToDelay > ( portTickType ) 0 )
- {
- vTaskSuspendAll();
- {
- /* A task that is removed from the event list while the
- scheduler is suspended will not get placed in the ready
- list or removed from the blocked list until the scheduler
- is resumed.
-
- This task cannot be in an event list as it is the currently
- executing task. */
-
- /* Calculate the time to wake - this may overflow but this is
- not a problem. */
- xTimeToWake = xTickCount + xTicksToDelay;
-
- /* We must remove ourselves from the ready list before adding
- ourselves to the blocked list as the same list item is used for
- both lists. */
- vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );
-
- /* The list item will be inserted in wake time order. */
- listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake );
-
- if( xTimeToWake < xTickCount )
- {
- /* Wake time has overflowed. Place this item in the
- overflow list. */
- vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );
- }
- else
- {
- /* The wake time has not overflowed, so we can use the
- current block list. */
- vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );
- }
- }
- xAlreadyYielded = xTaskResumeAll();
- }
-
- /* Force a reschedule if xTaskResumeAll has not already done so, we may
- have put ourselves to sleep. */
- if( !xAlreadyYielded )
- {
- taskYIELD();
- }
- }
-
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
-
- unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask )
- {
- tskTCB *pxTCB;
- unsigned portBASE_TYPE uxReturn;
-
- taskENTER_CRITICAL();
- {
- /* If null is passed in here then we are changing the
- priority of the calling function. */
- pxTCB = prvGetTCBFromHandle( pxTask );
- uxReturn = pxTCB->uxPriority;
- }
- taskEXIT_CRITICAL();
-
- return uxReturn;
- }
-
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskPrioritySet == 1 )
-
- void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority )
- {
- tskTCB *pxTCB;
- unsigned portBASE_TYPE uxCurrentPriority, xYieldRequired = pdFALSE;
-
- /* Ensure the new priority is valid. */
- if( uxNewPriority >= configMAX_PRIORITIES )
- {
- uxNewPriority = configMAX_PRIORITIES - 1;
- }
-
- taskENTER_CRITICAL();
- {
- /* If null is passed in here then we are changing the
- priority of the calling function. */
- pxTCB = prvGetTCBFromHandle( pxTask );
- uxCurrentPriority = pxTCB->uxPriority;
-
- if( uxCurrentPriority != uxNewPriority )
- {
- /* The priority change may have readied a task of higher
- priority than the calling task. */
- if( uxNewPriority > pxCurrentTCB->uxPriority )
- {
- if( pxTask != NULL )
- {
- /* The priority of another task is being raised. If we
- were raising the priority of the currently running task
- there would be no need to switch as it must have already
- been the highest priority task. */
- xYieldRequired = pdTRUE;
- }
- }
- else if( pxTask == NULL )
- {
- /* Setting our own priority down means there may now be another
- task of higher priority that is ready to execute. */
- xYieldRequired = pdTRUE;
- }
-
- pxTCB->uxPriority = uxNewPriority;
- listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxNewPriority );
-
- /* If the task is in the blocked or suspended list we need do
- nothing more than change it's priority variable. However, if
- the task is in a ready list it needs to be removed and placed
- in the queue appropriate to its new priority. */
- if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxCurrentPriority ] ), &( pxTCB->xGenericListItem ) ) )
- {
- /* The task is currently in its ready list - remove before adding
- it to it's new ready list. As we are in a critical section we
- can do this even if the scheduler is suspended. */
- vListRemove( &( pxTCB->xGenericListItem ) );
- prvAddTaskToReadyQueue( pxTCB );
- }
-
- if( xYieldRequired == pdTRUE )
- {
- taskYIELD();
- }
- }
- }
- taskEXIT_CRITICAL();
- }
-
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskSuspend == 1 )
-
- void vTaskSuspend( xTaskHandle pxTaskToSuspend )
- {
- tskTCB *pxTCB;
-
- taskENTER_CRITICAL();
- {
- /* Ensure a yield is performed if the current task is being
- suspended. */
- if( pxTaskToSuspend == pxCurrentTCB )
- {
- pxTaskToSuspend = NULL;
- }
-
- /* If null is passed in here then we are suspending ourselves. */
- pxTCB = prvGetTCBFromHandle( pxTaskToSuspend );
-
- /* Remove task from the ready/delayed list and place in the suspended list. */
- vListRemove( &( pxTCB->xGenericListItem ) );
-
- /* Is the task waiting on an event also? */
- if( pxTCB->xEventListItem.pvContainer )
- {
- vListRemove( &( pxTCB->xEventListItem ) );
- }
-
- vListInsertEnd( ( xList * ) &xSuspendedTaskList, &( pxTCB->xGenericListItem ) );
- }
- taskEXIT_CRITICAL();
-
- /* We may have just suspended the current task. */
- if( ( void * ) pxTaskToSuspend == NULL )
- {
- taskYIELD();
- }
- }
-
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskSuspend == 1 )
-
- static portBASE_TYPE prvIsTaskSuspended( const tskTCB * const pxTCB )
- {
- portBASE_TYPE xReturn = pdFALSE;
-
- /* Is the task we are attempting to resume actually in the
- suspended list? */
- if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ) != pdFALSE )
- {
- /* Has the task already been resumed from within an ISR? */
- if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) != pdTRUE )
- {
- /* Is it in the suspended list because it is in the
- Suspended state? It is possible to be in the suspended
- list because it is blocked on a task with no timeout
- specified. */
- if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) == pdTRUE )
- {
- xReturn = pdTRUE;
- }
- }
- }
-
- return xReturn;
- }
-
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskSuspend == 1 )
-
- void vTaskResume( xTaskHandle pxTaskToResume )
- {
- tskTCB *pxTCB;
-
- /* Remove the task from whichever list it is currently in, and place
- it in the ready list. */
- pxTCB = ( tskTCB * ) pxTaskToResume;
-
- /* The parameter cannot be NULL as it is impossible to resume the
- currently executing task. */
- if( pxTCB != NULL )
- {
- taskENTER_CRITICAL();
- {
- if( prvIsTaskSuspended( pxTCB ) == pdTRUE )
- {
- /* As we are in a critical section we can access the ready
- lists even if the scheduler is suspended. */
- vListRemove( &( pxTCB->xGenericListItem ) );
- prvAddTaskToReadyQueue( pxTCB );
-
- /* We may have just resumed a higher priority task. */
- if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
- {
- /* This yield may not cause the task just resumed to run, but
- will leave the lists in the correct state for the next yield. */
- taskYIELD();
- }
- }
- }
- taskEXIT_CRITICAL();
- }
- }
-
-#endif
-
-/*-----------------------------------------------------------*/
-
-#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
-
- portBASE_TYPE xTaskResumeFromISR( xTaskHandle pxTaskToResume )
- {
- portBASE_TYPE xYieldRequired = pdFALSE;
- tskTCB *pxTCB;
-
- pxTCB = ( tskTCB * ) pxTaskToResume;
-
- if( prvIsTaskSuspended( pxTCB ) == pdTRUE )
- {
- if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )
- {
- xYieldRequired = ( pxTCB->uxPriority >= pxCurrentTCB->uxPriority );
- vListRemove( &( pxTCB->xGenericListItem ) );
- prvAddTaskToReadyQueue( pxTCB );
- }
- else
- {
- /* We cannot access the delayed or ready lists, so will hold this
- task pending until the scheduler is resumed, at which point a
- yield will be preformed if necessary. */
- vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
- }
- }
-
- return xYieldRequired;
- }
-
-#endif
-
-
-
-
-/*-----------------------------------------------------------
- * PUBLIC SCHEDULER CONTROL documented in task.h
- *----------------------------------------------------------*/
-
-
-void vTaskStartScheduler( void )
-{
-portBASE_TYPE xReturn;
-
- /* Add the idle task at the lowest priority. */
- xReturn = xTaskCreate( prvIdleTask, ( signed portCHAR * ) "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL );
-
- if( xReturn == pdPASS )
- {
- /* Interrupts are turned off here, to ensure a tick does not occur
- before or during the call to xPortStartScheduler(). The stacks of
- the created tasks contain a status word with interrupts switched on
- so interrupts will automatically get re-enabled when the first task
- starts to run.
-
- STEPPING THROUGH HERE USING A DEBUGGER CAN CAUSE BIG PROBLEMS IF THE
- DEBUGGER ALLOWS INTERRUPTS TO BE PROCESSED. */
- portDISABLE_INTERRUPTS();
-
- xSchedulerRunning = pdTRUE;
- xTickCount = ( portTickType ) 0;
-
- /* Setting up the timer tick is hardware specific and thus in the
- portable interface. */
- if( xPortStartScheduler() )
- {
- /* Should not reach here as if the scheduler is running the
- function will not return. */
- }
- else
- {
- /* Should only reach here if a task calls xTaskEndScheduler(). */
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-void vTaskEndScheduler( void )
-{
- /* Stop the scheduler interrupts and call the portable scheduler end
- routine so the original ISRs can be restored if necessary. The port
- layer must ensure interrupts enable bit is left in the correct state. */
- portDISABLE_INTERRUPTS();
- xSchedulerRunning = pdFALSE;
- vPortEndScheduler();
-}
-/*----------------------------------------------------------*/
-
-void vTaskSuspendAll( void )
-{
- portENTER_CRITICAL();
- ++uxSchedulerSuspended;
- portEXIT_CRITICAL();
-}
-/*----------------------------------------------------------*/
-
-signed portBASE_TYPE xTaskResumeAll( void )
-{
-register tskTCB *pxTCB;
-signed portBASE_TYPE xAlreadyYielded = pdFALSE;
-
- /* It is possible that an ISR caused a task to be removed from an event
- list while the scheduler was suspended. If this was the case then the
- removed task will have been added to the xPendingReadyList. Once the
- scheduler has been resumed it is safe to move all the pending ready
- tasks from this list into their appropriate ready list. */
- portENTER_CRITICAL();
- {
- --uxSchedulerSuspended;
-
- if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )
- {
- if( uxCurrentNumberOfTasks > ( unsigned portBASE_TYPE ) 0 )
- {
- portBASE_TYPE xYieldRequired = pdFALSE;
-
- /* Move any readied tasks from the pending list into the
- appropriate ready list. */
- while( ( pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xPendingReadyList ) ) ) != NULL )
- {
- vListRemove( &( pxTCB->xEventListItem ) );
- vListRemove( &( pxTCB->xGenericListItem ) );
- prvAddTaskToReadyQueue( pxTCB );
-
- /* If we have moved a task that has a priority higher than
- the current task then we should yield. */
- if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
- {
- xYieldRequired = pdTRUE;
- }
- }
-
- /* If any ticks occurred while the scheduler was suspended then
- they should be processed now. This ensures the tick count does not
- slip, and that any delayed tasks are resumed at the correct time. */
- if( uxMissedTicks > ( unsigned portBASE_TYPE ) 0 )
- {
- while( uxMissedTicks > ( unsigned portBASE_TYPE ) 0 )
- {
- vTaskIncrementTick();
- --uxMissedTicks;
- }
-
- /* As we have processed some ticks it is appropriate to yield
- to ensure the highest priority task that is ready to run is
- the task actually running. */
- xYieldRequired = pdTRUE;
- }
-
- if( ( xYieldRequired == pdTRUE ) || ( xMissedYield == pdTRUE ) )
- {
- xAlreadyYielded = pdTRUE;
- xMissedYield = pdFALSE;
- taskYIELD();
- }
- }
- }
- }
- portEXIT_CRITICAL();
-
- return xAlreadyYielded;
-}
-
-
-
-
-
-
-/*-----------------------------------------------------------
- * PUBLIC TASK UTILITIES documented in task.h
- *----------------------------------------------------------*/
-
-
-
-portTickType xTaskGetTickCount( void )
-{
-portTickType xTicks;
-
- /* Critical section required if running on a 16 bit processor. */
- taskENTER_CRITICAL();
- {
- xTicks = xTickCount;
- }
- taskEXIT_CRITICAL();
-
- return xTicks;
-}
-/*-----------------------------------------------------------*/
-
-unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void )
-{
-unsigned portBASE_TYPE uxNumberOfTasks;
-
- taskENTER_CRITICAL();
- uxNumberOfTasks = uxCurrentNumberOfTasks;
- taskEXIT_CRITICAL();
-
- return uxNumberOfTasks;
-}
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_vTaskDelete == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
-
- void vTaskList( signed portCHAR *pcWriteBuffer )
- {
- unsigned portBASE_TYPE uxQueue;
-
- /* This is a VERY costly function that should be used for debug only.
- It leaves interrupts disabled for a LONG time. */
-
- vTaskSuspendAll();
- {
- /* Run through all the lists that could potentially contain a TCB and
- report the task name, state and stack high water mark. */
-
- pcWriteBuffer[ 0 ] = ( signed portCHAR ) 0x00;
- strcat( ( portCHAR * ) pcWriteBuffer, ( const portCHAR * ) "\r\n" );
-
- uxQueue = uxTopUsedPriority + 1;
-
- do
- {
- uxQueue--;
-
- if( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxQueue ] ) ) )
- {
- prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &( pxReadyTasksLists[ uxQueue ] ), tskREADY_CHAR );
- }
- }while( uxQueue > ( unsigned portSHORT ) tskIDLE_PRIORITY );
-
- if( !listLIST_IS_EMPTY( pxDelayedTaskList ) )
- {
- prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxDelayedTaskList, tskBLOCKED_CHAR );
- }
-
- if( !listLIST_IS_EMPTY( pxOverflowDelayedTaskList ) )
- {
- prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxOverflowDelayedTaskList, tskBLOCKED_CHAR );
- }
-
- if( !listLIST_IS_EMPTY( &xTasksWaitingTermination ) )
- {
- prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &xTasksWaitingTermination, tskDELETED_CHAR );
- }
-
- if( !listLIST_IS_EMPTY( &xSuspendedTaskList ) )
- {
- prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &xSuspendedTaskList, tskSUSPENDED_CHAR );
- }
- }
- xTaskResumeAll();
- }
-
-#endif
-/*----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
- void vTaskStartTrace( signed portCHAR * pcBuffer, unsigned portLONG ulBufferSize )
- {
- portENTER_CRITICAL();
- {
- pcTraceBuffer = ( volatile signed portCHAR * volatile )pcBuffer;
- pcTraceBufferStart = pcBuffer;
- pcTraceBufferEnd = pcBuffer + ( ulBufferSize - tskSIZE_OF_EACH_TRACE_LINE );
- xTracing = pdTRUE;
- }
- portEXIT_CRITICAL();
- }
-
-#endif
-/*----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
- unsigned portLONG ulTaskEndTrace( void )
- {
- unsigned portLONG ulBufferLength;
-
- portENTER_CRITICAL();
- xTracing = pdFALSE;
- portEXIT_CRITICAL();
-
- ulBufferLength = ( unsigned portLONG ) ( pcTraceBuffer - pcTraceBufferStart );
-
- return ulBufferLength;
- }
-
-#endif
-
-
-
-/*-----------------------------------------------------------
- * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
- * documented in task.h
- *----------------------------------------------------------*/
-
-
-inline void vTaskIncrementTick( void )
-{
- /* Called by the portable layer each time a tick interrupt occurs.
- Increments the tick then checks to see if the new tick value will cause any
- tasks to be unblocked. */
- if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )
- {
- ++xTickCount;
- if( xTickCount == ( portTickType ) 0 )
- {
- xList *pxTemp;
-
- /* Tick count has overflowed so we need to swap the delay lists.
- If there are any items in pxDelayedTaskList here then there is
- an error! */
- pxTemp = pxDelayedTaskList;
- pxDelayedTaskList = pxOverflowDelayedTaskList;
- pxOverflowDelayedTaskList = pxTemp;
- xNumOfOverflows++;
- }
-
- /* See if this tick has made a timeout expire. */
- prvCheckDelayedTasks();
- }
- else
- {
- ++uxMissedTicks;
-
- /* The tick hook gets called at regular intervals, even if the
- scheduler is locked. */
- #if ( configUSE_TICK_HOOK == 1 )
- {
- extern void vApplicationTickHook( void );
-
- vApplicationTickHook();
- }
- #endif
- }
-
- #if ( configUSE_TICK_HOOK == 1 )
- {
- extern void vApplicationTickHook( void );
-
- /* Guard against the tick hook being called when the missed tick
- count is being unwound (when the scheduler is being unlocked. */
- if( uxMissedTicks == 0 )
- {
- vApplicationTickHook();
- }
- }
- #endif
-}
-/*-----------------------------------------------------------*/
-
-#if ( ( INCLUDE_vTaskCleanUpResources == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
-
- void vTaskCleanUpResources( void )
- {
- unsigned portSHORT usQueue;
- volatile tskTCB *pxTCB;
-
- usQueue = ( unsigned portSHORT ) uxTopUsedPriority + ( unsigned portSHORT ) 1;
-
- /* Remove any TCB's from the ready queues. */
- do
- {
- usQueue--;
-
- while( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ usQueue ] ) ) )
- {
- listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &( pxReadyTasksLists[ usQueue ] ) );
- vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) );
-
- prvDeleteTCB( ( tskTCB * ) pxTCB );
- }
- }while( usQueue > ( unsigned portSHORT ) tskIDLE_PRIORITY );
-
- /* Remove any TCB's from the delayed queue. */
- while( !listLIST_IS_EMPTY( &xDelayedTaskList1 ) )
- {
- listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xDelayedTaskList1 );
- vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) );
-
- prvDeleteTCB( ( tskTCB * ) pxTCB );
- }
-
- /* Remove any TCB's from the overflow delayed queue. */
- while( !listLIST_IS_EMPTY( &xDelayedTaskList2 ) )
- {
- listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xDelayedTaskList2 );
- vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) );
-
- prvDeleteTCB( ( tskTCB * ) pxTCB );
- }
-
- while( !listLIST_IS_EMPTY( &xSuspendedTaskList ) )
- {
- listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xSuspendedTaskList );
- vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) );
-
- prvDeleteTCB( ( tskTCB * ) pxTCB );
- }
- }
-
-#endif
-/*-----------------------------------------------------------*/
-
-void vTaskSwitchContext( void )
-{
- if( uxSchedulerSuspended != ( unsigned portBASE_TYPE ) pdFALSE )
- {
- /* The scheduler is currently suspended - do not allow a context
- switch. */
- xMissedYield = pdTRUE;
- return;
- }
-
- /* Find the highest priority queue that contains ready tasks. */
- while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopReadyPriority ] ) ) )
- {
- --uxTopReadyPriority;
- }
-
- /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the tasks of the
- same priority get an equal share of the processor time. */
- listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopReadyPriority ] ) );
- vWriteTraceToBuffer();
-}
-/*-----------------------------------------------------------*/
-
-void vTaskPlaceOnEventList( xList *pxEventList, portTickType xTicksToWait )
-{
-portTickType xTimeToWake;
-
- /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE
- SCHEDULER SUSPENDED. */
-
- /* Place the event list item of the TCB in the appropriate event list.
- This is placed in the list in priority order so the highest priority task
- is the first to be woken by the event. */
- vListInsert( ( xList * ) pxEventList, ( xListItem * ) &( pxCurrentTCB->xEventListItem ) );
-
- /* We must remove ourselves from the ready list before adding ourselves
- to the blocked list as the same list item is used for both lists. We have
- exclusive access to the ready lists as the scheduler is locked. */
- vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );
-
-
- #if ( INCLUDE_vTaskSuspend == 1 )
- {
- if( xTicksToWait == portMAX_DELAY )
- {
- /* Add ourselves to the suspended task list instead of a delayed task
- list to ensure we are not woken by a timing event. We will block
- indefinitely. */
- vListInsertEnd( ( xList * ) &xSuspendedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );
- }
- else
- {
- /* Calculate the time at which the task should be woken if the event does
- not occur. This may overflow but this doesn't matter. */
- xTimeToWake = xTickCount + xTicksToWait;
-
- listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake );
-
- if( xTimeToWake < xTickCount )
- {
- /* Wake time has overflowed. Place this item in the overflow list. */
- vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );
- }
- else
- {
- /* The wake time has not overflowed, so we can use the current block list. */
- vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );
- }
- }
- }
- #else
- {
- /* Calculate the time at which the task should be woken if the event does
- not occur. This may overflow but this doesn't matter. */
- xTimeToWake = xTickCount + xTicksToWait;
-
- listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake );
-
- if( xTimeToWake < xTickCount )
- {
- /* Wake time has overflowed. Place this item in the overflow list. */
- vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );
- }
- else
- {
- /* The wake time has not overflowed, so we can use the current block list. */
- vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );
- }
- }
- #endif
-}
-/*-----------------------------------------------------------*/
-
-signed portBASE_TYPE xTaskRemoveFromEventList( const xList *pxEventList )
-{
-tskTCB *pxUnblockedTCB;
-portBASE_TYPE xReturn;
-
- /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE
- SCHEDULER SUSPENDED. It can also be called from within an ISR. */
-
- /* The event list is sorted in priority order, so we can remove the
- first in the list, remove the TCB from the delayed list, and add
- it to the ready list.
-
- If an event is for a queue that is locked then this function will never
- get called - the lock count on the queue will get modified instead. This
- means we can always expect exclusive access to the event list here. */
- pxUnblockedTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
- vListRemove( &( pxUnblockedTCB->xEventListItem ) );
-
- if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )
- {
- vListRemove( &( pxUnblockedTCB->xGenericListItem ) );
- prvAddTaskToReadyQueue( pxUnblockedTCB );
- }
- else
- {
- /* We cannot access the delayed or ready lists, so will hold this
- task pending until the scheduler is resumed. */
- vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
- }
-
- if( pxUnblockedTCB->uxPriority >= pxCurrentTCB->uxPriority )
- {
- /* Return true if the task removed from the event list has
- a higher priority than the calling task. This allows
- the calling task to know if it should force a context
- switch now. */
- xReturn = pdTRUE;
- }
- else
- {
- xReturn = pdFALSE;
- }
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vTaskSetTimeOutState( xTimeOutType *pxTimeOut )
-{
- pxTimeOut->xOverflowCount = xNumOfOverflows;
- pxTimeOut->xTimeOnEntering = xTickCount;
-}
-/*-----------------------------------------------------------*/
-
-portBASE_TYPE xTaskCheckForTimeOut( xTimeOutType *pxTimeOut, portTickType * const pxTicksToWait )
-{
-portBASE_TYPE xReturn;
-
- #if ( INCLUDE_vTaskSuspend == 1 )
- /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is
- the maximum block time then the task should block indefinitely, and
- therefore never time out. */
- if( *pxTicksToWait == portMAX_DELAY )
- {
- xReturn = pdFALSE;
- }
- else /* We are not blocking indefinitely, perform the checks below. */
- #endif
-
- if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xTickCount >= pxTimeOut->xTimeOnEntering ) )
- {
- /* The tick count is greater than the time at which vTaskSetTimeout()
- was called, but has also overflowed since vTaskSetTimeOut() was called.
- It must have wrapped all the way around and gone past us again. This
- passed since vTaskSetTimeout() was called. */
- xReturn = pdTRUE;
- }
- else if( ( xTickCount - pxTimeOut->xTimeOnEntering ) < *pxTicksToWait )
- {
- /* Not a genuine timeout. Adjust parameters for time remaining. */
- *pxTicksToWait -= ( xTickCount - pxTimeOut->xTimeOnEntering );
- vTaskSetTimeOutState( pxTimeOut );
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vTaskMissedYield( void )
-{
- xMissedYield = pdTRUE;
-}
-
-/*
- * -----------------------------------------------------------
- * The Idle task.
- * ----------------------------------------------------------
- *
- * The portTASK_FUNCTION() macro is used to allow port/compiler specific
- * language extensions. The equivalent prototype for this function is:
- *
- * void prvIdleTask( void *pvParameters );
- *
- */
-static portTASK_FUNCTION( prvIdleTask, pvParameters )
-{
- /* Stop warnings. */
- ( void ) pvParameters;
-
- for( ;; )
- {
- /* See if any tasks have been deleted. */
- prvCheckTasksWaitingTermination();
-
- #if ( configUSE_PREEMPTION == 0 )
- {
- /* If we are not using preemption we keep forcing a task switch to
- see if any other task has become available. If we are using
- preemption we don't need to do this as any task becoming available
- will automatically get the processor anyway. */
- taskYIELD();
- }
- #endif
-
- #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
- {
- /* When using preemption tasks of equal priority will be
- timesliced. If a task that is sharing the idle priority is ready
- to run then the idle task should yield before the end of the
- timeslice.
-
- A critical region is not required here as we are just reading from
- the list, and an occasional incorrect value will not matter. If
- the ready list at the idle priority contains more than one task
- then a task other than the idle task is ready to execute. */
- if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( unsigned portBASE_TYPE ) 1 )
- {
- taskYIELD();
- }
- }
- #endif
-
- #if ( configUSE_IDLE_HOOK == 1 )
- {
- extern void vApplicationIdleHook( void );
-
- /* Call the user defined function from within the idle task. This
- allows the application designer to add background functionality
- without the overhead of a separate task.
- NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
- CALL A FUNCTION THAT MIGHT BLOCK. */
- vApplicationIdleHook();
- }
- #endif
- }
-} /*lint !e715 pvParameters is not accessed but all task functions require the same prototype. */
-
-
-
-
-
-
-
-/*-----------------------------------------------------------
- * File private functions documented at the top of the file.
- *----------------------------------------------------------*/
-
-
-
-static void prvInitialiseTCBVariables( tskTCB *pxTCB, unsigned portSHORT usStackDepth, const signed portCHAR * const pcName, unsigned portBASE_TYPE uxPriority )
-{
- pxTCB->usStackDepth = usStackDepth;
-
- /* Store the function name in the TCB. */
- strncpy( ( char * ) pxTCB->pcTaskName, ( const char * ) pcName, ( unsigned portSHORT ) configMAX_TASK_NAME_LEN );
- pxTCB->pcTaskName[ ( unsigned portSHORT ) configMAX_TASK_NAME_LEN - ( unsigned portSHORT ) 1 ] = '\0';
-
- /* This is used as an array index so must ensure it's not too large. */
- if( uxPriority >= configMAX_PRIORITIES )
- {
- uxPriority = configMAX_PRIORITIES - 1;
- }
-
- pxTCB->uxPriority = uxPriority;
-
- vListInitialiseItem( &( pxTCB->xGenericListItem ) );
- vListInitialiseItem( &( pxTCB->xEventListItem ) );
-
- /* Set the pxTCB as a link back from the xListItem. This is so we can get
- back to the containing TCB from a generic item in a list. */
- listSET_LIST_ITEM_OWNER( &( pxTCB->xGenericListItem ), pxTCB );
-
- /* Event lists are always in priority order. */
- listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority );
- listSET_LIST_ITEM_OWNER( &( pxTCB->xEventListItem ), pxTCB );
-}
-/*-----------------------------------------------------------*/
-
-static void prvInitialiseTaskLists( void )
-{
-unsigned portBASE_TYPE uxPriority;
-
- for( uxPriority = 0; uxPriority < configMAX_PRIORITIES; uxPriority++ )
- {
- vListInitialise( ( xList * ) &( pxReadyTasksLists[ uxPriority ] ) );
- }
-
- vListInitialise( ( xList * ) &xDelayedTaskList1 );
- vListInitialise( ( xList * ) &xDelayedTaskList2 );
- vListInitialise( ( xList * ) &xPendingReadyList );
-
- #if ( INCLUDE_vTaskDelete == 1 )
- {
- vListInitialise( ( xList * ) &xTasksWaitingTermination );
- }
- #endif
-
- #if ( INCLUDE_vTaskSuspend == 1 )
- {
- vListInitialise( ( xList * ) &xSuspendedTaskList );
- }
- #endif
-
- /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
- using list2. */
- pxDelayedTaskList = &xDelayedTaskList1;
- pxOverflowDelayedTaskList = &xDelayedTaskList2;
-}
-/*-----------------------------------------------------------*/
-
-static void prvCheckTasksWaitingTermination( void )
-{
- #if ( INCLUDE_vTaskDelete == 1 )
- {
- portBASE_TYPE xListIsEmpty;
-
- /* ucTasksDeleted is used to prevent vTaskSuspendAll() being called
- too often in the idle task. */
- if( uxTasksDeleted > ( unsigned portBASE_TYPE ) 0 )
- {
- vTaskSuspendAll();
- xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination );
- xTaskResumeAll();
-
- if( !xListIsEmpty )
- {
- tskTCB *pxTCB;
-
- portENTER_CRITICAL();
- {
- pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xTasksWaitingTermination ) );
- vListRemove( &( pxTCB->xGenericListItem ) );
- --uxCurrentNumberOfTasks;
- --uxTasksDeleted;
- }
- portEXIT_CRITICAL();
-
- prvDeleteTCB( pxTCB );
- }
- }
- }
- #endif
-}
-/*-----------------------------------------------------------*/
-
-static tskTCB *prvAllocateTCBAndStack( unsigned portSHORT usStackDepth )
-{
-tskTCB *pxNewTCB;
-
- /* Allocate space for the TCB. Where the memory comes from depends on
- the implementation of the port malloc function. */
- pxNewTCB = ( tskTCB * ) pvPortMalloc( sizeof( tskTCB ) );
-
- if( pxNewTCB != NULL )
- {
- /* Allocate space for the stack used by the task being created.
- The base of the stack memory stored in the TCB so the task can
- be deleted later if required. */
- pxNewTCB->pxStack = ( portSTACK_TYPE * ) pvPortMalloc( ( ( size_t )usStackDepth ) * sizeof( portSTACK_TYPE ) );
-
- if( pxNewTCB->pxStack == NULL )
- {
- /* Could not allocate the stack. Delete the allocated TCB. */
- vPortFree( pxNewTCB );
- pxNewTCB = NULL;
- }
- else
- {
- /* Just to help debugging. */
- memset( pxNewTCB->pxStack, tskSTACK_FILL_BYTE, usStackDepth * sizeof( portSTACK_TYPE ) );
- }
- }
-
- return pxNewTCB;
-}
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
- static void prvListTaskWithinSingleList( signed portCHAR *pcWriteBuffer, xList *pxList, signed portCHAR cStatus )
- {
- volatile tskTCB *pxNextTCB, *pxFirstTCB;
- static portCHAR pcStatusString[ 50 ];
- unsigned portSHORT usStackRemaining;
-
- /* Write the details of all the TCB's in pxList into the buffer. */
- listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );
- do
- {
- listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );
- usStackRemaining = usTaskCheckFreeStackSpace( ( unsigned portCHAR * ) pxNextTCB->pxStack );
- sprintf( pcStatusString, ( portCHAR * ) "%s\t\t%c\t%u\t%u\t%u\r\n", pxNextTCB->pcTaskName, cStatus, ( unsigned int ) pxNextTCB->uxPriority, usStackRemaining, ( unsigned int ) pxNextTCB->uxTCBNumber );
- strcat( ( portCHAR * ) pcWriteBuffer, ( portCHAR * ) pcStatusString );
-
- } while( pxNextTCB != pxFirstTCB );
- }
-
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
- unsigned portSHORT usTaskCheckFreeStackSpace( const unsigned portCHAR *pucStackByte )
- {
- register unsigned portSHORT usCount = 0;
-
- while( *pucStackByte == tskSTACK_FILL_BYTE )
- {
- pucStackByte -= portSTACK_GROWTH;
- usCount++;
- }
-
- usCount /= sizeof( portSTACK_TYPE );
-
- return usCount;
- }
-#endif
-/*-----------------------------------------------------------*/
-
-
-
-#if ( ( INCLUDE_vTaskDelete == 1 ) || ( INCLUDE_vTaskCleanUpResources == 1 ) )
-
- static void prvDeleteTCB( tskTCB *pxTCB )
- {
- /* Free up the memory allocated by the scheduler for the task. It is up to
- the task to free any memory allocated at the application level. */
- vPortFree( pxTCB->pxStack );
- vPortFree( pxTCB );
- }
-
-#endif
-
-
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 )
-
- xTaskHandle xTaskGetCurrentTaskHandle( void )
- {
- xTaskHandle xReturn;
-
- portENTER_CRITICAL();
- {
- xReturn = ( xTaskHandle ) pxCurrentTCB;
- }
- portEXIT_CRITICAL();
-
- return xReturn;
- }
-
-#endif
-
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetSchedulerState == 1 )
-
- portBASE_TYPE xTaskGetSchedulerState( void )
- {
- portBASE_TYPE xReturn;
-
- if( xSchedulerRunning == pdFALSE )
- {
- xReturn = taskSCHEDULER_NOT_STARTED;
- }
- else
- {
- if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )
- {
- xReturn = taskSCHEDULER_RUNNING;
- }
- else
- {
- xReturn = taskSCHEDULER_SUSPENDED;
- }
- }
-
- return xReturn;
- }
-
-#endif
-
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOSConfig.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOSConfig.h
deleted file mode 100644
index fecd8241..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOSConfig.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * MODBUS Slave Library: A portable MODBUS slave for MODBUS ASCII/RTU/TCP.
- * Copyright (c) 2007 Christian Walter
- * All rights reserved.
- *
- * $Id$
- */
-
-#ifndef FREERTOS_CONFIG_H
-#define FREERTOS_CONFIG_H
-
-/* ----------------------- Defines ------------------------------------------*/
-
-#define vPortYieldProcessor swi_handler
-
-#define configUSE_PREEMPTION ( 1 )
-#define configUSE_IDLE_HOOK ( 0 )
-#define configUSE_TICK_HOOK ( 1 )
-#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 48054857UL )
-#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
-#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
-#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 )
-#define configTOTAL_HEAP_SIZE ( ( size_t ) 2048 )
-#define configMAX_TASK_NAME_LEN ( 16 )
-#define configUSE_TRACE_FACILITY ( 1 )
-#define configUSE_16_BIT_TICKS ( 0 )
-#define configIDLE_SHOULD_YIELD ( 1 )
-#define configUSE_CO_ROUTINES ( 0 )
-#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
-
-#define INCLUDE_vTaskPrioritySet ( 1 )
-#define INCLUDE_uxTaskPriorityGet ( 1 )
-#define INCLUDE_vTaskDelete ( 1 )
-#define INCLUDE_vTaskCleanUpResources ( 0 )
-#define INCLUDE_vTaskSuspend ( 1 )
-#define INCLUDE_vTaskDelayUntil ( 1 )
-#define INCLUDE_vTaskDelay ( 1 )
-#define INCLUDE_xTaskGetCurrentTaskHandle ( 1 )
-
-#endif
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/demo.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/demo.c
deleted file mode 100644
index e2fd1e61..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/demo.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * FreeModbus Libary: ARM7 Demo Application
- * Copyright (C) 2006 Christian Walter
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
- * File: $Id$
- */
-
-/* ----------------------- System includes ----------------------------------*/
-#include "assert.h"
-
-/* ----------------------- Platform includes --------------------------------*/
-#include "support/AT91SAM7X256.h"
-#include "support/lib_AT91SAM7X256.h"
-
-#include "FreeRTOS.h"
-#include "task.h"
-#include "queue.h"
-
-/* ----------------------- Modbus includes ----------------------------------*/
-#include "mb.h"
-
-/* ----------------------- Defines ------------------------------------------*/
-#define REG_HOLDING_START 0x1000
-#define REG_HOLDING_NREGS 130
-#define REG_INPUT_START 0x1000
-#define REG_INPUT_NREGS 4
-
-/* ----------------------- Static variables ---------------------------------*/
-static USHORT usRegHoldingStart = REG_HOLDING_START;
-static USHORT usRegHoldingBuf[REG_HOLDING_NREGS];
-static USHORT usRegInputStart = REG_INPUT_START;
-static USHORT usRegInputBuf[REG_INPUT_NREGS];
-
-/* ----------------------- Static functions ---------------------------------*/
-STATIC void vModbusTask( void *pvParameters );
-STATIC void vSetupHardware( void );
-
-/* ----------------------- Start implementation -----------------------------*/
-int
-main( void )
-{
- vSetupHardware( );
-
- ( void )xTaskCreate( vModbusTask, NULL, configMINIMAL_STACK_SIZE, NULL,
- tskIDLE_PRIORITY, NULL );
-
- vTaskStartScheduler( );
- return 0;
-}
-
-static void
-vModbusTask( void *pvParameters )
-{
- int i;
-
- /* Select either ASCII or RTU Mode. */
- ( void )eMBInit( MB_RTU, 0x0A, 0, 38400, MB_PAR_EVEN );
-
- /* Initialize the holding register values before starting the
- * Modbus stack
- */
- for( i = 0; i < REG_HOLDING_NREGS; i++ )
- {
- usRegHoldingBuf[i] = ( unsigned short )i;
- }
- /* Initialize the input register values before starting the
- * Modbus stack
- */
- for( i = 0; i < REG_INPUT_NREGS; i++ )
- {
- usRegInputBuf[i] = ( unsigned short )i;
- }
-
- /* Enable the Modbus Protocol Stack. */
- ( void )eMBEnable( );
- for( ;; )
- {
- /* Call the main polling loop of the Modbus protocol stack. */
- ( void )eMBPoll( );
- }
-}
-
-eMBErrorCode
-eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs )
-{
- eMBErrorCode eStatus = MB_ENOERR;
- int iRegIndex;
-
- if( ( usAddress >= REG_INPUT_START )
- && ( usAddress + usNRegs <= REG_INPUT_START + REG_INPUT_NREGS ) )
- {
- iRegIndex = ( int )( usAddress - usRegInputStart );
- while( usNRegs > 0 )
- {
- *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] >> 8 );
- *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] & 0xFF );
- iRegIndex++;
- usNRegs--;
- }
- }
- else
- {
- eStatus = MB_ENOREG;
- }
-
- return eStatus;
-}
-
-eMBErrorCode
-eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, eMBRegisterMode eMode )
-{
- eMBErrorCode eStatus = MB_ENOERR;
- int iRegIndex;
-
- if( ( usAddress >= REG_HOLDING_START ) &&
- ( usAddress + usNRegs <= REG_HOLDING_START + REG_HOLDING_NREGS ) )
- {
- iRegIndex = ( int )( usAddress - usRegHoldingStart );
- switch ( eMode )
- {
- /* Pass current register values to the protocol stack. */
- case MB_REG_READ:
- while( usNRegs > 0 )
- {
- *pucRegBuffer++ = ( unsigned char )( usRegHoldingBuf[iRegIndex] >> 8 );
- *pucRegBuffer++ = ( unsigned char )( usRegHoldingBuf[iRegIndex] & 0xFF );
- iRegIndex++;
- usNRegs--;
- }
- break;
-
- /* Update current register values with new values from the
- * protocol stack. */
- case MB_REG_WRITE:
- while( usNRegs > 0 )
- {
- usRegHoldingBuf[iRegIndex] = *pucRegBuffer++ << 8;
- usRegHoldingBuf[iRegIndex] |= *pucRegBuffer++;
- iRegIndex++;
- usNRegs--;
- }
- }
- }
- else
- {
- eStatus = MB_ENOREG;
- }
- return eStatus;
-}
-
-
-eMBErrorCode
-eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, eMBRegisterMode eMode )
-{
- return MB_ENOREG;
-}
-
-eMBErrorCode
-eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete )
-{
- return MB_ENOREG;
-}
-
-
-void
-vSetupHardware( void )
-{
- vMBPInit( );
-
- /* Enable the peripheral clock. */
- AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA;
- AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOB;
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/demo.hzp b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/demo.hzp
deleted file mode 100644
index 6711ff76..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/demo.hzp
+++ /dev/null
@@ -1,115 +0,0 @@
-
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diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/demo.hzs b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/demo.hzs
deleted file mode 100644
index b3e86b6e..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/demo.hzs
+++ /dev/null
@@ -1,105 +0,0 @@
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diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/port.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/port.h
deleted file mode 100644
index 636c923f..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/port.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * FreeModbus Libary: ARM7/AT91SAM7X Port
- * Copyright (C) 2006 Christian Walter
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
- * File: $Id$
- */
-
-#ifndef _PORT_H
-#define _PORT_H
-
-#include
-#include
-
-#include "FreeRTOS.h"
-
-#ifdef _cplusplus
-extern "C"
-{
-#endif
-
-/* ----------------------- Defines ------------------------------------------*/
-
-#define INLINE inline
-#define STATIC static
-
-#define PR_BEGIN_EXTERN_C extern "C" {
-#define PR_END_EXTERN_C }
-
-#define MB_PORT_HAS_CLOSE 1
-#define ENTER_CRITICAL_SECTION( ) vMBPPortEnterCritical( )
-#define EXIT_CRITICAL_SECTION( ) vMBPPortExitCritical( )
-
-#ifndef TRUE
-#define TRUE ( BOOL )1
-#endif
-
-#ifndef FALSE
-#define FALSE ( BOOL )0
-#endif
-
-/* ----------------------- Type definitions ---------------------------------*/
- typedef char BOOL;
-
- typedef signed char BYTE;
- typedef unsigned char UBYTE;
-
- typedef unsigned char UCHAR;
- typedef char CHAR;
-
- typedef unsigned short USHORT;
- typedef short SHORT;
-
- typedef unsigned long ULONG;
- typedef long LONG;
-
-/* ----------------------- Function prototypes ------------------------------*/
- BOOL bMBPIsWithinException( void );
- void vMBPInit( void );
- void vMBPPortEnterCritical( void );
- void vMBPPortExitCritical( void );
-
-#ifdef _cplusplus
-}
-#endif
-
-#endif
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/portevent.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/portevent.c
deleted file mode 100644
index ebbde2ea..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/portevent.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * FreeModbus Libary: ARM7/AT91SAM7X Port
- * Copyright (C) 2006 Christian Walter
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
- * File: $Id$
- */
-/* ----------------------- System includes ----------------------------------*/
-#include
-
-/* ----------------------- Platform includes --------------------------------*/
-#include "FreeRTOS.h"
-#include "task.h"
-#include "queue.h"
-
-/* ----------------------- Modbus includes ----------------------------------*/
-#include "mb.h"
-#include "mbport.h"
-
-/* ----------------------- Defines ------------------------------------------*/
-#define HDL_RESET( x ) do { \
- ( x )->xQueueHdl = 0; \
-} while( 0 );
-
-/* ----------------------- Type definitions ---------------------------------*/
-typedef struct
-{
- xQueueHandle xQueueHdl;
-} xEventInternalHandle;
-
-/* ----------------------- Static variables ---------------------------------*/
-STATIC BOOL bIsInitialized = FALSE;
-STATIC xEventInternalHandle arxEventHdls[1];
-
-/* ----------------------- Static functions ---------------------------------*/
-
-/* ----------------------- Start implementation -----------------------------*/
-
-BOOL
-xMBPortEventInit( void )
-{
- BOOL bOkay = FALSE;
- xQueueHandle xQueueHdl;
-
- ENTER_CRITICAL_SECTION( );
- xQueueHdl = xQueueCreate( 1, sizeof( eMBEventType ) );
- if( 0 != xQueueHdl )
- {
- arxEventHdls[0].xQueueHdl = xQueueHdl;
- bIsInitialized = TRUE;
- bOkay = TRUE;
- }
- EXIT_CRITICAL_SECTION( );
-
- return bOkay;
-}
-
-void
-vMBPortEventClose( )
-{
- ENTER_CRITICAL_SECTION( );
- if( bIsInitialized )
- {
- if( 0 != arxEventHdls[0].xQueueHdl )
- {
- vQueueDelete( arxEventHdls[0].xQueueHdl );
- }
- HDL_RESET( &arxEventHdls[0] );
- }
- EXIT_CRITICAL_SECTION( );
-}
-
-BOOL
-xMBPortEventPost( eMBEventType eEvent )
-{
- portBASE_TYPE xEventSent = pdFALSE;
-
- ENTER_CRITICAL_SECTION( );
- if( bIsInitialized )
- {
- if( bMBPIsWithinException( ) )
- {
- xEventSent =
- xQueueSendFromISR( arxEventHdls[0].xQueueHdl, ( const void * )&eEvent, pdFALSE );
- }
- else
- {
- xEventSent = xQueueSend( arxEventHdls[0].xQueueHdl, ( const void * )&eEvent, pdFALSE );
- }
- }
- EXIT_CRITICAL_SECTION( );
- return xEventSent == pdTRUE ? TRUE : FALSE;
-}
-
-BOOL
-xMBPortEventGet( eMBEventType * peEvent )
-{
- BOOL bEventInQueue = FALSE;
-
- ENTER_CRITICAL_SECTION( );
- if( bIsInitialized )
- {
- if( pdTRUE == xQueueReceive( arxEventHdls[0].xQueueHdl, peEvent, portTICK_RATE_MS * 50 ) )
- {
- bEventInQueue = TRUE;
- }
- }
- EXIT_CRITICAL_SECTION( );
- return bEventInQueue;
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/portother.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/portother.c
deleted file mode 100644
index f881374e..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/portother.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * FreeModbus Libary: ARM7/AT91SAM7X Port
- * Copyright (C) 2006 Christian Walter
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
- * File: $Id$
- */
-
-/* ----------------------- System includes ----------------------------------*/
-#include
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* ----------------------- Platform includes --------------------------------*/
-#include "AT91SAM7X256.h"
-#include "lib_AT91SAM7X256.h"
-
-/* ----------------------- Modbus includes ----------------------------------*/
-#include "port.h"
-
-/* ----------------------- Defines ------------------------------------------*/
-
-/* ----------------------- Type definitions ---------------------------------*/
-
-/* ----------------------- Function prototypes ------------------------------*/
-void vMBPortSerialClose( void );
-void vMBPortEventClose( void );
-void vMBPortTimerClose( void );
-
-/* ----------------------- Static variables ---------------------------------*/
-
-/* ----------------------- Static functions ---------------------------------*/
-STATIC void vDefaultHandler( void ) __attribute__ ( ( interrupt( "IRQ" ) ) );
-STATIC void vDefaultSpuriousHandler( void ) __attribute__ ( ( interrupt( "IRQ" ) ) );
-
-/* ----------------------- Start implementation -----------------------------*/
-
-void
-vMBPInit( void )
-{
- AT91F_AIC_Open( AT91C_BASE_AIC, AT91C_AIC_BRANCH_OPCODE, AT91C_AIC_BRANCH_OPCODE,
- vDefaultHandler, vDefaultSpuriousHandler, AT91C_AIC_DCR_PROT );
-}
-
-void
-__assert( const char *pcFile, const char *pcAssertion, int iLine )
-{
- volatile BOOL bBreakOut = FALSE;
-
- ( void )pcFile;
- ( void )pcAssertion;
- ( void )iLine;
- ENTER_CRITICAL_SECTION( );
- while( !bBreakOut );
-}
-
-BOOL
-bMBPIsWithinException( void )
-{
- BOOL bMBPIsWithinException = TRUE;
- unsigned int uiCPSR;
- asm volatile ( "MRS %0, CPSR":"=r" ( uiCPSR ): );
-
- switch ( uiCPSR & 0x000000001F )
- {
- case 0x00000010U: /* User Mode */
- case 0x0000001FU: /* System Mode */
- bMBPIsWithinException = FALSE;
- break;
- }
- return bMBPIsWithinException;
-}
-
-void
-vMBPPortEnterCritical( void )
-{
- if( !bMBPIsWithinException( ) )
- {
- portENTER_CRITICAL( );
- }
-}
-
-void
-vMBPPortExitCritical( void )
-{
- if( !bMBPIsWithinException( ) )
- {
- portEXIT_CRITICAL( );
- }
-}
-
-void
-vMBPortClose( void )
-{
- vMBPortSerialClose( );
- vMBPortEventClose( );
- vMBPortTimerClose( );
-}
-
-void
-vDefaultSpuriousHandler( void )
-{
-}
-
-void
-vDefaultHandler( void )
-{
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/portserial.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/portserial.c
deleted file mode 100644
index d68d9add..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/portserial.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/*
- * FreeModbus Libary: ARM7/AT91SAM7X Port
- * Copyright (C) 2006 Christian Walter
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
- * File: $Id$
- */
-
-/* ----------------------- System includes ----------------------------------*/
-#include
-#include
-
-/* ----------------------- Platform includes --------------------------------*/
-#include "AT91SAM7X256.h"
-#include "lib_AT91SAM7X256.h"
-
-/* ----------------------- Modbus includes ----------------------------------*/
-#include "mb.h"
-#include "mbport.h"
-
-/* ----------------------- Defines ------------------------------------------*/
-
-#define USART_INTERRUPT_LEVEL ( 7 )
-#define USART_USART0_IDX ( 0 )
-#define USART_USART1_IDX ( 1 )
-
-#define IDX_INVALID ( 255 )
-#define UART_BAUDRATE_MIN ( 300 )
-#define UART_BAUDRATE_MAX ( 115200 )
-
-#define UART_INIT( ubIdx ) do { \
- if( AT91C_ID_US0 == ubIdx ) \
- { \
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, AT91C_PA0_RXD0 | AT91C_PA1_TXD0 | AT91C_PA3_RTS0, 0 ); \
- } \
- else if( AT91C_ID_US1 == ubIdx ) \
- { \
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, AT91C_PA5_RXD1 | AT91C_PA6_TXD1 | AT91C_PA8_RTS1, 0 ); \
- } \
- else \
- { \
- assert( 0 ); \
- } \
-} while( 0 )
-
-#define HDL_RESET( x ) do { \
- ( x )->pxCOM = NULL; \
- ( x )->uiAT91C_ID_USX = 0; \
- ( x )->pvIRQHandlerFN = NULL; \
- ( x )->bIsRxEnabled = FALSE; \
- ( x )->bIsTxEnabled = FALSE; \
-} while( 0 );
-
-/* ----------------------- Type definitions ---------------------------------*/
-
-typedef struct
-{
- AT91PS_USART pxCOM;
- unsigned int uiAT91C_ID_USX;
- volatile BOOL bIsRxEnabled;
- volatile BOOL bIsTxEnabled;
- void ( *pvIRQHandlerFN ) ( void );
-} xMBPSerialIntHandle;
-
-/* ----------------------- Static variables ---------------------------------*/
-STATIC xMBPSerialIntHandle xSerialHdls[1];
-STATIC BOOL bIsInitalized = FALSE;
-
-/* ----------------------- Static functions ---------------------------------*/
-STATIC void vUSART0ISR( void ) __attribute__ ( ( interrupt( "IRQ" ) ) );
-STATIC void vUSART1ISR( void ) __attribute__ ( ( interrupt( "IRQ" ) ) );
-
-/* ----------------------- Start implementation -----------------------------*/
-
-BOOL
-xMBPortSerialInit( UCHAR ucPort, ULONG ulBaudRate, UCHAR ucDataBits, eMBParity eParity )
-{
- BOOL bOkay = TRUE;
- unsigned int uiUARTMode = 0;
-
- ENTER_CRITICAL_SECTION( );
- if( !bIsInitalized )
- {
- HDL_RESET( &xSerialHdls[0] );
- bIsInitalized = TRUE;
- }
-
- uiUARTMode = AT91C_US_USMODE_RS485 | AT91C_US_CLKS_CLOCK;
- switch ( eParity )
- {
- case MB_PAR_NONE:
- uiUARTMode |= AT91C_US_PAR_NONE;
- uiUARTMode |= AT91C_US_NBSTOP_2_BIT;
- break;
- case MB_PAR_EVEN:
- uiUARTMode |= AT91C_US_PAR_EVEN;
- uiUARTMode |= AT91C_US_NBSTOP_1_BIT;
- break;
- case MB_PAR_ODD:
- uiUARTMode |= AT91C_US_PAR_ODD;
- uiUARTMode |= AT91C_US_NBSTOP_1_BIT;
- break;
- default:
- break;
- }
- switch ( ucDataBits )
- {
- case 8:
- uiUARTMode |= AT91C_US_CHRL_8_BITS;
- break;
- case 7:
- uiUARTMode |= AT91C_US_CHRL_7_BITS;
- break;
- default:
- break;
- }
- if( bOkay )
- {
- if( ( ucPort == USART_USART0_IDX ) && ( NULL == xSerialHdls[0].pxCOM ) )
- {
- xSerialHdls[0].pxCOM = AT91C_BASE_US0;
- xSerialHdls[0].uiAT91C_ID_USX = AT91C_ID_US0;
- xSerialHdls[0].pvIRQHandlerFN = vUSART0ISR;
- }
- else if( ( ucPort == USART_USART1_IDX ) && ( NULL == xSerialHdls[0].pxCOM ) )
- {
- xSerialHdls[0].pxCOM = AT91C_BASE_US1;
- xSerialHdls[0].uiAT91C_ID_USX = AT91C_ID_US1;
- xSerialHdls[0].pvIRQHandlerFN = vUSART1ISR;
- }
- else
- {
- bOkay = FALSE;
- }
-
- if( bOkay )
- {
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << xSerialHdls[0].uiAT91C_ID_USX );
- AT91F_US_Configure( xSerialHdls[0].pxCOM, configCPU_CLOCK_HZ, uiUARTMode, ulBaudRate,
- 0 );
- xSerialHdls[0].pxCOM->US_CR = AT91C_US_TXEN | AT91C_US_RXEN;
- AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, xSerialHdls[0].uiAT91C_ID_USX,
- USART_INTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL,
- xSerialHdls[0].pvIRQHandlerFN );
- AT91F_AIC_EnableIt( AT91C_BASE_AIC, xSerialHdls[0].uiAT91C_ID_USX );
- UART_INIT( xSerialHdls[0].uiAT91C_ID_USX );
- }
- }
- else
- {
- bOkay = FALSE;
- }
-
- EXIT_CRITICAL_SECTION( );
- return bOkay;
-}
-
-void
-vMBPortSerialClose( void )
-{
- if( bIsInitalized )
- {
- if( NULL != xSerialHdls[0].pxCOM )
- {
- AT91F_AIC_DisableIt( AT91C_BASE_AIC, xSerialHdls[0].uiAT91C_ID_USX );
- AT91F_US_Close( xSerialHdls[0].pxCOM );
- HDL_RESET( &xSerialHdls[0] );
- }
- }
-}
-
-void
-vMBPortSerialEnable( BOOL xRxEnable, BOOL xTxEnable )
-{
- ENTER_CRITICAL_SECTION( );
- assert( NULL != xSerialHdls[0].pxCOM );
- if( xRxEnable )
- {
- AT91F_US_EnableIt( xSerialHdls[0].pxCOM, AT91C_US_RXRDY );
- xSerialHdls[0].bIsRxEnabled = TRUE;
- }
- else
- {
- AT91F_US_DisableIt( xSerialHdls[0].pxCOM, AT91C_US_RXRDY );
- xSerialHdls[0].bIsRxEnabled = FALSE;
- }
-
- if( xTxEnable )
- {
- AT91F_US_EnableIt( xSerialHdls[0].pxCOM, AT91C_US_TXRDY );
- xSerialHdls[0].bIsTxEnabled = TRUE;
- }
- else
- {
- AT91F_US_DisableIt( xSerialHdls[0].pxCOM, AT91C_US_TXRDY );
- xSerialHdls[0].bIsTxEnabled = FALSE;
- }
- EXIT_CRITICAL_SECTION( );
-}
-
-STATIC INLINE void
-vUSARTIRQHandler( void )
-{
- unsigned int uiUSARTStatus = xSerialHdls[0].pxCOM->US_CSR;
-
- if( xSerialHdls[0].bIsRxEnabled && ( uiUSARTStatus & AT91C_US_RXRDY ) )
- {
- pxMBFrameCBByteReceived( );
- }
- if( xSerialHdls[0].bIsTxEnabled && ( uiUSARTStatus & AT91C_US_TXRDY ) )
- {
- pxMBFrameCBTransmitterEmpty( );
- }
-}
-
-BOOL
-xMBPortSerialPutByte( CHAR ucByte )
-{
- assert( NULL != xSerialHdls[0].pxCOM );
- AT91F_US_PutChar( xSerialHdls[0].pxCOM, ucByte );
- return TRUE;
-}
-
-BOOL
-xMBPortSerialGetByte( CHAR * pucByte )
-{
- assert( NULL != xSerialHdls[0].pxCOM );
- *pucByte = ( CHAR ) AT91F_US_GetChar( xSerialHdls[0].pxCOM );
- return TRUE;
-}
-
-void
-vUSART0ISR( void )
-{
- assert( NULL != xSerialHdls[0].pxCOM );
- vUSARTIRQHandler( );
- AT91C_BASE_AIC->AIC_EOICR = 0;
-}
-
-void
-vUSART1ISR( void )
-{
- assert( NULL != xSerialHdls[0].pxCOM );
- vUSARTIRQHandler( );
- AT91C_BASE_AIC->AIC_EOICR = 0;
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/porttimer.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/porttimer.c
deleted file mode 100644
index 9f266043..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/porttimer.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * MODBUS Library: AT91SAM7X/FreeRTOS port
- * Copyright (c) 2007 Christian Walter
- * All rights reserved.
- *
- * $Id$
- */
-
-/* ----------------------- System includes ----------------------------------*/
-#include
-
-/* ----------------------- FreeRTOS includes --------------------------------*/
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* ----------------------- Platform includes --------------------------------*/
-#include "port.h"
-
-/* ----------------------- Modbus includes ----------------------------------*/
-#include "mb.h"
-#include "mbport.h"
-
-/* ----------------------- Defines ------------------------------------------*/
-#define TIMER_TIMEOUT_INVALID ( 65535U )
-
-/* ----------------------- Type definitions ---------------------------------*/
-typedef struct
-{
- volatile USHORT usNTimeOutMS;
- volatile USHORT usNTimeLeft;
-} xTimerInternalHandle;
-
-/* ----------------------- Static variables ---------------------------------*/
-STATIC xTimerInternalHandle arxTimerHdls[1];
-STATIC BOOL bIsInitalized = FALSE;
-
-/* ----------------------- Static functions ---------------------------------*/
-
-/* ----------------------- Start implementation -----------------------------*/
-
-BOOL
-xMBPortTimersInit( USHORT usTim1Timerout50us )
-{
- USHORT usTimeoutMS;
-
- ENTER_CRITICAL_SECTION( );
- usTimeoutMS = ( usTim1Timerout50us + 10 ) / 20;
- if( 0 == usTimeoutMS )
- {
- usTimeoutMS = 1;
- }
- arxTimerHdls[0].usNTimeOutMS = usTimeoutMS;
- arxTimerHdls[0].usNTimeLeft = TIMER_TIMEOUT_INVALID;
- bIsInitalized = TRUE;
- EXIT_CRITICAL_SECTION( );
-
- return TRUE;
-}
-
-void
-vMBPortTimerClose( void )
-{
- ENTER_CRITICAL_SECTION( );
- if( bIsInitalized )
- {
- arxTimerHdls[0].usNTimeLeft = TIMER_TIMEOUT_INVALID;
- bIsInitalized = FALSE;
- }
- EXIT_CRITICAL_SECTION( );
-}
-
-void
-vMBPortTimersEnable( )
-{
- assert( bIsInitalized );
- ENTER_CRITICAL_SECTION( );
- arxTimerHdls[0].usNTimeLeft = arxTimerHdls[0].usNTimeOutMS;
- EXIT_CRITICAL_SECTION( );
-}
-
-void
-vMBPortTimersDisable( )
-{
- assert( bIsInitalized );
- ENTER_CRITICAL_SECTION( );
- arxTimerHdls[0].usNTimeLeft = TIMER_TIMEOUT_INVALID;
- EXIT_CRITICAL_SECTION( );
-}
-
-void
-vApplicationTickHook( void )
-{
- if( bIsInitalized )
- {
- if( TIMER_TIMEOUT_INVALID != arxTimerHdls[0].usNTimeLeft )
- {
- arxTimerHdls[0].usNTimeLeft--;
- if( 0 == arxTimerHdls[0].usNTimeLeft )
- {
- arxTimerHdls[0].usNTimeLeft = TIMER_TIMEOUT_INVALID;
- pxMBPortCBTimerExpired( );
- }
- }
- }
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/support/AT91SAM7X256.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/support/AT91SAM7X256.h
deleted file mode 100644
index 032a97e5..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/support/AT91SAM7X256.h
+++ /dev/null
@@ -1,2551 +0,0 @@
-// ----------------------------------------------------------------------------
-// ATMEL Microcontroller Software Support - ROUSSET -
-// ----------------------------------------------------------------------------
-// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ----------------------------------------------------------------------------
-// File Name : AT91SAM7X256.h
-// Object : AT91SAM7X256 definitions
-// Generated : AT91 SW Application Group 01/16/2006 (16:36:21)
-//
-// CVS Reference : /AT91SAM7X256.pl/1.15/Wed Nov 2 13:56:49 2005//
-// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005//
-// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
-// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005//
-// CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 14:57:50 2005//
-// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
-// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
-// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
-// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
-// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
-// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
-// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
-// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
-// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
-// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
-// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
-// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
-// CVS Reference : /SSC_6078B.pl/1.1/Wed Jul 13 15:19:19 2005//
-// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
-// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
-// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005//
-// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:05:35 2005//
-// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
-// ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7X256_H
-#define AT91SAM7X256_H
-
-typedef volatile unsigned int AT91_REG; // Hardware register definition
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR System Peripherals
-// *****************************************************************************
-typedef struct _AT91S_SYS
-{
- AT91_REG AIC_SMR[32]; // Source Mode Register
- AT91_REG AIC_SVR[32]; // Source Vector Register
- AT91_REG AIC_IVR; // IRQ Vector Register
- AT91_REG AIC_FVR; // FIQ Vector Register
- AT91_REG AIC_ISR; // Interrupt Status Register
- AT91_REG AIC_IPR; // Interrupt Pending Register
- AT91_REG AIC_IMR; // Interrupt Mask Register
- AT91_REG AIC_CISR; // Core Interrupt Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG AIC_IECR; // Interrupt Enable Command Register
- AT91_REG AIC_IDCR; // Interrupt Disable Command Register
- AT91_REG AIC_ICCR; // Interrupt Clear Command Register
- AT91_REG AIC_ISCR; // Interrupt Set Command Register
- AT91_REG AIC_EOICR; // End of Interrupt Command Register
- AT91_REG AIC_SPU; // Spurious Vector Register
- AT91_REG AIC_DCR; // Debug Control Register (Protect)
- AT91_REG Reserved1[1]; //
- AT91_REG AIC_FFER; // Fast Forcing Enable Register
- AT91_REG AIC_FFDR; // Fast Forcing Disable Register
- AT91_REG AIC_FFSR; // Fast Forcing Status Register
- AT91_REG Reserved2[45]; //
- AT91_REG DBGU_CR; // Control Register
- AT91_REG DBGU_MR; // Mode Register
- AT91_REG DBGU_IER; // Interrupt Enable Register
- AT91_REG DBGU_IDR; // Interrupt Disable Register
- AT91_REG DBGU_IMR; // Interrupt Mask Register
- AT91_REG DBGU_CSR; // Channel Status Register
- AT91_REG DBGU_RHR; // Receiver Holding Register
- AT91_REG DBGU_THR; // Transmitter Holding Register
- AT91_REG DBGU_BRGR; // Baud Rate Generator Register
- AT91_REG Reserved3[7]; //
- AT91_REG DBGU_CIDR; // Chip ID Register
- AT91_REG DBGU_EXID; // Chip ID Extension Register
- AT91_REG DBGU_FNTR; // Force NTRST Register
- AT91_REG Reserved4[45]; //
- AT91_REG DBGU_RPR; // Receive Pointer Register
- AT91_REG DBGU_RCR; // Receive Counter Register
- AT91_REG DBGU_TPR; // Transmit Pointer Register
- AT91_REG DBGU_TCR; // Transmit Counter Register
- AT91_REG DBGU_RNPR; // Receive Next Pointer Register
- AT91_REG DBGU_RNCR; // Receive Next Counter Register
- AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
- AT91_REG DBGU_TNCR; // Transmit Next Counter Register
- AT91_REG DBGU_PTCR; // PDC Transfer Control Register
- AT91_REG DBGU_PTSR; // PDC Transfer Status Register
- AT91_REG Reserved5[54]; //
- AT91_REG PIOA_PER; // PIO Enable Register
- AT91_REG PIOA_PDR; // PIO Disable Register
- AT91_REG PIOA_PSR; // PIO Status Register
- AT91_REG Reserved6[1]; //
- AT91_REG PIOA_OER; // Output Enable Register
- AT91_REG PIOA_ODR; // Output Disable Registerr
- AT91_REG PIOA_OSR; // Output Status Register
- AT91_REG Reserved7[1]; //
- AT91_REG PIOA_IFER; // Input Filter Enable Register
- AT91_REG PIOA_IFDR; // Input Filter Disable Register
- AT91_REG PIOA_IFSR; // Input Filter Status Register
- AT91_REG Reserved8[1]; //
- AT91_REG PIOA_SODR; // Set Output Data Register
- AT91_REG PIOA_CODR; // Clear Output Data Register
- AT91_REG PIOA_ODSR; // Output Data Status Register
- AT91_REG PIOA_PDSR; // Pin Data Status Register
- AT91_REG PIOA_IER; // Interrupt Enable Register
- AT91_REG PIOA_IDR; // Interrupt Disable Register
- AT91_REG PIOA_IMR; // Interrupt Mask Register
- AT91_REG PIOA_ISR; // Interrupt Status Register
- AT91_REG PIOA_MDER; // Multi-driver Enable Register
- AT91_REG PIOA_MDDR; // Multi-driver Disable Register
- AT91_REG PIOA_MDSR; // Multi-driver Status Register
- AT91_REG Reserved9[1]; //
- AT91_REG PIOA_PPUDR; // Pull-up Disable Register
- AT91_REG PIOA_PPUER; // Pull-up Enable Register
- AT91_REG PIOA_PPUSR; // Pull-up Status Register
- AT91_REG Reserved10[1]; //
- AT91_REG PIOA_ASR; // Select A Register
- AT91_REG PIOA_BSR; // Select B Register
- AT91_REG PIOA_ABSR; // AB Select Status Register
- AT91_REG Reserved11[9]; //
- AT91_REG PIOA_OWER; // Output Write Enable Register
- AT91_REG PIOA_OWDR; // Output Write Disable Register
- AT91_REG PIOA_OWSR; // Output Write Status Register
- AT91_REG Reserved12[85]; //
- AT91_REG PIOB_PER; // PIO Enable Register
- AT91_REG PIOB_PDR; // PIO Disable Register
- AT91_REG PIOB_PSR; // PIO Status Register
- AT91_REG Reserved13[1]; //
- AT91_REG PIOB_OER; // Output Enable Register
- AT91_REG PIOB_ODR; // Output Disable Registerr
- AT91_REG PIOB_OSR; // Output Status Register
- AT91_REG Reserved14[1]; //
- AT91_REG PIOB_IFER; // Input Filter Enable Register
- AT91_REG PIOB_IFDR; // Input Filter Disable Register
- AT91_REG PIOB_IFSR; // Input Filter Status Register
- AT91_REG Reserved15[1]; //
- AT91_REG PIOB_SODR; // Set Output Data Register
- AT91_REG PIOB_CODR; // Clear Output Data Register
- AT91_REG PIOB_ODSR; // Output Data Status Register
- AT91_REG PIOB_PDSR; // Pin Data Status Register
- AT91_REG PIOB_IER; // Interrupt Enable Register
- AT91_REG PIOB_IDR; // Interrupt Disable Register
- AT91_REG PIOB_IMR; // Interrupt Mask Register
- AT91_REG PIOB_ISR; // Interrupt Status Register
- AT91_REG PIOB_MDER; // Multi-driver Enable Register
- AT91_REG PIOB_MDDR; // Multi-driver Disable Register
- AT91_REG PIOB_MDSR; // Multi-driver Status Register
- AT91_REG Reserved16[1]; //
- AT91_REG PIOB_PPUDR; // Pull-up Disable Register
- AT91_REG PIOB_PPUER; // Pull-up Enable Register
- AT91_REG PIOB_PPUSR; // Pull-up Status Register
- AT91_REG Reserved17[1]; //
- AT91_REG PIOB_ASR; // Select A Register
- AT91_REG PIOB_BSR; // Select B Register
- AT91_REG PIOB_ABSR; // AB Select Status Register
- AT91_REG Reserved18[9]; //
- AT91_REG PIOB_OWER; // Output Write Enable Register
- AT91_REG PIOB_OWDR; // Output Write Disable Register
- AT91_REG PIOB_OWSR; // Output Write Status Register
- AT91_REG Reserved19[341]; //
- AT91_REG PMC_SCER; // System Clock Enable Register
- AT91_REG PMC_SCDR; // System Clock Disable Register
- AT91_REG PMC_SCSR; // System Clock Status Register
- AT91_REG Reserved20[1]; //
- AT91_REG PMC_PCER; // Peripheral Clock Enable Register
- AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
- AT91_REG PMC_PCSR; // Peripheral Clock Status Register
- AT91_REG Reserved21[1]; //
- AT91_REG PMC_MOR; // Main Oscillator Register
- AT91_REG PMC_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved22[1]; //
- AT91_REG PMC_PLLR; // PLL Register
- AT91_REG PMC_MCKR; // Master Clock Register
- AT91_REG Reserved23[3]; //
- AT91_REG PMC_PCKR[4]; // Programmable Clock Register
- AT91_REG Reserved24[4]; //
- AT91_REG PMC_IER; // Interrupt Enable Register
- AT91_REG PMC_IDR; // Interrupt Disable Register
- AT91_REG PMC_SR; // Status Register
- AT91_REG PMC_IMR; // Interrupt Mask Register
- AT91_REG Reserved25[36]; //
- AT91_REG RSTC_RCR; // Reset Control Register
- AT91_REG RSTC_RSR; // Reset Status Register
- AT91_REG RSTC_RMR; // Reset Mode Register
- AT91_REG Reserved26[5]; //
- AT91_REG RTTC_RTMR; // Real-time Mode Register
- AT91_REG RTTC_RTAR; // Real-time Alarm Register
- AT91_REG RTTC_RTVR; // Real-time Value Register
- AT91_REG RTTC_RTSR; // Real-time Status Register
- AT91_REG PITC_PIMR; // Period Interval Mode Register
- AT91_REG PITC_PISR; // Period Interval Status Register
- AT91_REG PITC_PIVR; // Period Interval Value Register
- AT91_REG PITC_PIIR; // Period Interval Image Register
- AT91_REG WDTC_WDCR; // Watchdog Control Register
- AT91_REG WDTC_WDMR; // Watchdog Mode Register
- AT91_REG WDTC_WDSR; // Watchdog Status Register
- AT91_REG Reserved27[5]; //
- AT91_REG VREG_MR; // Voltage Regulator Mode Register
-} AT91S_SYS , *AT91PS_SYS;
-
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
-// *****************************************************************************
-typedef struct _AT91S_AIC
-{
- AT91_REG AIC_SMR[32]; // Source Mode Register
- AT91_REG AIC_SVR[32]; // Source Vector Register
- AT91_REG AIC_IVR; // IRQ Vector Register
- AT91_REG AIC_FVR; // FIQ Vector Register
- AT91_REG AIC_ISR; // Interrupt Status Register
- AT91_REG AIC_IPR; // Interrupt Pending Register
- AT91_REG AIC_IMR; // Interrupt Mask Register
- AT91_REG AIC_CISR; // Core Interrupt Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG AIC_IECR; // Interrupt Enable Command Register
- AT91_REG AIC_IDCR; // Interrupt Disable Command Register
- AT91_REG AIC_ICCR; // Interrupt Clear Command Register
- AT91_REG AIC_ISCR; // Interrupt Set Command Register
- AT91_REG AIC_EOICR; // End of Interrupt Command Register
- AT91_REG AIC_SPU; // Spurious Vector Register
- AT91_REG AIC_DCR; // Debug Control Register (Protect)
- AT91_REG Reserved1[1]; //
- AT91_REG AIC_FFER; // Fast Forcing Enable Register
- AT91_REG AIC_FFDR; // Fast Forcing Disable Register
- AT91_REG AIC_FFSR; // Fast Forcing Status Register
-} AT91S_AIC , *AT91PS_AIC;
-
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
-#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
-#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
-#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
-#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
-#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
-// *****************************************************************************
-typedef struct _AT91S_PDC
-{
- AT91_REG PDC_RPR; // Receive Pointer Register
- AT91_REG PDC_RCR; // Receive Counter Register
- AT91_REG PDC_TPR; // Transmit Pointer Register
- AT91_REG PDC_TCR; // Transmit Counter Register
- AT91_REG PDC_RNPR; // Receive Next Pointer Register
- AT91_REG PDC_RNCR; // Receive Next Counter Register
- AT91_REG PDC_TNPR; // Transmit Next Pointer Register
- AT91_REG PDC_TNCR; // Transmit Next Counter Register
- AT91_REG PDC_PTCR; // PDC Transfer Control Register
- AT91_REG PDC_PTSR; // PDC Transfer Status Register
-} AT91S_PDC , *AT91PS_PDC;
-
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Debug Unit
-// *****************************************************************************
-typedef struct _AT91S_DBGU
-{
- AT91_REG DBGU_CR; // Control Register
- AT91_REG DBGU_MR; // Mode Register
- AT91_REG DBGU_IER; // Interrupt Enable Register
- AT91_REG DBGU_IDR; // Interrupt Disable Register
- AT91_REG DBGU_IMR; // Interrupt Mask Register
- AT91_REG DBGU_CSR; // Channel Status Register
- AT91_REG DBGU_RHR; // Receiver Holding Register
- AT91_REG DBGU_THR; // Transmitter Holding Register
- AT91_REG DBGU_BRGR; // Baud Rate Generator Register
- AT91_REG Reserved0[7]; //
- AT91_REG DBGU_CIDR; // Chip ID Register
- AT91_REG DBGU_EXID; // Chip ID Extension Register
- AT91_REG DBGU_FNTR; // Force NTRST Register
- AT91_REG Reserved1[45]; //
- AT91_REG DBGU_RPR; // Receive Pointer Register
- AT91_REG DBGU_RCR; // Receive Counter Register
- AT91_REG DBGU_TPR; // Transmit Pointer Register
- AT91_REG DBGU_TCR; // Transmit Counter Register
- AT91_REG DBGU_RNPR; // Receive Next Pointer Register
- AT91_REG DBGU_RNCR; // Receive Next Counter Register
- AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
- AT91_REG DBGU_TNCR; // Transmit Next Counter Register
- AT91_REG DBGU_PTCR; // PDC Transfer Control Register
- AT91_REG DBGU_PTSR; // PDC Transfer Status Register
-} AT91S_DBGU , *AT91PS_DBGU;
-
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type
-#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity
-#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity
-#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)
-#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
-#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity
-#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
-#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
-// *****************************************************************************
-typedef struct _AT91S_PIO
-{
- AT91_REG PIO_PER; // PIO Enable Register
- AT91_REG PIO_PDR; // PIO Disable Register
- AT91_REG PIO_PSR; // PIO Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG PIO_OER; // Output Enable Register
- AT91_REG PIO_ODR; // Output Disable Registerr
- AT91_REG PIO_OSR; // Output Status Register
- AT91_REG Reserved1[1]; //
- AT91_REG PIO_IFER; // Input Filter Enable Register
- AT91_REG PIO_IFDR; // Input Filter Disable Register
- AT91_REG PIO_IFSR; // Input Filter Status Register
- AT91_REG Reserved2[1]; //
- AT91_REG PIO_SODR; // Set Output Data Register
- AT91_REG PIO_CODR; // Clear Output Data Register
- AT91_REG PIO_ODSR; // Output Data Status Register
- AT91_REG PIO_PDSR; // Pin Data Status Register
- AT91_REG PIO_IER; // Interrupt Enable Register
- AT91_REG PIO_IDR; // Interrupt Disable Register
- AT91_REG PIO_IMR; // Interrupt Mask Register
- AT91_REG PIO_ISR; // Interrupt Status Register
- AT91_REG PIO_MDER; // Multi-driver Enable Register
- AT91_REG PIO_MDDR; // Multi-driver Disable Register
- AT91_REG PIO_MDSR; // Multi-driver Status Register
- AT91_REG Reserved3[1]; //
- AT91_REG PIO_PPUDR; // Pull-up Disable Register
- AT91_REG PIO_PPUER; // Pull-up Enable Register
- AT91_REG PIO_PPUSR; // Pull-up Status Register
- AT91_REG Reserved4[1]; //
- AT91_REG PIO_ASR; // Select A Register
- AT91_REG PIO_BSR; // Select B Register
- AT91_REG PIO_ABSR; // AB Select Status Register
- AT91_REG Reserved5[9]; //
- AT91_REG PIO_OWER; // Output Write Enable Register
- AT91_REG PIO_OWDR; // Output Write Disable Register
- AT91_REG PIO_OWSR; // Output Write Status Register
-} AT91S_PIO , *AT91PS_PIO;
-
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Clock Generator Controler
-// *****************************************************************************
-typedef struct _AT91S_CKGR
-{
- AT91_REG CKGR_MOR; // Main Oscillator Register
- AT91_REG CKGR_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved0[1]; //
- AT91_REG CKGR_PLLR; // PLL Register
-} AT91S_CKGR , *AT91PS_CKGR;
-
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
-#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
-#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
-#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Power Management Controler
-// *****************************************************************************
-typedef struct _AT91S_PMC
-{
- AT91_REG PMC_SCER; // System Clock Enable Register
- AT91_REG PMC_SCDR; // System Clock Disable Register
- AT91_REG PMC_SCSR; // System Clock Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG PMC_PCER; // Peripheral Clock Enable Register
- AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
- AT91_REG PMC_PCSR; // Peripheral Clock Status Register
- AT91_REG Reserved1[1]; //
- AT91_REG PMC_MOR; // Main Oscillator Register
- AT91_REG PMC_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved2[1]; //
- AT91_REG PMC_PLLR; // PLL Register
- AT91_REG PMC_MCKR; // Master Clock Register
- AT91_REG Reserved3[3]; //
- AT91_REG PMC_PCKR[4]; // Programmable Clock Register
- AT91_REG Reserved4[4]; //
- AT91_REG PMC_IER; // Interrupt Enable Register
- AT91_REG PMC_IDR; // Interrupt Disable Register
- AT91_REG PMC_SR; // Status Register
- AT91_REG PMC_IMR; // Interrupt Mask Register
-} AT91S_PMC , *AT91PS_PMC;
-
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
-#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
-#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
-#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
-#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
-#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
-#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
-#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
-#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
-#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
-#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Reset Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RSTC
-{
- AT91_REG RSTC_RCR; // Reset Control Register
- AT91_REG RSTC_RSR; // Reset Status Register
- AT91_REG RSTC_RMR; // Reset Mode Register
-} AT91S_RSTC , *AT91PS_RSTC;
-
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type
-#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
-#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
-#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Length
-#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RTTC
-{
- AT91_REG RTTC_RTMR; // Real-time Mode Register
- AT91_REG RTTC_RTAR; // Real-time Alarm Register
- AT91_REG RTTC_RTVR; // Real-time Value Register
- AT91_REG RTTC_RTSR; // Real-time Status Register
-} AT91S_RTTC , *AT91PS_RTTC;
-
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PITC
-{
- AT91_REG PITC_PIMR; // Period Interval Mode Register
- AT91_REG PITC_PISR; // Period Interval Status Register
- AT91_REG PITC_PIVR; // Period Interval Value Register
- AT91_REG PITC_PIIR; // Period Interval Image Register
-} AT91S_PITC , *AT91PS_PITC;
-
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_WDTC
-{
- AT91_REG WDTC_WDCR; // Watchdog Control Register
- AT91_REG WDTC_WDMR; // Watchdog Mode Register
- AT91_REG WDTC_WDSR; // Watchdog Status Register
-} AT91S_WDTC , *AT91PS_WDTC;
-
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_VREG
-{
- AT91_REG VREG_MR; // Voltage Regulator Mode Register
-} AT91S_VREG , *AT91PS_VREG;
-
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Memory Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_MC
-{
- AT91_REG MC_RCR; // MC Remap Control Register
- AT91_REG MC_ASR; // MC Abort Status Register
- AT91_REG MC_AASR; // MC Abort Address Status Register
- AT91_REG Reserved0[21]; //
- AT91_REG MC_FMR; // MC Flash Mode Register
- AT91_REG MC_FCR; // MC Flash Command Register
- AT91_REG MC_FSR; // MC Flash Status Register
-} AT91S_MC , *AT91PS_MC;
-
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
-#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
-#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
-#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
-#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
-#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
-#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
-#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error
-#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error
-#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State
-#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
-#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
-#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
-#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command
-#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
-#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
-#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number
-#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
-#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Serial Parallel Interface
-// *****************************************************************************
-typedef struct _AT91S_SPI
-{
- AT91_REG SPI_CR; // Control Register
- AT91_REG SPI_MR; // Mode Register
- AT91_REG SPI_RDR; // Receive Data Register
- AT91_REG SPI_TDR; // Transmit Data Register
- AT91_REG SPI_SR; // Status Register
- AT91_REG SPI_IER; // Interrupt Enable Register
- AT91_REG SPI_IDR; // Interrupt Disable Register
- AT91_REG SPI_IMR; // Interrupt Mask Register
- AT91_REG Reserved0[4]; //
- AT91_REG SPI_CSR[4]; // Chip Select Register
- AT91_REG Reserved1[48]; //
- AT91_REG SPI_RPR; // Receive Pointer Register
- AT91_REG SPI_RCR; // Receive Counter Register
- AT91_REG SPI_TPR; // Transmit Pointer Register
- AT91_REG SPI_TCR; // Transmit Counter Register
- AT91_REG SPI_RNPR; // Receive Next Pointer Register
- AT91_REG SPI_RNCR; // Receive Next Counter Register
- AT91_REG SPI_TNPR; // Transmit Next Pointer Register
- AT91_REG SPI_TNCR; // Transmit Next Counter Register
- AT91_REG SPI_PTCR; // PDC Transfer Control Register
- AT91_REG SPI_PTSR; // PDC Transfer Status Register
-} AT91S_SPI , *AT91PS_SPI;
-
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
-#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
-#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
-#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
-#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
-#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
-#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
-#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
-#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
-#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
-#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
-#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Usart
-// *****************************************************************************
-typedef struct _AT91S_USART
-{
- AT91_REG US_CR; // Control Register
- AT91_REG US_MR; // Mode Register
- AT91_REG US_IER; // Interrupt Enable Register
- AT91_REG US_IDR; // Interrupt Disable Register
- AT91_REG US_IMR; // Interrupt Mask Register
- AT91_REG US_CSR; // Channel Status Register
- AT91_REG US_RHR; // Receiver Holding Register
- AT91_REG US_THR; // Transmitter Holding Register
- AT91_REG US_BRGR; // Baud Rate Generator Register
- AT91_REG US_RTOR; // Receiver Time-out Register
- AT91_REG US_TTGR; // Transmitter Time-guard Register
- AT91_REG Reserved0[5]; //
- AT91_REG US_FIDI; // FI_DI_Ratio Register
- AT91_REG US_NER; // Nb Errors Register
- AT91_REG Reserved1[1]; //
- AT91_REG US_IF; // IRDA_FILTER Register
- AT91_REG Reserved2[44]; //
- AT91_REG US_RPR; // Receive Pointer Register
- AT91_REG US_RCR; // Receive Counter Register
- AT91_REG US_TPR; // Transmit Pointer Register
- AT91_REG US_TCR; // Transmit Counter Register
- AT91_REG US_RNPR; // Receive Next Pointer Register
- AT91_REG US_RNCR; // Receive Next Counter Register
- AT91_REG US_TNPR; // Transmit Next Pointer Register
- AT91_REG US_TNCR; // Transmit Next Counter Register
- AT91_REG US_PTCR; // PDC Transfer Control Register
- AT91_REG US_PTSR; // PDC Transfer Status Register
-} AT91S_USART , *AT91PS_USART;
-
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
-#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode
-#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal
-#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485
-#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking
-#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem
-#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
-#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
-#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA
-#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
-#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
-#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
-#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
-#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
-#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
-#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
-#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
-#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
-#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_SSC
-{
- AT91_REG SSC_CR; // Control Register
- AT91_REG SSC_CMR; // Clock Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG SSC_RCMR; // Receive Clock ModeRegister
- AT91_REG SSC_RFMR; // Receive Frame Mode Register
- AT91_REG SSC_TCMR; // Transmit Clock Mode Register
- AT91_REG SSC_TFMR; // Transmit Frame Mode Register
- AT91_REG SSC_RHR; // Receive Holding Register
- AT91_REG SSC_THR; // Transmit Holding Register
- AT91_REG Reserved1[2]; //
- AT91_REG SSC_RSHR; // Receive Sync Holding Register
- AT91_REG SSC_TSHR; // Transmit Sync Holding Register
- AT91_REG Reserved2[2]; //
- AT91_REG SSC_SR; // Status Register
- AT91_REG SSC_IER; // Interrupt Enable Register
- AT91_REG SSC_IDR; // Interrupt Disable Register
- AT91_REG SSC_IMR; // Interrupt Mask Register
- AT91_REG Reserved3[44]; //
- AT91_REG SSC_RPR; // Receive Pointer Register
- AT91_REG SSC_RCR; // Receive Counter Register
- AT91_REG SSC_TPR; // Transmit Pointer Register
- AT91_REG SSC_TCR; // Transmit Counter Register
- AT91_REG SSC_RNPR; // Receive Next Pointer Register
- AT91_REG SSC_RNCR; // Receive Next Counter Register
- AT91_REG SSC_TNPR; // Transmit Next Pointer Register
- AT91_REG SSC_TNCR; // Transmit Next Counter Register
- AT91_REG SSC_PTCR; // PDC Transfer Control Register
- AT91_REG SSC_PTSR; // PDC Transfer Status Register
-} AT91S_SSC , *AT91PS_SSC;
-
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection
-#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock
-#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal
-#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_CKG ((unsigned int) 0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection
-#define AT91C_SSC_CKG_NONE ((unsigned int) 0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
-#define AT91C_SSC_CKG_LOW ((unsigned int) 0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low
-#define AT91C_SSC_CKG_HIGH ((unsigned int) 0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High
-#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection
-#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start
-#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input
-#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input
-#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input
-#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input
-#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input
-#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input
-#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0
-#define AT91C_SSC_STOP ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection
-#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length
-#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_CP0 ((unsigned int) 0x1 << 8) // (SSC) Compare 0
-#define AT91C_SSC_CP1 ((unsigned int) 0x1 << 9) // (SSC) Compare 1
-#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Two-wire Interface
-// *****************************************************************************
-typedef struct _AT91S_TWI
-{
- AT91_REG TWI_CR; // Control Register
- AT91_REG TWI_MMR; // Master Mode Register
- AT91_REG Reserved0[1]; //
- AT91_REG TWI_IADR; // Internal Address Register
- AT91_REG TWI_CWGR; // Clock Waveform Generator Register
- AT91_REG Reserved1[3]; //
- AT91_REG TWI_SR; // Status Register
- AT91_REG TWI_IER; // Interrupt Enable Register
- AT91_REG TWI_IDR; // Interrupt Disable Register
- AT91_REG TWI_IMR; // Interrupt Mask Register
- AT91_REG TWI_RHR; // Receive Holding Register
- AT91_REG TWI_THR; // Transmit Holding Register
-} AT91S_TWI , *AT91PS_TWI;
-
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size
-#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address
-#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address
-#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address
-#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR PWMC Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC_CH
-{
- AT91_REG PWMC_CMR; // Channel Mode Register
- AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
- AT91_REG PWMC_CPRDR; // Channel Period Register
- AT91_REG PWMC_CCNTR; // Channel Counter Register
- AT91_REG PWMC_CUPDR; // Channel Update Register
- AT91_REG PWMC_Reserved[3]; // Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH)
-#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH)
-#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC
-{
- AT91_REG PWMC_MR; // PWMC Mode Register
- AT91_REG PWMC_ENA; // PWMC Enable Register
- AT91_REG PWMC_DIS; // PWMC Disable Register
- AT91_REG PWMC_SR; // PWMC Status Register
- AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
- AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
- AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
- AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
- AT91_REG Reserved0[55]; //
- AT91_REG PWMC_VR; // PWMC Version Register
- AT91_REG Reserved1[64]; //
- AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel
-} AT91S_PWMC , *AT91PS_PWMC;
-
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A
-#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC)
-#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR USB Device Interface
-// *****************************************************************************
-typedef struct _AT91S_UDP
-{
- AT91_REG UDP_NUM; // Frame Number Register
- AT91_REG UDP_GLBSTATE; // Global State Register
- AT91_REG UDP_FADDR; // Function Address Register
- AT91_REG Reserved0[1]; //
- AT91_REG UDP_IER; // Interrupt Enable Register
- AT91_REG UDP_IDR; // Interrupt Disable Register
- AT91_REG UDP_IMR; // Interrupt Mask Register
- AT91_REG UDP_ISR; // Interrupt Status Register
- AT91_REG UDP_ICR; // Interrupt Clear Register
- AT91_REG Reserved1[1]; //
- AT91_REG UDP_RSTEP; // Reset Endpoint Register
- AT91_REG Reserved2[1]; //
- AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
- AT91_REG Reserved3[2]; //
- AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
- AT91_REG Reserved4[3]; //
- AT91_REG UDP_TXVC; // Transceiver Control Register
-} AT91S_UDP , *AT91PS_UDP;
-
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured
-#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type
-#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control
-#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT
-#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT
-#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT
-#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN
-#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN
-#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP)
-#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_TC
-{
- AT91_REG TC_CCR; // Channel Control Register
- AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
- AT91_REG Reserved0[2]; //
- AT91_REG TC_CV; // Counter Value
- AT91_REG TC_RA; // Register A
- AT91_REG TC_RB; // Register B
- AT91_REG TC_RC; // Register C
- AT91_REG TC_SR; // Status Register
- AT91_REG TC_IER; // Interrupt Enable Register
- AT91_REG TC_IDR; // Interrupt Disable Register
- AT91_REG TC_IMR; // Interrupt Mask Register
-} AT91S_TC , *AT91PS_TC;
-
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection
-#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0
-#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1
-#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert
-#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection
-#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal
-#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock
-#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock
-#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection
-#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
-#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
-#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
-#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
-#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
-#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
-#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
-#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
-#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
-#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
-#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
-#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
-#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None
-#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
-#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
-#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
-#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
-#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None
-#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
-#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
-#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
-#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
-#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
-#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
-#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
-#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
-#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
-#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
-#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
-#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
-#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
-#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
-#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
-#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
-#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
-#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
-#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
-#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
-#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
-#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
-#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
-#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
-#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
-#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
-#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
-#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
-#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
-#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Timer Counter Interface
-// *****************************************************************************
-typedef struct _AT91S_TCB
-{
- AT91S_TC TCB_TC0; // TC Channel 0
- AT91_REG Reserved0[4]; //
- AT91S_TC TCB_TC1; // TC Channel 1
- AT91_REG Reserved1[4]; //
- AT91S_TC TCB_TC2; // TC Channel 2
- AT91_REG Reserved2[4]; //
- AT91_REG TCB_BCR; // TC Block Control Register
- AT91_REG TCB_BMR; // TC Block Mode Register
-} AT91S_TCB , *AT91PS_TCB;
-
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection
-#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
-#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
-#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
-#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection
-#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
-#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
-#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
-#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection
-#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
-#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
-#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
-#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN_MB
-{
- AT91_REG CAN_MB_MMR; // MailBox Mode Register
- AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register
- AT91_REG CAN_MB_MID; // MailBox ID Register
- AT91_REG CAN_MB_MFID; // MailBox Family ID Register
- AT91_REG CAN_MB_MSR; // MailBox Status Register
- AT91_REG CAN_MB_MDL; // MailBox Data Low Register
- AT91_REG CAN_MB_MDH; // MailBox Data High Register
- AT91_REG CAN_MB_MCR; // MailBox Control Register
-} AT91S_CAN_MB , *AT91PS_CAN_MB;
-
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
-#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB)
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
-#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
-#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
-#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Control Area Network Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN
-{
- AT91_REG CAN_MR; // Mode Register
- AT91_REG CAN_IER; // Interrupt Enable Register
- AT91_REG CAN_IDR; // Interrupt Disable Register
- AT91_REG CAN_IMR; // Interrupt Mask Register
- AT91_REG CAN_SR; // Status Register
- AT91_REG CAN_BR; // Baudrate Register
- AT91_REG CAN_TIM; // Timer Register
- AT91_REG CAN_TIMESTP; // Time Stamp Register
- AT91_REG CAN_ECR; // Error Counter Register
- AT91_REG CAN_TCR; // Transfer Command Register
- AT91_REG CAN_ACR; // Abort Command Register
- AT91_REG Reserved0[52]; //
- AT91_REG CAN_VR; // Version Register
- AT91_REG Reserved1[64]; //
- AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0
- AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1
- AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2
- AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3
- AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4
- AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5
- AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6
- AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7
- AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8
- AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9
- AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10
- AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11
- AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12
- AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13
- AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14
- AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15
-} AT91S_CAN , *AT91PS_CAN;
-
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
-#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
-#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
-#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
-#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
-#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
-#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
-#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
-// *****************************************************************************
-typedef struct _AT91S_EMAC
-{
- AT91_REG EMAC_NCR; // Network Control Register
- AT91_REG EMAC_NCFGR; // Network Configuration Register
- AT91_REG EMAC_NSR; // Network Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG EMAC_TSR; // Transmit Status Register
- AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer
- AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer
- AT91_REG EMAC_RSR; // Receive Status Register
- AT91_REG EMAC_ISR; // Interrupt Status Register
- AT91_REG EMAC_IER; // Interrupt Enable Register
- AT91_REG EMAC_IDR; // Interrupt Disable Register
- AT91_REG EMAC_IMR; // Interrupt Mask Register
- AT91_REG EMAC_MAN; // PHY Maintenance Register
- AT91_REG EMAC_PTR; // Pause Time Register
- AT91_REG EMAC_PFR; // Pause Frames received Register
- AT91_REG EMAC_FTO; // Frames Transmitted OK Register
- AT91_REG EMAC_SCF; // Single Collision Frame Register
- AT91_REG EMAC_MCF; // Multiple Collision Frame Register
- AT91_REG EMAC_FRO; // Frames Received OK Register
- AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register
- AT91_REG EMAC_ALE; // Alignment Error Register
- AT91_REG EMAC_DTF; // Deferred Transmission Frame Register
- AT91_REG EMAC_LCOL; // Late Collision Register
- AT91_REG EMAC_ECOL; // Excessive Collision Register
- AT91_REG EMAC_TUND; // Transmit Underrun Error Register
- AT91_REG EMAC_CSE; // Carrier Sense Error Register
- AT91_REG EMAC_RRE; // Receive Ressource Error Register
- AT91_REG EMAC_ROV; // Receive Overrun Errors Register
- AT91_REG EMAC_RSE; // Receive Symbol Errors Register
- AT91_REG EMAC_ELE; // Excessive Length Errors Register
- AT91_REG EMAC_RJA; // Receive Jabbers Register
- AT91_REG EMAC_USF; // Undersize Frames Register
- AT91_REG EMAC_STE; // SQE Test Error Register
- AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register
- AT91_REG EMAC_TPF; // Transmitted Pause Frames Register
- AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]
- AT91_REG EMAC_HRT; // Hash Address Top[63:32]
- AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes
- AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes
- AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes
- AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes
- AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes
- AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes
- AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes
- AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes
- AT91_REG EMAC_TID; // Type ID Checking Register
- AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register
- AT91_REG EMAC_USRIO; // USER Input/Output Register
- AT91_REG EMAC_WOL; // Wake On LAN Register
- AT91_REG Reserved1[13]; //
- AT91_REG EMAC_REV; // Revision Register
-} AT91S_EMAC , *AT91PS_EMAC;
-
-// -------- EMAC_NCR : (EMAC Offset: 0x0) --------
-#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local.
-#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable.
-#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable.
-#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable.
-#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers.
-#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers.
-#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers.
-#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure.
-#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission.
-#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt.
-#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame
-#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
-// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
-#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed.
-#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex.
-#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames.
-#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames.
-#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast.
-#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable
-#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable.
-#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes.
-#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable.
-#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC)
-#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
-#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
-#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
-#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC)
-#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC)
-#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
-#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
-#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
-#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
-#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
-#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
-#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC)
-#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
-// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
-#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC)
-#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC)
-#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC)
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
-#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC)
-#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC)
-#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC)
-#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go
-#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame
-#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC)
-#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC)
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
-#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC)
-#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC)
-#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC)
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
-#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC)
-#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC)
-#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC)
-#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC)
-#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC)
-#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC)
-#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC)
-#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC)
-#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC)
-#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC)
-#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC)
-#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC)
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
-#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC)
-#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC)
-#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC)
-#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC)
-#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC)
-#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC)
-// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
-#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII
-#define AT91C_EMAC_CLKEN ((unsigned int) 0x1 << 1) // (EMAC) Clock Enable
-// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
-#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address
-#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
-#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
-#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
-// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
-#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC)
-#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC)
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
-// *****************************************************************************
-typedef struct _AT91S_ADC
-{
- AT91_REG ADC_CR; // ADC Control Register
- AT91_REG ADC_MR; // ADC Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG ADC_CHER; // ADC Channel Enable Register
- AT91_REG ADC_CHDR; // ADC Channel Disable Register
- AT91_REG ADC_CHSR; // ADC Channel Status Register
- AT91_REG ADC_SR; // ADC Status Register
- AT91_REG ADC_LCDR; // ADC Last Converted Data Register
- AT91_REG ADC_IER; // ADC Interrupt Enable Register
- AT91_REG ADC_IDR; // ADC Interrupt Disable Register
- AT91_REG ADC_IMR; // ADC Interrupt Mask Register
- AT91_REG ADC_CDR0; // ADC Channel Data Register 0
- AT91_REG ADC_CDR1; // ADC Channel Data Register 1
- AT91_REG ADC_CDR2; // ADC Channel Data Register 2
- AT91_REG ADC_CDR3; // ADC Channel Data Register 3
- AT91_REG ADC_CDR4; // ADC Channel Data Register 4
- AT91_REG ADC_CDR5; // ADC Channel Data Register 5
- AT91_REG ADC_CDR6; // ADC Channel Data Register 6
- AT91_REG ADC_CDR7; // ADC Channel Data Register 7
- AT91_REG Reserved1[44]; //
- AT91_REG ADC_RPR; // Receive Pointer Register
- AT91_REG ADC_RCR; // Receive Counter Register
- AT91_REG ADC_TPR; // Transmit Pointer Register
- AT91_REG ADC_TCR; // Transmit Counter Register
- AT91_REG ADC_RNPR; // Receive Next Pointer Register
- AT91_REG ADC_RNCR; // Receive Next Counter Register
- AT91_REG ADC_TNPR; // Transmit Next Pointer Register
- AT91_REG ADC_TNCR; // Transmit Next Counter Register
- AT91_REG ADC_PTCR; // PDC Transfer Control Register
- AT91_REG ADC_PTSR; // PDC Transfer Status Register
-} AT91S_ADC , *AT91PS_ADC;
-
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset
-#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable
-#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection
-#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
-#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
-#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
-#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
-#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
-#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
-#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.
-#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution
-#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
-#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode
-#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
-// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
-#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
-#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
-#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
-#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4
-#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5
-#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6
-#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7
-// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-
-// *****************************************************************************
-// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ==========
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
-#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
-#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
-#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
-// ========== Register definition for PIOB peripheral ==========
-#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
-#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
-#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
-#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
-#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
-#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
-#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
-#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
-// ========== Register definition for VREG peripheral ==========
-#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
-#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
-// ========== Register definition for PDC_SPI1 peripheral ==========
-#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-// ========== Register definition for SPI1 peripheral ==========
-#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register
-#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register
-// ========== Register definition for PDC_SPI0 peripheral ==========
-#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-// ========== Register definition for SPI0 peripheral ==========
-#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register
-#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
-#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
-// ========== Register definition for PDC_SSC peripheral ==========
-#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
-// ========== Register definition for SSC peripheral ==========
-#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
-#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
-#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
-#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
-#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
-#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
-#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
-#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
-// ========== Register definition for TCB peripheral ==========
-#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for CAN_MB0 peripheral ==========
-#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register
-#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
-#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
-#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register
-#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register
-#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register
-#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register
-// ========== Register definition for CAN_MB1 peripheral ==========
-#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register
-#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
-#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
-#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register
-#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register
-#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register
-#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register
-// ========== Register definition for CAN_MB2 peripheral ==========
-#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register
-#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
-#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
-#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register
-#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register
-#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register
-#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register
-// ========== Register definition for CAN_MB3 peripheral ==========
-#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register
-#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
-#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
-#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register
-#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register
-#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register
-#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register
-// ========== Register definition for CAN_MB4 peripheral ==========
-#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register
-#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
-#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
-#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register
-#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register
-#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register
-#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register
-// ========== Register definition for CAN_MB5 peripheral ==========
-#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register
-#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
-#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
-#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
-#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register
-#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register
-#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
-// ========== Register definition for CAN_MB6 peripheral ==========
-#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
-#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register
-#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register
-#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
-#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register
-#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
-#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
-// ========== Register definition for CAN_MB7 peripheral ==========
-#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
-#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register
-#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register
-#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
-#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register
-#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
-#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
-#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
-// ========== Register definition for CAN peripheral ==========
-#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register
-#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register
-#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register
-#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register
-#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register
-#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register
-#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register
-#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register
-#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register
-#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register
-#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register
-#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register
-// ========== Register definition for EMAC peripheral ==========
-#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register
-#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
-#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register
-#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register
-#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
-#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
-#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
-#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
-#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
-#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register
-#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
-#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register
-#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register
-#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
-#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register
-#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register
-#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
-#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register
-#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register
-#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register
-#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
-#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register
-#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32]
-#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register
-#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
-#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
-#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
-#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register
-#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register
-// ========== Register definition for PDC_ADC peripheral ==========
-#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ==========
-#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
-
-// *****************************************************************************
-// PIO DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0
-#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data
-#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1
-#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data
-#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data
-#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock
-#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_SPI0_NPCS0 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
-#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
-#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1
-#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
-#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1
-#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
-#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input
-#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_SPI0_MISO ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave
-#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_SPI0_MOSI ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave
-#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_SPI0_SPCK ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock
-#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive
-#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2
-#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock
-#define AT91C_PA2_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit
-#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync
-#define AT91C_PA21_SPI1_NPCS0 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
-#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock
-#define AT91C_PA22_SPI1_SPCK ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock
-#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data
-#define AT91C_PA23_SPI1_MOSI ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave
-#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data
-#define AT91C_PA24_SPI1_MISO ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave
-#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock
-#define AT91C_PA25_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync
-#define AT91C_PA26_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data
-#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3
-#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data
-#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input
-#define AT91C_PA29_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3
-#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send
-#define AT91C_PA3_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0
-#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4
-#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send
-#define AT91C_PA4_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data
-#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data
-#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7
-#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock
-#define AT91C_PA7_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8
-#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send
-#define AT91C_PA8_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9
-#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send
-#define AT91C_PA9_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0
-#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0
-#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1
-#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
-#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
-#define AT91C_PB10_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
-#define AT91C_PB11_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
-#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input
-#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
-#define AT91C_PB13_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
-#define AT91C_PB14_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_ERXDV_ECRSDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected
-#define AT91C_PB16_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock
-#define AT91C_PB17_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger
-#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0
-#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input
-#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2
-#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1
-#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0
-#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2
-#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1
-#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3
-#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2
-#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready
-#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready
-#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator
-#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0
-#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1
-#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1
-#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2
-#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3
-#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30
-#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2
-#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3
-#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4
-#define AT91C_PB4_ECRS ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5
-#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
-#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6
-#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
-#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7
-#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error
-#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8
-#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
-#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9
-#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
-
-// *****************************************************************************
-// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral
-#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A
-#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B
-#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1
-#define AT91C_ID_US0 ((unsigned int) 6) // USART 0
-#define AT91C_ID_US1 ((unsigned int) 7) // USART 1
-#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller
-#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface
-#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller
-#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port
-#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0
-#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1
-#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2
-#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller
-#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC
-#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter
-#define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved
-#define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved
-#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
-#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
-#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
-#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
-#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
-#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
-#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
-#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
-#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
-#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
-#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
-#define AT91C_ALL_INT ((unsigned int) 0xC003FFFF) // ALL VALID INTERRUPTS
-
-// *****************************************************************************
-// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address
-#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address
-#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address
-#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address
-#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address
-#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address
-#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address
-#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address
-#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address
-#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address
-#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address
-#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
-
-// *****************************************************************************
-// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-// ISRAM
-#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbytes)
-// IFLASH
-#define AT91C_IFLASH ((char *) 0x00100000) // Internal FLASH base address
-#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal FLASH size in byte (256 Kbytes)
-#define AT91C_IFLASH_PAGE_SIZE ((unsigned int) 256) // Internal FLASH Page Size: 256 bytes
-#define AT91C_IFLASH_LOCK_REGION_SIZE ((unsigned int) 16384) // Internal FLASH Lock Region Size: 16 Kbytes
-#define AT91C_IFLASH_NB_OF_PAGES ((unsigned int) 1024) // Internal FLASH Number of Pages: 1024 bytes
-#define AT91C_IFLASH_NB_OF_LOCK_BITS ((unsigned int) 16) // Internal FLASH Number of Lock Bits: 16 bytes
-
-#endif
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/support/AT91SAM7_target.js b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/support/AT91SAM7_target.js
deleted file mode 100644
index 3fc546e1..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/support/AT91SAM7_target.js
+++ /dev/null
@@ -1,64 +0,0 @@
-/******************************************************************************
- Target Script for Atmel AT91SAM7.
-
- Copyright (c) 2007 Rowley Associates Limited.
-
- This file may be distributed under the terms of the License Agreement
- provided with this software.
-
- THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE
- WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- ******************************************************************************/
-
-function Reset()
-{
- /* Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF; */
- TargetInterface.pokeWord(0xffffffff,0xFFFFF124);
- TargetInterface.pokeWord(0xffffffff,0xFFFFF128);
- /* disable peripheral clock Peripheral Clock Disable Register */
- TargetInterface.pokeWord(0xffffffff,0xFFFFFC14);
-
- /* Reset and stop target */
- TargetInterface.stopAndReset(1);
-
- CKGR_MOR_VAL = 0x00004001;
- CKGR_PLLR_VAL = 0x10483F0E; /* Set up the PLL (MCK, UDPCK = 18.432MHz * 73 / 14 / 2 = 48.05486MHz) */
- CKGR_MCKR_VAL1 = 0x00000004;
- CKGR_MCKR_VAL2 = 0x00000007;
-
- if (TargetInterface.setMaximumJTAGFrequency)
- {
- /* Configure Clock (post 1.6 version) */
- TargetInterface.setMaximumJTAGFrequency(32768);
- TargetInterface.pokeWord(0xFFFFFC20, CKGR_MOR_VAL);
- TargetInterface.pokeWord(0xFFFFFC2C, CKGR_PLLR_VAL);
- TargetInterface.pokeWord(0xFFFFFC30, CKGR_MCKR_VAL1);
- TargetInterface.pokeWord(0xFFFFFC30, CKGR_MCKR_VAL2);
- TargetInterface.setMaximumJTAGFrequency(10000000);
- }
- else
- {
- /* Configure Clock (1.6 version) */
- TargetInterface.pokeWord(0xFFFFFC20, CKGR_MOR_VAL);
- TargetInterface.delay(10);
- TargetInterface.pokeWord(0xFFFFFC2C, CKGR_PLLR_VAL);
- TargetInterface.delay(10);
- TargetInterface.pokeWord(0xFFFFFC30, CKGR_MCKR_VAL1);
- TargetInterface.delay(10);
- TargetInterface.pokeWord(0xFFFFFC30, CKGR_MCKR_VAL2);
- TargetInterface.delay(10);
- }
-}
-
-function RAMReset()
-{
- Reset();
- /* Remap SRAM to 0x00000000 */
- TargetInterface.pokeWord(0xFFFFFF00, 1); // MC_RCR
-}
-
-function FLASHReset()
-{
- Reset();
-}
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/support/lib_AT91SAM7X256.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/support/lib_AT91SAM7X256.h
deleted file mode 100644
index 69c2a0b2..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/support/lib_AT91SAM7X256.h
+++ /dev/null
@@ -1,4119 +0,0 @@
-//* ----------------------------------------------------------------------------
-//* ATMEL Microcontroller Software Support - ROUSSET -
-//* ----------------------------------------------------------------------------
-//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//* ----------------------------------------------------------------------------
-//* File Name : lib_AT91SAM7X256.h
-//* Object : AT91SAM7X256 inlined functions
-//* Generated : AT91 SW Application Group 01/16/2006 (16:36:21)
-//*
-//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
-//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002//
-//* CVS Reference : /lib_dbgu.h/1.1/Thu Aug 25 12:56:22 2005//
-//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005//
-//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
-//* CVS Reference : /lib_spi2.h/1.2/Tue Aug 23 15:37:28 2005//
-//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
-//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
-//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004//
-//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
-//* CVS Reference : /lib_pmc_SAM7X.h/1.5/Fri Nov 4 09:41:32 2005//
-//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004//
-//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004//
-//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
-//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
-//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004//
-//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
-//* CVS Reference : /lib_udp.h/1.5/Tue Aug 30 12:13:47 2005//
-//* CVS Reference : /lib_aic_6075b.h/1.2/Thu Jul 7 07:48:22 2005//
-//* CVS Reference : /lib_can_AT91.h/1.5/Tue Aug 23 15:37:07 2005//
-//* ----------------------------------------------------------------------------
-
-#ifndef lib_AT91SAM7X256_H
-#define lib_AT91SAM7X256_H
-
-#include "AT91SAM7X256.h"
-
-/* *****************************************************************************
- SOFTWARE API FOR AIC
- ***************************************************************************** */
-#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_ConfigureIt
-//* \brief Interrupt Handler Initialization
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_AIC_ConfigureIt( AT91PS_AIC pAic, // \arg pointer to the AIC registers
- unsigned int irq_id, // \arg interrupt number to initialize
- unsigned int priority, // \arg priority to give to the interrupt
- unsigned int src_type, // \arg activation and sense of activation
- void ( *newHandler ) ( ) ) // \arg address of the interrupt handler
-{
- unsigned int oldHandler;
- unsigned int mask;
-
- oldHandler = pAic->AIC_SVR[irq_id];
-
- mask = 0x1 << irq_id;
- //* Disable the interrupt on the interrupt controller
- pAic->AIC_IDCR = mask;
- //* Save the interrupt handler routine pointer and the interrupt priority
- pAic->AIC_SVR[irq_id] = ( unsigned int )newHandler;
- //* Store the Source Mode Register
- pAic->AIC_SMR[irq_id] = src_type | priority;
- //* Clear the interrupt on the interrupt controller
- pAic->AIC_ICCR = mask;
-
- return oldHandler;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_EnableIt
-//* \brief Enable corresponding IT number
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_AIC_EnableIt( AT91PS_AIC pAic, // \arg pointer to the AIC registers
- unsigned int irq_id ) // \arg interrupt number to initialize
-{
- //* Enable the interrupt on the interrupt controller
- pAic->AIC_IECR = 0x1 << irq_id;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_DisableIt
-//* \brief Disable corresponding IT number
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_AIC_DisableIt( AT91PS_AIC pAic, // \arg pointer to the AIC registers
- unsigned int irq_id ) // \arg interrupt number to initialize
-{
- unsigned int mask = 0x1 << irq_id;
-
- //* Disable the interrupt on the interrupt controller
- pAic->AIC_IDCR = mask;
- //* Clear the interrupt on the Interrupt Controller ( if one is pending )
- pAic->AIC_ICCR = mask;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_ClearIt
-//* \brief Clear corresponding IT number
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_AIC_ClearIt( AT91PS_AIC pAic, // \arg pointer to the AIC registers
- unsigned int irq_id ) // \arg interrupt number to initialize
-{
- //* Clear the interrupt on the Interrupt Controller ( if one is pending )
- pAic->AIC_ICCR = ( 0x1 << irq_id );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_AcknowledgeIt
-//* \brief Acknowledge corresponding IT number
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_AIC_AcknowledgeIt( AT91PS_AIC pAic ) // \arg pointer to the AIC registers
-{
- pAic->AIC_EOICR = pAic->AIC_EOICR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_SetExceptionVector
-//* \brief Configure vector handler
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_AIC_SetExceptionVector( unsigned int *pVector, // \arg pointer to the AIC registers
- void ( *Handler ) ( ) ) // \arg Interrupt Handler
-{
- unsigned int oldVector = *pVector;
-
- if( ( unsigned int )Handler == ( unsigned int )AT91C_AIC_BRANCH_OPCODE )
- *pVector = ( unsigned int )AT91C_AIC_BRANCH_OPCODE;
- else
- *pVector =
- ( ( ( ( ( unsigned int )Handler ) - ( ( unsigned int )pVector ) - 0x8 ) >> 2 ) & 0x00FFFFFF ) | 0xEA000000;
-
- return oldVector;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_Trig
-//* \brief Trig an IT
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_AIC_Trig( AT91PS_AIC pAic, // \arg pointer to the AIC registers
- unsigned int irq_id ) // \arg interrupt number
-{
- pAic->AIC_ISCR = ( 0x1 << irq_id );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_IsActive
-//* \brief Test if an IT is active
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_AIC_IsActive( AT91PS_AIC pAic, // \arg pointer to the AIC registers
- unsigned int irq_id ) // \arg Interrupt Number
-{
- return ( pAic->AIC_ISR & ( 0x1 << irq_id ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_IsPending
-//* \brief Test if an IT is pending
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_AIC_IsPending( AT91PS_AIC pAic, // \arg pointer to the AIC registers
- unsigned int irq_id ) // \arg Interrupt Number
-{
- return ( pAic->AIC_IPR & ( 0x1 << irq_id ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_Open
-//* \brief Set exception vectors and AIC registers to default values
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_AIC_Open( AT91PS_AIC pAic, // \arg pointer to the AIC registers
- void ( *IrqHandler ) ( ), // \arg Default IRQ vector exception
- void ( *FiqHandler ) ( ), // \arg Default FIQ vector exception
- void ( *DefaultHandler ) ( ), // \arg Default Handler set in ISR
- void ( *SpuriousHandler ) ( ), // \arg Default Spurious Handler
- unsigned int protectMode ) // \arg Debug Control Register
-{
- int i;
-
- // Disable all interrupts and set IVR to the default handler
- for( i = 0; i < 32; ++i )
- {
- AT91F_AIC_DisableIt( pAic, i );
- AT91F_AIC_ConfigureIt( pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler );
- }
-
- // Set the IRQ exception vector
- AT91F_AIC_SetExceptionVector( ( unsigned int * )0x18, IrqHandler );
- // Set the Fast Interrupt exception vector
- AT91F_AIC_SetExceptionVector( ( unsigned int * )0x1C, FiqHandler );
-
- pAic->AIC_SPU = ( unsigned int )SpuriousHandler;
- pAic->AIC_DCR = protectMode;
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR PDC
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_SetNextRx
-//* \brief Set the next receive transfer descriptor
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, // \arg pointer to a PDC controller
- char *address, // \arg address to the next bloc to be received
- unsigned int bytes ) // \arg number of bytes to be received
-{
- pPDC->PDC_RNPR = ( unsigned int )address;
- pPDC->PDC_RNCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_SetNextTx
-//* \brief Set the next transmit transfer descriptor
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, // \arg pointer to a PDC controller
- char *address, // \arg address to the next bloc to be transmitted
- unsigned int bytes ) // \arg number of bytes to be transmitted
-{
- pPDC->PDC_TNPR = ( unsigned int )address;
- pPDC->PDC_TNCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_SetRx
-//* \brief Set the receive transfer descriptor
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PDC_SetRx( AT91PS_PDC pPDC, // \arg pointer to a PDC controller
- char *address, // \arg address to the next bloc to be received
- unsigned int bytes ) // \arg number of bytes to be received
-{
- pPDC->PDC_RPR = ( unsigned int )address;
- pPDC->PDC_RCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_SetTx
-//* \brief Set the transmit transfer descriptor
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PDC_SetTx( AT91PS_PDC pPDC, // \arg pointer to a PDC controller
- char *address, // \arg address to the next bloc to be transmitted
- unsigned int bytes ) // \arg number of bytes to be transmitted
-{
- pPDC->PDC_TPR = ( unsigned int )address;
- pPDC->PDC_TCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_EnableTx
-//* \brief Enable transmit
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PDC_EnableTx( AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
-{
- pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_EnableRx
-//* \brief Enable receive
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PDC_EnableRx( AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
-{
- pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_DisableTx
-//* \brief Disable transmit
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PDC_DisableTx( AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
-{
- pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_DisableRx
-//* \brief Disable receive
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PDC_DisableRx( AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
-{
- pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_IsTxEmpty
-//* \brief Test if the current transfer descriptor has been sent
-//*----------------------------------------------------------------------------
-static __inline int
-AT91F_PDC_IsTxEmpty( // \return return 1 if transfer is complete
- AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
-{
- return !( pPDC->PDC_TCR );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_IsNextTxEmpty
-//* \brief Test if the next transfer descriptor has been moved to the current td
-//*----------------------------------------------------------------------------
-static __inline int
-AT91F_PDC_IsNextTxEmpty( // \return return 1 if transfer is complete
- AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
-{
- return !( pPDC->PDC_TNCR );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_IsRxEmpty
-//* \brief Test if the current transfer descriptor has been filled
-//*----------------------------------------------------------------------------
-static __inline int
-AT91F_PDC_IsRxEmpty( // \return return 1 if transfer is complete
- AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
-{
- return !( pPDC->PDC_RCR );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_IsNextRxEmpty
-//* \brief Test if the next transfer descriptor has been moved to the current td
-//*----------------------------------------------------------------------------
-static __inline int
-AT91F_PDC_IsNextRxEmpty( // \return return 1 if transfer is complete
- AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
-{
- return !( pPDC->PDC_RNCR );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_Open
-//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PDC_Open( AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
-{
- //* Disable the RX and TX PDC transfer requests
- AT91F_PDC_DisableRx( pPDC );
- AT91F_PDC_DisableTx( pPDC );
-
- //* Reset all Counter register Next buffer first
- AT91F_PDC_SetNextTx( pPDC, ( char * )0, 0 );
- AT91F_PDC_SetNextRx( pPDC, ( char * )0, 0 );
- AT91F_PDC_SetTx( pPDC, ( char * )0, 0 );
- AT91F_PDC_SetRx( pPDC, ( char * )0, 0 );
-
- //* Enable the RX and TX PDC transfer requests
- AT91F_PDC_EnableRx( pPDC );
- AT91F_PDC_EnableTx( pPDC );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_Close
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PDC_Close( AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
-{
- //* Disable the RX and TX PDC transfer requests
- AT91F_PDC_DisableRx( pPDC );
- AT91F_PDC_DisableTx( pPDC );
-
- //* Reset all Counter register Next buffer first
- AT91F_PDC_SetNextTx( pPDC, ( char * )0, 0 );
- AT91F_PDC_SetNextRx( pPDC, ( char * )0, 0 );
- AT91F_PDC_SetTx( pPDC, ( char * )0, 0 );
- AT91F_PDC_SetRx( pPDC, ( char * )0, 0 );
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_SendFrame
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PDC_SendFrame( AT91PS_PDC pPDC,
- char *pBuffer, unsigned int szBuffer, char *pNextBuffer, unsigned int szNextBuffer )
-{
- if( AT91F_PDC_IsTxEmpty( pPDC ) )
- {
- //* Buffer and next buffer can be initialized
- AT91F_PDC_SetTx( pPDC, pBuffer, szBuffer );
- AT91F_PDC_SetNextTx( pPDC, pNextBuffer, szNextBuffer );
- return 2;
- }
- else if( AT91F_PDC_IsNextTxEmpty( pPDC ) )
- {
- //* Only one buffer can be initialized
- AT91F_PDC_SetNextTx( pPDC, pBuffer, szBuffer );
- return 1;
- }
- else
- {
- //* All buffer are in use...
- return 0;
- }
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PDC_ReceiveFrame
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PDC_ReceiveFrame( AT91PS_PDC pPDC,
- char *pBuffer, unsigned int szBuffer, char *pNextBuffer, unsigned int szNextBuffer )
-{
- if( AT91F_PDC_IsRxEmpty( pPDC ) )
- {
- //* Buffer and next buffer can be initialized
- AT91F_PDC_SetRx( pPDC, pBuffer, szBuffer );
- AT91F_PDC_SetNextRx( pPDC, pNextBuffer, szNextBuffer );
- return 2;
- }
- else if( AT91F_PDC_IsNextRxEmpty( pPDC ) )
- {
- //* Only one buffer can be initialized
- AT91F_PDC_SetNextRx( pPDC, pBuffer, szBuffer );
- return 1;
- }
- else
- {
- //* All buffer are in use...
- return 0;
- }
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR DBGU
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_DBGU_InterruptEnable
-//* \brief Enable DBGU Interrupt
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_DBGU_InterruptEnable( AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
- unsigned int flag ) // \arg dbgu interrupt to be enabled
-{
- pDbgu->DBGU_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_DBGU_InterruptDisable
-//* \brief Disable DBGU Interrupt
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_DBGU_InterruptDisable( AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
- unsigned int flag ) // \arg dbgu interrupt to be disabled
-{
- pDbgu->DBGU_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_DBGU_GetInterruptMaskStatus
-//* \brief Return DBGU Interrupt Mask Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
- AT91PS_DBGU pDbgu ) // \arg pointer to a DBGU controller
-{
- return pDbgu->DBGU_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_DBGU_IsInterruptMasked
-//* \brief Test if DBGU Interrupt is Masked
-//*----------------------------------------------------------------------------
-static __inline int
-AT91F_DBGU_IsInterruptMasked( AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_DBGU_GetInterruptMaskStatus( pDbgu ) & flag );
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR PIO
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_CfgPeriph
-//* \brief Enable pins to be drived by peripheral
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIO_CfgPeriph( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int periphAEnable, // \arg PERIPH A to enable
- unsigned int periphBEnable ) // \arg PERIPH B to enable
-{
- pPio->PIO_ASR = periphAEnable;
- pPio->PIO_BSR = periphBEnable;
- pPio->PIO_PDR = ( periphAEnable | periphBEnable ); // Set in Periph mode
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_CfgOutput
-//* \brief Enable PIO in output mode
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIO_CfgOutput( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int pioEnable ) // \arg PIO to be enabled
-{
- pPio->PIO_PER = pioEnable; // Set in PIO mode
- pPio->PIO_OER = pioEnable; // Configure in Output
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_CfgInput
-//* \brief Enable PIO in input mode
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIO_CfgInput( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int inputEnable ) // \arg PIO to be enabled
-{
- // Disable output
- pPio->PIO_ODR = inputEnable;
- pPio->PIO_PER = inputEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_CfgOpendrain
-//* \brief Configure PIO in open drain
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIO_CfgOpendrain( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int multiDrvEnable ) // \arg pio to be configured in open drain
-{
- // Configure the multi-drive option
- pPio->PIO_MDDR = ~multiDrvEnable;
- pPio->PIO_MDER = multiDrvEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_CfgPullup
-//* \brief Enable pullup on PIO
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIO_CfgPullup( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int pullupEnable ) // \arg enable pullup on PIO
-{
- // Connect or not Pullup
- pPio->PIO_PPUDR = ~pullupEnable;
- pPio->PIO_PPUER = pullupEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_CfgDirectDrive
-//* \brief Enable direct drive on PIO
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIO_CfgDirectDrive( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int directDrive ) // \arg PIO to be configured with direct drive
-{
- // Configure the Direct Drive
- pPio->PIO_OWDR = ~directDrive;
- pPio->PIO_OWER = directDrive;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_CfgInputFilter
-//* \brief Enable input filter on input PIO
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIO_CfgInputFilter( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int inputFilter ) // \arg PIO to be configured with input filter
-{
- // Configure the Direct Drive
- pPio->PIO_IFDR = ~inputFilter;
- pPio->PIO_IFER = inputFilter;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_GetInput
-//* \brief Return PIO input value
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PIO_GetInput( // \return PIO input
- AT91PS_PIO pPio ) // \arg pointer to a PIO controller
-{
- return pPio->PIO_PDSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_IsInputSet
-//* \brief Test if PIO is input flag is active
-//*----------------------------------------------------------------------------
-static __inline int
-AT91F_PIO_IsInputSet( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_PIO_GetInput( pPio ) & flag );
-}
-
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_SetOutput
-//* \brief Set to 1 output PIO
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIO_SetOutput( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg output to be set
-{
- pPio->PIO_SODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_ClearOutput
-//* \brief Set to 0 output PIO
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIO_ClearOutput( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg output to be cleared
-{
- pPio->PIO_CODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_ForceOutput
-//* \brief Force output when Direct drive option is enabled
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIO_ForceOutput( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg output to be forced
-{
- pPio->PIO_ODSR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_Enable
-//* \brief Enable PIO
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIO_Enable( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg pio to be enabled
-{
- pPio->PIO_PER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_Disable
-//* \brief Disable PIO
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIO_Disable( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg pio to be disabled
-{
- pPio->PIO_PDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_GetStatus
-//* \brief Return PIO Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PIO_GetStatus( // \return PIO Status
- AT91PS_PIO pPio ) // \arg pointer to a PIO controller
-{
- return pPio->PIO_PSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_IsSet
-//* \brief Test if PIO is Set
-//*----------------------------------------------------------------------------
-static __inline int
-AT91F_PIO_IsSet( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_PIO_GetStatus( pPio ) & flag );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_OutputEnable
-//* \brief Output Enable PIO
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIO_OutputEnable( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg pio output to be enabled
-{
- pPio->PIO_OER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_OutputDisable
-//* \brief Output Enable PIO
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIO_OutputDisable( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg pio output to be disabled
-{
- pPio->PIO_ODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_GetOutputStatus
-//* \brief Return PIO Output Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PIO_GetOutputStatus( // \return PIO Output Status
- AT91PS_PIO pPio ) // \arg pointer to a PIO controller
-{
- return pPio->PIO_OSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_IsOuputSet
-//* \brief Test if PIO Output is Set
-//*----------------------------------------------------------------------------
-static __inline int
-AT91F_PIO_IsOutputSet( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_PIO_GetOutputStatus( pPio ) & flag );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_InputFilterEnable
-//* \brief Input Filter Enable PIO
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIO_InputFilterEnable( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg pio input filter to be enabled
-{
- pPio->PIO_IFER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_InputFilterDisable
-//* \brief Input Filter Disable PIO
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIO_InputFilterDisable( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg pio input filter to be disabled
-{
- pPio->PIO_IFDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_GetInputFilterStatus
-//* \brief Return PIO Input Filter Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
- AT91PS_PIO pPio ) // \arg pointer to a PIO controller
-{
- return pPio->PIO_IFSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_IsInputFilterSet
-//* \brief Test if PIO Input filter is Set
-//*----------------------------------------------------------------------------
-static __inline int
-AT91F_PIO_IsInputFilterSet( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_PIO_GetInputFilterStatus( pPio ) & flag );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_GetOutputDataStatus
-//* \brief Return PIO Output Data Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status
- AT91PS_PIO pPio ) // \arg pointer to a PIO controller
-{
- return pPio->PIO_ODSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_InterruptEnable
-//* \brief Enable PIO Interrupt
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIO_InterruptEnable( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg pio interrupt to be enabled
-{
- pPio->PIO_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_InterruptDisable
-//* \brief Disable PIO Interrupt
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIO_InterruptDisable( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg pio interrupt to be disabled
-{
- pPio->PIO_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_GetInterruptMaskStatus
-//* \brief Return PIO Interrupt Mask Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
- AT91PS_PIO pPio ) // \arg pointer to a PIO controller
-{
- return pPio->PIO_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_GetInterruptStatus
-//* \brief Return PIO Interrupt Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
- AT91PS_PIO pPio ) // \arg pointer to a PIO controller
-{
- return pPio->PIO_ISR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_IsInterruptMasked
-//* \brief Test if PIO Interrupt is Masked
-//*----------------------------------------------------------------------------
-static __inline int
-AT91F_PIO_IsInterruptMasked( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_PIO_GetInterruptMaskStatus( pPio ) & flag );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_IsInterruptSet
-//* \brief Test if PIO Interrupt is Set
-//*----------------------------------------------------------------------------
-static __inline int
-AT91F_PIO_IsInterruptSet( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_PIO_GetInterruptStatus( pPio ) & flag );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_MultiDriverEnable
-//* \brief Multi Driver Enable PIO
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIO_MultiDriverEnable( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg pio to be enabled
-{
- pPio->PIO_MDER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_MultiDriverDisable
-//* \brief Multi Driver Disable PIO
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIO_MultiDriverDisable( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg pio to be disabled
-{
- pPio->PIO_MDDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_GetMultiDriverStatus
-//* \brief Return PIO Multi Driver Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
- AT91PS_PIO pPio ) // \arg pointer to a PIO controller
-{
- return pPio->PIO_MDSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_IsMultiDriverSet
-//* \brief Test if PIO MultiDriver is Set
-//*----------------------------------------------------------------------------
-static __inline int
-AT91F_PIO_IsMultiDriverSet( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_PIO_GetMultiDriverStatus( pPio ) & flag );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_A_RegisterSelection
-//* \brief PIO A Register Selection
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIO_A_RegisterSelection( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg pio A register selection
-{
- pPio->PIO_ASR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_B_RegisterSelection
-//* \brief PIO B Register Selection
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIO_B_RegisterSelection( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg pio B register selection
-{
- pPio->PIO_BSR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_Get_AB_RegisterStatus
-//* \brief Return PIO Interrupt Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
- AT91PS_PIO pPio ) // \arg pointer to a PIO controller
-{
- return pPio->PIO_ABSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_IsAB_RegisterSet
-//* \brief Test if PIO AB Register is Set
-//*----------------------------------------------------------------------------
-static __inline int
-AT91F_PIO_IsAB_RegisterSet( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_PIO_Get_AB_RegisterStatus( pPio ) & flag );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_OutputWriteEnable
-//* \brief Output Write Enable PIO
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIO_OutputWriteEnable( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg pio output write to be enabled
-{
- pPio->PIO_OWER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_OutputWriteDisable
-//* \brief Output Write Disable PIO
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIO_OutputWriteDisable( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg pio output write to be disabled
-{
- pPio->PIO_OWDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_GetOutputWriteStatus
-//* \brief Return PIO Output Write Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
- AT91PS_PIO pPio ) // \arg pointer to a PIO controller
-{
- return pPio->PIO_OWSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_IsOutputWriteSet
-//* \brief Test if PIO OutputWrite is Set
-//*----------------------------------------------------------------------------
-static __inline int
-AT91F_PIO_IsOutputWriteSet( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_PIO_GetOutputWriteStatus( pPio ) & flag );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_GetCfgPullup
-//* \brief Return PIO Configuration Pullup
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup
- AT91PS_PIO pPio ) // \arg pointer to a PIO controller
-{
- return pPio->PIO_PPUSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_IsOutputDataStatusSet
-//* \brief Test if PIO Output Data Status is Set
-//*----------------------------------------------------------------------------
-static __inline int
-AT91F_PIO_IsOutputDataStatusSet( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_PIO_GetOutputDataStatus( pPio ) & flag );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIO_IsCfgPullupStatusSet
-//* \brief Test if PIO Configuration Pullup Status is Set
-//*----------------------------------------------------------------------------
-static __inline int
-AT91F_PIO_IsCfgPullupStatusSet( AT91PS_PIO pPio, // \arg pointer to a PIO controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( ~AT91F_PIO_GetCfgPullup( pPio ) & flag );
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR PMC
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_CfgSysClkEnableReg
-//* \brief Configure the System Clock Enable Register of the PMC controller
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PMC_CfgSysClkEnableReg( AT91PS_PMC pPMC, // \arg pointer to PMC controller
- unsigned int mode )
-{
- //* Write to the SCER register
- pPMC->PMC_SCER = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_CfgSysClkDisableReg
-//* \brief Configure the System Clock Disable Register of the PMC controller
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PMC_CfgSysClkDisableReg( AT91PS_PMC pPMC, // \arg pointer to PMC controller
- unsigned int mode )
-{
- //* Write to the SCDR register
- pPMC->PMC_SCDR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_GetSysClkStatusReg
-//* \brief Return the System Clock Status Register of the PMC controller
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PMC_GetSysClkStatusReg( AT91PS_PMC pPMC // pointer to a CAN controller
- )
-{
- return pPMC->PMC_SCSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_EnablePeriphClock
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PMC_EnablePeriphClock( AT91PS_PMC pPMC, // \arg pointer to PMC controller
- unsigned int periphIds ) // \arg IDs of peripherals
-{
- pPMC->PMC_PCER = periphIds;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_DisablePeriphClock
-//* \brief Disable peripheral clock
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PMC_DisablePeriphClock( AT91PS_PMC pPMC, // \arg pointer to PMC controller
- unsigned int periphIds ) // \arg IDs of peripherals
-{
- pPMC->PMC_PCDR = periphIds;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_GetPeriphClock
-//* \brief Get peripheral clock status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PMC_GetPeriphClock( AT91PS_PMC pPMC ) // \arg pointer to PMC controller
-{
- return pPMC->PMC_PCSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CKGR_CfgMainOscillatorReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_CKGR_CfgMainOscillatorReg( AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
- unsigned int mode )
-{
- pCKGR->CKGR_MOR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CKGR_GetMainOscillatorReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_CKGR_GetMainOscillatorReg( AT91PS_CKGR pCKGR ) // \arg pointer to CKGR controller
-{
- return pCKGR->CKGR_MOR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CKGR_EnableMainOscillator
-//* \brief Enable the main oscillator
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_CKGR_EnableMainOscillator( AT91PS_CKGR pCKGR ) // \arg pointer to CKGR controller
-{
- pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CKGR_DisableMainOscillator
-//* \brief Disable the main oscillator
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_CKGR_DisableMainOscillator( AT91PS_CKGR pCKGR ) // \arg pointer to CKGR controller
-{
- pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CKGR_CfgMainOscStartUpTime
-//* \brief Cfg MOR Register according to the main osc startup time
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
- unsigned int startup_time, // \arg main osc startup time in microsecond (us)
- unsigned int slowClock ) // \arg slowClock in Hz
-{
- pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
- pCKGR->CKGR_MOR |= ( ( slowClock * startup_time ) / ( 8 * 1000000 ) ) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CKGR_GetMainClockFreqReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_CKGR_GetMainClockFreqReg( AT91PS_CKGR pCKGR ) // \arg pointer to CKGR controller
-{
- return pCKGR->CKGR_MCFR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CKGR_GetMainClock
-//* \brief Return Main clock in Hz
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_CKGR_GetMainClock( AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
- unsigned int slowClock ) // \arg slowClock in Hz
-{
- return ( ( pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF ) * slowClock ) >> 4;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_CfgMCKReg
-//* \brief Cfg Master Clock Register
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PMC_CfgMCKReg( AT91PS_PMC pPMC, // \arg pointer to PMC controller
- unsigned int mode )
-{
- pPMC->PMC_MCKR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_GetMCKReg
-//* \brief Return Master Clock Register
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PMC_GetMCKReg( AT91PS_PMC pPMC ) // \arg pointer to PMC controller
-{
- return pPMC->PMC_MCKR;
-}
-
-//*------------------------------------------------------------------------------
-//* \fn AT91F_PMC_GetMasterClock
-//* \brief Return master clock in Hz which correponds to processor clock for ARM7
-//*------------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PMC_GetMasterClock( AT91PS_PMC pPMC, // \arg pointer to PMC controller
- AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
- unsigned int slowClock ) // \arg slowClock in Hz
-{
- unsigned int reg = pPMC->PMC_MCKR;
- unsigned int prescaler = ( 1 << ( ( reg & AT91C_PMC_PRES ) >> 2 ) );
- unsigned int pllDivider, pllMultiplier;
-
- switch ( reg & AT91C_PMC_CSS )
- {
- case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
- return slowClock / prescaler;
- case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
- return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / prescaler;
- case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
- reg = pCKGR->CKGR_PLLR;
- pllDivider = ( reg & AT91C_CKGR_DIV );
- pllMultiplier = ( ( reg & AT91C_CKGR_MUL ) >> 16 ) + 1;
- return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / pllDivider * pllMultiplier / prescaler;
- }
- return 0;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_EnablePCK
-//* \brief Enable Programmable Clock x Output
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PMC_EnablePCK( AT91PS_PMC pPMC, // \arg pointer to PMC controller
- unsigned int pck, // \arg Programmable Clock x Output
- unsigned int mode )
-{
- pPMC->PMC_PCKR[pck] = mode;
- pPMC->PMC_SCER = ( 1 << pck ) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_DisablePCK
-//* \brief Disable Programmable Clock x Output
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PMC_DisablePCK( AT91PS_PMC pPMC, // \arg pointer to PMC controller
- unsigned int pck ) // \arg Programmable Clock x Output
-{
- pPMC->PMC_SCDR = ( 1 << pck ) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_EnableIt
-//* \brief Enable PMC interrupt
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PMC_EnableIt( AT91PS_PMC pPMC, // pointer to a PMC controller
- unsigned int flag ) // IT to be enabled
-{
- //* Write to the IER register
- pPMC->PMC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_DisableIt
-//* \brief Disable PMC interrupt
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PMC_DisableIt( AT91PS_PMC pPMC, // pointer to a PMC controller
- unsigned int flag ) // IT to be disabled
-{
- //* Write to the IDR register
- pPMC->PMC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_GetStatus
-//* \brief Return PMC Interrupt Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PMC_GetStatus( // \return PMC Interrupt Status
- AT91PS_PMC pPMC ) // pointer to a PMC controller
-{
- return pPMC->PMC_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_GetInterruptMaskStatus
-//* \brief Return PMC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
- AT91PS_PMC pPMC ) // pointer to a PMC controller
-{
- return pPMC->PMC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_IsInterruptMasked
-//* \brief Test if PMC Interrupt is Masked
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PMC_IsInterruptMasked( AT91PS_PMC pPMC, // \arg pointer to a PMC controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_PMC_GetInterruptMaskStatus( pPMC ) & flag );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_IsStatusSet
-//* \brief Test if PMC Status is Set
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PMC_IsStatusSet( AT91PS_PMC pPMC, // \arg pointer to a PMC controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_PMC_GetStatus( pPMC ) & flag );
-}
-
-// ----------------------------------------------------------------------------
-// \fn AT91F_CKGR_CfgPLLReg
-// \brief Cfg the PLL Register
-// ----------------------------------------------------------------------------
-static __inline void
-AT91F_CKGR_CfgPLLReg( AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
- unsigned int mode )
-{
- pCKGR->CKGR_PLLR = mode;
-}
-
-// ----------------------------------------------------------------------------
-// \fn AT91F_CKGR_GetPLLReg
-// \brief Get the PLL Register
-// ----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_CKGR_GetPLLReg( AT91PS_CKGR pCKGR ) // \arg pointer to CKGR controller
-{
- return pCKGR->CKGR_PLLR;
-}
-
-
-/* *****************************************************************************
- SOFTWARE API FOR RSTC
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_RSTSoftReset
-//* \brief Start Software Reset
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_RSTSoftReset( AT91PS_RSTC pRSTC, unsigned int reset )
-{
- pRSTC->RSTC_RCR = ( 0xA5000000 | reset );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_RSTSetMode
-//* \brief Set Reset Mode
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_RSTSetMode( AT91PS_RSTC pRSTC, unsigned int mode )
-{
- pRSTC->RSTC_RMR = ( 0xA5000000 | mode );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_RSTGetMode
-//* \brief Get Reset Mode
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_RSTGetMode( AT91PS_RSTC pRSTC )
-{
- return ( pRSTC->RSTC_RMR );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_RSTGetStatus
-//* \brief Get Reset Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_RSTGetStatus( AT91PS_RSTC pRSTC )
-{
- return ( pRSTC->RSTC_RSR );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_RSTIsSoftRstActive
-//* \brief Return !=0 if software reset is still not completed
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_RSTIsSoftRstActive( AT91PS_RSTC pRSTC )
-{
- return ( ( pRSTC->RSTC_RSR ) & AT91C_RSTC_SRCMP );
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR RTTC
- ***************************************************************************** */
-//*--------------------------------------------------------------------------------------
-//* \fn AT91F_SetRTT_TimeBase()
-//* \brief Set the RTT prescaler according to the TimeBase in ms
-//*--------------------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_RTTSetTimeBase( AT91PS_RTTC pRTTC, unsigned int ms )
-{
- if( ms > 2000 )
- return 1; // AT91C_TIME_OUT_OF_RANGE
- pRTTC->RTTC_RTMR &= ~0xFFFF;
- pRTTC->RTTC_RTMR |= ( ( ( ms << 15 ) / 1000 ) & 0xFFFF );
- return 0;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn AT91F_RTTSetPrescaler()
-//* \brief Set the new prescaler value
-//*--------------------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_RTTSetPrescaler( AT91PS_RTTC pRTTC, unsigned int rtpres )
-{
- pRTTC->RTTC_RTMR &= ~0xFFFF;
- pRTTC->RTTC_RTMR |= ( rtpres & 0xFFFF );
- return ( pRTTC->RTTC_RTMR );
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn AT91F_RTTRestart()
-//* \brief Restart the RTT prescaler
-//*--------------------------------------------------------------------------------------
-static __inline void
-AT91F_RTTRestart( AT91PS_RTTC pRTTC )
-{
- pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;
-}
-
-
-//*--------------------------------------------------------------------------------------
-//* \fn AT91F_RTT_SetAlarmINT()
-//* \brief Enable RTT Alarm Interrupt
-//*--------------------------------------------------------------------------------------
-static __inline void
-AT91F_RTTSetAlarmINT( AT91PS_RTTC pRTTC )
-{
- pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn AT91F_RTT_ClearAlarmINT()
-//* \brief Disable RTT Alarm Interrupt
-//*--------------------------------------------------------------------------------------
-static __inline void
-AT91F_RTTClearAlarmINT( AT91PS_RTTC pRTTC )
-{
- pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn AT91F_RTT_SetRttIncINT()
-//* \brief Enable RTT INC Interrupt
-//*--------------------------------------------------------------------------------------
-static __inline void
-AT91F_RTTSetRttIncINT( AT91PS_RTTC pRTTC )
-{
- pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn AT91F_RTT_ClearRttIncINT()
-//* \brief Disable RTT INC Interrupt
-//*--------------------------------------------------------------------------------------
-static __inline void
-AT91F_RTTClearRttIncINT( AT91PS_RTTC pRTTC )
-{
- pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn AT91F_RTT_SetAlarmValue()
-//* \brief Set RTT Alarm Value
-//*--------------------------------------------------------------------------------------
-static __inline void
-AT91F_RTTSetAlarmValue( AT91PS_RTTC pRTTC, unsigned int alarm )
-{
- pRTTC->RTTC_RTAR = alarm;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn AT91F_RTT_GetAlarmValue()
-//* \brief Get RTT Alarm Value
-//*--------------------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_RTTGetAlarmValue( AT91PS_RTTC pRTTC )
-{
- return ( pRTTC->RTTC_RTAR );
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn AT91F_RTTGetStatus()
-//* \brief Read the RTT status
-//*--------------------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_RTTGetStatus( AT91PS_RTTC pRTTC )
-{
- return ( pRTTC->RTTC_RTSR );
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn AT91F_RTT_ReadValue()
-//* \brief Read the RTT value
-//*--------------------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_RTTReadValue( AT91PS_RTTC pRTTC )
-{
- register volatile unsigned int val1, val2;
-
- do
- {
- val1 = pRTTC->RTTC_RTVR;
- val2 = pRTTC->RTTC_RTVR;
- }
- while( val1 != val2 );
- return ( val1 );
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR PITC
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PITInit
-//* \brief System timer init : period in µsecond, system clock freq in MHz
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PITInit( AT91PS_PITC pPITC, unsigned int period, unsigned int pit_frequency )
-{
- pPITC->PITC_PIMR = period ? ( period * pit_frequency + 8 ) >> 4 : 0; // +8 to avoid %10 and /10
- pPITC->PITC_PIMR |= AT91C_PITC_PITEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PITSetPIV
-//* \brief Set the PIT Periodic Interval Value
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PITSetPIV( AT91PS_PITC pPITC, unsigned int piv )
-{
- pPITC->PITC_PIMR = piv | ( pPITC->PITC_PIMR & ( AT91C_PITC_PITEN | AT91C_PITC_PITIEN ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PITEnableInt
-//* \brief Enable PIT periodic interrupt
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PITEnableInt( AT91PS_PITC pPITC )
-{
- pPITC->PITC_PIMR |= AT91C_PITC_PITIEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PITDisableInt
-//* \brief Disable PIT periodic interrupt
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PITDisableInt( AT91PS_PITC pPITC )
-{
- pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PITGetMode
-//* \brief Read PIT mode register
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PITGetMode( AT91PS_PITC pPITC )
-{
- return ( pPITC->PITC_PIMR );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PITGetStatus
-//* \brief Read PIT status register
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PITGetStatus( AT91PS_PITC pPITC )
-{
- return ( pPITC->PITC_PISR );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PITGetPIIR
-//* \brief Read PIT CPIV and PICNT without ressetting the counters
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PITGetPIIR( AT91PS_PITC pPITC )
-{
- return ( pPITC->PITC_PIIR );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PITGetPIVR
-//* \brief Read System timer CPIV and PICNT without ressetting the counters
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PITGetPIVR( AT91PS_PITC pPITC )
-{
- return ( pPITC->PITC_PIVR );
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR WDTC
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_WDTSetMode
-//* \brief Set Watchdog Mode Register
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_WDTSetMode( AT91PS_WDTC pWDTC, unsigned int Mode )
-{
- pWDTC->WDTC_WDMR = Mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_WDTRestart
-//* \brief Restart Watchdog
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_WDTRestart( AT91PS_WDTC pWDTC )
-{
- pWDTC->WDTC_WDCR = 0xA5000001;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_WDTSGettatus
-//* \brief Get Watchdog Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_WDTSGettatus( AT91PS_WDTC pWDTC )
-{
- return ( pWDTC->WDTC_WDSR & 0x3 );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_WDTGetPeriod
-//* \brief Translate ms into Watchdog Compatible value
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_WDTGetPeriod( unsigned int ms )
-{
- if( ( ms < 4 ) || ( ms > 16000 ) )
- return 0;
- return ( ( ms << 8 ) / 1000 );
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR VREG
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_VREG_Enable_LowPowerMode
-//* \brief Enable VREG Low Power Mode
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_VREG_Enable_LowPowerMode( AT91PS_VREG pVREG )
-{
- pVREG->VREG_MR |= AT91C_VREG_PSTDBY;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_VREG_Disable_LowPowerMode
-//* \brief Disable VREG Low Power Mode
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_VREG_Disable_LowPowerMode( AT91PS_VREG pVREG )
-{
- pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY;
-} /* *****************************************************************************
- SOFTWARE API FOR MC
- ***************************************************************************** */
-
-#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_MC_Remap
-//* \brief Make Remap
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_MC_Remap( void ) //
-{
- AT91PS_MC pMC = ( AT91PS_MC ) AT91C_BASE_MC;
-
- pMC->MC_RCR = AT91C_MC_RCB;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_MC_EFC_CfgModeReg
-//* \brief Configure the EFC Mode Register of the MC controller
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_MC_EFC_CfgModeReg( AT91PS_MC pMC, // pointer to a MC controller
- unsigned int mode ) // mode register
-{
- // Write to the FMR register
- pMC->MC_FMR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_MC_EFC_GetModeReg
-//* \brief Return MC EFC Mode Regsiter
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_MC_EFC_GetModeReg( AT91PS_MC pMC ) // pointer to a MC controller
-{
- return pMC->MC_FMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_MC_EFC_ComputeFMCN
-//* \brief Return MC EFC Mode Regsiter
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_MC_EFC_ComputeFMCN( int master_clock ) // master clock in Hz
-{
- return ( master_clock / 1000000 + 2 );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_MC_EFC_PerformCmd
-//* \brief Perform EFC Command
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_MC_EFC_PerformCmd( AT91PS_MC pMC, // pointer to a MC controller
- unsigned int transfer_cmd )
-{
- pMC->MC_FCR = transfer_cmd;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_MC_EFC_GetStatus
-//* \brief Return MC EFC Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_MC_EFC_GetStatus( AT91PS_MC pMC ) // pointer to a MC controller
-{
- return pMC->MC_FSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_MC_EFC_IsInterruptMasked
-//* \brief Test if EFC MC Interrupt is Masked
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_MC_EFC_IsInterruptMasked( AT91PS_MC pMC, // \arg pointer to a MC controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_MC_EFC_GetModeReg( pMC ) & flag );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_MC_EFC_IsInterruptSet
-//* \brief Test if EFC MC Interrupt is Set
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_MC_EFC_IsInterruptSet( AT91PS_MC pMC, // \arg pointer to a MC controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_MC_EFC_GetStatus( pMC ) & flag );
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR SPI
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_CfgCs
-//* \brief Configure SPI chip select register
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_SPI_CfgCs( AT91PS_SPI pSPI, // pointer to a SPI controller
- int cs, // SPI cs number (0 to 3)
- int val ) // chip select register
-{
- //* Write to the CSR register
- *( pSPI->SPI_CSR + cs ) = val;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_EnableIt
-//* \brief Enable SPI interrupt
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_SPI_EnableIt( AT91PS_SPI pSPI, // pointer to a SPI controller
- unsigned int flag ) // IT to be enabled
-{
- //* Write to the IER register
- pSPI->SPI_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_DisableIt
-//* \brief Disable SPI interrupt
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_SPI_DisableIt( AT91PS_SPI pSPI, // pointer to a SPI controller
- unsigned int flag ) // IT to be disabled
-{
- //* Write to the IDR register
- pSPI->SPI_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_Reset
-//* \brief Reset the SPI controller
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_SPI_Reset( AT91PS_SPI pSPI // pointer to a SPI controller
- )
-{
- //* Write to the CR register
- pSPI->SPI_CR = AT91C_SPI_SWRST;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_Enable
-//* \brief Enable the SPI controller
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_SPI_Enable( AT91PS_SPI pSPI // pointer to a SPI controller
- )
-{
- //* Write to the CR register
- pSPI->SPI_CR = AT91C_SPI_SPIEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_Disable
-//* \brief Disable the SPI controller
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_SPI_Disable( AT91PS_SPI pSPI // pointer to a SPI controller
- )
-{
- //* Write to the CR register
- pSPI->SPI_CR = AT91C_SPI_SPIDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_CfgMode
-//* \brief Enable the SPI controller
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_SPI_CfgMode( AT91PS_SPI pSPI, // pointer to a SPI controller
- int mode ) // mode register
-{
- //* Write to the MR register
- pSPI->SPI_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_CfgPCS
-//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_SPI_CfgPCS( AT91PS_SPI pSPI, // pointer to a SPI controller
- char PCS_Device ) // PCS of the Device
-{
- //* Write to the MR register
- pSPI->SPI_MR &= 0xFFF0FFFF;
- pSPI->SPI_MR |= ( ( PCS_Device << 16 ) & AT91C_SPI_PCS );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_ReceiveFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_SPI_ReceiveFrame( AT91PS_SPI pSPI,
- char *pBuffer, unsigned int szBuffer, char *pNextBuffer, unsigned int szNextBuffer )
-{
- return AT91F_PDC_ReceiveFrame( ( AT91PS_PDC ) & ( pSPI->SPI_RPR ), pBuffer, szBuffer, pNextBuffer, szNextBuffer );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_SendFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_SPI_SendFrame( AT91PS_SPI pSPI,
- char *pBuffer, unsigned int szBuffer, char *pNextBuffer, unsigned int szNextBuffer )
-{
- return AT91F_PDC_SendFrame( ( AT91PS_PDC ) & ( pSPI->SPI_RPR ), pBuffer, szBuffer, pNextBuffer, szNextBuffer );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_Close
-//* \brief Close SPI: disable IT disable transfert, close PDC
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_SPI_Close( AT91PS_SPI pSPI ) // \arg pointer to a SPI controller
-{
- //* Reset all the Chip Select register
- pSPI->SPI_CSR[0] = 0;
- pSPI->SPI_CSR[1] = 0;
- pSPI->SPI_CSR[2] = 0;
- pSPI->SPI_CSR[3] = 0;
-
- //* Reset the SPI mode
- pSPI->SPI_MR = 0;
-
- //* Disable all interrupts
- pSPI->SPI_IDR = 0xFFFFFFFF;
-
- //* Abort the Peripheral Data Transfers
- AT91F_PDC_Close( ( AT91PS_PDC ) & ( pSPI->SPI_RPR ) );
-
- //* Disable receiver and transmitter and stop any activity immediately
- pSPI->SPI_CR = AT91C_SPI_SPIDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_PutChar
-//* \brief Send a character,does not check if ready to send
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_SPI_PutChar( AT91PS_SPI pSPI, unsigned int character, unsigned int cs_number )
-{
- unsigned int value_for_cs;
-
- value_for_cs = ( ~( 1 << cs_number ) ) & 0xF; //Place a zero among a 4 ONEs number
- pSPI->SPI_TDR = ( character & 0xFFFF ) | ( value_for_cs << 16 );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_GetChar
-//* \brief Receive a character,does not check if a character is available
-//*----------------------------------------------------------------------------
-static __inline int
-AT91F_SPI_GetChar( const AT91PS_SPI pSPI )
-{
- return ( ( pSPI->SPI_RDR ) & 0xFFFF );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_GetInterruptMaskStatus
-//* \brief Return SPI Interrupt Mask Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
- AT91PS_SPI pSpi ) // \arg pointer to a SPI controller
-{
- return pSpi->SPI_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI_IsInterruptMasked
-//* \brief Test if SPI Interrupt is Masked
-//*----------------------------------------------------------------------------
-static __inline int
-AT91F_SPI_IsInterruptMasked( AT91PS_SPI pSpi, // \arg pointer to a SPI controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_SPI_GetInterruptMaskStatus( pSpi ) & flag );
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR USART
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_Baudrate
-//* \brief Calculate the baudrate
-//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
-#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_NONE + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CLKS_CLOCK )
-
-//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
-#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_NONE + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CLKS_EXT )
-
-//* Standard Synchronous Mode : 8 bits , 1 stop , no parity
-#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
- AT91C_US_USMODE_NORMAL + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_NONE + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CLKS_CLOCK )
-
-//* SCK used Label
-#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
-
-//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
-#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
- AT91C_US_CLKS_CLOCK +\
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_EVEN + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CKLO +\
- AT91C_US_OVER)
-
-//* Standard IRDA mode
-#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \
- AT91C_US_NBSTOP_1_BIT + \
- AT91C_US_PAR_NONE + \
- AT91C_US_CHRL_8_BITS + \
- AT91C_US_CLKS_CLOCK )
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_Baudrate
-//* \brief Caluculate baud_value according to the main clock and the baud rate
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_US_Baudrate( const unsigned int main_clock, // \arg peripheral clock
- const unsigned int baud_rate ) // \arg UART baudrate
-{
- unsigned int baud_value = ( ( main_clock * 10 ) / ( baud_rate * 16 ) );
-
- if( ( baud_value % 10 ) >= 5 )
- baud_value = ( baud_value / 10 ) + 1;
- else
- baud_value /= 10;
- return baud_value;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_SetBaudrate
-//* \brief Set the baudrate according to the CPU clock
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_US_SetBaudrate( AT91PS_USART pUSART, // \arg pointer to a USART controller
- unsigned int mainClock, // \arg peripheral clock
- unsigned int speed ) // \arg UART baudrate
-{
- //* Define the baud rate divisor register
- pUSART->US_BRGR = AT91F_US_Baudrate( mainClock, speed );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_SetTimeguard
-//* \brief Set USART timeguard
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_US_SetTimeguard( AT91PS_USART pUSART, // \arg pointer to a USART controller
- unsigned int timeguard ) // \arg timeguard value
-{
- //* Write the Timeguard Register
- pUSART->US_TTGR = timeguard;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_EnableIt
-//* \brief Enable USART IT
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_US_EnableIt( AT91PS_USART pUSART, // \arg pointer to a USART controller
- unsigned int flag ) // \arg IT to be enabled
-{
- //* Write to the IER register
- pUSART->US_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_DisableIt
-//* \brief Disable USART IT
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_US_DisableIt( AT91PS_USART pUSART, // \arg pointer to a USART controller
- unsigned int flag ) // \arg IT to be disabled
-{
- //* Write to the IER register
- pUSART->US_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_Configure
-//* \brief Configure USART
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_US_Configure( AT91PS_USART pUSART, // \arg pointer to a USART controller
- unsigned int mainClock, // \arg peripheral clock
- unsigned int mode, // \arg mode Register to be programmed
- unsigned int baudRate, // \arg baudrate to be programmed
- unsigned int timeguard ) // \arg timeguard to be programmed
-{
- //* Disable interrupts
- pUSART->US_IDR = ( unsigned int )-1;
-
- //* Reset receiver and transmitter
- pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS;
-
- //* Define the baud rate divisor register
- AT91F_US_SetBaudrate( pUSART, mainClock, baudRate );
-
- //* Write the Timeguard Register
- AT91F_US_SetTimeguard( pUSART, timeguard );
-
- //* Clear Transmit and Receive Counters
- AT91F_PDC_Open( ( AT91PS_PDC ) & ( pUSART->US_RPR ) );
-
- //* Define the USART mode
- pUSART->US_MR = mode;
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_EnableRx
-//* \brief Enable receiving characters
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_US_EnableRx( AT91PS_USART pUSART ) // \arg pointer to a USART controller
-{
- //* Enable receiver
- pUSART->US_CR = AT91C_US_RXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_EnableTx
-//* \brief Enable sending characters
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_US_EnableTx( AT91PS_USART pUSART ) // \arg pointer to a USART controller
-{
- //* Enable transmitter
- pUSART->US_CR = AT91C_US_TXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_ResetRx
-//* \brief Reset Receiver and re-enable it
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_US_ResetRx( AT91PS_USART pUSART ) // \arg pointer to a USART controller
-{
- //* Reset receiver
- pUSART->US_CR = AT91C_US_RSTRX;
- //* Re-Enable receiver
- pUSART->US_CR = AT91C_US_RXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_ResetTx
-//* \brief Reset Transmitter and re-enable it
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_US_ResetTx( AT91PS_USART pUSART ) // \arg pointer to a USART controller
-{
- //* Reset transmitter
- pUSART->US_CR = AT91C_US_RSTTX;
- //* Enable transmitter
- pUSART->US_CR = AT91C_US_TXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_DisableRx
-//* \brief Disable Receiver
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_US_DisableRx( AT91PS_USART pUSART ) // \arg pointer to a USART controller
-{
- //* Disable receiver
- pUSART->US_CR = AT91C_US_RXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_DisableTx
-//* \brief Disable Transmitter
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_US_DisableTx( AT91PS_USART pUSART ) // \arg pointer to a USART controller
-{
- //* Disable transmitter
- pUSART->US_CR = AT91C_US_TXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_Close
-//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_US_Close( AT91PS_USART pUSART ) // \arg pointer to a USART controller
-{
- //* Reset the baud rate divisor register
- pUSART->US_BRGR = 0;
-
- //* Reset the USART mode
- pUSART->US_MR = 0;
-
- //* Reset the Timeguard Register
- pUSART->US_TTGR = 0;
-
- //* Disable all interrupts
- pUSART->US_IDR = 0xFFFFFFFF;
-
- //* Abort the Peripheral Data Transfers
- AT91F_PDC_Close( ( AT91PS_PDC ) & ( pUSART->US_RPR ) );
-
- //* Disable receiver and transmitter and stop any activity immediately
- pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_TxReady
-//* \brief Return 1 if a character can be written in US_THR
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_US_TxReady( AT91PS_USART pUSART ) // \arg pointer to a USART controller
-{
- return ( pUSART->US_CSR & AT91C_US_TXRDY );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_RxReady
-//* \brief Return 1 if a character can be read in US_RHR
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_US_RxReady( AT91PS_USART pUSART ) // \arg pointer to a USART controller
-{
- return ( pUSART->US_CSR & AT91C_US_RXRDY );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_Error
-//* \brief Return the error flag
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_US_Error( AT91PS_USART pUSART ) // \arg pointer to a USART controller
-{
- return ( pUSART->US_CSR & ( AT91C_US_OVRE | // Overrun error
- AT91C_US_FRAME | // Framing error
- AT91C_US_PARE ) ); // Parity error
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_PutChar
-//* \brief Send a character,does not check if ready to send
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_US_PutChar( AT91PS_USART pUSART, int character )
-{
- pUSART->US_THR = ( character & 0x1FF );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_GetChar
-//* \brief Receive a character,does not check if a character is available
-//*----------------------------------------------------------------------------
-static __inline int
-AT91F_US_GetChar( const AT91PS_USART pUSART )
-{
- return ( ( pUSART->US_RHR ) & 0x1FF );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_SendFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_US_SendFrame( AT91PS_USART pUSART,
- char *pBuffer, unsigned int szBuffer, char *pNextBuffer, unsigned int szNextBuffer )
-{
- return AT91F_PDC_SendFrame( ( AT91PS_PDC ) & ( pUSART->US_RPR ), pBuffer, szBuffer, pNextBuffer, szNextBuffer );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_ReceiveFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_US_ReceiveFrame( AT91PS_USART pUSART,
- char *pBuffer, unsigned int szBuffer, char *pNextBuffer, unsigned int szNextBuffer )
-{
- return AT91F_PDC_ReceiveFrame( ( AT91PS_PDC ) & ( pUSART->US_RPR ), pBuffer, szBuffer, pNextBuffer, szNextBuffer );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US_SetIrdaFilter
-//* \brief Set the value of IrDa filter tregister
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_US_SetIrdaFilter( AT91PS_USART pUSART, unsigned char value )
-{
- pUSART->US_IF = value;
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR SSC
- ***************************************************************************** */
-//* Define the standard I2S mode configuration
-
-//* Configuration to set in the SSC Transmit Clock Mode Register
-//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
-//* nb_slot_by_frame : number of channels
-#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
- AT91C_SSC_CKS_DIV +\
- AT91C_SSC_CKO_CONTINOUS +\
- AT91C_SSC_CKG_NONE +\
- AT91C_SSC_START_FALL_RF +\
- AT91C_SSC_STTOUT +\
- ((1<<16) & AT91C_SSC_STTDLY) +\
- ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
-
-
-//* Configuration to set in the SSC Transmit Frame Mode Register
-//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
-//* nb_slot_by_frame : number of channels
-#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
- (nb_bit_by_slot-1) +\
- AT91C_SSC_MSBF +\
- (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\
- (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
- AT91C_SSC_FSOS_NEGATIVE)
-
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_SetBaudrate
-//* \brief Set the baudrate according to the CPU clock
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_SSC_SetBaudrate( AT91PS_SSC pSSC, // \arg pointer to a SSC controller
- unsigned int mainClock, // \arg peripheral clock
- unsigned int speed ) // \arg SSC baudrate
-{
- unsigned int baud_value;
-
- //* Define the baud rate divisor register
- if( speed == 0 )
- baud_value = 0;
- else
- {
- baud_value = ( unsigned int )( mainClock * 10 ) / ( 2 * speed );
- if( ( baud_value % 10 ) >= 5 )
- baud_value = ( baud_value / 10 ) + 1;
- else
- baud_value /= 10;
- }
-
- pSSC->SSC_CMR = baud_value;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_Configure
-//* \brief Configure SSC
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_SSC_Configure( AT91PS_SSC pSSC, // \arg pointer to a SSC controller
- unsigned int syst_clock, // \arg System Clock Frequency
- unsigned int baud_rate, // \arg Expected Baud Rate Frequency
- unsigned int clock_rx, // \arg Receiver Clock Parameters
- unsigned int mode_rx, // \arg mode Register to be programmed
- unsigned int clock_tx, // \arg Transmitter Clock Parameters
- unsigned int mode_tx ) // \arg mode Register to be programmed
-{
- //* Disable interrupts
- pSSC->SSC_IDR = ( unsigned int )-1;
-
- //* Reset receiver and transmitter
- pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS;
-
- //* Define the Clock Mode Register
- AT91F_SSC_SetBaudrate( pSSC, syst_clock, baud_rate );
-
- //* Write the Receive Clock Mode Register
- pSSC->SSC_RCMR = clock_rx;
-
- //* Write the Transmit Clock Mode Register
- pSSC->SSC_TCMR = clock_tx;
-
- //* Write the Receive Frame Mode Register
- pSSC->SSC_RFMR = mode_rx;
-
- //* Write the Transmit Frame Mode Register
- pSSC->SSC_TFMR = mode_tx;
-
- //* Clear Transmit and Receive Counters
- AT91F_PDC_Open( ( AT91PS_PDC ) & ( pSSC->SSC_RPR ) );
-
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_EnableRx
-//* \brief Enable receiving datas
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_SSC_EnableRx( AT91PS_SSC pSSC ) // \arg pointer to a SSC controller
-{
- //* Enable receiver
- pSSC->SSC_CR = AT91C_SSC_RXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_DisableRx
-//* \brief Disable receiving datas
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_SSC_DisableRx( AT91PS_SSC pSSC ) // \arg pointer to a SSC controller
-{
- //* Disable receiver
- pSSC->SSC_CR = AT91C_SSC_RXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_EnableTx
-//* \brief Enable sending datas
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_SSC_EnableTx( AT91PS_SSC pSSC ) // \arg pointer to a SSC controller
-{
- //* Enable transmitter
- pSSC->SSC_CR = AT91C_SSC_TXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_DisableTx
-//* \brief Disable sending datas
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_SSC_DisableTx( AT91PS_SSC pSSC ) // \arg pointer to a SSC controller
-{
- //* Disable transmitter
- pSSC->SSC_CR = AT91C_SSC_TXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_EnableIt
-//* \brief Enable SSC IT
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_SSC_EnableIt( AT91PS_SSC pSSC, // \arg pointer to a SSC controller
- unsigned int flag ) // \arg IT to be enabled
-{
- //* Write to the IER register
- pSSC->SSC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_DisableIt
-//* \brief Disable SSC IT
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_SSC_DisableIt( AT91PS_SSC pSSC, // \arg pointer to a SSC controller
- unsigned int flag ) // \arg IT to be disabled
-{
- //* Write to the IDR register
- pSSC->SSC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_ReceiveFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_SSC_ReceiveFrame( AT91PS_SSC pSSC,
- char *pBuffer, unsigned int szBuffer, char *pNextBuffer, unsigned int szNextBuffer )
-{
- return AT91F_PDC_ReceiveFrame( ( AT91PS_PDC ) & ( pSSC->SSC_RPR ), pBuffer, szBuffer, pNextBuffer, szNextBuffer );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_SendFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_SSC_SendFrame( AT91PS_SSC pSSC,
- char *pBuffer, unsigned int szBuffer, char *pNextBuffer, unsigned int szNextBuffer )
-{
- return AT91F_PDC_SendFrame( ( AT91PS_PDC ) & ( pSSC->SSC_RPR ), pBuffer, szBuffer, pNextBuffer, szNextBuffer );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_GetInterruptMaskStatus
-//* \brief Return SSC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
- AT91PS_SSC pSsc ) // \arg pointer to a SSC controller
-{
- return pSsc->SSC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_IsInterruptMasked
-//* \brief Test if SSC Interrupt is Masked
-//*----------------------------------------------------------------------------
-static __inline int
-AT91F_SSC_IsInterruptMasked( AT91PS_SSC pSsc, // \arg pointer to a SSC controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_SSC_GetInterruptMaskStatus( pSsc ) & flag );
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR TWI
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TWI_EnableIt
-//* \brief Enable TWI IT
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_TWI_EnableIt( AT91PS_TWI pTWI, // \arg pointer to a TWI controller
- unsigned int flag ) // \arg IT to be enabled
-{
- //* Write to the IER register
- pTWI->TWI_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TWI_DisableIt
-//* \brief Disable TWI IT
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_TWI_DisableIt( AT91PS_TWI pTWI, // \arg pointer to a TWI controller
- unsigned int flag ) // \arg IT to be disabled
-{
- //* Write to the IDR register
- pTWI->TWI_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TWI_Configure
-//* \brief Configure TWI in master mode
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_TWI_Configure( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller
-{
- //* Disable interrupts
- pTWI->TWI_IDR = ( unsigned int )-1;
-
- //* Reset peripheral
- pTWI->TWI_CR = AT91C_TWI_SWRST;
-
- //* Set Master mode
- pTWI->TWI_CR = AT91C_TWI_MSEN;
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TWI_GetInterruptMaskStatus
-//* \brief Return TWI Interrupt Mask Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
- AT91PS_TWI pTwi ) // \arg pointer to a TWI controller
-{
- return pTwi->TWI_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TWI_IsInterruptMasked
-//* \brief Test if TWI Interrupt is Masked
-//*----------------------------------------------------------------------------
-static __inline int
-AT91F_TWI_IsInterruptMasked( AT91PS_TWI pTwi, // \arg pointer to a TWI controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_TWI_GetInterruptMaskStatus( pTwi ) & flag );
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR PWMC
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWM_GetStatus
-//* \brief Return PWM Interrupt Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
- AT91PS_PWMC pPWM ) // pointer to a PWM controller
-{
- return pPWM->PWMC_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWM_InterruptEnable
-//* \brief Enable PWM Interrupt
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PWMC_InterruptEnable( AT91PS_PWMC pPwm, // \arg pointer to a PWM controller
- unsigned int flag ) // \arg PWM interrupt to be enabled
-{
- pPwm->PWMC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWM_InterruptDisable
-//* \brief Disable PWM Interrupt
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PWMC_InterruptDisable( AT91PS_PWMC pPwm, // \arg pointer to a PWM controller
- unsigned int flag ) // \arg PWM interrupt to be disabled
-{
- pPwm->PWMC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWM_GetInterruptMaskStatus
-//* \brief Return PWM Interrupt Mask Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
- AT91PS_PWMC pPwm ) // \arg pointer to a PWM controller
-{
- return pPwm->PWMC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWM_IsInterruptMasked
-//* \brief Test if PWM Interrupt is Masked
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PWMC_IsInterruptMasked( AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_PWMC_GetInterruptMaskStatus( pPWM ) & flag );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWM_IsStatusSet
-//* \brief Test if PWM Interrupt is Set
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_PWMC_IsStatusSet( AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_PWMC_GetStatus( pPWM ) & flag );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWM_CfgChannel
-//* \brief Test if PWM Interrupt is Set
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PWMC_CfgChannel( AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
- unsigned int channelId, // \arg PWM channel ID
- unsigned int mode, // \arg PWM mode
- unsigned int period, // \arg PWM period
- unsigned int duty ) // \arg PWM duty cycle
-{
- pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
- pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
- pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWM_StartChannel
-//* \brief Enable channel
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PWMC_StartChannel( AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
- unsigned int flag ) // \arg Channels IDs to be enabled
-{
- pPWM->PWMC_ENA = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWM_StopChannel
-//* \brief Disable channel
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PWMC_StopChannel( AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
- unsigned int flag ) // \arg Channels IDs to be enabled
-{
- pPWM->PWMC_DIS = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWM_UpdateChannel
-//* \brief Update Period or Duty Cycle
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PWMC_UpdateChannel( AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
- unsigned int channelId, // \arg PWM channel ID
- unsigned int update ) // \arg Channels IDs to be enabled
-{
- pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR UDP
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_EnableIt
-//* \brief Enable UDP IT
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_UDP_EnableIt( AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned int flag ) // \arg IT to be enabled
-{
- //* Write to the IER register
- pUDP->UDP_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_DisableIt
-//* \brief Disable UDP IT
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_UDP_DisableIt( AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned int flag ) // \arg IT to be disabled
-{
- //* Write to the IDR register
- pUDP->UDP_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_SetAddress
-//* \brief Set UDP functional address
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_UDP_SetAddress( AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned char address ) // \arg new UDP address
-{
- pUDP->UDP_FADDR = ( AT91C_UDP_FEN | address );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_EnableEp
-//* \brief Enable Endpoint
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_UDP_EnableEp( AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned char endpoint ) // \arg endpoint number
-{
- pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_DisableEp
-//* \brief Enable Endpoint
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_UDP_DisableEp( AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned char endpoint ) // \arg endpoint number
-{
- pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_SetState
-//* \brief Set UDP Device state
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_UDP_SetState( AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned int flag ) // \arg new UDP address
-{
- pUDP->UDP_GLBSTATE &= ~( AT91C_UDP_FADDEN | AT91C_UDP_CONFG );
- pUDP->UDP_GLBSTATE |= flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_GetState
-//* \brief return UDP Device state
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_UDP_GetState( // \return the UDP device state
- AT91PS_UDP pUDP ) // \arg pointer to a UDP controller
-{
- return ( pUDP->UDP_GLBSTATE & ( AT91C_UDP_FADDEN | AT91C_UDP_CONFG ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_ResetEp
-//* \brief Reset UDP endpoint
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_UDP_ResetEp( // \return the UDP device state
- AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned int flag ) // \arg Endpoints to be reset
-{
- pUDP->UDP_RSTEP = flag;
- pUDP->UDP_RSTEP = 0;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_EpStall
-//* \brief Endpoint will STALL requests
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_UDP_EpStall( AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned char endpoint ) // \arg endpoint number
-{
- pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_EpWrite
-//* \brief Write value in the DPR
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_UDP_EpWrite( AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned char endpoint, // \arg endpoint number
- unsigned char value ) // \arg value to be written in the DPR
-{
- pUDP->UDP_FDR[endpoint] = value;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_EpRead
-//* \brief Return value from the DPR
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_UDP_EpRead( AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned char endpoint ) // \arg endpoint number
-{
- return pUDP->UDP_FDR[endpoint];
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_EpEndOfWr
-//* \brief Notify the UDP that values in DPR are ready to be sent
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_UDP_EpEndOfWr( AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned char endpoint ) // \arg endpoint number
-{
- pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_EpClear
-//* \brief Clear flag in the endpoint CSR register
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_UDP_EpClear( AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned char endpoint, // \arg endpoint number
- unsigned int flag ) // \arg flag to be cleared
-{
- pUDP->UDP_CSR[endpoint] &= ~( flag );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_EpSet
-//* \brief Set flag in the endpoint CSR register
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_UDP_EpSet( AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned char endpoint, // \arg endpoint number
- unsigned int flag ) // \arg flag to be cleared
-{
- pUDP->UDP_CSR[endpoint] |= flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_EpStatus
-//* \brief Return the endpoint CSR register
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_UDP_EpStatus( AT91PS_UDP pUDP, // \arg pointer to a UDP controller
- unsigned char endpoint ) // \arg endpoint number
-{
- return pUDP->UDP_CSR[endpoint];
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_GetInterruptMaskStatus
-//* \brief Return UDP Interrupt Mask Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_UDP_GetInterruptMaskStatus( AT91PS_UDP pUdp ) // \arg pointer to a UDP controller
-{
- return pUdp->UDP_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_IsInterruptMasked
-//* \brief Test if UDP Interrupt is Masked
-//*----------------------------------------------------------------------------
-static __inline int
-AT91F_UDP_IsInterruptMasked( AT91PS_UDP pUdp, // \arg pointer to a UDP controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_UDP_GetInterruptMaskStatus( pUdp ) & flag );
-}
-
-// ----------------------------------------------------------------------------
-// \fn AT91F_UDP_InterruptStatusRegister
-// \brief Return the Interrupt Status Register
-// ----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_UDP_InterruptStatusRegister( AT91PS_UDP pUDP ) // \arg pointer to a UDP controller
-{
- return pUDP->UDP_ISR;
-}
-
-// ----------------------------------------------------------------------------
-// \fn AT91F_UDP_InterruptClearRegister
-// \brief Clear Interrupt Register
-// ----------------------------------------------------------------------------
-static __inline void
-AT91F_UDP_InterruptClearRegister( AT91PS_UDP pUDP, // \arg pointer to UDP controller
- unsigned int flag ) // \arg IT to be cleat
-{
- pUDP->UDP_ICR = flag;
-}
-
-// ----------------------------------------------------------------------------
-// \fn AT91F_UDP_EnableTransceiver
-// \brief Enable transceiver
-// ----------------------------------------------------------------------------
-static __inline void
-AT91F_UDP_EnableTransceiver( AT91PS_UDP pUDP ) // \arg pointer to a UDP controller
-{
- pUDP->UDP_TXVC &= ~AT91C_UDP_TXVDIS;
-}
-
-// ----------------------------------------------------------------------------
-// \fn AT91F_UDP_DisableTransceiver
-// \brief Disable transceiver
-// ----------------------------------------------------------------------------
-static __inline void
-AT91F_UDP_DisableTransceiver( AT91PS_UDP pUDP ) // \arg pointer to a UDP controller
-{
- pUDP->UDP_TXVC = AT91C_UDP_TXVDIS;
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR TC
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TC_InterruptEnable
-//* \brief Enable TC Interrupt
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_TC_InterruptEnable( AT91PS_TC pTc, // \arg pointer to a TC controller
- unsigned int flag ) // \arg TC interrupt to be enabled
-{
- pTc->TC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TC_InterruptDisable
-//* \brief Disable TC Interrupt
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_TC_InterruptDisable( AT91PS_TC pTc, // \arg pointer to a TC controller
- unsigned int flag ) // \arg TC interrupt to be disabled
-{
- pTc->TC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TC_GetInterruptMaskStatus
-//* \brief Return TC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
- AT91PS_TC pTc ) // \arg pointer to a TC controller
-{
- return pTc->TC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TC_IsInterruptMasked
-//* \brief Test if TC Interrupt is Masked
-//*----------------------------------------------------------------------------
-static __inline int
-AT91F_TC_IsInterruptMasked( AT91PS_TC pTc, // \arg pointer to a TC controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_TC_GetInterruptMaskStatus( pTc ) & flag );
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR CAN
- ***************************************************************************** */
-#define STANDARD_FORMAT 0
-#define EXTENDED_FORMAT 1
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_InitMailboxRegisters()
-//* \brief Configure the corresponding mailbox
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_InitMailboxRegisters( AT91PS_CAN_MB CAN_Mailbox,
- int mode_reg,
- int acceptance_mask_reg, int id_reg, int data_low_reg, int data_high_reg, int control_reg )
-{
- CAN_Mailbox->CAN_MB_MCR = 0x0;
- CAN_Mailbox->CAN_MB_MMR = mode_reg;
- CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg;
- CAN_Mailbox->CAN_MB_MID = id_reg;
- CAN_Mailbox->CAN_MB_MDL = data_low_reg;
- CAN_Mailbox->CAN_MB_MDH = data_high_reg;
- CAN_Mailbox->CAN_MB_MCR = control_reg;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_EnableCAN()
-//* \brief
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_EnableCAN( AT91PS_CAN pCAN ) // pointer to a CAN controller
-{
- pCAN->CAN_MR |= AT91C_CAN_CANEN;
-
- // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver
- while( ( pCAN->CAN_SR & AT91C_CAN_WAKEUP ) != AT91C_CAN_WAKEUP );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_DisableCAN()
-//* \brief
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_DisableCAN( AT91PS_CAN pCAN ) // pointer to a CAN controller
-{
- pCAN->CAN_MR &= ~AT91C_CAN_CANEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_EnableIt
-//* \brief Enable CAN interrupt
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_CAN_EnableIt( AT91PS_CAN pCAN, // pointer to a CAN controller
- unsigned int flag ) // IT to be enabled
-{
- //* Write to the IER register
- pCAN->CAN_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_DisableIt
-//* \brief Disable CAN interrupt
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_CAN_DisableIt( AT91PS_CAN pCAN, // pointer to a CAN controller
- unsigned int flag ) // IT to be disabled
-{
- //* Write to the IDR register
- pCAN->CAN_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetStatus
-//* \brief Return CAN Interrupt Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_CAN_GetStatus( // \return CAN Interrupt Status
- AT91PS_CAN pCAN ) // pointer to a CAN controller
-{
- return pCAN->CAN_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetInterruptMaskStatus
-//* \brief Return CAN Interrupt Mask Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status
- AT91PS_CAN pCAN ) // pointer to a CAN controller
-{
- return pCAN->CAN_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_IsInterruptMasked
-//* \brief Test if CAN Interrupt is Masked
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_CAN_IsInterruptMasked( AT91PS_CAN pCAN, // \arg pointer to a CAN controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_CAN_GetInterruptMaskStatus( pCAN ) & flag );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_IsStatusSet
-//* \brief Test if CAN Interrupt is Set
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_CAN_IsStatusSet( AT91PS_CAN pCAN, // \arg pointer to a CAN controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_CAN_GetStatus( pCAN ) & flag );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_CfgModeReg
-//* \brief Configure the Mode Register of the CAN controller
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_CAN_CfgModeReg( AT91PS_CAN pCAN, // pointer to a CAN controller
- unsigned int mode ) // mode register
-{
- //* Write to the MR register
- pCAN->CAN_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetModeReg
-//* \brief Return the Mode Register of the CAN controller value
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_CAN_GetModeReg( AT91PS_CAN pCAN // pointer to a CAN controller
- )
-{
- return pCAN->CAN_MR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_CfgBaudrateReg
-//* \brief Configure the Baudrate of the CAN controller for the network
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_CAN_CfgBaudrateReg( AT91PS_CAN pCAN, // pointer to a CAN controller
- unsigned int baudrate_cfg )
-{
- //* Write to the BR register
- pCAN->CAN_BR = baudrate_cfg;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetBaudrate
-//* \brief Return the Baudrate of the CAN controller for the network value
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_CAN_GetBaudrate( AT91PS_CAN pCAN // pointer to a CAN controller
- )
-{
- return pCAN->CAN_BR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetInternalCounter
-//* \brief Return CAN Timer Regsiter Value
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_CAN_GetInternalCounter( AT91PS_CAN pCAN // pointer to a CAN controller
- )
-{
- return pCAN->CAN_TIM;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetTimestamp
-//* \brief Return CAN Timestamp Register Value
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_CAN_GetTimestamp( AT91PS_CAN pCAN // pointer to a CAN controller
- )
-{
- return pCAN->CAN_TIMESTP;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetErrorCounter
-//* \brief Return CAN Error Counter Register Value
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_CAN_GetErrorCounter( AT91PS_CAN pCAN // pointer to a CAN controller
- )
-{
- return pCAN->CAN_ECR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_InitTransferRequest
-//* \brief Request for a transfer on the corresponding mailboxes
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_CAN_InitTransferRequest( AT91PS_CAN pCAN, // pointer to a CAN controller
- unsigned int transfer_cmd )
-{
- pCAN->CAN_TCR = transfer_cmd;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_InitAbortRequest
-//* \brief Abort the corresponding mailboxes
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_CAN_InitAbortRequest( AT91PS_CAN pCAN, // pointer to a CAN controller
- unsigned int abort_cmd )
-{
- pCAN->CAN_ACR = abort_cmd;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_CfgMessageModeReg
-//* \brief Program the Message Mode Register
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_CAN_CfgMessageModeReg( AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
- unsigned int mode )
-{
- CAN_Mailbox->CAN_MB_MMR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetMessageModeReg
-//* \brief Return the Message Mode Register
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_CAN_GetMessageModeReg( AT91PS_CAN_MB CAN_Mailbox ) // pointer to a CAN Mailbox
-{
- return CAN_Mailbox->CAN_MB_MMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_CfgMessageIDReg
-//* \brief Program the Message ID Register
-//* \brief Version == 0 for Standard messsage, Version == 1 for Extended
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_CAN_CfgMessageIDReg( AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
- unsigned int id, unsigned char version )
-{
- if( version == 0 ) // IDvA Standard Format
- CAN_Mailbox->CAN_MB_MID = id << 18;
- else // IDvB Extended Format
- CAN_Mailbox->CAN_MB_MID = id | ( 1 << 29 ); // set MIDE bit
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetMessageIDReg
-//* \brief Return the Message ID Register
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_CAN_GetMessageIDReg( AT91PS_CAN_MB CAN_Mailbox ) // pointer to a CAN Mailbox
-{
- return CAN_Mailbox->CAN_MB_MID;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg
-//* \brief Program the Message Acceptance Mask Register
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_CAN_CfgMessageAcceptanceMaskReg( AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
- unsigned int mask )
-{
- CAN_Mailbox->CAN_MB_MAM = mask;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg
-//* \brief Return the Message Acceptance Mask Register
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_CAN_GetMessageAcceptanceMaskReg( AT91PS_CAN_MB CAN_Mailbox ) // pointer to a CAN Mailbox
-{
- return CAN_Mailbox->CAN_MB_MAM;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetFamilyID
-//* \brief Return the Message ID Register
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_CAN_GetFamilyID( AT91PS_CAN_MB CAN_Mailbox ) // pointer to a CAN Mailbox
-{
- return CAN_Mailbox->CAN_MB_MFID;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_CfgMessageCtrl
-//* \brief Request and config for a transfer on the corresponding mailbox
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_CAN_CfgMessageCtrlReg( AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
- unsigned int message_ctrl_cmd )
-{
- CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetMessageStatus
-//* \brief Return CAN Mailbox Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_CAN_GetMessageStatus( AT91PS_CAN_MB CAN_Mailbox ) // pointer to a CAN Mailbox
-{
- return CAN_Mailbox->CAN_MB_MSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_CfgMessageDataLow
-//* \brief Program data low value
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_CAN_CfgMessageDataLow( AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
- unsigned int data )
-{
- CAN_Mailbox->CAN_MB_MDL = data;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetMessageDataLow
-//* \brief Return data low value
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_CAN_GetMessageDataLow( AT91PS_CAN_MB CAN_Mailbox ) // pointer to a CAN Mailbox
-{
- return CAN_Mailbox->CAN_MB_MDL;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_CfgMessageDataHigh
-//* \brief Program data high value
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_CAN_CfgMessageDataHigh( AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox
- unsigned int data )
-{
- CAN_Mailbox->CAN_MB_MDH = data;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_GetMessageDataHigh
-//* \brief Return data high value
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_CAN_GetMessageDataHigh( AT91PS_CAN_MB CAN_Mailbox ) // pointer to a CAN Mailbox
-{
- return CAN_Mailbox->CAN_MB_MDH;
-}
-
-/* *****************************************************************************
- SOFTWARE API FOR ADC
- ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_EnableIt
-//* \brief Enable ADC interrupt
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_ADC_EnableIt( AT91PS_ADC pADC, // pointer to a ADC controller
- unsigned int flag ) // IT to be enabled
-{
- //* Write to the IER register
- pADC->ADC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_DisableIt
-//* \brief Disable ADC interrupt
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_ADC_DisableIt( AT91PS_ADC pADC, // pointer to a ADC controller
- unsigned int flag ) // IT to be disabled
-{
- //* Write to the IDR register
- pADC->ADC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetStatus
-//* \brief Return ADC Interrupt Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_ADC_GetStatus( // \return ADC Interrupt Status
- AT91PS_ADC pADC ) // pointer to a ADC controller
-{
- return pADC->ADC_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetInterruptMaskStatus
-//* \brief Return ADC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
- AT91PS_ADC pADC ) // pointer to a ADC controller
-{
- return pADC->ADC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_IsInterruptMasked
-//* \brief Test if ADC Interrupt is Masked
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_ADC_IsInterruptMasked( AT91PS_ADC pADC, // \arg pointer to a ADC controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_ADC_GetInterruptMaskStatus( pADC ) & flag );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_IsStatusSet
-//* \brief Test if ADC Status is Set
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_ADC_IsStatusSet( AT91PS_ADC pADC, // \arg pointer to a ADC controller
- unsigned int flag ) // \arg flag to be tested
-{
- return ( AT91F_ADC_GetStatus( pADC ) & flag );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_CfgModeReg
-//* \brief Configure the Mode Register of the ADC controller
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_ADC_CfgModeReg( AT91PS_ADC pADC, // pointer to a ADC controller
- unsigned int mode ) // mode register
-{
- //* Write to the MR register
- pADC->ADC_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetModeReg
-//* \brief Return the Mode Register of the ADC controller value
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_ADC_GetModeReg( AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- return pADC->ADC_MR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_CfgTimings
-//* \brief Configure the different necessary timings of the ADC controller
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_ADC_CfgTimings( AT91PS_ADC pADC, // pointer to a ADC controller
- unsigned int mck_clock, // in MHz
- unsigned int adc_clock, // in MHz
- unsigned int startup_time, // in us
- unsigned int sample_and_hold_time ) // in ns
-{
- unsigned int prescal, startup, shtim;
-
- prescal = mck_clock / ( 2 * adc_clock ) - 1;
- startup = adc_clock * startup_time / 8 - 1;
- shtim = adc_clock * sample_and_hold_time / 1000 - 1;
-
- //* Write to the MR register
- pADC->ADC_MR =
- ( ( prescal << 8 ) & AT91C_ADC_PRESCAL ) | ( ( startup << 16 ) & AT91C_ADC_STARTUP ) | ( ( shtim << 24 ) &
- AT91C_ADC_SHTIM );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_EnableChannel
-//* \brief Return ADC Timer Register Value
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_ADC_EnableChannel( AT91PS_ADC pADC, // pointer to a ADC controller
- unsigned int channel ) // mode register
-{
- //* Write to the CHER register
- pADC->ADC_CHER = channel;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_DisableChannel
-//* \brief Return ADC Timer Register Value
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_ADC_DisableChannel( AT91PS_ADC pADC, // pointer to a ADC controller
- unsigned int channel ) // mode register
-{
- //* Write to the CHDR register
- pADC->ADC_CHDR = channel;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetChannelStatus
-//* \brief Return ADC Timer Register Value
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_ADC_GetChannelStatus( AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- return pADC->ADC_CHSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_StartConversion
-//* \brief Software request for a analog to digital conversion
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_ADC_StartConversion( AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- pADC->ADC_CR = AT91C_ADC_START;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_SoftReset
-//* \brief Software reset
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_ADC_SoftReset( AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- pADC->ADC_CR = AT91C_ADC_SWRST;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetLastConvertedData
-//* \brief Return the Last Converted Data
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_ADC_GetLastConvertedData( AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- return pADC->ADC_LCDR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetConvertedDataCH0
-//* \brief Return the Channel 0 Converted Data
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_ADC_GetConvertedDataCH0( AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- return pADC->ADC_CDR0;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetConvertedDataCH1
-//* \brief Return the Channel 1 Converted Data
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_ADC_GetConvertedDataCH1( AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- return pADC->ADC_CDR1;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetConvertedDataCH2
-//* \brief Return the Channel 2 Converted Data
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_ADC_GetConvertedDataCH2( AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- return pADC->ADC_CDR2;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetConvertedDataCH3
-//* \brief Return the Channel 3 Converted Data
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_ADC_GetConvertedDataCH3( AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- return pADC->ADC_CDR3;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetConvertedDataCH4
-//* \brief Return the Channel 4 Converted Data
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_ADC_GetConvertedDataCH4( AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- return pADC->ADC_CDR4;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetConvertedDataCH5
-//* \brief Return the Channel 5 Converted Data
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_ADC_GetConvertedDataCH5( AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- return pADC->ADC_CDR5;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetConvertedDataCH6
-//* \brief Return the Channel 6 Converted Data
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_ADC_GetConvertedDataCH6( AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- return pADC->ADC_CDR6;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_GetConvertedDataCH7
-//* \brief Return the Channel 7 Converted Data
-//*----------------------------------------------------------------------------
-static __inline unsigned int
-AT91F_ADC_GetConvertedDataCH7( AT91PS_ADC pADC // pointer to a ADC controller
- )
-{
- return pADC->ADC_CDR7;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_MC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for MC
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_MC_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_SYS ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_DBGU_CfgPMC
-//* \brief Enable Peripheral clock in PMC for DBGU
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_DBGU_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_SYS ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_DBGU_CfgPIO
-//* \brief Configure PIO controllers to drive DBGU signals
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_DBGU_CfgPIO( void )
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, // PIO controller base address
- ( ( unsigned int )AT91C_PA28_DTXD ) | ( ( unsigned int )AT91C_PA27_DRXD ), // Peripheral A
- 0 ); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWMC_CH3_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH3 signals
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PWMC_CH3_CfgPIO( void )
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address
- ( ( unsigned int )AT91C_PB22_PWM3 ), // Peripheral A
- ( ( unsigned int )AT91C_PB30_PWM3 ) ); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWMC_CH2_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH2 signals
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PWMC_CH2_CfgPIO( void )
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address
- ( ( unsigned int )AT91C_PB21_PWM2 ), // Peripheral A
- ( ( unsigned int )AT91C_PB29_PWM2 ) ); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWMC_CH1_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH1 signals
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PWMC_CH1_CfgPIO( void )
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address
- ( ( unsigned int )AT91C_PB20_PWM1 ), // Peripheral A
- ( ( unsigned int )AT91C_PB28_PWM1 ) ); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWMC_CH0_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH0 signals
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PWMC_CH0_CfgPIO( void )
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address
- ( ( unsigned int )AT91C_PB19_PWM0 ), // Peripheral A
- ( ( unsigned int )AT91C_PB27_PWM0 ) ); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_EMAC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for EMAC
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_EMAC_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_EMAC ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_EMAC_CfgPIO
-//* \brief Configure PIO controllers to drive EMAC signals
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_EMAC_CfgPIO( void )
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address
- ( ( unsigned int )AT91C_PB9_EMDIO ) | ( ( unsigned int )AT91C_PB17_ERXCK ) | ( ( unsigned int )AT91C_PB15_ERXDV_ECRSDV ) | ( ( unsigned int )AT91C_PB8_EMDC ) | ( ( unsigned int )AT91C_PB16_ECOL ) | ( ( unsigned int )AT91C_PB7_ERXER ) | ( ( unsigned int )AT91C_PB5_ERX0 ) | ( ( unsigned int )AT91C_PB6_ERX1 ) | ( ( unsigned int )AT91C_PB13_ERX2 ) | ( ( unsigned int )AT91C_PB1_ETXEN ) | ( ( unsigned int )AT91C_PB14_ERX3 ) | ( ( unsigned int )AT91C_PB12_ETXER ) | ( ( unsigned int )AT91C_PB2_ETX0 ) | ( ( unsigned int )AT91C_PB3_ETX1 ) | ( ( unsigned int )AT91C_PB10_ETX2 ) | ( ( unsigned int )AT91C_PB18_EF100 ) | ( ( unsigned int )AT91C_PB11_ETX3 ) | ( ( unsigned int )AT91C_PB4_ECRS ) | ( ( unsigned int )AT91C_PB0_ETXCK_EREFCK ), // Peripheral A
- 0 ); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_VREG_CfgPMC
-//* \brief Enable Peripheral clock in PMC for VREG
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_VREG_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_SYS ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for SSC
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_SSC_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_SSC ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SSC_CfgPIO
-//* \brief Configure PIO controllers to drive SSC signals
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_SSC_CfgPIO( void )
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, // PIO controller base address
- ( ( unsigned int )AT91C_PA23_TD ) | ( ( unsigned int )AT91C_PA21_TF ) | ( ( unsigned int )AT91C_PA25_RK ) | ( ( unsigned int )AT91C_PA24_RD ) | ( ( unsigned int )AT91C_PA26_RF ) | ( ( unsigned int )AT91C_PA22_TK ), // Peripheral A
- 0 ); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI1_CfgPMC
-//* \brief Enable Peripheral clock in PMC for SPI1
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_SPI1_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_SPI1 ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI1_CfgPIO
-//* \brief Configure PIO controllers to drive SPI1 signals
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_SPI1_CfgPIO( void )
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, // PIO controller base address
- 0, // Peripheral A
- ( ( unsigned int )AT91C_PA23_SPI1_MOSI ) | ( ( unsigned int )AT91C_PA21_SPI1_NPCS0 ) | ( ( unsigned int )AT91C_PA25_SPI1_NPCS1 ) | ( ( unsigned int )AT91C_PA2_SPI1_NPCS1 ) | ( ( unsigned int )AT91C_PA24_SPI1_MISO ) | ( ( unsigned int )AT91C_PA22_SPI1_SPCK ) | ( ( unsigned int )AT91C_PA26_SPI1_NPCS2 ) | ( ( unsigned int )AT91C_PA3_SPI1_NPCS2 ) | ( ( unsigned int )AT91C_PA29_SPI1_NPCS3 ) | ( ( unsigned int )AT91C_PA4_SPI1_NPCS3 ) ); // Peripheral B
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address
- 0, // Peripheral A
- ( ( unsigned int )AT91C_PB10_SPI1_NPCS1 ) | ( ( unsigned int )AT91C_PB11_SPI1_NPCS2 ) | ( ( unsigned int )AT91C_PB16_SPI1_NPCS3 ) ); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI0_CfgPMC
-//* \brief Enable Peripheral clock in PMC for SPI0
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_SPI0_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_SPI0 ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_SPI0_CfgPIO
-//* \brief Configure PIO controllers to drive SPI0 signals
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_SPI0_CfgPIO( void )
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, // PIO controller base address
- ( ( unsigned int )AT91C_PA17_SPI0_MOSI ) | ( ( unsigned int )AT91C_PA12_SPI0_NPCS0 ) | ( ( unsigned int )AT91C_PA13_SPI0_NPCS1 ) | ( ( unsigned int )AT91C_PA16_SPI0_MISO ) | ( ( unsigned int )AT91C_PA14_SPI0_NPCS2 ) | ( ( unsigned int )AT91C_PA18_SPI0_SPCK ) | ( ( unsigned int )AT91C_PA15_SPI0_NPCS3 ), // Peripheral A
- ( ( unsigned int )AT91C_PA7_SPI0_NPCS1 ) | ( ( unsigned int )AT91C_PA8_SPI0_NPCS2 ) | ( ( unsigned int )AT91C_PA9_SPI0_NPCS3 ) ); // Peripheral B
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address
- 0, // Peripheral A
- ( ( unsigned int )AT91C_PB13_SPI0_NPCS1 ) | ( ( unsigned int )AT91C_PB14_SPI0_NPCS2 ) | ( ( unsigned int )AT91C_PB17_SPI0_NPCS3 ) ); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PWMC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for PWMC
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PWMC_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_PWMC ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TC0_CfgPMC
-//* \brief Enable Peripheral clock in PMC for TC0
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_TC0_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_TC0 ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TC0_CfgPIO
-//* \brief Configure PIO controllers to drive TC0 signals
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_TC0_CfgPIO( void )
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address
- ( ( unsigned int )AT91C_PB23_TIOA0 ) | ( ( unsigned int )AT91C_PB24_TIOB0 ), // Peripheral A
- ( ( unsigned int )AT91C_PB12_TCLK0 ) ); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TC1_CfgPMC
-//* \brief Enable Peripheral clock in PMC for TC1
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_TC1_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_TC1 ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TC1_CfgPIO
-//* \brief Configure PIO controllers to drive TC1 signals
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_TC1_CfgPIO( void )
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address
- ( ( unsigned int )AT91C_PB25_TIOA1 ) | ( ( unsigned int )AT91C_PB26_TIOB1 ), // Peripheral A
- ( ( unsigned int )AT91C_PB19_TCLK1 ) ); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TC2_CfgPMC
-//* \brief Enable Peripheral clock in PMC for TC2
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_TC2_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_TC2 ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TC2_CfgPIO
-//* \brief Configure PIO controllers to drive TC2 signals
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_TC2_CfgPIO( void )
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, // PIO controller base address
- 0, // Peripheral A
- ( ( unsigned int )AT91C_PA15_TCLK2 ) ); // Peripheral B
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address
- ( ( unsigned int )AT91C_PB27_TIOA2 ) | ( ( unsigned int )AT91C_PB28_TIOB2 ), // Peripheral A
- 0 ); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PITC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for PITC
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PITC_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_SYS ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for ADC
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_ADC_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_ADC ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_ADC_CfgPIO
-//* \brief Configure PIO controllers to drive ADC signals
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_ADC_CfgPIO( void )
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address
- 0, // Peripheral A
- ( ( unsigned int )AT91C_PB18_ADTRG ) ); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for PMC
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PMC_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_SYS ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PMC_CfgPIO
-//* \brief Configure PIO controllers to drive PMC signals
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PMC_CfgPIO( void )
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, // PIO controller base address
- 0, // Peripheral A
- ( ( unsigned int )AT91C_PA13_PCK1 ) | ( ( unsigned int )AT91C_PA30_PCK2 ) | ( ( unsigned int )AT91C_PA27_PCK3 ) ); // Peripheral B
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address
- ( ( unsigned int )AT91C_PB29_PCK1 ) | ( ( unsigned int )AT91C_PB30_PCK2 ), // Peripheral A
- ( ( unsigned int )AT91C_PB21_PCK1 ) | ( ( unsigned int )AT91C_PB22_PCK2 ) | ( ( unsigned int )AT91C_PB20_PCK0 ) | ( ( unsigned int )AT91C_PB0_PCK0 ) ); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_RSTC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for RSTC
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_RSTC_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_SYS ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_RTTC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for RTTC
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_RTTC_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_SYS ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIOA_CfgPMC
-//* \brief Enable Peripheral clock in PMC for PIOA
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIOA_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_PIOA ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_PIOB_CfgPMC
-//* \brief Enable Peripheral clock in PMC for PIOB
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_PIOB_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_PIOB ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TWI_CfgPMC
-//* \brief Enable Peripheral clock in PMC for TWI
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_TWI_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_TWI ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_TWI_CfgPIO
-//* \brief Configure PIO controllers to drive TWI signals
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_TWI_CfgPIO( void )
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, // PIO controller base address
- ( ( unsigned int )AT91C_PA10_TWD ) | ( ( unsigned int )AT91C_PA11_TWCK ), // Peripheral A
- 0 ); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_WDTC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for WDTC
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_WDTC_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_SYS ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US1_CfgPMC
-//* \brief Enable Peripheral clock in PMC for US1
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_US1_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_US1 ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US1_CfgPIO
-//* \brief Configure PIO controllers to drive US1 signals
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_US1_CfgPIO( void )
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, // PIO controller base address
- ( ( unsigned int )AT91C_PA5_RXD1 ) | ( ( unsigned int )AT91C_PA6_TXD1 ) | ( ( unsigned int )AT91C_PA8_RTS1 ) | ( ( unsigned int )AT91C_PA7_SCK1 ) | ( ( unsigned int )AT91C_PA9_CTS1 ), // Peripheral A
- 0 ); // Peripheral B
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address
- 0, // Peripheral A
- ( ( unsigned int )AT91C_PB25_DTR1 ) | ( ( unsigned int )AT91C_PB23_DCD1 ) | ( ( unsigned int )AT91C_PB24_DSR1 ) | ( ( unsigned int )AT91C_PB26_RI1 ) ); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US0_CfgPMC
-//* \brief Enable Peripheral clock in PMC for US0
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_US0_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_US0 ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_US0_CfgPIO
-//* \brief Configure PIO controllers to drive US0 signals
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_US0_CfgPIO( void )
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, // PIO controller base address
- ( ( unsigned int )AT91C_PA0_RXD0 ) | ( ( unsigned int )AT91C_PA1_TXD0 ) | ( ( unsigned int )AT91C_PA3_RTS0 ) | ( ( unsigned int )AT91C_PA2_SCK0 ) | ( ( unsigned int )AT91C_PA4_CTS0 ), // Peripheral A
- 0 ); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_UDP_CfgPMC
-//* \brief Enable Peripheral clock in PMC for UDP
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_UDP_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_UDP ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for AIC
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_AIC_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_IRQ0 ) |
- ( ( unsigned int )1 << AT91C_ID_FIQ ) | ( ( unsigned int )1 << AT91C_ID_IRQ1 ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_AIC_CfgPIO
-//* \brief Configure PIO controllers to drive AIC signals
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_AIC_CfgPIO( void )
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, // PIO controller base address
- ( ( unsigned int )AT91C_PA30_IRQ0 ) | ( ( unsigned int )AT91C_PA29_FIQ ), // Peripheral A
- ( ( unsigned int )AT91C_PA14_IRQ1 ) ); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_CfgPMC
-//* \brief Enable Peripheral clock in PMC for CAN
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_CAN_CfgPMC( void )
-{
- AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address
- ( ( unsigned int )1 << AT91C_ID_CAN ) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn AT91F_CAN_CfgPIO
-//* \brief Configure PIO controllers to drive CAN signals
-//*----------------------------------------------------------------------------
-static __inline void
-AT91F_CAN_CfgPIO( void )
-{
- // Configure PIO controllers to periph mode
- AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, // PIO controller base address
- ( ( unsigned int )AT91C_PA20_CANTX ) | ( ( unsigned int )AT91C_PA19_CANRX ), // Peripheral A
- 0 ); // Peripheral B
-}
-
-#endif // lib_AT91SAM7X256_H
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/system/crt0.s b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/system/crt0.s
deleted file mode 100644
index 3488c5a5..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/system/crt0.s
+++ /dev/null
@@ -1,232 +0,0 @@
-/*****************************************************************************
- * Copyright (c) 2001, 2002 Rowley Associates Limited. *
- * *
- * This file may be distributed under the terms of the License Agreement *
- * provided with this software. *
- * *
- * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE *
- * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
- *****************************************************************************/
-
-/*****************************************************************************
- * Preprocessor Definitions
- * ------------------------
- * APP_ENTRY_POINT
- *
- * Defines the application entry point function, if undefined this setting
- * defaults to "main".
- *
- * INITIALIZE_STACKS
- *
- * If defined, the contents of the stacks will be initialized to a the
- * value 0xCC.
- *
- * INITIALIZE_SECONDARY_SECTIONS
- *
- * If defined, the .text2, .data2 and .bss2 sections will be initialized.
- *
- * SUPERVISOR_START
- *
- * If defined, the application will start up in supervisor mode. If
- * undefined the application will start up in system mode.
- *
- *****************************************************************************/
-
- .section .init, "ax"
- .code 32
- .align 4
-
-#ifndef APP_ENTRY_POINT
-#define APP_ENTRY_POINT main
-#endif
-
- .weak _start
- .global __start
- .global __gccmain
- .extern APP_ENTRY_POINT
- .extern exit
-
-/*****************************************************************************
- * Function : _start *
- * Description : Main entry point and startup code for C system. *
- *****************************************************************************/
-_start:
-__start:
- mrs r0, cpsr
- bic r0, r0, #0x1F
-
- /* Setup stacks */
- orr r1, r0, #0x1B /* Undefined mode */
- msr cpsr_cxsf, r1
- ldr sp, =__stack_und_end__
-
- orr r1, r0, #0x17 /* Abort mode */
- msr cpsr_cxsf, r1
- ldr sp, =__stack_abt_end__
-
- orr r1, r0, #0x12 /* IRQ mode */
- msr cpsr_cxsf, r1
- ldr sp, =__stack_irq_end__
-
- orr r1, r0, #0x11 /* FIQ mode */
- msr cpsr_cxsf, r1
- ldr sp, =__stack_fiq_end__
-
- orr r1, r0, #0x13 /* Supervisor mode */
- msr cpsr_cxsf, r1
- ldr sp, =__stack_svc_end__
-#ifdef SUPERVISOR_START
- /* Start application in supervisor mode */
- ldr r1, =__stack_end__ /* Setup user/system mode stack */
- mov r2, sp
- stmfd r2!, {r1}
- ldmfd r2, {sp}^
-#else
- /* Start application in system mode */
- orr r1, r0, #0x1F /* System mode */
- msr cpsr_cxsf, r1
- ldr sp, =__stack_end__
-#endif
-
-#ifdef INITIALIZE_STACKS
- mov r2, #0xCC
- ldr r0, =__stack_und_start__
- ldr r1, =__stack_und_end__
- bl memory_set
- ldr r0, =__stack_abt_start__
- ldr r1, =__stack_abt_end__
- bl memory_set
- ldr r0, =__stack_irq_start__
- ldr r1, =__stack_irq_end__
- bl memory_set
- ldr r0, =__stack_fiq_start__
- ldr r1, =__stack_fiq_end__
- bl memory_set
- ldr r0, =__stack_svc_start__
- ldr r1, =__stack_svc_end__
- bl memory_set
- ldr r0, =__stack_start__
- ldr r1, =__stack_end__
- bl memory_set
-#endif
-
- /* Copy from initialised data section to data section (if necessary). */
- ldr r0, =__data_load_start__
- ldr r1, =__data_start__
- ldr r2, =__data_end__
- bl memory_copy
-
- /* Copy from initialised text section to text section (if necessary). */
- ldr r0, =__text_load_start__
- ldr r1, =__text_start__
- ldr r2, =__text_end__
- bl memory_copy
-
- /* Copy from initialised fast_text section to fast_text section (if necessary). */
- ldr r0, =__fast_load_start__
- ldr r1, =__fast_start__
- ldr r2, =__fast_end__
- bl memory_copy
-
- /* Zero the bss. */
- ldr r0, =__bss_start__
- ldr r1, =__bss_end__
- mov r2, #0
- bl memory_set
-
-#ifdef INITIALIZE_SECONDARY_SECTIONS
- ldr r0, =__data2_load_start__
- ldr r1, =__data2_start__
- ldr r2, =__data2_end__
- bl memory_copy
-
- /* Copy from initialised text2 section to text2 section (if necessary). */
- ldr r0, =__text2_load_start__
- ldr r1, =__text2_start__
- ldr r2, =__text2_end__
- bl memory_copy
-
- /* Zero bss2. */
- ldr r0, =__bss2_start__
- ldr r1, =__bss2_end__
- mov r2, #0
- bl memory_set
-
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-
- /* Initialise the heap */
- ldr r0, = __heap_start__
- ldr r1, = __heap_end__
- sub r1, r1, r0 /* r1 = r1-r0 */
- mov r2, #0
- str r2, [r0], #+4 /* *r0++ = 0 */
- str r1, [r0] /* *r0 = __heap_end__ - __heap_start__ */
-
- /* Call constructors */
- ldr r0, =__ctors_start__
- ldr r1, =__ctors_end__
-ctor_loop:
- cmp r0, r1
- beq ctor_end
- ldr r2, [r0], #+4
- stmfd sp!, {r0-r1}
- mov lr, pc
- mov pc, r2
- ldmfd sp!, {r0-r1}
- b ctor_loop
-ctor_end:
-
- /* Setup initial call frame */
- mov lr, #4
- mov r12, sp
- stmfd sp!, {r11-r12, lr-pc}
- sub r11, r12, #0x00000004
-
-start:
- /* Jump to application entry point */
- mov r0, #0
- mov r1, #0
- ldr r2, =APP_ENTRY_POINT
- mov lr, pc
-#ifdef __ARM_ARCH_3__
- mov pc, r2
-#else
- bx r2
-#endif
-
- /* Call destructors */
- ldr r0, =__dtors_start__
- ldr r1, =__dtors_end__
-dtor_loop:
- cmp r0, r1
- beq dtor_end
- ldr r2, [r0], #+4
- stmfd sp!, {r0-r1}
- mov lr, pc
- mov pc, r2
- ldmfd sp!, {r0-r1}
- b dtor_loop
-dtor_end:
-
- /* Returned from application entry point, loop forever. */
-exit_loop:
- b exit_loop
-
-memory_copy:
- cmp r0, r1
- moveq pc, lr
- subs r2, r2, r1
- moveq pc, lr
-1:
- ldrb r3, [r0], #+1
- strb r3, [r1], #+1
- subs r2, r2, #1
- bne 1b
- mov pc, lr
-
-memory_set:
- cmp r0, r1
- moveq pc, lr
- strb r2, [r0], #1
- b memory_set
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/system/startup.s b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/system/startup.s
deleted file mode 100644
index ce619a06..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/system/startup.s
+++ /dev/null
@@ -1,236 +0,0 @@
-/*****************************************************************************
- Exception handlers and startup code for Atmel AT91SAM7.
-
- Copyright (c) 2004 Rowley Associates Limited.
-
- This file may be distributed under the terms of the License Agreement
- provided with this software.
-
- THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE
- WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *****************************************************************************/
-
-/*****************************************************************************
- * Preprocessor Definitions
- * ------------------------
- *
- * VECTORED_IRQ_INTERRUPTS
- *
- * Enable vectored IRQ interrupts. If defined, the PC register will be loaded
- * with the contents of the AIC_IVR register on an IRQ exception.
- *
- * STARTUP_FROM_RESET
- *
- * If defined, the program will startup from power-on/reset. If not defined
- * the program will just loop endlessly from power-on/reset.
- *
- * This definition is not defined by default on this target because the
- * debugger is unable to reset this target and maintain control of it over the
- * JTAG interface. The advantage of doing this is that it allows the debugger
- * to reset the CPU and run programs from a known reset CPU state on each run.
- * It also acts as a safety net if you accidently download a program in FLASH
- * that crashes and prevents the debugger from taking control over JTAG
- * rendering the target unusable over JTAG. The obvious disadvantage of doing
- * this is that your application will not startup without the debugger.
- *
- * We advise that on this target you keep STARTUP_FROM_RESET undefined whilst
- * you are developing and only define STARTUP_FROM_RESET when development is
- * complete.
- *
- * MC_FMR_FMCN_VAL
- *
- * Override the default Flash Mode Register FMCN value by defining
- * MC_FMR_FMCN_VAL.
- *
- * MC_FMR_FWS_VAL
- *
- * Override the default Flash Mode Register FWS value by defining
- * MC_FMR_FWS_VAL.
- *
- * CKGR_MOR_VAL
- *
- * Override the default Main Oscillator Register value by defining
- * CKGR_MOR_VAL.
- *
- * CKGR_PLLR_VAL
- *
- * Override the default Clock Generator PLL Register value by defining
- * CKGR_PLLR_VAL.
- *
- * NO_WATCHDOG_DISABLE
- *
- * If defined, the watchdog will not be disabled.
- *
- * NO_USER_RESET
- *
- * If defined, user reset will not be enabled.
- *
- * NO_PROTECTION_MODE
- *
- * If defined, AIC protection mode will not be enabled. AIC protection
- * mode allows the AIC_IVR register to be accessed by the debugger (for
- * example through the memory or register window). With protection mode
- * disabled accesses of the AIC_IVR register by the debugger are likely
- * to disrupt interrupt behaviour.
- *
- *****************************************************************************/
-
-#include
-
-#ifndef MC_FMR_FMCN_VAL
-#define MC_FMR_FMCN_VAL 72
-#endif
-
-#ifndef MC_FMR_FWS_VAL
-#define MC_FMR_FWS_VAL 1
-#endif
-
-#ifndef CKGR_MOR_VAL
-#define CKGR_MOR_VAL (0x40 << CKGR_MOR_OSCOUNT_BIT) | CKGR_MOR_MOSCEN
-#endif
-
-#ifndef CKGR_PLLR_VAL
-#if OSCILLATOR_CLOCK_FREQUENCY==18432000
-/* MCK, UDPCK = 18.432MHz * 73 / 14 / 2 = 48.05486MHz */
-#define CKGR_PLLR_VAL (1 << CKGR_PLLR_USBDIV_BIT) | (72 << CKGR_PLLR_MUL_BIT) | (0 << CKGR_PLLR_OUT_BIT) | (63 << CKGR_PLLR_PLLCOUNT_BIT) | (14 << CKGR_PLLR_DIV_BIT)
-#else
-#error OSCILLATOR_CLOCK_FREQUENCY not supported
-#endif
-#endif
-
- .section .vectors, "ax"
- .code 32
- .align 0
- .global _vectors
- .global reset_handler
-
-/*****************************************************************************
- Exception Vectors
- *****************************************************************************/
-_vectors:
-#ifdef STARTUP_FROM_RESET
- ldr pc, [pc, #reset_handler_address - . - 8] /* reset */
-#else
- b . /* reset - infinite loop */
-#endif
- ldr pc, [pc, #undef_handler_address - . - 8] /* undefined instruction */
- ldr pc, [pc, #swi_handler_address - . - 8] /* swi handler */
- ldr pc, [pc, #pabort_handler_address - . - 8] /* abort prefetch */
- ldr pc, [pc, #dabort_handler_address - . - 8] /* abort data */
- nop
- ldr pc, [pc, #-0xF20] /* irq */
- ldr pc, [pc, #fiq_handler_address - . - 8] /* fiq */
-
-reset_handler_address:
- .word reset_handler
-undef_handler_address:
- .word undef_handler
-swi_handler_address:
- .word swi_handler
-pabort_handler_address:
- .word pabort_handler
-dabort_handler_address:
- .word dabort_handler
-irq_handler_address:
- .word irq_handler
-fiq_handler_address:
- .word fiq_handler
-
- .section .init, "ax"
- .code 32
- .align 0
-
-/******************************************************************************
- Reset handler
- ******************************************************************************/
-reset_handler:
- /* Set up FLASH wait state */
- ldr r1, =MC_BASE
- ldr r0, =(MC_FMR_FMCN_VAL << MC_FMR_FMCN_BIT) | (MC_FMR_FWS_VAL << MC_FMR_FWS_BIT)
- str r0, [r1, #MC_FMR_OFFSET]
-
- /* Disable Watchdog */
- ldr r1, =WDT_BASE
- ldr r0, =WDT_MR_WDDIS
- str r0, [r1, #WDT_MR_OFFSET]
-
-#ifndef NO_PROTECTION_MODE
- /* Enable protect mode */
- ldr r1, =AIC_BASE
- ldr r0, =0x00000001
- str r0, [r1, #AIC_DCR_OFFSET]
-#endif
-
- /* Enable the main oscillator */
- ldr r1, =PMC_BASE
- ldr r0, =CKGR_MOR_VAL
- str r0, [r1, #CKGR_MOR_OFFSET]
-
-1:/* Wait for main oscillator to stabilize */
- ldr r0, [r1, #PMC_SR_OFFSET]
- tst r0, #PMC_SR_MOSCS
- beq 1b
-
- /* Set up the PLL */
- ldr r0, =CKGR_PLLR_VAL
- str r0, [r1, #CKGR_PLLR_OFFSET]
-
-1:/* Wait for PLL to lock */
- ldr r0, [r1, #PMC_SR_OFFSET]
- tst r0, #PMC_SR_LOCK
- beq 1b
-
- /* Set the master clock prescaler */
- ldr r0, =(1 << PMC_MCKR_PRES_BIT)
- str r0, [r1, #PMC_MCKR_OFFSET]
-
-1:/* Wait for MCKRDY */
- ldr r0, [r1, #PMC_SR_OFFSET]
- tst r0, #PMC_SR_MCKRDY
- beq 1b
-
- /* Select PLL as clock source */
- ldr r0, =((1 << PMC_MCKR_PRES_BIT) | 3 << PMC_MCKR_CSS_BIT)
- str r0, [r1, #PMC_MCKR_OFFSET]
-
-#ifdef __FLASH_BUILD
- /* Copy exception vectors into Internal SRAM */
- mov r8, #0x00200000
- ldr r9, =_vectors
- ldmia r9!, {r0-r7}
- stmia r8!, {r0-r7}
- ldmia r9!, {r0-r6}
- stmia r8!, {r0-r6}
-
- /* Remap Internal SRAM to 0x00000000 */
- ldr r1, =MC_BASE
- ldr r0, =1
- strb r0, [r1, #MC_RCR_OFFSET]
-#endif
-
- /* Jump to the default C runtime startup code. */
- b _start
-
-/******************************************************************************
- Default exception handlers
- (These are declared weak symbols so they can be redefined in user code)
- ******************************************************************************/
-undef_handler:
- b . /* Endless loop */
-
-swi_handler:
- b . /* Endless loop */
-
-pabort_handler:
- b . /* Endless loop */
-
-dabort_handler:
- b . /* Endless loop */
-
-irq_handler:
- b . /* Endless loop */
-
-fiq_handler:
- b . /* Endless loop */
-
- .weak undef_handler, swi_handler, pabort_handler, dabort_handler, irq_handler, fiq_handler
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/README.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/README.txt
deleted file mode 100644
index 49e53ec6..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/README.txt
+++ /dev/null
@@ -1,68 +0,0 @@
-
- FREEMODBUS 1.5 ATSAM3S EXAMPLE
- ==============================
-
-REQUIREMENTS
-============
-
-This example contains a simple demo program for FreeMODBUS for the AT91SAM3S
-Cortex M3 controllers on the SAM3S-EK [0] evaluation kit. It requires a wired
-RS485 connection to a host processor and a MODBUS master software on the PC
-side to be useful. Demo versions of MODBUS master stacks can be found in
-[1], [2] and [3]. Commercial MODBUS stacks are available from [4].
-
-INSTALLATION
-============
-The SAM3S-EK evaluation board should be modified as following to enable RS485
-data transmission.
-
- - Place Jumpers JP11, JP10 and JP12
- - Place a solder drop accross R25
-
-Warning: The RS485 shares data lines with USART1. It is therefore absolutely
-necessary to set PA23 to a high level.
-
-SOURCE
-======
-
-TESTING
-=======
-
-Start the MODBUS sample application and test if the input registers starting
-at protocol address 1000 can be read. There are four registers values avai-
-lable and the output should look like:
-
-Polling slave (Ctrl-C to stop) ...
-[1000]: 6474
-[1001]: 0
-[1002]: 0
-[1003]: 0
-Polling slave (Ctrl-C to stop) ...
-[1000]: -8831
-[1001]: 0
-[1002]: 0
-[1003]: 0
-Polling slave (Ctrl-C to stop) ...
-
-The simple testing utility used in the 'demo_rtu.bat' script can be found at
-[3].
-
-PROBLEMS
-========
-
-In case you can get no communication working make sure that the RS485 line is
-biased correctly. The SAM3S-EK does not populate the RS485 bias resistors by
-default and if you have a RS485 master which does not bias the lines either
-you will get wrong characters. For this R24 and R30 on the bottom side of the
-evaluation kit of the PCB should be populated.
-
-REFERENCES
-==========
-
-[0] Atmel SAM3S-EK: http://www.atmel.com/dyn/products/tools_card_v2.asp?tool_id=4678
-[1] WinTech ModScan32: http://www.win-tech.com/html/modscan32.htm
-[2] Modus Poll: http://www.modbustools.com/modbus_poll.asp
-[3] FieldTalk Modpoll: http://www.focus-sw.com/fieldtalk/modpoll.html
-[4] Embedded Solutions: http://www.embedded-solutions.at
-
-Version: $Id: README.txt,v 1.1 2010/06/05 09:57:46 wolti Exp $
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/AT91SAM3S4.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/AT91SAM3S4.h
deleted file mode 100644
index a11e72a3..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/AT91SAM3S4.h
+++ /dev/null
@@ -1,7010 +0,0 @@
-/* ---------------------------------------------------------------------------- */
-/* Atmel Microcontroller Software Support */
-/* ---------------------------------------------------------------------------- */
-/* Copyright (c) 2009, Atmel Corporation */
-/* */
-/* All rights reserved. */
-/* */
-/* Redistribution and use in source and binary forms, with or without */
-/* modification, are permitted provided that the following condition is met: */
-/* */
-/* - Redistributions of source code must retain the above copyright notice, */
-/* this list of conditions and the disclaimer below. */
-/* */
-/* Atmel's name may not be used to endorse or promote products derived from */
-/* this software without specific prior written permission. */
-/* */
-/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
-/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
-/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
-/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
-/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
-/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
-/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
-/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
-/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
-/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
-/* ---------------------------------------------------------------------------- */
-/* */
-/* File Name : AT91SAM3S.h */
-/* Object : AT91SAM3S definitions */
-/* Generated by : AT91 SW Application Group */
-/* Generated on : 2009-10-26 */
-
-#ifndef AT91SAM3S_H
-#define AT91SAM3S_H
-
-/** \addtogroup AT91SAM3S_definitions AT91SAM3S definitions
- This file defines all structures and symbols for AT91SAM3S:
- - registers and bitfields
- - peripheral base address
- - peripheral ID
- - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __ASSEMBLY__
-#include
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
-#else
-typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
-#endif
-typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *) value)
-#define REG_ACCESS(type, address) (*(type*)address) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ***************************************************************************** */
-/* CMSIS DEFINITIONS FOR AT91SAM3S */
-/* ***************************************************************************** */
-/** \addtogroup AT91SAM3S_cmsis CMSIS Definitions */
-
-/*@{*/
-
-/**
- * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
- */
-#define __MPU_PRESENT 0 /**< AT91SAM3S does not provide a MPU present or not */
-#define __NVIC_PRIO_BITS 4 /**< AT91SAM3S uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
-
-/**< Interrupt Number Definition */
-typedef enum IRQn
-{
-/****** Cortex-M3 Processor Exceptions Numbers ***************************************/
- NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
- MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */
-/****** AT91SAM3S specific Interrupt Numbers *****************************************/
-
- SUPC_IRQn = 0, /**< 0 AT91SAM3S Supply Controller (SUPC) */
- RSTC_IRQn = 1, /**< 1 AT91SAM3S Reset Controller (RSTC) */
- RTC_IRQn = 2, /**< 2 AT91SAM3S Real Time Clock (RTC) */
- RTT_IRQn = 3, /**< 3 AT91SAM3S Real Time Timer (RTT) */
- WDT_IRQn = 4, /**< 4 AT91SAM3S Watchdog Timer (WDT) */
- PMC_IRQn = 5, /**< 5 AT91SAM3S Power Management Controller (PMC) */
- EFC_IRQn = 6, /**< 6 AT91SAM3S Enhanced Flash Controller (EFC) */
- UART0_IRQn = 8, /**< 8 AT91SAM3S UART 0 (UART0) */
- UART1_IRQn = 9, /**< 9 AT91SAM3S UART 1 (UART1) */
- SMC_IRQn = 10, /**< 10 AT91SAM3S Static Memory Controller (SMC) */
- PIOA_IRQn = 11, /**< 11 AT91SAM3S Parallel I/O Controller A (PIOA) */
- PIOB_IRQn = 12, /**< 12 AT91SAM3S Parallel I/O Controller B (PIOB) */
- PIOC_IRQn = 13, /**< 13 AT91SAM3S Parallel I/O Controller C (PIOC) */
- USART0_IRQn = 14, /**< 14 AT91SAM3S USART 0 (USART0) */
- USART1_IRQn = 15, /**< 15 AT91SAM3S USART 1 (USART1) */
- HSMCI_IRQn = 18, /**< 18 AT91SAM3S Multimedia Card Interface (HSMCI) */
- TWI0_IRQn = 19, /**< 19 AT91SAM3S Two Wire Interface 0 (TWI0) */
- TWI1_IRQn = 20, /**< 20 AT91SAM3S Two Wire Interface 1 (TWI1) */
- SPI_IRQn = 21, /**< 21 AT91SAM3S Serial Peripheral Interface (SPI) */
- SSC_IRQn = 22, /**< 22 AT91SAM3S Synchronous Serial Controler (SSC) */
- TC0_IRQn = 23, /**< 23 AT91SAM3S Timer/Counter 0 (TC0) */
- TC1_IRQn = 24, /**< 24 AT91SAM3S Timer/Counter 1 (TC1) */
- TC2_IRQn = 25, /**< 25 AT91SAM3S Timer/Counter 2 (TC2) */
- TC3_IRQn = 26, /**< 26 AT91SAM3S Timer/Counter 3 (TC3) */
- TC4_IRQn = 27, /**< 27 AT91SAM3S Timer/Counter 4 (TC4) */
- TC5_IRQn = 28, /**< 28 AT91SAM3S Timer/Counter 5 (TC5) */
- ADC_IRQn = 29, /**< 29 AT91SAM3S Analog To Digital Converter (ADC) */
- DACC_IRQn = 30, /**< 30 AT91SAM3S Digital To Analog Converter (DACC) */
- PWM_IRQn = 31, /**< 31 AT91SAM3S Pulse Width Modulation (PWM) */
- CRCCU_IRQn = 32, /**< 32 AT91SAM3S CRC Calculation Unit (CRCCU) */
- ACC_IRQn = 33, /**< 33 AT91SAM3S Analog Comparator (ACC) */
- UDP_IRQn = 34 /**< 34 AT91SAM3S USB Device Port (UDP) */
-} IRQn_Type;
-/*@}*/
-
-/* ***************************************************************************** */
-/** SOFTWARE PERIPHERAL API DEFINITION FOR AT91SAM3S */
-/* ***************************************************************************** */
-/** \addtogroup AT91SAM3S_api Peripheral Software API */
-/*@{*/
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_ACC Analog Comparator Controller */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Acc hardware registers */
-typedef struct {
- WoReg ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */
- RwReg ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */
- RwReg Reserved1[7];
- WoReg ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */
- WoReg ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */
- RoReg ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */
- RoReg ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */
- RwReg Reserved2[24];
- RwReg ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */
- RwReg Reserved3[19];
- RwReg ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protect Mode Register */
- RoReg ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protect Status Register */
-} Acc;
-#endif /* __ASSEMBLY__ */
-/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */
-#define ACC_CR_SWRST (0x1 << 0) /**< \brief (ACC_CR) SoftWare ReSeT */
-/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */
-#define ACC_MR_SELPLUS (0x7 << 0) /**< \brief (ACC_MR) SELection for PLUS comparator input */
-#define ACC_MR_SELMINUS (0x7 << 4) /**< \brief (ACC_MR) SELection for MINUS comparator input */
-#define ACC_MR_ACEN (0x1 << 8) /**< \brief (ACC_MR) Analog Comparator ENable */
-#define ACC_MR_ACEN_EN (0x1 << 8) /**< \brief (ACC_MR) Analog Comparator ENable */
-#define ACC_MR_ACEN_DIS (0x0 << 8) /**< \brief (ACC_MR) Analog Comparator Disable */
-#define ACC_MR_EDGETYP (0x3 << 9) /**< \brief (ACC_MR) EDGE TYPe */
-#define ACC_MR_EDGETYP_RISING (0x0 << 9) /**< \brief (ACC_MR) EDGE TYPe ,RISING edge*/
-#define ACC_MR_EDGETYP_FALLING (0x1 << 9) /**< \brief (ACC_MR) EDGE TYPe,falling edge */
-#define ACC_MR_EDGETYP_ANY (0x2 << 9) /**< \brief (ACC_MR) EDGE TYPe,any edge */
-#define ACC_MR_INV (0x1 << 12) /**< \brief (ACC_MR) INVert comparator output */
-#define ACC_MR_INV_EN (0x1 << 12) /**< \brief (ACC_MR) INVert comparator output */
-#define ACC_MR_INV_DIS (0x0 << 12) /**< \brief (ACC_MR) DIRECTLY */
-#define ACC_MR_SELFS (0x1 << 13) /**< \brief (ACC_MR) SELection of Fault Source */
-#define ACC_MR_SELFS_CF (0x0 << 13) /**< \brief (ACC_MR) SELection of Fault Source */
-#define ACC_MR_SELFS_OUTPUT (0x1 << 13) /**< \brief (ACC_MR) SELection of Fault Source */
-#define ACC_MR_FE (0x1 << 14) /**< \brief (ACC_MR) Fault Enable */
-#define ACC_MR_FE_EN (0x1 << 14) /**< \brief (ACC_MR) Fault Enable */
-#define ACC_MR_FE_DIS (0x0 << 14) /**< \brief (ACC_MR) Fault Enable */
-/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */
-#define ACC_IER_CE (0x1 << 0) /**< \brief (ACC_IER) Comparison Edge */
-/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */
-#define ACC_IDR_CE (0x1 << 0) /**< \brief (ACC_IDR) Comparison Edge */
-/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */
-#define ACC_IMR_CE (0x1 << 0) /**< \brief (ACC_IMR) Comparison Edge */
-/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */
-#define ACC_ISR_CE (0x1 << 0) /**< \brief (ACC_ISR) Comparison Edge */
-#define ACC_ISR_SCO (0x1 << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */
-#define ACC_ISR_MASK (0x1 << 31) /**< \brief (ACC_ISR) */
-/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */
-#define ACC_ACR_ISEL (0x1 << 0) /**< \brief (ACC_ACR) Current SELection */
-#define ACC_ACR_HYST (0x3 << 1) /**< \brief (ACC_ACR) HYSTeresis selection */
-/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protect Mode Register -------- */
-#define ACC_WPMR_WPEN (0x1 << 0) /**< \brief (ACC_WPMR) Write Protect Enable */
-#define ACC_WPMR_WPKEY (0xffffff << 8) /**< \brief (ACC_WPMR) Write Protect KEY */
-/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protect Status Register -------- */
-#define ACC_WPSR_WPROTERR (0x1 << 0) /**< \brief (ACC_WPSR) Write PROTection ERRor */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Analog-to-digital Converter */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_ADC Analog-to-digital Converter */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Adc hardware registers */
-typedef struct {
- WoReg ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */
- RwReg ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */
- RwReg ADC_SEQ1R; /**< \brief (Adc Offset: 0x08) Channel Sequence 1Register */
- RwReg ADC_SEQ2R; /**< \brief (Adc Offset: 0x0C) Channel Sequence 2 Register */
- WoReg ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */
- WoReg ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */
- RoReg ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */
- RwReg Reserved1[1];
- RoReg ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */
- WoReg ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */
- WoReg ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */
- RoReg ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */
- RoReg ADC_ISR; /**< \brief (Adc Offset: 0x30) Interrupt Status Register */
- RwReg Reserved2[2];
- RoReg ADC_OVER; /**< \brief (Adc Offset: 0x3C) Overrun Status Register */
- RwReg ADC_EMR; /**< \brief (Adc Offset: 0x40) Extended Mode Register */
- RwReg ADC_CWR; /**< \brief (Adc Offset: 0x44) Compare Window Register */
- RwReg ADC_CGR; /**< \brief (Adc Offset: 0x48) Channel Gain Register */
- RwReg ADC_COR; /**< \brief (Adc Offset: 0x4C) Channel Offset Register */
- RoReg ADC_CDR0; /**< \brief (Adc Offset: 0x50) Channel Data Register 0 */
- RoReg ADC_CDR1; /**< \brief (Adc Offset: 0x54) Channel Data Register 1 */
- RoReg ADC_CDR2; /**< \brief (Adc Offset: 0x58) Channel Data Register 2 */
- RoReg ADC_CDR3; /**< \brief (Adc Offset: 0x5C) Channel Data Register 3 */
- RoReg ADC_CDR4; /**< \brief (Adc Offset: 0x60) Channel Data Register 4 */
- RoReg ADC_CDR5; /**< \brief (Adc Offset: 0x64) Channel Data Register 5 */
- RoReg ADC_CDR6; /**< \brief (Adc Offset: 0x68) Channel Data Register 6 */
- RoReg ADC_CDR7; /**< \brief (Adc Offset: 0x6C) Channel Data Register 7 */
- RoReg ADC_CDR8; /**< \brief (Adc Offset: 0x70) Channel Data Register 8 */
- RoReg ADC_CDR9; /**< \brief (Adc Offset: 0x74) Channel Data Register 9 */
- RoReg ADC_CDR10; /**< \brief (Adc Offset: 0x78) Channel Data Register 10 */
- RoReg ADC_CDR11; /**< \brief (Adc Offset: 0x7C) Channel Data Register 11 */
- RoReg ADC_CDR12; /**< \brief (Adc Offset: 0x80) Channel Data Register 12 */
- RoReg ADC_CDR13; /**< \brief (Adc Offset: 0x84) Channel Data Register 13 */
- RoReg ADC_CDR14; /**< \brief (Adc Offset: 0x88) Channel Data Register 14 */
- RoReg ADC_CDR15; /**< \brief (Adc Offset: 0x8C) Channel Data Register 15 */
- RwReg Reserved3[1];
- RwReg ADC_ACR; /**< \brief (Adc Offset: 0x94) Analog Control Register */
- RwReg Reserved4[19];
- RwReg ADC_WPMR; /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */
- RoReg ADC_WPSR; /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */
- RwReg Reserved5[5];
- RwReg ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */
- RwReg ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */
- RwReg ADC_TPR; /**< \brief (Adc Offset: 0x108) Transmit Pointer Register */
- RwReg ADC_TCR; /**< \brief (Adc Offset: 0x10C) Transmit Counter Register */
- RwReg ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */
- RwReg ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */
- RwReg ADC_TNPR; /**< \brief (Adc Offset: 0x118) Transmit Next Pointer Register */
- RwReg ADC_TNCR; /**< \brief (Adc Offset: 0x11C) Transmit Next Counter Register */
- WoReg ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */
- RoReg ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */
-} Adc;
-#endif /* __ASSEMBLY__ */
-/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */
-#define ADC_CR_SWRST (0x1 << 0) /**< \brief (ADC_CR) Software Reset */
-#define ADC_CR_START (0x1 << 1) /**< \brief (ADC_CR) Start Conversion */
-/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */
-#define ADC_MR_TRGEN (0x1 << 0) /**< \brief (ADC_MR) Trigger Enable */
-#define ADC_MR_TRGEN_DIS (0x0 << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software.*/
-#define ADC_MR_TRGEN_EN (0x1) /**< (ADC) Hardware trigger selected by TRGSEL field is enabled.*/
-#define ADC_MR_TRGSEL (0x7 << 1) /**< \brief (ADC_MR) Trigger Selection */
-#define ADC_MR_TRGSEL_EXT (0x0 << 1) /**< \brief (ADC_MR) Selected TRGSEL = External Trigger*/
-#define ADC_MR_TRGSEL_TIOA0 (0x1 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO0*/
-#define ADC_MR_TRGSEL_TIOA1 (0x2 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO1*/
-#define ADC_MR_TRGSEL_TIOA2 (0x3 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO2*/
-#define ADC_MR_TRGSEL_PWM0_TRIG (0x4 << 1) /**< \brief (ADC_MR) Selected TRGSEL = PWM trigger*/
-#define ADC_MR_TRGSEL_PWM1_TRIG (0x5 << 1) /**< \brief (ADC_MR) Selected TRGSEL = PWM Trigger*/
-#define ADC_MR_TRGSEL_RESERVED (0x6 << 1) /**< \brief (ADC_MR) Selected TRGSEL = Reserved*/
-#define ADC_MR_LOWRES (0x1 << 4) /**< \brief (ADC_MR) Resolution */
-#define ADC_MR_LOWRES_12_BIT (0x0 << 4) /**< \brief (ADC_MR) 12-bit resolution*/
-#define ADC_MR_LOWRES_10_BIT (0x1 << 4) /**< \brief (ADC_MR) 10-bit resolution*/
-#define ADC_MR_SLEEP (0x1 << 5) /**< \brief (ADC_MR) Sleep Mode */
-#define ADC_MR_SLEEP_NORMAL (0x0 << 5) /**< \brief (ADC12B) Normal Mode*/
-#define ADC_MR_FWUP (0x1 << 6) /**< \brief (ADC_MR) Fast Wake Up */
-#define ADC_MR_FREERUN (0x1 << 7) /**< \brief (ADC_MR) Free Run Mode */
-#define ADC_MR_PRESCAL (0xff << 8) /**< \brief (ADC_MR) Prescaler Rate Selection */
-#define ADC_MR_STARTUP (0xf << 16) /**< \brief (ADC_MR) Start Up Time */
-#define ADC_MR_SETTLING (0x3 << 20) /**< \brief (ADC_MR) Analog Settling Time */
-#define ADC_MR_ANACH (0x1 << 23) /**< \brief (ADC_MR) Analog Change */
-#define ADC_MR_TRACKTIM (0xf << 24) /**< \brief (ADC_MR) Tracking Time */
-#define ADC_MR_TRANSFER (0x3 << 28) /**< \brief (ADC_MR) */
-#define ADC_MR_USEQ (0x1 << 31) /**< \brief (ADC_MR) User Sequence Enable */
-/* -------- ADC_SEQ1R : (ADC Offset: 0x08) Channel Sequence 1Register -------- */
-#define ADC_SEQ1R_USCH1 (0x7 << 0) /**< \brief (ADC_SEQ1R) User Sequence Number 1 */
-#define ADC_SEQ1R_USCH2 (0x7 << 4) /**< \brief (ADC_SEQ1R) User Sequence Number 2 */
-#define ADC_SEQ1R_USCH3 (0x7 << 8) /**< \brief (ADC_SEQ1R) User Sequence Number 3 */
-#define ADC_SEQ1R_USCH4 (0x7 << 12) /**< \brief (ADC_SEQ1R) User Sequence Number 4 */
-#define ADC_SEQ1R_USCH5 (0x7 << 16) /**< \brief (ADC_SEQ1R) User Sequence Number 5 */
-#define ADC_SEQ1R_USCH6 (0x7 << 20) /**< \brief (ADC_SEQ1R) User Sequence Number 6 */
-#define ADC_SEQ1R_USCH7 (0x7 << 24) /**< \brief (ADC_SEQ1R) User Sequence Number 7 */
-#define ADC_SEQ1R_USCH8 (0x7 << 28) /**< \brief (ADC_SEQ1R) User Sequence Number 8 */
-/* -------- ADC_SEQ2R : (ADC Offset: 0x0C) Channel Sequence 2 Register -------- */
-#define ADC_SEQ2R_USCH9 (0x7 << 0) /**< \brief (ADC_SEQ2R) User Sequence Number 9 */
-#define ADC_SEQ2R_USCH10 (0x7 << 4) /**< \brief (ADC_SEQ2R) User Sequence Number 10 */
-#define ADC_SEQ2R_USCH11 (0x7 << 8) /**< \brief (ADC_SEQ2R) User Sequence Number 11 */
-#define ADC_SEQ2R_USCH12 (0x7 << 12) /**< \brief (ADC_SEQ2R) User Sequence Number 12 */
-#define ADC_SEQ2R_USCH13 (0x7 << 16) /**< \brief (ADC_SEQ2R) User Sequence Number 13 */
-#define ADC_SEQ2R_USCH14 (0x7 << 20) /**< \brief (ADC_SEQ2R) User Sequence Number 14 */
-#define ADC_SEQ2R_USCH15 (0x7 << 24) /**< \brief (ADC_SEQ2R) User Sequence Number 15 */
-#define ADC_SEQ2R_USCH16 (0x7 << 28) /**< \brief (ADC_SEQ2R) User Sequence Number 16 */
-/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */
-#define ADC_CHER_CH0 (0x1 << 0) /**< \brief (ADC_CHER) Channel 0 Enable */
-#define ADC_CHER_CH1 (0x1 << 1) /**< \brief (ADC_CHER) Channel 1 Enable */
-#define ADC_CHER_CH2 (0x1 << 2) /**< \brief (ADC_CHER) Channel 2 Enable */
-#define ADC_CHER_CH3 (0x1 << 3) /**< \brief (ADC_CHER) Channel 3 Enable */
-#define ADC_CHER_CH4 (0x1 << 4) /**< \brief (ADC_CHER) Channel 4 Enable */
-#define ADC_CHER_CH5 (0x1 << 5) /**< \brief (ADC_CHER) Channel 5 Enable */
-#define ADC_CHER_CH6 (0x1 << 6) /**< \brief (ADC_CHER) Channel 6 Enable */
-#define ADC_CHER_CH7 (0x1 << 7) /**< \brief (ADC_CHER) Channel 7 Enable */
-#define ADC_CHER_CH8 (0x1 << 8) /**< \brief (ADC_CHER) Channel 8 Enable */
-#define ADC_CHER_CH9 (0x1 << 9) /**< \brief (ADC_CHER) Channel 9 Enable */
-#define ADC_CHER_CH10 (0x1 << 10) /**< \brief (ADC_CHER) Channel 10 Enable */
-#define ADC_CHER_CH11 (0x1 << 11) /**< \brief (ADC_CHER) Channel 11 Enable */
-#define ADC_CHER_CH12 (0x1 << 12) /**< \brief (ADC_CHER) Channel 12 Enable */
-#define ADC_CHER_CH13 (0x1 << 13) /**< \brief (ADC_CHER) Channel 13 Enable */
-#define ADC_CHER_CH14 (0x1 << 14) /**< \brief (ADC_CHER) Channel 14 Enable */
-#define ADC_CHER_CH15 (0x1 << 15) /**< \brief (ADC_CHER) Channel 15 Enable */
-/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */
-#define ADC_CHDR_CH0 (0x1 << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */
-#define ADC_CHDR_CH1 (0x1 << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */
-#define ADC_CHDR_CH2 (0x1 << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */
-#define ADC_CHDR_CH3 (0x1 << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */
-#define ADC_CHDR_CH4 (0x1 << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */
-#define ADC_CHDR_CH5 (0x1 << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */
-#define ADC_CHDR_CH6 (0x1 << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */
-#define ADC_CHDR_CH7 (0x1 << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */
-#define ADC_CHDR_CH8 (0x1 << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */
-#define ADC_CHDR_CH9 (0x1 << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */
-#define ADC_CHDR_CH10 (0x1 << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */
-#define ADC_CHDR_CH11 (0x1 << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */
-#define ADC_CHDR_CH12 (0x1 << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */
-#define ADC_CHDR_CH13 (0x1 << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */
-#define ADC_CHDR_CH14 (0x1 << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */
-#define ADC_CHDR_CH15 (0x1 << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */
-/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */
-#define ADC_CHSR_CH0 (0x1 << 0) /**< \brief (ADC_CHSR) Channel 0 Status */
-#define ADC_CHSR_CH1 (0x1 << 1) /**< \brief (ADC_CHSR) Channel 1 Status */
-#define ADC_CHSR_CH2 (0x1 << 2) /**< \brief (ADC_CHSR) Channel 2 Status */
-#define ADC_CHSR_CH3 (0x1 << 3) /**< \brief (ADC_CHSR) Channel 3 Status */
-#define ADC_CHSR_CH4 (0x1 << 4) /**< \brief (ADC_CHSR) Channel 4 Status */
-#define ADC_CHSR_CH5 (0x1 << 5) /**< \brief (ADC_CHSR) Channel 5 Status */
-#define ADC_CHSR_CH6 (0x1 << 6) /**< \brief (ADC_CHSR) Channel 6 Status */
-#define ADC_CHSR_CH7 (0x1 << 7) /**< \brief (ADC_CHSR) Channel 7 Status */
-#define ADC_CHSR_CH8 (0x1 << 8) /**< \brief (ADC_CHSR) Channel 8 Status */
-#define ADC_CHSR_CH9 (0x1 << 9) /**< \brief (ADC_CHSR) Channel 9 Status */
-#define ADC_CHSR_CH10 (0x1 << 10) /**< \brief (ADC_CHSR) Channel 10 Status */
-#define ADC_CHSR_CH11 (0x1 << 11) /**< \brief (ADC_CHSR) Channel 11 Status */
-#define ADC_CHSR_CH12 (0x1 << 12) /**< \brief (ADC_CHSR) Channel 12 Status */
-#define ADC_CHSR_CH13 (0x1 << 13) /**< \brief (ADC_CHSR) Channel 13 Status */
-#define ADC_CHSR_CH14 (0x1 << 14) /**< \brief (ADC_CHSR) Channel 14 Status */
-#define ADC_CHSR_CH15 (0x1 << 15) /**< \brief (ADC_CHSR) Channel 15 Status */
-/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */
-#define ADC_LCDR_LDATA (0xfff << 0) /**< \brief (ADC_LCDR) Last Data Converted */
-#define ADC_LCDR_CHNB (0xf << 12) /**< \brief (ADC_LCDR) Channel Number */
-/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */
-#define ADC_IER_EOC0 (0x1 << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */
-#define ADC_IER_EOC1 (0x1 << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */
-#define ADC_IER_EOC2 (0x1 << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */
-#define ADC_IER_EOC3 (0x1 << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */
-#define ADC_IER_EOC4 (0x1 << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */
-#define ADC_IER_EOC5 (0x1 << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */
-#define ADC_IER_EOC6 (0x1 << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */
-#define ADC_IER_EOC7 (0x1 << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */
-#define ADC_IER_EOC8 (0x1 << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */
-#define ADC_IER_EOC9 (0x1 << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */
-#define ADC_IER_EOC10 (0x1 << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */
-#define ADC_IER_EOC11 (0x1 << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */
-#define ADC_IER_EOC12 (0x1 << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */
-#define ADC_IER_EOC13 (0x1 << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */
-#define ADC_IER_EOC14 (0x1 << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */
-#define ADC_IER_EOC15 (0x1 << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */
-#define ADC_IER_DRDY (0x1 << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */
-#define ADC_IER_GOVRE (0x1 << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */
-#define ADC_IER_COMPE (0x1 << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */
-#define ADC_IER_ENDRX (0x1 << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */
-#define ADC_IER_RXBUFF (0x1 << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */
-/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */
-#define ADC_IDR_EOC0 (0x1 << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */
-#define ADC_IDR_EOC1 (0x1 << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */
-#define ADC_IDR_EOC2 (0x1 << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */
-#define ADC_IDR_EOC3 (0x1 << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */
-#define ADC_IDR_EOC4 (0x1 << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */
-#define ADC_IDR_EOC5 (0x1 << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */
-#define ADC_IDR_EOC6 (0x1 << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */
-#define ADC_IDR_EOC7 (0x1 << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */
-#define ADC_IDR_EOC8 (0x1 << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */
-#define ADC_IDR_EOC9 (0x1 << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */
-#define ADC_IDR_EOC10 (0x1 << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */
-#define ADC_IDR_EOC11 (0x1 << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */
-#define ADC_IDR_EOC12 (0x1 << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */
-#define ADC_IDR_EOC13 (0x1 << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */
-#define ADC_IDR_EOC14 (0x1 << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */
-#define ADC_IDR_EOC15 (0x1 << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */
-#define ADC_IDR_DRDY (0x1 << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */
-#define ADC_IDR_GOVRE (0x1 << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */
-#define ADC_IDR_COMPE (0x1 << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */
-#define ADC_IDR_ENDRX (0x1 << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */
-#define ADC_IDR_RXBUFF (0x1 << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */
-/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */
-#define ADC_IMR_EOC0 (0x1 << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */
-#define ADC_IMR_EOC1 (0x1 << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */
-#define ADC_IMR_EOC2 (0x1 << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */
-#define ADC_IMR_EOC3 (0x1 << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */
-#define ADC_IMR_EOC4 (0x1 << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */
-#define ADC_IMR_EOC5 (0x1 << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */
-#define ADC_IMR_EOC6 (0x1 << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */
-#define ADC_IMR_EOC7 (0x1 << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */
-#define ADC_IMR_EOC8 (0x1 << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */
-#define ADC_IMR_EOC9 (0x1 << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */
-#define ADC_IMR_EOC10 (0x1 << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */
-#define ADC_IMR_EOC11 (0x1 << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */
-#define ADC_IMR_EOC12 (0x1 << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */
-#define ADC_IMR_EOC13 (0x1 << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */
-#define ADC_IMR_EOC14 (0x1 << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */
-#define ADC_IMR_EOC15 (0x1 << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */
-#define ADC_IMR_DRDY (0x1 << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */
-#define ADC_IMR_GOVRE (0x1 << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */
-#define ADC_IMR_COMPE (0x1 << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */
-#define ADC_IMR_ENDRX (0x1 << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */
-#define ADC_IMR_RXBUFF (0x1 << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */
-/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */
-#define ADC_ISR_EOC0 (0x1 << 0) /**< \brief (ADC_ISR) End of Conversion 0 */
-#define ADC_ISR_EOC1 (0x1 << 1) /**< \brief (ADC_ISR) End of Conversion 1 */
-#define ADC_ISR_EOC2 (0x1 << 2) /**< \brief (ADC_ISR) End of Conversion 2 */
-#define ADC_ISR_EOC3 (0x1 << 3) /**< \brief (ADC_ISR) End of Conversion 3 */
-#define ADC_ISR_EOC4 (0x1 << 4) /**< \brief (ADC_ISR) End of Conversion 4 */
-#define ADC_ISR_EOC5 (0x1 << 5) /**< \brief (ADC_ISR) End of Conversion 5 */
-#define ADC_ISR_EOC6 (0x1 << 6) /**< \brief (ADC_ISR) End of Conversion 6 */
-#define ADC_ISR_EOC7 (0x1 << 7) /**< \brief (ADC_ISR) End of Conversion 7 */
-#define ADC_ISR_EOC8 (0x1 << 8) /**< \brief (ADC_ISR) End of Conversion 8 */
-#define ADC_ISR_EOC9 (0x1 << 9) /**< \brief (ADC_ISR) End of Conversion 9 */
-#define ADC_ISR_EOC10 (0x1 << 10) /**< \brief (ADC_ISR) End of Conversion 10 */
-#define ADC_ISR_EOC11 (0x1 << 11) /**< \brief (ADC_ISR) End of Conversion 11 */
-#define ADC_ISR_EOC12 (0x1 << 12) /**< \brief (ADC_ISR) End of Conversion 12 */
-#define ADC_ISR_EOC13 (0x1 << 13) /**< \brief (ADC_ISR) End of Conversion 13 */
-#define ADC_ISR_EOC14 (0x1 << 14) /**< \brief (ADC_ISR) End of Conversion 14 */
-#define ADC_ISR_EOC15 (0x1 << 15) /**< \brief (ADC_ISR) End of Conversion 15 */
-#define ADC_ISR_DRDY (0x1 << 24) /**< \brief (ADC_ISR) Data Ready */
-#define ADC_ISR_GOVRE (0x1 << 25) /**< \brief (ADC_ISR) General Overrun Error */
-#define ADC_ISR_COMPE (0x1 << 26) /**< \brief (ADC_ISR) Comparison Error */
-#define ADC_ISR_ENDRX (0x1 << 27) /**< \brief (ADC_ISR) End of RX Buffer */
-#define ADC_ISR_RXBUFF (0x1 << 28) /**< \brief (ADC_ISR) RX Buffer Full */
-/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */
-#define ADC_OVER_OVRE0 (0x1 << 0) /**< \brief (ADC_OVER) Overrun Error 0 */
-#define ADC_OVER_OVRE1 (0x1 << 1) /**< \brief (ADC_OVER) Overrun Error 1 */
-#define ADC_OVER_OVRE2 (0x1 << 2) /**< \brief (ADC_OVER) Overrun Error 2 */
-#define ADC_OVER_OVRE3 (0x1 << 3) /**< \brief (ADC_OVER) Overrun Error 3 */
-#define ADC_OVER_OVRE4 (0x1 << 4) /**< \brief (ADC_OVER) Overrun Error 4 */
-#define ADC_OVER_OVRE5 (0x1 << 5) /**< \brief (ADC_OVER) Overrun Error 5 */
-#define ADC_OVER_OVRE6 (0x1 << 6) /**< \brief (ADC_OVER) Overrun Error 6 */
-#define ADC_OVER_OVRE7 (0x1 << 7) /**< \brief (ADC_OVER) Overrun Error 7 */
-#define ADC_OVER_OVRE8 (0x1 << 8) /**< \brief (ADC_OVER) Overrun Error 8 */
-#define ADC_OVER_OVRE9 (0x1 << 9) /**< \brief (ADC_OVER) Overrun Error 9 */
-#define ADC_OVER_OVRE10 (0x1 << 10) /**< \brief (ADC_OVER) Overrun Error 10 */
-#define ADC_OVER_OVRE11 (0x1 << 11) /**< \brief (ADC_OVER) Overrun Error 11 */
-#define ADC_OVER_OVRE12 (0x1 << 12) /**< \brief (ADC_OVER) Overrun Error 12 */
-#define ADC_OVER_OVRE13 (0x1 << 13) /**< \brief (ADC_OVER) Overrun Error 13 */
-#define ADC_OVER_OVRE14 (0x1 << 14) /**< \brief (ADC_OVER) Overrun Error 14 */
-#define ADC_OVER_OVRE15 (0x1 << 15) /**< \brief (ADC_OVER) Overrun Error 15 */
-/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */
-#define ADC_EMR_CMPMODE (0x3 << 0) /**< \brief (ADC_EMR) Comparison Mode */
-#define ADC_EMR_CMPMODE_LOW (0x0 << 0) /**< \brief (ADC_EMR) Comparison Mode,lower than low threshold */
-#define ADC_EMR_CMPMODE_HIGH (0x1 << 0) /**< \brief (ADC_EMR) Comparison Mode,higher than high threshold */
-#define ADC_EMR_CMPMODE_IN (0x2 << 0) /**< \brief (ADC_EMR) Comparison Mode, in the comparison window */
-#define ADC_EMR_CMPMODE_OUT (0x3 << 0) /**< \brief (ADC_EMR) Comparison Mode, out of the comparison window */
-#define ADC_EMR_CMPSEL (0xf << 4) /**< \brief (ADC_EMR) Comparison Selected Channel */
-#define ADC_EMR_CMPALL (0x1 << 9) /**< \brief (ADC_EMR) Compare All Channels */
-#define ADC_EMR_TAG (0x1 << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */
-/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */
-#define ADC_CWR_LOWTHRES (0xfff << 0) /**< \brief (ADC_CWR) Low Threshold */
-#define ADC_CWR_HIGHTHRES (0xfff << 16) /**< \brief (ADC_CWR) High Threshold */
-/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */
-#define ADC_CGR_GAIN0 (0x3 << 0) /**< \brief (ADC_CGR) Gain for channel 0 */
-#define ADC_CGR_GAIN1 (0x3 << 2) /**< \brief (ADC_CGR) Gain for channel 1 */
-#define ADC_CGR_GAIN2 (0x3 << 4) /**< \brief (ADC_CGR) Gain for channel 2 */
-#define ADC_CGR_GAIN3 (0x3 << 6) /**< \brief (ADC_CGR) Gain for channel 3 */
-#define ADC_CGR_GAIN4 (0x3 << 8) /**< \brief (ADC_CGR) Gain for channel 4 */
-#define ADC_CGR_GAIN5 (0x3 << 10) /**< \brief (ADC_CGR) Gain for channel 5 */
-#define ADC_CGR_GAIN6 (0x3 << 12) /**< \brief (ADC_CGR) Gain for channel 6 */
-#define ADC_CGR_GAIN7 (0x3 << 14) /**< \brief (ADC_CGR) Gain for channel 7 */
-#define ADC_CGR_GAIN8 (0x3 << 16) /**< \brief (ADC_CGR) Gain for channel 8 */
-#define ADC_CGR_GAIN9 (0x3 << 18) /**< \brief (ADC_CGR) Gain for channel 9 */
-#define ADC_CGR_GAIN10 (0x3 << 20) /**< \brief (ADC_CGR) Gain for channel 10 */
-#define ADC_CGR_GAIN11 (0x3 << 22) /**< \brief (ADC_CGR) Gain for channel 11 */
-#define ADC_CGR_GAIN12 (0x3 << 24) /**< \brief (ADC_CGR) Gain for channel 12 */
-#define ADC_CGR_GAIN13 (0x3 << 26) /**< \brief (ADC_CGR) Gain for channel 13 */
-#define ADC_CGR_GAIN14 (0x3 << 28) /**< \brief (ADC_CGR) Gain for channel 14 */
-#define ADC_CGR_GAIN15 (0x3 << 30) /**< \brief (ADC_CGR) Gain for channel 15 */
-/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */
-#define ADC_COR_OFF0 (0x1 << 0) /**< \brief (ADC_COR) Offset for channel 0 */
-#define ADC_COR_OFF1 (0x1 << 1) /**< \brief (ADC_COR) Offset for channel 1 */
-#define ADC_COR_OFF2 (0x1 << 2) /**< \brief (ADC_COR) Offset for channel 2 */
-#define ADC_COR_OFF3 (0x1 << 3) /**< \brief (ADC_COR) Offset for channel 3 */
-#define ADC_COR_OFF4 (0x1 << 4) /**< \brief (ADC_COR) Offset for channel 4 */
-#define ADC_COR_OFF5 (0x1 << 5) /**< \brief (ADC_COR) Offset for channel 5 */
-#define ADC_COR_OFF6 (0x1 << 6) /**< \brief (ADC_COR) Offset for channel 6 */
-#define ADC_COR_OFF7 (0x1 << 7) /**< \brief (ADC_COR) Offset for channel 7 */
-#define ADC_COR_OFF8 (0x1 << 8) /**< \brief (ADC_COR) Offset for channel 8 */
-#define ADC_COR_OFF9 (0x1 << 9) /**< \brief (ADC_COR) Offset for channel 9 */
-#define ADC_COR_OFF10 (0x1 << 10) /**< \brief (ADC_COR) Offset for channel 10 */
-#define ADC_COR_OFF11 (0x1 << 11) /**< \brief (ADC_COR) Offset for channel 11 */
-#define ADC_COR_OFF12 (0x1 << 12) /**< \brief (ADC_COR) Offset for channel 12 */
-#define ADC_COR_OFF13 (0x1 << 13) /**< \brief (ADC_COR) Offset for channel 13 */
-#define ADC_COR_OFF14 (0x1 << 14) /**< \brief (ADC_COR) Offset for channel 14 */
-#define ADC_COR_OFF15 (0x1 << 15) /**< \brief (ADC_COR) Offset for channel 15 */
-#define ADC_COR_DIFF0 (0x1 << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */
-#define ADC_COR_DIFF1 (0x1 << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */
-#define ADC_COR_DIFF2 (0x1 << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */
-#define ADC_COR_DIFF3 (0x1 << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */
-#define ADC_COR_DIFF4 (0x1 << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */
-#define ADC_COR_DIFF5 (0x1 << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */
-#define ADC_COR_DIFF6 (0x1 << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */
-#define ADC_COR_DIFF7 (0x1 << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */
-#define ADC_COR_DIFF8 (0x1 << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */
-#define ADC_COR_DIFF9 (0x1 << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */
-#define ADC_COR_DIFF10 (0x1 << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */
-#define ADC_COR_DIFF11 (0x1 << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */
-#define ADC_COR_DIFF12 (0x1 << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */
-#define ADC_COR_DIFF13 (0x1 << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */
-#define ADC_COR_DIFF14 (0x1 << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */
-#define ADC_COR_DIFF15 (0x1 << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */
-/* -------- ADC_CDR0 : (ADC Offset: 0x50) Channel Data Register 0 -------- */
-#define ADC_CDR0_DATA (0x3ff << 0) /**< \brief (ADC_CDR0) Converted Data */
-/* -------- ADC_CDR1 : (ADC Offset: 0x54) Channel Data Register 1 -------- */
-#define ADC_CDR1_DATA (0x3ff << 0) /**< \brief (ADC_CDR1) Converted Data */
-/* -------- ADC_CDR2 : (ADC Offset: 0x58) Channel Data Register 2 -------- */
-#define ADC_CDR2_DATA (0x3ff << 0) /**< \brief (ADC_CDR2) Converted Data */
-/* -------- ADC_CDR3 : (ADC Offset: 0x5C) Channel Data Register 3 -------- */
-#define ADC_CDR3_DATA (0x3ff << 0) /**< \brief (ADC_CDR3) Converted Data */
-/* -------- ADC_CDR4 : (ADC Offset: 0x60) Channel Data Register 4 -------- */
-#define ADC_CDR4_DATA (0x3ff << 0) /**< \brief (ADC_CDR4) Converted Data */
-/* -------- ADC_CDR5 : (ADC Offset: 0x64) Channel Data Register 5 -------- */
-#define ADC_CDR5_DATA (0x3ff << 0) /**< \brief (ADC_CDR5) Converted Data */
-/* -------- ADC_CDR6 : (ADC Offset: 0x68) Channel Data Register 6 -------- */
-#define ADC_CDR6_DATA (0x3ff << 0) /**< \brief (ADC_CDR6) Converted Data */
-/* -------- ADC_CDR15 : (ADC Offset: 0x6C) Channel Data Register 15 -------- */
-#define ADC_CDR15_DATA (0x3ff << 0) /**< \brief (ADC_CDR15) Converted Data */
-/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */
-#define ADC_ACR_TSON (0x1 << 4) /**< \brief (ADC_ACR) Temperature Sensor On */
-#define ADC_ACR_IBCTL (0x3 << 8) /**< \brief (ADC_ACR) ADC Bias Current Control */
-/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */
-#define ADC_WPMR_WPEN (0x1 << 0) /**< \brief (ADC_WPMR) Write Protect Enable */
-#define ADC_WPMR_WPKEY (0xffffff << 8) /**< \brief (ADC_WPMR) Write Protect KEY */
-/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */
-#define ADC_WPSR_WPVS (0x1 << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */
-#define ADC_WPSR_WPVSRC (0xffff << 8) /**< \brief (ADC_WPSR) Write Protect Violation Source */
-/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */
-#define ADC_RPR_RXPTR (0xffffffff << 0) /**< \brief (ADC_RPR) Receive Pointer Register */
-/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */
-#define ADC_RCR_RXCTR (0xffff << 0) /**< \brief (ADC_RCR) Receive Counter Register */
-/* -------- ADC_TPR : (ADC Offset: 0x108) Transmit Pointer Register -------- */
-#define ADC_TPR_TXPTR (0xffffffff << 0) /**< \brief (ADC_TPR) Transmit Counter Register */
-/* -------- ADC_TCR : (ADC Offset: 0x10C) Transmit Counter Register -------- */
-#define ADC_TCR_TXCTR (0xffff << 0) /**< \brief (ADC_TCR) Transmit Counter Register */
-/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */
-#define ADC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (ADC_RNPR) Receive Next Pointer */
-/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */
-#define ADC_RNCR_RXNCTR (0xffff << 0) /**< \brief (ADC_RNCR) Receive Next Counter */
-/* -------- ADC_TNPR : (ADC Offset: 0x118) Transmit Next Pointer Register -------- */
-#define ADC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (ADC_TNPR) Transmit Next Pointer */
-/* -------- ADC_TNCR : (ADC Offset: 0x11C) Transmit Next Counter Register -------- */
-#define ADC_TNCR_TXNCTR (0xffff << 0) /**< \brief (ADC_TNCR) Transmit Counter Next */
-/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */
-#define ADC_PTCR_RXTEN (0x1 << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */
-#define ADC_PTCR_RXTDIS (0x1 << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */
-#define ADC_PTCR_TXTEN (0x1 << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */
-#define ADC_PTCR_TXTDIS (0x1 << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */
-/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */
-#define ADC_PTSR_RXTEN (0x1 << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */
-#define ADC_PTSR_TXTEN (0x1 << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Chip Identifier */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_CHIPID Chip Identifier */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Chipid hardware registers */
-typedef struct {
- RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */
- RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */
-} Chipid;
-#endif /* __ASSEMBLY__ */
-/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
-#define CHIPID_CIDR_VERSION (0x1f << 0) /**< \brief (CHIPID_CIDR) Version of the Device */
-#define CHIPID_CIDR_EPROC (0x7 << 5) /**< \brief (CHIPID_CIDR) Embedded Processor */
-#define CHIPID_CIDR_NVPSIZ (0xf << 8) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */
-#define CHIPID_CIDR_NVPSIZ2 (0xf << 12) /**< \brief (CHIPID_CIDR) */
-#define CHIPID_CIDR_SRAMSIZ (0xf << 16) /**< \brief (CHIPID_CIDR) Internal SRAM Size */
-#define CHIPID_CIDR_ARCH (0xff << 20) /**< \brief (CHIPID_CIDR) Architecture Identifier */
-#define CHIPID_CIDR_NVPTYP (0x7 << 28) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */
-#define CHIPID_CIDR_EXT (0x1 << 31) /**< \brief (CHIPID_CIDR) Extension Flag */
-/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
-#define CHIPID_EXID_EXID (0xffffffff << 0) /**< \brief (CHIPID_EXID) Chip ID Extension */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_CRCCU Cyclic Redundancy Check Calculation Unit */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Crccu hardware registers */
-typedef struct {
- RwReg CRCCU_DSCR; /**< \brief (Crccu Offset: 0x00000000) CRCCU Descriptor Base Register */
- RwReg Reserved1[1];
- WoReg CRCCU_DMA_EN; /**< \brief (Crccu Offset: 0x00000008) CRCCU DMA Enable Register */
- WoReg CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x0000000C) CRCCU DMA Disable Register */
- RoReg CRCCU_DMA_SR; /**< \brief (Crccu Offset: 0x00000010) CRCCU DMA Status Register */
- WoReg CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x00000014) CRCCU DMA Interrupt Enable Register */
- WoReg CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x00000018) CRCCU DMA Interrupt Disable Register */
- RoReg CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register */
- RoReg CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x00000020) CRCCU DMA Interrupt Status Register */
- RwReg Reserved2[4];
- WoReg CRCCU_CR; /**< \brief (Crccu Offset: 0x00000034) CRCCU Control Register */
- RwReg CRCCU_MR; /**< \brief (Crccu Offset: 0x00000038) CRCCU Mode Register */
- RoReg CRCCU_SR; /**< \brief (Crccu Offset: 0x0000003C) CRCCU Status Register */
- WoReg CRCCU_IER; /**< \brief (Crccu Offset: 0x00000040) CRCCU Interrupt Enable Register */
- WoReg CRCCU_IDR; /**< \brief (Crccu Offset: 0x00000044) CRCCU Interrupt Disable Register */
- RoReg CRCCU_IMR; /**< \brief (Crccu Offset: 0x00000048) CRCCU Interrupt Mask Register */
- RoReg CRCCU_ISR; /**< \brief (Crccu Offset: 0x0000004C) CRCCU Interrupt Status Register */
-} Crccu;
-#endif /* __ASSEMBLY__ */
-/* -------- CRCCU_DSCR : (CRCCU Offset: 0x00000000) CRCCU Descriptor Base Register -------- */
-#define CRCCU_DSCR_DSCR (0x7fffff << 9) /**< \brief (CRCCU_DSCR) Descriptor Base Address */
-/* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x00000008) CRCCU DMA Enable Register -------- */
-#define CRCCU_DMA_EN_DMAEN (0x1 << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable Register */
-/* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x0000000C) CRCCU DMA Disable Register -------- */
-#define CRCCU_DMA_DIS_DMADIS (0x1 << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable Register */
-/* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x00000010) CRCCU DMA Status Register -------- */
-#define CRCCU_DMA_SR_DMASR (0x1 << 0) /**< \brief (CRCCU_DMA_SR) DMA Status Register */
-/* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x00000014) CRCCU DMA Interrupt Enable Register -------- */
-#define CRCCU_DMA_IER_DMAIER (0x1 << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable register */
-/* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x00000018) CRCCU DMA Interrupt Disable Register -------- */
-#define CRCCU_DMA_IDR_DMAIDR (0x1 << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable register */
-/* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register -------- */
-#define CRCCU_DMA_IMR_DMAIMR (0x1 << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask Register */
-/* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x00000020) CRCCU DMA Interrupt Status Register -------- */
-#define CRCCU_DMA_ISR_DMAISR (0x1 << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status register */
-/* -------- CRCCU_CR : (CRCCU Offset: 0x00000034) CRCCU Control Register -------- */
-#define CRCCU_CR_RESET (0x1 << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */
-/* -------- CRCCU_MR : (CRCCU Offset: 0x00000038) CRCCU Mode Register -------- */
-#define CRCCU_MR_ENABLE (0x1 << 0) /**< \brief (CRCCU_MR) CRC Enable */
-#define CRCCU_MR_COMPARE (0x1 << 1) /**< \brief (CRCCU_MR) CRC Compare */
-#define CRCCU_MR_PTYPE (0x3 << 2) /**< \brief (CRCCU_MR) Primitive Polynomial */
-#define CRCCU_MR_PTYPE_CCIT8023 (0x0 << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */
-#define CRCCU_MR_PTYPE_CASTAGNOLI (0x1 << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */
-#define CRCCU_MR_PTYPE_CCIT16 (0x2 << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */
-#define CRCCU_MR_DIVIDER (0xf << 4) /**< \brief (CRCCU_MR) Request Divider */
-/* -------- CRCCU_SR : (CRCCU Offset: 0x0000003C) CRCCU Status Register -------- */
-#define CRCCU_SR_CRC (0xffffffff << 0) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */
-/* -------- CRCCU_IER : (CRCCU Offset: 0x00000040) CRCCU Interrupt Enable Register -------- */
-#define CRCCU_IER_ERRIER (0x1 << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */
-/* -------- CRCCU_IDR : (CRCCU Offset: 0x00000044) CRCCU Interrupt Disable Register -------- */
-#define CRCCU_IDR_ERRIDR (0x1 << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */
-/* -------- CRCCU_IMR : (CRCCU Offset: 0x00000048) CRCCU Interrupt Mask Register -------- */
-#define CRCCU_IMR_ERRIMR (0x1 << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */
-/* -------- CRCCU_ISR : (CRCCU Offset: 0x0000004C) CRCCU Interrupt Status Register -------- */
-#define CRCCU_ISR_ERRISR (0x1 << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_DACC Digital-to-Analog Converter Controller */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Dacc hardware registers */
-typedef struct {
- WoReg DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */
- RwReg DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */
- RwReg Reserved1[2];
- WoReg DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */
- WoReg DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */
- RoReg DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */
- RwReg Reserved2[1];
- WoReg DACC_CDR; /**< \brief (Dacc Offset: 0x20) Conversion Data Register */
- WoReg DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */
- WoReg DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */
- RoReg DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */
- RoReg DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */
- RwReg Reserved3[24];
- RwReg DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */
- RwReg Reserved4[19];
- RwReg DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */
- RoReg DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */
- RwReg Reserved5[5];
- RwReg DACC_RPR; /**< \brief (Dacc Offset: 0x100) Receive Pointer Register */
- RwReg DACC_RCR; /**< \brief (Dacc Offset: 0x104) Receive Counter Register */
- RwReg DACC_TPR; /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */
- RwReg DACC_TCR; /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */
- RwReg DACC_RNPR; /**< \brief (Dacc Offset: 0x110) Receive Next Pointer Register */
- RwReg DACC_RNCR; /**< \brief (Dacc Offset: 0x114) Receive Next Counter Register */
- RwReg DACC_TNPR; /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */
- RwReg DACC_TNCR; /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */
- WoReg DACC_PTCR; /**< \brief (Dacc Offset: 0x120) Transfer Control Register */
- RoReg DACC_PTSR; /**< \brief (Dacc Offset: 0x124) Transfer Status Register */
-} Dacc;
-#endif /* __ASSEMBLY__ */
-/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */
-#define DACC_CR_SWRST (0x1 << 0) /**< \brief (DACC_CR) Software Reset */
-/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */
-#define DACC_MR_TRGEN (0x1 << 0) /**< \brief (DACC_MR) Trigger Enable */
-#define DACC_MR_TRGEN_DIS (0x0 << 0) // (DACC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software.
-#define DACC_MR_TRGEN_EN (0x1 << 0) // (DACC_MR) Hardware trigger selected by TRGSEL field is enabled.
-
-#define DACC_MR_TRGSEL (0x7 << 1) /**< \brief (DACC_MR) Trigger Selection */
-#define DACC_MR_TRGSEL_EXT_TRIG (0x0 << 1) // (DACC_MR) External trigger
-#define DACC_MR_TRGSEL_TIOA_0 (0x1 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 0
-#define DACC_MR_TRGSEL_TIOA_1 (0x2 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 1
-#define DACC_MR_TRGSEL_TIOA_2 (0x3 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 2
-#define DACC_MR_TRGSEL_PWM_0 (0x4 << 1) // (DACC_MR) PWM Event Line 0
-#define DACC_MR_TRGSEL_PWM_1 (0x5 << 1) // (DACC_MR) PWM Event Line 1
-#define DACC_MR_WORD (0x1 << 4) /**< \brief (DACC_MR) Word Transfer */
-#define DACC_MR_WORD_HALF (0x0 << 4) /**< \brief (DACC_MR) Half-Word Transfer */
-#define DACC_MR_WORD_WORLD (0x1 << 4) /**< \brief (DACC_MR) Word Transfer */
-#define DACC_MR_SLEEP (0x1 << 5) /**< \brief (DACC_MR) Sleep Mode */
-#define DACC_MR_SLEEP_NORMAL (0x0 << 5) // (DACC_MR) Normal Mode
-#define DACC_MR_SLEEP_SLEEP (0x1 << 5) // (DACC_MR) Sleep Modes
-#define DACC_MR_FASTWKUP (0x1 << 6) /**< \brief (DACC_MR) Fast Wake up Mode */
-#define DACC_MR_REFRESH (0xff << 8) /**< \brief (DACC_MR) Refresh Period */
-#define DACC_MR_USER_SEL (0x3 << 16) /**< \brief (DACC_MR) User Channel Selection */
-#define DACC_MR_USER_SEL_0 (0x0 << 16) /**< \brief (DACC_MR) User Channel Selection */
-#define DACC_MR_USER_SEL_1 (0x1 << 16) /**< \brief (DACC_MR) User Channel Selection */
-#define DACC_MR_TAG (0x1 << 20) /**< \brief (DACC_MR) Tag Selection Mode */
-#define DACC_MR_MAXS (0x1 << 21) /**< \brief (DACC_MR) Max Speed Mode */
-#define DACC_MR_STARTUP (0x3f << 24) /**< \brief (DACC_MR) Startup Time Selection */
-/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */
-#define DACC_CHER_CH0 (0x1 << 0) /**< \brief (DACC_CHER) Channel 0 Enable */
-#define DACC_CHER_CH1 (0x1 << 1) /**< \brief (DACC_CHER) Channel 1 Enable */
-#define DACC_CHER_CH2 (0x1 << 2) /**< \brief (DACC_CHER) Channel 2 Enable */
-/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */
-#define DACC_CHDR_CH0 (0x1 << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */
-#define DACC_CHDR_CH1 (0x1 << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */
-#define DACC_CHDR_CH2 (0x1 << 2) /**< \brief (DACC_CHDR) Channel 2 Disable */
-/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */
-#define DACC_CHSR_CH0 (0x1 << 0) /**< \brief (DACC_CHSR) Channel 0 Status */
-#define DACC_CHSR_CH1 (0x1 << 1) /**< \brief (DACC_CHSR) Channel 1 Status */
-#define DACC_CHSR_CH2 (0x1 << 2) /**< \brief (DACC_CHSR) Channel 2 Status */
-/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */
-#define DACC_CDR_DATA (0xffffffff << 0) /**< \brief (DACC_CDR) Data to Convert */
-/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */
-#define DACC_IER_TXRDY (0x1 << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */
-#define DACC_IER_EOC (0x1 << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */
-#define DACC_IER_ENDTX (0x1 << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */
-#define DACC_IER_TXBUFE (0x1 << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */
-/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */
-#define DACC_IDR_TXRDY (0x1 << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */
-#define DACC_IDR_EOC (0x1 << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */
-#define DACC_IDR_ENDTX (0x1 << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */
-#define DACC_IDR_TXBUFE (0x1 << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */
-/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */
-#define DACC_IMR_TXRDY (0x1 << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */
-#define DACC_IMR_EOC (0x1 << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */
-#define DACC_IMR_ENDTX (0x1 << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */
-#define DACC_IMR_TXBUFE (0x1 << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */
-/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */
-#define DACC_ISR_TXRDY (0x1 << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */
-#define DACC_ISR_EOC (0x1 << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */
-#define DACC_ISR_ENDTX (0x1 << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */
-#define DACC_ISR_TXBUFE (0x1 << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */
-/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */
-#define DACC_ACR_IBCTLCH0 (0x3 << 0) /**< \brief (DACC_ACR) Analog Output Current Control */
-#define DACC_ACR_IBCTLCH1 (0x3 << 2) /**< \brief (DACC_ACR) Analog Output Current Control */
-#define DACC_ACR_IBCTLDACCORE (0x3 << 8) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */
-/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */
-#define DACC_WPMR_WPEN (0x1 << 0) /**< \brief (DACC_WPMR) Write Protect Enable */
-#define DACC_WPMR_WPKEY (0xffffff << 8) /**< \brief (DACC_WPMR) Write Protect KEY */
-/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */
-#define DACC_WPSR_WPROTERR (0x1 << 0) /**< \brief (DACC_WPSR) Write protection error */
-#define DACC_WPSR_WPROTADDR (0xff << 8) /**< \brief (DACC_WPSR) Write protection error address */
-/* -------- DACC_RPR : (DACC Offset: 0x100) Receive Pointer Register -------- */
-#define DACC_RPR_RXPTR (0xffffffff << 0) /**< \brief (DACC_RPR) Receive Pointer Register */
-/* -------- DACC_RCR : (DACC Offset: 0x104) Receive Counter Register -------- */
-#define DACC_RCR_RXCTR (0xffff << 0) /**< \brief (DACC_RCR) Receive Counter Register */
-/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */
-#define DACC_TPR_TXPTR (0xffffffff << 0) /**< \brief (DACC_TPR) Transmit Counter Register */
-/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */
-#define DACC_TCR_TXCTR (0xffff << 0) /**< \brief (DACC_TCR) Transmit Counter Register */
-/* -------- DACC_RNPR : (DACC Offset: 0x110) Receive Next Pointer Register -------- */
-#define DACC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (DACC_RNPR) Receive Next Pointer */
-/* -------- DACC_RNCR : (DACC Offset: 0x114) Receive Next Counter Register -------- */
-#define DACC_RNCR_RXNCTR (0xffff << 0) /**< \brief (DACC_RNCR) Receive Next Counter */
-/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */
-#define DACC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (DACC_TNPR) Transmit Next Pointer */
-/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */
-#define DACC_TNCR_TXNCTR (0xffff << 0) /**< \brief (DACC_TNCR) Transmit Counter Next */
-/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */
-#define DACC_PTCR_RXTEN (0x1 << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */
-#define DACC_PTCR_RXTDIS (0x1 << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */
-#define DACC_PTCR_TXTEN (0x1 << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */
-#define DACC_PTCR_TXTDIS (0x1 << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */
-/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */
-#define DACC_PTSR_RXTEN (0x1 << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */
-#define DACC_PTSR_TXTEN (0x1 << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_EFC Embedded Flash Controller */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Efc hardware registers */
-typedef struct {
- RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */
- WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */
- RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */
- RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */
-} Efc;
-#endif /* __ASSEMBLY__ */
-/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
-#define EEFC_FMR_FRDY (0x1 << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */
-#define EEFC_FMR_FWS (0xf << 8) /**< \brief (EEFC_FMR) Flash Wait State */
-#define EEFC_FMR_FAM (0x1 << 24) /**< \brief (EEFC_FMR) Flash Access Mode */
-/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
-#define EEFC_FCR_FCMD (0xff << 0) /**< \brief (EEFC_FCR) Flash Command */
-#define EEFC_FCR_FARG (0xffff << 8) /**< \brief (EEFC_FCR) Flash Command Argument */
-#define EEFC_FCR_FKEY (0xff << 24) /**< \brief (EEFC_FCR) Flash Writing Protection Key */
-/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
-#define EEFC_FSR_FRDY (0x1 << 0) /**< \brief (EEFC_FSR) Flash Ready Status */
-#define EEFC_FSR_FCMDE (0x1 << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */
-#define EEFC_FSR_FLOCKE (0x1 << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */
-/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
-#define EEFC_FRR_FVALUE (0xffffffff << 0) /**< \brief (EEFC_FRR) Flash Result Value */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_GPBR General Purpose Backup Register */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Gpbr hardware registers */
-typedef struct {
- RwReg SYS_GPBR0; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register 0 */
- RwReg SYS_GPBR1; /**< \brief (Gpbr Offset: 0x4) General Purpose Backup Register 1 */
- RwReg SYS_GPBR2; /**< \brief (Gpbr Offset: 0x8) General Purpose Backup Register 2 */
- RwReg SYS_GPBR3; /**< \brief (Gpbr Offset: 0xC) General Purpose Backup Register 3 */
-} Gpbr;
-#endif /* __ASSEMBLY__ */
-/* -------- SYS_GPBR0 : (GPBR Offset: 0x0) General Purpose Backup Register 0 -------- */
-#define SYS_GPBR0_GPBR_VALUE0 (0xffffffff << 0) /**< \brief (SYS_GPBR0) Value of GPBR x */
-/* -------- SYS_GPBR1 : (GPBR Offset: 0x4) General Purpose Backup Register 1 -------- */
-#define SYS_GPBR1_GPBR_VALUE1 (0xffffffff << 0) /**< \brief (SYS_GPBR1) Value of GPBR x */
-/* -------- SYS_GPBR2 : (GPBR Offset: 0x8) General Purpose Backup Register 2 -------- */
-#define SYS_GPBR2_GPBR_VALUE2 (0xffffffff << 0) /**< \brief (SYS_GPBR2) Value of GPBR x */
-/* -------- SYS_GPBR3 : (GPBR Offset: 0xC) General Purpose Backup Register 3 -------- */
-#define SYS_GPBR3_GPBR_VALUE3 (0xffffffff << 0) /**< \brief (SYS_GPBR3) Value of GPBR x */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_HSMCI High Speed MultiMedia Card Interface */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Hsmci hardware registers */
-typedef struct {
- WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */
- RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */
- RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */
- RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */
- RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */
- WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */
- RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */
- RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */
- RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */
- RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */
- WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */
- RwReg Reserved1[2];
- RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */
- WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */
- WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */
- RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */
- RwReg Reserved2[1];
- RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */
- RwReg Reserved3[35];
- RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */
- RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */
- RwReg Reserved4[5];
- RwReg HSMCI_RPR; /**< \brief (Hsmci Offset: 0x100) Receive Pointer Register */
- RwReg HSMCI_RCR; /**< \brief (Hsmci Offset: 0x104) Receive Counter Register */
- RwReg HSMCI_TPR; /**< \brief (Hsmci Offset: 0x108) Transmit Pointer Register */
- RwReg HSMCI_TCR; /**< \brief (Hsmci Offset: 0x10C) Transmit Counter Register */
- RwReg HSMCI_RNPR; /**< \brief (Hsmci Offset: 0x110) Receive Next Pointer Register */
- RwReg HSMCI_RNCR; /**< \brief (Hsmci Offset: 0x114) Receive Next Counter Register */
- RwReg HSMCI_TNPR; /**< \brief (Hsmci Offset: 0x118) Transmit Next Pointer Register */
- RwReg HSMCI_TNCR; /**< \brief (Hsmci Offset: 0x11C) Transmit Next Counter Register */
- WoReg HSMCI_PTCR; /**< \brief (Hsmci Offset: 0x120) Transfer Control Register */
- RoReg HSMCI_PTSR; /**< \brief (Hsmci Offset: 0x124) Transfer Status Register */
-} Hsmci;
-#endif /* __ASSEMBLY__ */
-/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */
-#define HSMCI_CR_MCIEN (0x1 << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */
-#define HSMCI_CR_MCIDIS (0x1 << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */
-#define HSMCI_CR_PWSEN (0x1 << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */
-#define HSMCI_CR_PWSDIS (0x1 << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */
-#define HSMCI_CR_SWRST (0x1 << 7) /**< \brief (HSMCI_CR) Software Reset */
-/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */
-#define HSMCI_MR_CLKDIV (0xff << 0) /**< \brief (HSMCI_MR) Clock Divider */
-#define HSMCI_MR_PWSDIV (0x7 << 8) /**< \brief (HSMCI_MR) Power Saving Divider */
-#define HSMCI_MR_RDPROOF (0x1 << 11) /**< \brief (HSMCI_MR) */
-#define HSMCI_MR_WRPROOF (0x1 << 12) /**< \brief (HSMCI_MR) */
-#define HSMCI_MR_FBYTE (0x1 << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */
-#define HSMCI_MR_PADV (0x1 << 14) /**< \brief (HSMCI_MR) Padding Value */
-#define HSMCI_MR_PDCMODE (0x1 << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */
-#define HSMCI_MR_BLKLEN (0xffff << 16) /**< \brief (HSMCI_MR) Data Block Length */
-/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */
-#define HSMCI_DTOR_DTOCYC (0xf << 0) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */
-#define HSMCI_DTOR_DTOMUL (0x7 << 4) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */
-/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */
-#define HSMCI_SDCR_SDCSEL (0x3 << 0) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */
-#define HSMCI_SDCR_SDCBUS (0x3 << 6) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */
-/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */
-#define HSMCI_ARGR_ARG (0xffffffff << 0) /**< \brief (HSMCI_ARGR) Command Argument */
-/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */
-#define HSMCI_CMDR_CMDNB (0x3f << 0) /**< \brief (HSMCI_CMDR) Command Number */
-#define HSMCI_CMDR_RSPTYP (0x3 << 6) /**< \brief (HSMCI_CMDR) Response Type */
-#define HSMCI_CMDR_SPCMD (0x7 << 8) /**< \brief (HSMCI_CMDR) Special Command */
-#define HSMCI_CMDR_OPDCMD (0x1 << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */
-#define HSMCI_CMDR_MAXLAT (0x1 << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */
-#define HSMCI_CMDR_TRCMD (0x3 << 16) /**< \brief (HSMCI_CMDR) Transfer Command */
-#define HSMCI_CMDR_TRDIR (0x1 << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */
-#define HSMCI_CMDR_TRTYP (0x7 << 19) /**< \brief (HSMCI_CMDR) Transfer Type */
-#define HSMCI_CMDR_IOSPCMD (0x3 << 24) /**< \brief (HSMCI_CMDR) SDIO Special Command */
-#define HSMCI_CMDR_ATACS (0x1 << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */
-#define HSMCI_CMDR_BOOT_ACK (0x1 << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */
-/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */
-#define HSMCI_BLKR_BCNT (0xffff << 0) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */
-#define HSMCI_BLKR_BLKLEN (0xffff << 16) /**< \brief (HSMCI_BLKR) Data Block Length */
-/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */
-#define HSMCI_CSTOR_CSTOCYC (0xf << 0) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */
-#define HSMCI_CSTOR_CSTOMUL (0x7 << 4) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */
-/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */
-#define HSMCI_RSPR_RSP (0xffffffff << 0) /**< \brief (HSMCI_RSPR[4]) Response */
-/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */
-#define HSMCI_RDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_RDR) Data to Read */
-/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */
-#define HSMCI_TDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_TDR) Data to Write */
-/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */
-#define HSMCI_SR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_SR) Command Ready */
-#define HSMCI_SR_RXRDY (0x1 << 1) /**< \brief (HSMCI_SR) Receiver Ready */
-#define HSMCI_SR_TXRDY (0x1 << 2) /**< \brief (HSMCI_SR) Transmit Ready */
-#define HSMCI_SR_BLKE (0x1 << 3) /**< \brief (HSMCI_SR) Data Block Ended */
-#define HSMCI_SR_DTIP (0x1 << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */
-#define HSMCI_SR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */
-#define HSMCI_SR_ENDRX (0x1 << 6) /**< \brief (HSMCI_SR) End of RX Buffer */
-#define HSMCI_SR_ENDTX (0x1 << 7) /**< \brief (HSMCI_SR) End of TX Buffer */
-#define HSMCI_SR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */
-#define HSMCI_SR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */
-#define HSMCI_SR_CSRCV (0x1 << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */
-#define HSMCI_SR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_SR) RX Buffer Full */
-#define HSMCI_SR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_SR) TX Buffer Empty */
-#define HSMCI_SR_RINDE (0x1 << 16) /**< \brief (HSMCI_SR) Response Index Error */
-#define HSMCI_SR_RDIRE (0x1 << 17) /**< \brief (HSMCI_SR) Response Direction Error */
-#define HSMCI_SR_RCRCE (0x1 << 18) /**< \brief (HSMCI_SR) Response CRC Error */
-#define HSMCI_SR_RENDE (0x1 << 19) /**< \brief (HSMCI_SR) Response End Bit Error */
-#define HSMCI_SR_RTOE (0x1 << 20) /**< \brief (HSMCI_SR) Response Time-out Error */
-#define HSMCI_SR_DCRCE (0x1 << 21) /**< \brief (HSMCI_SR) Data CRC Error */
-#define HSMCI_SR_DTOE (0x1 << 22) /**< \brief (HSMCI_SR) Data Time-out Error */
-#define HSMCI_SR_CSTOE (0x1 << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */
-#define HSMCI_SR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_SR) FIFO empty flag */
-#define HSMCI_SR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_SR) Transfer Done flag */
-#define HSMCI_SR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */
-#define HSMCI_SR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */
-#define HSMCI_SR_OVRE (0x1 << 30) /**< \brief (HSMCI_SR) Overrun */
-#define HSMCI_SR_UNRE (0x1 << 31) /**< \brief (HSMCI_SR) Underrun */
-/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */
-#define HSMCI_IER_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */
-#define HSMCI_IER_RXRDY (0x1 << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */
-#define HSMCI_IER_TXRDY (0x1 << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */
-#define HSMCI_IER_BLKE (0x1 << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */
-#define HSMCI_IER_DTIP (0x1 << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */
-#define HSMCI_IER_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */
-#define HSMCI_IER_ENDRX (0x1 << 6) /**< \brief (HSMCI_IER) End of Receive Buffer Interrupt Enable */
-#define HSMCI_IER_ENDTX (0x1 << 7) /**< \brief (HSMCI_IER) End of Transmit Buffer Interrupt Enable */
-#define HSMCI_IER_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */
-#define HSMCI_IER_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */
-#define HSMCI_IER_CSRCV (0x1 << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */
-#define HSMCI_IER_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IER) Receive Buffer Full Interrupt Enable */
-#define HSMCI_IER_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IER) Transmit Buffer Empty Interrupt Enable */
-#define HSMCI_IER_RINDE (0x1 << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */
-#define HSMCI_IER_RDIRE (0x1 << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */
-#define HSMCI_IER_RCRCE (0x1 << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */
-#define HSMCI_IER_RENDE (0x1 << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */
-#define HSMCI_IER_RTOE (0x1 << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */
-#define HSMCI_IER_DCRCE (0x1 << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */
-#define HSMCI_IER_DTOE (0x1 << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */
-#define HSMCI_IER_CSTOE (0x1 << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */
-#define HSMCI_IER_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */
-#define HSMCI_IER_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */
-#define HSMCI_IER_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */
-#define HSMCI_IER_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */
-#define HSMCI_IER_OVRE (0x1 << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */
-#define HSMCI_IER_UNRE (0x1 << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */
-/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */
-#define HSMCI_IDR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */
-#define HSMCI_IDR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */
-#define HSMCI_IDR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */
-#define HSMCI_IDR_BLKE (0x1 << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */
-#define HSMCI_IDR_DTIP (0x1 << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */
-#define HSMCI_IDR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */
-#define HSMCI_IDR_ENDRX (0x1 << 6) /**< \brief (HSMCI_IDR) End of Receive Buffer Interrupt Disable */
-#define HSMCI_IDR_ENDTX (0x1 << 7) /**< \brief (HSMCI_IDR) End of Transmit Buffer Interrupt Disable */
-#define HSMCI_IDR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */
-#define HSMCI_IDR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */
-#define HSMCI_IDR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */
-#define HSMCI_IDR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IDR) Receive Buffer Full Interrupt Disable */
-#define HSMCI_IDR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable */
-#define HSMCI_IDR_RINDE (0x1 << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */
-#define HSMCI_IDR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */
-#define HSMCI_IDR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */
-#define HSMCI_IDR_RENDE (0x1 << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */
-#define HSMCI_IDR_RTOE (0x1 << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */
-#define HSMCI_IDR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */
-#define HSMCI_IDR_DTOE (0x1 << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */
-#define HSMCI_IDR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */
-#define HSMCI_IDR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */
-#define HSMCI_IDR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */
-#define HSMCI_IDR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */
-#define HSMCI_IDR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */
-#define HSMCI_IDR_OVRE (0x1 << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */
-#define HSMCI_IDR_UNRE (0x1 << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */
-/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */
-#define HSMCI_IMR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */
-#define HSMCI_IMR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */
-#define HSMCI_IMR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */
-#define HSMCI_IMR_BLKE (0x1 << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */
-#define HSMCI_IMR_DTIP (0x1 << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */
-#define HSMCI_IMR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */
-#define HSMCI_IMR_ENDRX (0x1 << 6) /**< \brief (HSMCI_IMR) End of Receive Buffer Interrupt Mask */
-#define HSMCI_IMR_ENDTX (0x1 << 7) /**< \brief (HSMCI_IMR) End of Transmit Buffer Interrupt Mask */
-#define HSMCI_IMR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */
-#define HSMCI_IMR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */
-#define HSMCI_IMR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */
-#define HSMCI_IMR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IMR) Receive Buffer Full Interrupt Mask */
-#define HSMCI_IMR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask */
-#define HSMCI_IMR_RINDE (0x1 << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */
-#define HSMCI_IMR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */
-#define HSMCI_IMR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */
-#define HSMCI_IMR_RENDE (0x1 << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */
-#define HSMCI_IMR_RTOE (0x1 << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */
-#define HSMCI_IMR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */
-#define HSMCI_IMR_DTOE (0x1 << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */
-#define HSMCI_IMR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */
-#define HSMCI_IMR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */
-#define HSMCI_IMR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */
-#define HSMCI_IMR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */
-#define HSMCI_IMR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */
-#define HSMCI_IMR_OVRE (0x1 << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */
-#define HSMCI_IMR_UNRE (0x1 << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */
-/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */
-#define HSMCI_CFG_FIFOMODE (0x1 << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */
-#define HSMCI_CFG_FERRCTRL (0x1 << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */
-#define HSMCI_CFG_HSMODE (0x1 << 8) /**< \brief (HSMCI_CFG) High Speed Mode */
-#define HSMCI_CFG_LSYNC (0x1 << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */
-/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */
-#define HSMCI_WPMR_WP_EN (0x1 << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */
-#define HSMCI_WPMR_WP_KEY (0xffffff << 8) /**< \brief (HSMCI_WPMR) Write Protection Key password */
-/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */
-#define HSMCI_WPSR_WP_VS (0xf << 0) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */
-#define HSMCI_WPSR_WP_VSRC (0xffff << 8) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */
-/* -------- HSMCI_RPR : (HSMCI Offset: 0x100) Receive Pointer Register -------- */
-#define HSMCI_RPR_RXPTR (0xffffffff << 0) /**< \brief (HSMCI_RPR) Receive Pointer Register */
-/* -------- HSMCI_RCR : (HSMCI Offset: 0x104) Receive Counter Register -------- */
-#define HSMCI_RCR_RXCTR (0xffff << 0) /**< \brief (HSMCI_RCR) Receive Counter Register */
-/* -------- HSMCI_TPR : (HSMCI Offset: 0x108) Transmit Pointer Register -------- */
-#define HSMCI_TPR_TXPTR (0xffffffff << 0) /**< \brief (HSMCI_TPR) Transmit Counter Register */
-/* -------- HSMCI_TCR : (HSMCI Offset: 0x10C) Transmit Counter Register -------- */
-#define HSMCI_TCR_TXCTR (0xffff << 0) /**< \brief (HSMCI_TCR) Transmit Counter Register */
-/* -------- HSMCI_RNPR : (HSMCI Offset: 0x110) Receive Next Pointer Register -------- */
-#define HSMCI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (HSMCI_RNPR) Receive Next Pointer */
-/* -------- HSMCI_RNCR : (HSMCI Offset: 0x114) Receive Next Counter Register -------- */
-#define HSMCI_RNCR_RXNCTR (0xffff << 0) /**< \brief (HSMCI_RNCR) Receive Next Counter */
-/* -------- HSMCI_TNPR : (HSMCI Offset: 0x118) Transmit Next Pointer Register -------- */
-#define HSMCI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (HSMCI_TNPR) Transmit Next Pointer */
-/* -------- HSMCI_TNCR : (HSMCI Offset: 0x11C) Transmit Next Counter Register -------- */
-#define HSMCI_TNCR_TXNCTR (0xffff << 0) /**< \brief (HSMCI_TNCR) Transmit Counter Next */
-/* -------- HSMCI_PTCR : (HSMCI Offset: 0x120) Transfer Control Register -------- */
-#define HSMCI_PTCR_RXTEN (0x1 << 0) /**< \brief (HSMCI_PTCR) Receiver Transfer Enable */
-#define HSMCI_PTCR_RXTDIS (0x1 << 1) /**< \brief (HSMCI_PTCR) Receiver Transfer Disable */
-#define HSMCI_PTCR_TXTEN (0x1 << 8) /**< \brief (HSMCI_PTCR) Transmitter Transfer Enable */
-#define HSMCI_PTCR_TXTDIS (0x1 << 9) /**< \brief (HSMCI_PTCR) Transmitter Transfer Disable */
-/* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */
-#define HSMCI_PTSR_RXTEN (0x1 << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */
-#define HSMCI_PTSR_TXTEN (0x1 << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_MATRIX AHB Bus Matrix */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Matrix hardware registers */
-typedef struct {
- RwReg MATRIX_MCFG[4]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */
- RwReg Reserved1[12];
- RwReg MATRIX_SCFG[5]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */
- RwReg Reserved2[11];
- RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */
- RwReg Reserved3[1];
- RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */
- RwReg Reserved4[1];
- RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */
- RwReg Reserved5[1];
- RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */
- RwReg Reserved6[1];
- RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */
- RwReg Reserved7[28];
- RwReg CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System IO Configuration register */
- RwReg Reserved8[1];
- RwReg CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register */
- RwReg Reserved9[49];
- RwReg MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */
- RoReg MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */
-} Matrix;
-#endif /* __ASSEMBLY__ */
-/* -------- MATRIX_MCFG[4] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */
-#define MATRIX_MCFG_ULBT (0x7 << 0) /**< \brief (MATRIX_MCFG[4]) Undefined Length Burst Type */
-/* -------- MATRIX_SCFG[5] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
-#define MATRIX_SCFG_SLOT_CYCLE (0xff << 0) /**< \brief (MATRIX_SCFG[5]) Maximum Number of Allowed Cycles for a Burst */
-#define MATRIX_SCFG_DEFMSTR_TYPE (0x3 << 16) /**< \brief (MATRIX_SCFG[5]) Default Master Type */
-#define MATRIX_SCFG_FIXED_DEFMSTR (0x7 << 18) /**< \brief (MATRIX_SCFG[5]) Fixed Default Master */
-#define MATRIX_SCFG_ARBT (0x3 << 24) /**< \brief (MATRIX_SCFG[5]) Arbitration Type */
-/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
-#define MATRIX_PRAS0_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS0) Master 0 Priority */
-#define MATRIX_PRAS0_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS0) Master 1 Priority */
-#define MATRIX_PRAS0_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS0) Master 2 Priority */
-#define MATRIX_PRAS0_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS0) Master 3 Priority */
-#define MATRIX_PRAS0_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS0) Master 4 Priority */
-/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
-#define MATRIX_PRAS1_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS1) Master 0 Priority */
-#define MATRIX_PRAS1_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS1) Master 1 Priority */
-#define MATRIX_PRAS1_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS1) Master 2 Priority */
-#define MATRIX_PRAS1_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS1) Master 3 Priority */
-#define MATRIX_PRAS1_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS1) Master 4 Priority */
-/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
-#define MATRIX_PRAS2_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS2) Master 0 Priority */
-#define MATRIX_PRAS2_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS2) Master 1 Priority */
-#define MATRIX_PRAS2_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS2) Master 2 Priority */
-#define MATRIX_PRAS2_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS2) Master 3 Priority */
-#define MATRIX_PRAS2_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS2) Master 4 Priority */
-/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
-#define MATRIX_PRAS3_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS3) Master 0 Priority */
-#define MATRIX_PRAS3_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS3) Master 1 Priority */
-#define MATRIX_PRAS3_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS3) Master 2 Priority */
-#define MATRIX_PRAS3_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS3) Master 3 Priority */
-#define MATRIX_PRAS3_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS3) Master 4 Priority */
-/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */
-#define MATRIX_PRAS4_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS4) Master 0 Priority */
-#define MATRIX_PRAS4_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS4) Master 1 Priority */
-#define MATRIX_PRAS4_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS4) Master 2 Priority */
-#define MATRIX_PRAS4_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS4) Master 3 Priority */
-#define MATRIX_PRAS4_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS4) Master 4 Priority */
-/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System IO Configuration register -------- */
-#define CCFG_SYSIO_SYSIO4 (0x1 << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */
-#define CCFG_SYSIO_SYSIO5 (0x1 << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */
-#define CCFG_SYSIO_SYSIO6 (0x1 << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */
-#define CCFG_SYSIO_SYSIO7 (0x1 << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */
-#define CCFG_SYSIO_SYSIO10 (0x1 << 10) /**< \brief (CCFG_SYSIO) PB10 or DDM Assignment */
-#define CCFG_SYSIO_SYSIO11 (0x1 << 11) /**< \brief (CCFG_SYSIO) PB11 or DDP Assignment */
-#define CCFG_SYSIO_SYSIO12 (0x1 << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */
-/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register -------- */
-#define CCFG_SMCNFCS_SMC_NFCS0 (0x1 << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */
-#define CCFG_SMCNFCS_SMC_NFCS1 (0x1 << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */
-#define CCFG_SMCNFCS_SMC_NFCS2 (0x1 << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */
-#define CCFG_SMCNFCS_SMC_NFCS3 (0x1 << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */
-/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */
-#define MATRIX_WPMR_WPEN (0x1 << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */
-#define MATRIX_WPMR_WPKEY (0xffffff << 8) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */
-/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */
-#define MATRIX_WPSR_WPVS (0x1 << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */
-#define MATRIX_WPSR_WPVSRC (0xffff << 8) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_PDC Peripheral DMA Controller */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Pdc hardware registers */
-typedef struct {
- RwReg Reserved1[64];
- RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x100) Receive Pointer Register */
- RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x104) Receive Counter Register */
- RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x108) Transmit Pointer Register */
- RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0x10C) Transmit Counter Register */
- RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x110) Receive Next Pointer Register */
- RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x114) Receive Next Counter Register */
- RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x118) Transmit Next Pointer Register */
- RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x11C) Transmit Next Counter Register */
- WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x120) Transfer Control Register */
- RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x124) Transfer Status Register */
-} Pdc;
-#endif /* __ASSEMBLY__ */
-/* -------- PERIPH_RPR : (PDC Offset: 0x100) Receive Pointer Register -------- */
-#define PERIPH_RPR_RXPTR (0xffffffff << 0) /**< \brief (PERIPH_RPR) Receive Pointer Register */
-/* -------- PERIPH_RCR : (PDC Offset: 0x104) Receive Counter Register -------- */
-#define PERIPH_RCR_RXCTR (0xffff << 0) /**< \brief (PERIPH_RCR) Receive Counter Register */
-/* -------- PERIPH_TPR : (PDC Offset: 0x108) Transmit Pointer Register -------- */
-#define PERIPH_TPR_TXPTR (0xffffffff << 0) /**< \brief (PERIPH_TPR) Transmit Counter Register */
-/* -------- PERIPH_TCR : (PDC Offset: 0x10C) Transmit Counter Register -------- */
-#define PERIPH_TCR_TXCTR (0xffff << 0) /**< \brief (PERIPH_TCR) Transmit Counter Register */
-/* -------- PERIPH_RNPR : (PDC Offset: 0x110) Receive Next Pointer Register -------- */
-#define PERIPH_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PERIPH_RNPR) Receive Next Pointer */
-/* -------- PERIPH_RNCR : (PDC Offset: 0x114) Receive Next Counter Register -------- */
-#define PERIPH_RNCR_RXNCTR (0xffff << 0) /**< \brief (PERIPH_RNCR) Receive Next Counter */
-/* -------- PERIPH_TNPR : (PDC Offset: 0x118) Transmit Next Pointer Register -------- */
-#define PERIPH_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */
-/* -------- PERIPH_TNCR : (PDC Offset: 0x11C) Transmit Next Counter Register -------- */
-#define PERIPH_TNCR_TXNCTR (0xffff << 0) /**< \brief (PERIPH_TNCR) Transmit Counter Next */
-/* -------- PERIPH_PTCR : (PDC Offset: 0x120) Transfer Control Register -------- */
-#define PERIPH_PTCR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */
-#define PERIPH_PTCR_RXTDIS (0x1 << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */
-#define PERIPH_PTCR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */
-#define PERIPH_PTCR_TXTDIS (0x1 << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */
-/* -------- PERIPH_PTSR : (PDC Offset: 0x124) Transfer Status Register -------- */
-#define PERIPH_PTSR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */
-#define PERIPH_PTSR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Parallel Input/Output */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_PIO Parallel Input/Output */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Pio hardware registers */
-typedef struct {
- WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */
- WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */
- RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */
- RwReg Reserved1[1];
- WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */
- WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */
- RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */
- RwReg Reserved2[1];
- WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */
- WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */
- RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */
- RwReg Reserved3[1];
- WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */
- WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */
- RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */
- RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */
- WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */
- WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */
- RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */
- RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */
- WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */
- WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */
- RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */
- RwReg Reserved4[1];
- WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */
- WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */
- RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */
- RwReg Reserved5[1];
- RwReg PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */
- RwReg Reserved6[2];
- WoReg PIO_SCIFSR; /**< \brief (Pio Offset: 0x0080) System Clock Glitch Input Filter Select Register */
- WoReg PIO_DIFSR; /**< \brief (Pio Offset: 0x0084) Debouncing Input Filter Select Register */
- RoReg PIO_IFDGSR; /**< \brief (Pio Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register */
- RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */
- WoReg PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */
- WoReg PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */
- RoReg PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */
- RwReg Reserved7[1];
- WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */
- WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */
- RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */
- RwReg Reserved8[1];
- WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */
- WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */
- RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */
- RwReg Reserved9[1];
- WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */
- WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */
- RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */
- RwReg Reserved10[1];
- WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */
- WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */
- RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */
- RwReg Reserved11[1];
- RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */
- RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */
- RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */
- RwReg Reserved12[5];
- RwReg PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */
- RwReg Reserved13[19];
- RwReg PIO_PCMR; /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */
- WoReg PIO_PCIER; /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */
- WoReg PIO_PCIDR; /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */
- RoReg PIO_PCIMR; /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */
- RoReg PIO_PCISR; /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */
- RoReg PIO_PCRHR; /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */
-} Pio;
-#endif /* __ASSEMBLY__ */
-/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */
-#define PIO_PER_P0 (0x1 << 0) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P1 (0x1 << 1) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P2 (0x1 << 2) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P3 (0x1 << 3) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P4 (0x1 << 4) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P5 (0x1 << 5) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P6 (0x1 << 6) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P7 (0x1 << 7) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P8 (0x1 << 8) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P9 (0x1 << 9) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P10 (0x1 << 10) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P11 (0x1 << 11) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P12 (0x1 << 12) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P13 (0x1 << 13) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P14 (0x1 << 14) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P15 (0x1 << 15) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P16 (0x1 << 16) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P17 (0x1 << 17) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P18 (0x1 << 18) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P19 (0x1 << 19) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P20 (0x1 << 20) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P21 (0x1 << 21) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P22 (0x1 << 22) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P23 (0x1 << 23) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P24 (0x1 << 24) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P25 (0x1 << 25) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P26 (0x1 << 26) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P27 (0x1 << 27) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P28 (0x1 << 28) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P29 (0x1 << 29) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P30 (0x1 << 30) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P31 (0x1 << 31) /**< \brief (PIO_PER) PIO Enable */
-/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */
-#define PIO_PDR_P0 (0x1 << 0) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P1 (0x1 << 1) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P2 (0x1 << 2) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P3 (0x1 << 3) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P4 (0x1 << 4) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P5 (0x1 << 5) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P6 (0x1 << 6) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P7 (0x1 << 7) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P8 (0x1 << 8) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P9 (0x1 << 9) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P10 (0x1 << 10) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P11 (0x1 << 11) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P12 (0x1 << 12) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P13 (0x1 << 13) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P14 (0x1 << 14) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P15 (0x1 << 15) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P16 (0x1 << 16) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P17 (0x1 << 17) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P18 (0x1 << 18) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P19 (0x1 << 19) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P20 (0x1 << 20) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P21 (0x1 << 21) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P22 (0x1 << 22) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P23 (0x1 << 23) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P24 (0x1 << 24) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P25 (0x1 << 25) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P26 (0x1 << 26) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P27 (0x1 << 27) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P28 (0x1 << 28) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P29 (0x1 << 29) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P30 (0x1 << 30) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P31 (0x1 << 31) /**< \brief (PIO_PDR) PIO Disable */
-/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */
-#define PIO_PSR_P0 (0x1 << 0) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P1 (0x1 << 1) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P2 (0x1 << 2) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P3 (0x1 << 3) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P4 (0x1 << 4) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P5 (0x1 << 5) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P6 (0x1 << 6) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P7 (0x1 << 7) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P8 (0x1 << 8) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P9 (0x1 << 9) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P10 (0x1 << 10) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P11 (0x1 << 11) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P12 (0x1 << 12) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P13 (0x1 << 13) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P14 (0x1 << 14) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P15 (0x1 << 15) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P16 (0x1 << 16) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P17 (0x1 << 17) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P18 (0x1 << 18) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P19 (0x1 << 19) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P20 (0x1 << 20) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P21 (0x1 << 21) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P22 (0x1 << 22) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P23 (0x1 << 23) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P24 (0x1 << 24) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P25 (0x1 << 25) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P26 (0x1 << 26) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P27 (0x1 << 27) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P28 (0x1 << 28) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P29 (0x1 << 29) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P30 (0x1 << 30) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P31 (0x1 << 31) /**< \brief (PIO_PSR) PIO Status */
-/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */
-#define PIO_OER_P0 (0x1 << 0) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P1 (0x1 << 1) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P2 (0x1 << 2) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P3 (0x1 << 3) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P4 (0x1 << 4) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P5 (0x1 << 5) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P6 (0x1 << 6) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P7 (0x1 << 7) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P8 (0x1 << 8) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P9 (0x1 << 9) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P10 (0x1 << 10) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P11 (0x1 << 11) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P12 (0x1 << 12) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P13 (0x1 << 13) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P14 (0x1 << 14) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P15 (0x1 << 15) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P16 (0x1 << 16) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P17 (0x1 << 17) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P18 (0x1 << 18) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P19 (0x1 << 19) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P20 (0x1 << 20) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P21 (0x1 << 21) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P22 (0x1 << 22) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P23 (0x1 << 23) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P24 (0x1 << 24) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P25 (0x1 << 25) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P26 (0x1 << 26) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P27 (0x1 << 27) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P28 (0x1 << 28) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P29 (0x1 << 29) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P30 (0x1 << 30) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P31 (0x1 << 31) /**< \brief (PIO_OER) Output Enable */
-/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */
-#define PIO_ODR_P0 (0x1 << 0) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P1 (0x1 << 1) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P2 (0x1 << 2) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P3 (0x1 << 3) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P4 (0x1 << 4) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P5 (0x1 << 5) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P6 (0x1 << 6) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P7 (0x1 << 7) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P8 (0x1 << 8) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P9 (0x1 << 9) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P10 (0x1 << 10) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P11 (0x1 << 11) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P12 (0x1 << 12) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P13 (0x1 << 13) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P14 (0x1 << 14) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P15 (0x1 << 15) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P16 (0x1 << 16) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P17 (0x1 << 17) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P18 (0x1 << 18) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P19 (0x1 << 19) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P20 (0x1 << 20) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P21 (0x1 << 21) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P22 (0x1 << 22) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P23 (0x1 << 23) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P24 (0x1 << 24) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P25 (0x1 << 25) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P26 (0x1 << 26) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P27 (0x1 << 27) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P28 (0x1 << 28) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P29 (0x1 << 29) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P30 (0x1 << 30) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P31 (0x1 << 31) /**< \brief (PIO_ODR) Output Disable */
-/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */
-#define PIO_OSR_P0 (0x1 << 0) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P1 (0x1 << 1) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P2 (0x1 << 2) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P3 (0x1 << 3) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P4 (0x1 << 4) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P5 (0x1 << 5) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P6 (0x1 << 6) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P7 (0x1 << 7) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P8 (0x1 << 8) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P9 (0x1 << 9) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P10 (0x1 << 10) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P11 (0x1 << 11) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P12 (0x1 << 12) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P13 (0x1 << 13) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P14 (0x1 << 14) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P15 (0x1 << 15) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P16 (0x1 << 16) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P17 (0x1 << 17) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P18 (0x1 << 18) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P19 (0x1 << 19) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P20 (0x1 << 20) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P21 (0x1 << 21) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P22 (0x1 << 22) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P23 (0x1 << 23) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P24 (0x1 << 24) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P25 (0x1 << 25) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P26 (0x1 << 26) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P27 (0x1 << 27) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P28 (0x1 << 28) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P29 (0x1 << 29) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P30 (0x1 << 30) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P31 (0x1 << 31) /**< \brief (PIO_OSR) Output Status */
-/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */
-#define PIO_IFER_P0 (0x1 << 0) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P1 (0x1 << 1) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P2 (0x1 << 2) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P3 (0x1 << 3) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P4 (0x1 << 4) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P5 (0x1 << 5) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P6 (0x1 << 6) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P7 (0x1 << 7) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P8 (0x1 << 8) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P9 (0x1 << 9) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P10 (0x1 << 10) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P11 (0x1 << 11) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P12 (0x1 << 12) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P13 (0x1 << 13) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P14 (0x1 << 14) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P15 (0x1 << 15) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P16 (0x1 << 16) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P17 (0x1 << 17) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P18 (0x1 << 18) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P19 (0x1 << 19) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P20 (0x1 << 20) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P21 (0x1 << 21) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P22 (0x1 << 22) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P23 (0x1 << 23) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P24 (0x1 << 24) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P25 (0x1 << 25) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P26 (0x1 << 26) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P27 (0x1 << 27) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P28 (0x1 << 28) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P29 (0x1 << 29) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P30 (0x1 << 30) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P31 (0x1 << 31) /**< \brief (PIO_IFER) Input Filter Enable */
-/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */
-#define PIO_IFDR_P0 (0x1 << 0) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P1 (0x1 << 1) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P2 (0x1 << 2) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P3 (0x1 << 3) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P4 (0x1 << 4) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P5 (0x1 << 5) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P6 (0x1 << 6) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P7 (0x1 << 7) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P8 (0x1 << 8) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P9 (0x1 << 9) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P10 (0x1 << 10) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P11 (0x1 << 11) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P12 (0x1 << 12) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P13 (0x1 << 13) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P14 (0x1 << 14) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P15 (0x1 << 15) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P16 (0x1 << 16) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P17 (0x1 << 17) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P18 (0x1 << 18) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P19 (0x1 << 19) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P20 (0x1 << 20) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P21 (0x1 << 21) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P22 (0x1 << 22) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P23 (0x1 << 23) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P24 (0x1 << 24) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P25 (0x1 << 25) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P26 (0x1 << 26) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P27 (0x1 << 27) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P28 (0x1 << 28) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P29 (0x1 << 29) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P30 (0x1 << 30) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P31 (0x1 << 31) /**< \brief (PIO_IFDR) Input Filter Disable */
-/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */
-#define PIO_IFSR_P0 (0x1 << 0) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P1 (0x1 << 1) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P2 (0x1 << 2) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P3 (0x1 << 3) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P4 (0x1 << 4) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P5 (0x1 << 5) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P6 (0x1 << 6) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P7 (0x1 << 7) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P8 (0x1 << 8) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P9 (0x1 << 9) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P10 (0x1 << 10) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P11 (0x1 << 11) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P12 (0x1 << 12) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P13 (0x1 << 13) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P14 (0x1 << 14) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P15 (0x1 << 15) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P16 (0x1 << 16) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P17 (0x1 << 17) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P18 (0x1 << 18) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P19 (0x1 << 19) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P20 (0x1 << 20) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P21 (0x1 << 21) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P22 (0x1 << 22) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P23 (0x1 << 23) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P24 (0x1 << 24) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P25 (0x1 << 25) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P26 (0x1 << 26) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P27 (0x1 << 27) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P28 (0x1 << 28) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P29 (0x1 << 29) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P30 (0x1 << 30) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P31 (0x1 << 31) /**< \brief (PIO_IFSR) Input Filer Status */
-/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */
-#define PIO_SODR_P0 (0x1 << 0) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P1 (0x1 << 1) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P2 (0x1 << 2) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P3 (0x1 << 3) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P4 (0x1 << 4) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P5 (0x1 << 5) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P6 (0x1 << 6) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P7 (0x1 << 7) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P8 (0x1 << 8) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P9 (0x1 << 9) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P10 (0x1 << 10) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P11 (0x1 << 11) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P12 (0x1 << 12) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P13 (0x1 << 13) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P14 (0x1 << 14) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P15 (0x1 << 15) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P16 (0x1 << 16) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P17 (0x1 << 17) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P18 (0x1 << 18) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P19 (0x1 << 19) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P20 (0x1 << 20) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P21 (0x1 << 21) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P22 (0x1 << 22) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P23 (0x1 << 23) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P24 (0x1 << 24) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P25 (0x1 << 25) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P26 (0x1 << 26) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P27 (0x1 << 27) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P28 (0x1 << 28) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P29 (0x1 << 29) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P30 (0x1 << 30) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P31 (0x1 << 31) /**< \brief (PIO_SODR) Set Output Data */
-/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */
-#define PIO_CODR_P0 (0x1 << 0) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P1 (0x1 << 1) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P2 (0x1 << 2) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P3 (0x1 << 3) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P4 (0x1 << 4) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P5 (0x1 << 5) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P6 (0x1 << 6) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P7 (0x1 << 7) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P8 (0x1 << 8) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P9 (0x1 << 9) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P10 (0x1 << 10) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P11 (0x1 << 11) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P12 (0x1 << 12) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P13 (0x1 << 13) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P14 (0x1 << 14) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P15 (0x1 << 15) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P16 (0x1 << 16) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P17 (0x1 << 17) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P18 (0x1 << 18) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P19 (0x1 << 19) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P20 (0x1 << 20) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P21 (0x1 << 21) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P22 (0x1 << 22) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P23 (0x1 << 23) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P24 (0x1 << 24) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P25 (0x1 << 25) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P26 (0x1 << 26) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P27 (0x1 << 27) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P28 (0x1 << 28) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P29 (0x1 << 29) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P30 (0x1 << 30) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P31 (0x1 << 31) /**< \brief (PIO_CODR) Clear Output Data */
-/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */
-#define PIO_ODSR_P0 (0x1 << 0) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P1 (0x1 << 1) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P2 (0x1 << 2) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P3 (0x1 << 3) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P4 (0x1 << 4) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P5 (0x1 << 5) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P6 (0x1 << 6) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P7 (0x1 << 7) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P8 (0x1 << 8) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P9 (0x1 << 9) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P10 (0x1 << 10) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P11 (0x1 << 11) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P12 (0x1 << 12) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P13 (0x1 << 13) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P14 (0x1 << 14) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P15 (0x1 << 15) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P16 (0x1 << 16) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P17 (0x1 << 17) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P18 (0x1 << 18) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P19 (0x1 << 19) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P20 (0x1 << 20) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P21 (0x1 << 21) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P22 (0x1 << 22) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P23 (0x1 << 23) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P24 (0x1 << 24) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P25 (0x1 << 25) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P26 (0x1 << 26) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P27 (0x1 << 27) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P28 (0x1 << 28) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P29 (0x1 << 29) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P30 (0x1 << 30) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P31 (0x1 << 31) /**< \brief (PIO_ODSR) Output Data Status */
-/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */
-#define PIO_PDSR_P0 (0x1 << 0) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P1 (0x1 << 1) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P2 (0x1 << 2) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P3 (0x1 << 3) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P4 (0x1 << 4) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P5 (0x1 << 5) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P6 (0x1 << 6) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P7 (0x1 << 7) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P8 (0x1 << 8) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P9 (0x1 << 9) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P10 (0x1 << 10) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P11 (0x1 << 11) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P12 (0x1 << 12) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P13 (0x1 << 13) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P14 (0x1 << 14) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P15 (0x1 << 15) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P16 (0x1 << 16) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P17 (0x1 << 17) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P18 (0x1 << 18) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P19 (0x1 << 19) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P20 (0x1 << 20) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P21 (0x1 << 21) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P22 (0x1 << 22) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P23 (0x1 << 23) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P24 (0x1 << 24) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P25 (0x1 << 25) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P26 (0x1 << 26) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P27 (0x1 << 27) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P28 (0x1 << 28) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P29 (0x1 << 29) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P30 (0x1 << 30) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P31 (0x1 << 31) /**< \brief (PIO_PDSR) Output Data Status */
-/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */
-#define PIO_IER_P0 (0x1 << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P1 (0x1 << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P2 (0x1 << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P3 (0x1 << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P4 (0x1 << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P5 (0x1 << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P6 (0x1 << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P7 (0x1 << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P8 (0x1 << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P9 (0x1 << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P10 (0x1 << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P11 (0x1 << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P12 (0x1 << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P13 (0x1 << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P14 (0x1 << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P15 (0x1 << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P16 (0x1 << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P17 (0x1 << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P18 (0x1 << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P19 (0x1 << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P20 (0x1 << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P21 (0x1 << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P22 (0x1 << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P23 (0x1 << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P24 (0x1 << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P25 (0x1 << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P26 (0x1 << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P27 (0x1 << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P28 (0x1 << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P29 (0x1 << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P30 (0x1 << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P31 (0x1 << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */
-#define PIO_IDR_P0 (0x1 << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P1 (0x1 << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P2 (0x1 << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P3 (0x1 << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P4 (0x1 << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P5 (0x1 << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P6 (0x1 << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P7 (0x1 << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P8 (0x1 << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P9 (0x1 << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P10 (0x1 << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P11 (0x1 << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P12 (0x1 << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P13 (0x1 << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P14 (0x1 << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P15 (0x1 << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P16 (0x1 << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P17 (0x1 << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P18 (0x1 << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P19 (0x1 << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P20 (0x1 << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P21 (0x1 << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P22 (0x1 << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P23 (0x1 << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P24 (0x1 << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P25 (0x1 << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P26 (0x1 << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P27 (0x1 << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P28 (0x1 << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P29 (0x1 << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P30 (0x1 << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P31 (0x1 << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */
-#define PIO_IMR_P0 (0x1 << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P1 (0x1 << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P2 (0x1 << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P3 (0x1 << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P4 (0x1 << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P5 (0x1 << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P6 (0x1 << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P7 (0x1 << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P8 (0x1 << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P9 (0x1 << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P10 (0x1 << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P11 (0x1 << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P12 (0x1 << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P13 (0x1 << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P14 (0x1 << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P15 (0x1 << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P16 (0x1 << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P17 (0x1 << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P18 (0x1 << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P19 (0x1 << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P20 (0x1 << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P21 (0x1 << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P22 (0x1 << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P23 (0x1 << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P24 (0x1 << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P25 (0x1 << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P26 (0x1 << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P27 (0x1 << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P28 (0x1 << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P29 (0x1 << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P30 (0x1 << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P31 (0x1 << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */
-#define PIO_ISR_P0 (0x1 << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P1 (0x1 << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P2 (0x1 << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P3 (0x1 << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P4 (0x1 << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P5 (0x1 << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P6 (0x1 << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P7 (0x1 << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P8 (0x1 << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P9 (0x1 << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P10 (0x1 << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P11 (0x1 << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P12 (0x1 << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P13 (0x1 << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P14 (0x1 << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P15 (0x1 << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P16 (0x1 << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P17 (0x1 << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P18 (0x1 << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P19 (0x1 << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P20 (0x1 << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P21 (0x1 << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P22 (0x1 << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P23 (0x1 << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P24 (0x1 << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P25 (0x1 << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P26 (0x1 << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P27 (0x1 << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P28 (0x1 << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P29 (0x1 << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P30 (0x1 << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P31 (0x1 << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */
-#define PIO_MDER_P0 (0x1 << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P1 (0x1 << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P2 (0x1 << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P3 (0x1 << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P4 (0x1 << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P5 (0x1 << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P6 (0x1 << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P7 (0x1 << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P8 (0x1 << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P9 (0x1 << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P10 (0x1 << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P11 (0x1 << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P12 (0x1 << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P13 (0x1 << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P14 (0x1 << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P15 (0x1 << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P16 (0x1 << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P17 (0x1 << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P18 (0x1 << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P19 (0x1 << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P20 (0x1 << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P21 (0x1 << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P22 (0x1 << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P23 (0x1 << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P24 (0x1 << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P25 (0x1 << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P26 (0x1 << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P27 (0x1 << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P28 (0x1 << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P29 (0x1 << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P30 (0x1 << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P31 (0x1 << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */
-/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */
-#define PIO_MDDR_P0 (0x1 << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P1 (0x1 << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P2 (0x1 << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P3 (0x1 << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P4 (0x1 << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P5 (0x1 << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P6 (0x1 << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P7 (0x1 << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P8 (0x1 << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P9 (0x1 << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P10 (0x1 << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P11 (0x1 << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P12 (0x1 << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P13 (0x1 << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P14 (0x1 << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P15 (0x1 << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P16 (0x1 << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P17 (0x1 << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P18 (0x1 << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P19 (0x1 << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P20 (0x1 << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P21 (0x1 << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P22 (0x1 << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P23 (0x1 << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P24 (0x1 << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P25 (0x1 << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P26 (0x1 << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P27 (0x1 << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P28 (0x1 << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P29 (0x1 << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P30 (0x1 << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P31 (0x1 << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */
-#define PIO_MDSR_P0 (0x1 << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P1 (0x1 << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P2 (0x1 << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P3 (0x1 << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P4 (0x1 << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P5 (0x1 << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P6 (0x1 << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P7 (0x1 << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P8 (0x1 << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P9 (0x1 << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P10 (0x1 << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P11 (0x1 << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P12 (0x1 << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P13 (0x1 << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P14 (0x1 << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P15 (0x1 << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P16 (0x1 << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P17 (0x1 << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P18 (0x1 << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P19 (0x1 << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P20 (0x1 << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P21 (0x1 << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P22 (0x1 << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P23 (0x1 << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P24 (0x1 << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P25 (0x1 << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P26 (0x1 << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P27 (0x1 << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P28 (0x1 << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P29 (0x1 << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P30 (0x1 << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P31 (0x1 << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */
-/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */
-#define PIO_PUDR_P0 (0x1 << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P1 (0x1 << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P2 (0x1 << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P3 (0x1 << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P4 (0x1 << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P5 (0x1 << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P6 (0x1 << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P7 (0x1 << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P8 (0x1 << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P9 (0x1 << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P10 (0x1 << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P11 (0x1 << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P12 (0x1 << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P13 (0x1 << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P14 (0x1 << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P15 (0x1 << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P16 (0x1 << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P17 (0x1 << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P18 (0x1 << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P19 (0x1 << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P20 (0x1 << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P21 (0x1 << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P22 (0x1 << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P23 (0x1 << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P24 (0x1 << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P25 (0x1 << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P26 (0x1 << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P27 (0x1 << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P28 (0x1 << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P29 (0x1 << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P30 (0x1 << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P31 (0x1 << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */
-/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */
-#define PIO_PUER_P0 (0x1 << 0) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P1 (0x1 << 1) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P2 (0x1 << 2) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P3 (0x1 << 3) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P4 (0x1 << 4) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P5 (0x1 << 5) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P6 (0x1 << 6) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P7 (0x1 << 7) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P8 (0x1 << 8) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P9 (0x1 << 9) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P10 (0x1 << 10) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P11 (0x1 << 11) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P12 (0x1 << 12) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P13 (0x1 << 13) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P14 (0x1 << 14) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P15 (0x1 << 15) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P16 (0x1 << 16) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P17 (0x1 << 17) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P18 (0x1 << 18) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P19 (0x1 << 19) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P20 (0x1 << 20) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P21 (0x1 << 21) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P22 (0x1 << 22) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P23 (0x1 << 23) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P24 (0x1 << 24) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P25 (0x1 << 25) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P26 (0x1 << 26) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P27 (0x1 << 27) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P28 (0x1 << 28) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P29 (0x1 << 29) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P30 (0x1 << 30) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P31 (0x1 << 31) /**< \brief (PIO_PUER) Pull Up Enable. */
-/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */
-#define PIO_PUSR_P0 (0x1 << 0) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P1 (0x1 << 1) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P2 (0x1 << 2) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P3 (0x1 << 3) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P4 (0x1 << 4) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P5 (0x1 << 5) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P6 (0x1 << 6) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P7 (0x1 << 7) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P8 (0x1 << 8) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P9 (0x1 << 9) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P10 (0x1 << 10) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P11 (0x1 << 11) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P12 (0x1 << 12) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P13 (0x1 << 13) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P14 (0x1 << 14) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P15 (0x1 << 15) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P16 (0x1 << 16) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P17 (0x1 << 17) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P18 (0x1 << 18) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P19 (0x1 << 19) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P20 (0x1 << 20) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P21 (0x1 << 21) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P22 (0x1 << 22) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P23 (0x1 << 23) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P24 (0x1 << 24) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P25 (0x1 << 25) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P26 (0x1 << 26) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P27 (0x1 << 27) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P28 (0x1 << 28) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P29 (0x1 << 29) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P30 (0x1 << 30) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P31 (0x1 << 31) /**< \brief (PIO_PUSR) Pull Up Status. */
-/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */
-#define PIO_ABCDSR_P0 (0x1 << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P1 (0x1 << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P2 (0x1 << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P3 (0x1 << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P4 (0x1 << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P5 (0x1 << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P6 (0x1 << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P7 (0x1 << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P8 (0x1 << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P9 (0x1 << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P10 (0x1 << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P11 (0x1 << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P12 (0x1 << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P13 (0x1 << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P14 (0x1 << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P15 (0x1 << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P16 (0x1 << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P17 (0x1 << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P18 (0x1 << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P19 (0x1 << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P20 (0x1 << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P21 (0x1 << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P22 (0x1 << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P23 (0x1 << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P24 (0x1 << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P25 (0x1 << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P26 (0x1 << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P27 (0x1 << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P28 (0x1 << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P29 (0x1 << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P30 (0x1 << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-#define PIO_ABCDSR_P31 (0x1 << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
-/* -------- PIO_SCIFSR : (PIO Offset: 0x0080) System Clock Glitch Input Filter Select Register -------- */
-#define PIO_SCIFSR_P0 (0x1 << 0) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P1 (0x1 << 1) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P2 (0x1 << 2) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P3 (0x1 << 3) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P4 (0x1 << 4) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P5 (0x1 << 5) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P6 (0x1 << 6) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P7 (0x1 << 7) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P8 (0x1 << 8) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P9 (0x1 << 9) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P10 (0x1 << 10) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P11 (0x1 << 11) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P12 (0x1 << 12) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P13 (0x1 << 13) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P14 (0x1 << 14) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P15 (0x1 << 15) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P16 (0x1 << 16) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P17 (0x1 << 17) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P18 (0x1 << 18) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P19 (0x1 << 19) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P20 (0x1 << 20) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P21 (0x1 << 21) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P22 (0x1 << 22) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P23 (0x1 << 23) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P24 (0x1 << 24) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P25 (0x1 << 25) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P26 (0x1 << 26) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P27 (0x1 << 27) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P28 (0x1 << 28) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P29 (0x1 << 29) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P30 (0x1 << 30) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P31 (0x1 << 31) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-/* -------- PIO_DIFSR : (PIO Offset: 0x0084) Debouncing Input Filter Select Register -------- */
-#define PIO_DIFSR_P0 (0x1 << 0) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P1 (0x1 << 1) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P2 (0x1 << 2) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P3 (0x1 << 3) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P4 (0x1 << 4) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P5 (0x1 << 5) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P6 (0x1 << 6) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P7 (0x1 << 7) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P8 (0x1 << 8) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P9 (0x1 << 9) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P10 (0x1 << 10) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P11 (0x1 << 11) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P12 (0x1 << 12) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P13 (0x1 << 13) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P14 (0x1 << 14) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P15 (0x1 << 15) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P16 (0x1 << 16) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P17 (0x1 << 17) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P18 (0x1 << 18) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P19 (0x1 << 19) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P20 (0x1 << 20) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P21 (0x1 << 21) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P22 (0x1 << 22) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P23 (0x1 << 23) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P24 (0x1 << 24) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P25 (0x1 << 25) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P26 (0x1 << 26) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P27 (0x1 << 27) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P28 (0x1 << 28) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P29 (0x1 << 29) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P30 (0x1 << 30) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P31 (0x1 << 31) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-/* -------- PIO_IFDGSR : (PIO Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register -------- */
-#define PIO_IFDGSR_P0 (0x1 << 0) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P1 (0x1 << 1) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P2 (0x1 << 2) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P3 (0x1 << 3) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P4 (0x1 << 4) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P5 (0x1 << 5) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P6 (0x1 << 6) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P7 (0x1 << 7) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P8 (0x1 << 8) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P9 (0x1 << 9) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P10 (0x1 << 10) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P11 (0x1 << 11) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P12 (0x1 << 12) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P13 (0x1 << 13) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P14 (0x1 << 14) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P15 (0x1 << 15) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P16 (0x1 << 16) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P17 (0x1 << 17) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P18 (0x1 << 18) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P19 (0x1 << 19) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P20 (0x1 << 20) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P21 (0x1 << 21) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P22 (0x1 << 22) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P23 (0x1 << 23) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P24 (0x1 << 24) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P25 (0x1 << 25) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P26 (0x1 << 26) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P27 (0x1 << 27) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P28 (0x1 << 28) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P29 (0x1 << 29) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P30 (0x1 << 30) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P31 (0x1 << 31) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */
-#define PIO_SCDR_DIV0 (0x1 << 0) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */
-#define PIO_SCDR_DIV1 (0x1 << 1) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */
-#define PIO_SCDR_DIV2 (0x1 << 2) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */
-#define PIO_SCDR_DIV3 (0x1 << 3) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */
-#define PIO_SCDR_DIV4 (0x1 << 4) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */
-#define PIO_SCDR_DIV5 (0x1 << 5) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */
-#define PIO_SCDR_DIV6 (0x1 << 6) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */
-#define PIO_SCDR_DIV7 (0x1 << 7) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */
-#define PIO_SCDR_DIV8 (0x1 << 8) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */
-#define PIO_SCDR_DIV9 (0x1 << 9) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */
-#define PIO_SCDR_DIV10 (0x1 << 10) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */
-#define PIO_SCDR_DIV11 (0x1 << 11) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */
-#define PIO_SCDR_DIV12 (0x1 << 12) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */
-#define PIO_SCDR_DIV13 (0x1 << 13) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */
-/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */
-#define PIO_PPDDR_P0 (0x1 << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P1 (0x1 << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P2 (0x1 << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P3 (0x1 << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P4 (0x1 << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P5 (0x1 << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P6 (0x1 << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P7 (0x1 << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P8 (0x1 << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P9 (0x1 << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P10 (0x1 << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P11 (0x1 << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P12 (0x1 << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P13 (0x1 << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P14 (0x1 << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P15 (0x1 << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P16 (0x1 << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P17 (0x1 << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P18 (0x1 << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P19 (0x1 << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P20 (0x1 << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P21 (0x1 << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P22 (0x1 << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P23 (0x1 << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P24 (0x1 << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P25 (0x1 << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P26 (0x1 << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P27 (0x1 << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P28 (0x1 << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P29 (0x1 << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P30 (0x1 << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-#define PIO_PPDDR_P31 (0x1 << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */
-/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */
-#define PIO_PPDER_P0 (0x1 << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P1 (0x1 << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P2 (0x1 << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P3 (0x1 << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P4 (0x1 << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P5 (0x1 << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P6 (0x1 << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P7 (0x1 << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P8 (0x1 << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P9 (0x1 << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P10 (0x1 << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P11 (0x1 << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P12 (0x1 << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P13 (0x1 << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P14 (0x1 << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P15 (0x1 << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P16 (0x1 << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P17 (0x1 << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P18 (0x1 << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P19 (0x1 << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P20 (0x1 << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P21 (0x1 << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P22 (0x1 << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P23 (0x1 << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P24 (0x1 << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P25 (0x1 << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P26 (0x1 << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P27 (0x1 << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P28 (0x1 << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P29 (0x1 << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P30 (0x1 << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */
-#define PIO_PPDER_P31 (0x1 << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */
-/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */
-#define PIO_PPDSR_P0 (0x1 << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P1 (0x1 << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P2 (0x1 << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P3 (0x1 << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P4 (0x1 << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P5 (0x1 << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P6 (0x1 << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P7 (0x1 << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P8 (0x1 << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P9 (0x1 << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P10 (0x1 << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P11 (0x1 << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P12 (0x1 << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P13 (0x1 << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P14 (0x1 << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P15 (0x1 << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P16 (0x1 << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P17 (0x1 << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P18 (0x1 << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P19 (0x1 << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P20 (0x1 << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P21 (0x1 << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P22 (0x1 << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P23 (0x1 << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P24 (0x1 << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P25 (0x1 << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P26 (0x1 << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P27 (0x1 << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P28 (0x1 << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P29 (0x1 << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P30 (0x1 << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */
-#define PIO_PPDSR_P31 (0x1 << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */
-/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */
-#define PIO_OWER_P0 (0x1 << 0) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P1 (0x1 << 1) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P2 (0x1 << 2) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P3 (0x1 << 3) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P4 (0x1 << 4) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P5 (0x1 << 5) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P6 (0x1 << 6) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P7 (0x1 << 7) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P8 (0x1 << 8) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P9 (0x1 << 9) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P10 (0x1 << 10) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P11 (0x1 << 11) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P12 (0x1 << 12) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P13 (0x1 << 13) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P14 (0x1 << 14) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P15 (0x1 << 15) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P16 (0x1 << 16) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P17 (0x1 << 17) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P18 (0x1 << 18) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P19 (0x1 << 19) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P20 (0x1 << 20) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P21 (0x1 << 21) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P22 (0x1 << 22) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P23 (0x1 << 23) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P24 (0x1 << 24) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P25 (0x1 << 25) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P26 (0x1 << 26) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P27 (0x1 << 27) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P28 (0x1 << 28) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P29 (0x1 << 29) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P30 (0x1 << 30) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P31 (0x1 << 31) /**< \brief (PIO_OWER) Output Write Enable. */
-/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */
-#define PIO_OWDR_P0 (0x1 << 0) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P1 (0x1 << 1) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P2 (0x1 << 2) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P3 (0x1 << 3) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P4 (0x1 << 4) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P5 (0x1 << 5) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P6 (0x1 << 6) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P7 (0x1 << 7) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P8 (0x1 << 8) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P9 (0x1 << 9) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P10 (0x1 << 10) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P11 (0x1 << 11) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P12 (0x1 << 12) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P13 (0x1 << 13) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P14 (0x1 << 14) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P15 (0x1 << 15) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P16 (0x1 << 16) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P17 (0x1 << 17) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P18 (0x1 << 18) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P19 (0x1 << 19) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P20 (0x1 << 20) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P21 (0x1 << 21) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P22 (0x1 << 22) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P23 (0x1 << 23) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P24 (0x1 << 24) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P25 (0x1 << 25) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P26 (0x1 << 26) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P27 (0x1 << 27) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P28 (0x1 << 28) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P29 (0x1 << 29) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P30 (0x1 << 30) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P31 (0x1 << 31) /**< \brief (PIO_OWDR) Output Write Disable. */
-/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */
-#define PIO_OWSR_P0 (0x1 << 0) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P1 (0x1 << 1) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P2 (0x1 << 2) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P3 (0x1 << 3) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P4 (0x1 << 4) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P5 (0x1 << 5) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P6 (0x1 << 6) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P7 (0x1 << 7) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P8 (0x1 << 8) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P9 (0x1 << 9) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P10 (0x1 << 10) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P11 (0x1 << 11) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P12 (0x1 << 12) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P13 (0x1 << 13) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P14 (0x1 << 14) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P15 (0x1 << 15) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P16 (0x1 << 16) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P17 (0x1 << 17) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P18 (0x1 << 18) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P19 (0x1 << 19) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P20 (0x1 << 20) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P21 (0x1 << 21) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P22 (0x1 << 22) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P23 (0x1 << 23) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P24 (0x1 << 24) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P25 (0x1 << 25) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P26 (0x1 << 26) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P27 (0x1 << 27) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P28 (0x1 << 28) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P29 (0x1 << 29) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P30 (0x1 << 30) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P31 (0x1 << 31) /**< \brief (PIO_OWSR) Output Write Status. */
-/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */
-#define PIO_AIMER_P0 (0x1 << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P1 (0x1 << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P2 (0x1 << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P3 (0x1 << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P4 (0x1 << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P5 (0x1 << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P6 (0x1 << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P7 (0x1 << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P8 (0x1 << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P9 (0x1 << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P10 (0x1 << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P11 (0x1 << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P12 (0x1 << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P13 (0x1 << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P14 (0x1 << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P15 (0x1 << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P16 (0x1 << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P17 (0x1 << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P18 (0x1 << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P19 (0x1 << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P20 (0x1 << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P21 (0x1 << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P22 (0x1 << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P23 (0x1 << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P24 (0x1 << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P25 (0x1 << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P26 (0x1 << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P27 (0x1 << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P28 (0x1 << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P29 (0x1 << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P30 (0x1 << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P31 (0x1 << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */
-#define PIO_AIMDR_P0 (0x1 << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P1 (0x1 << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P2 (0x1 << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P3 (0x1 << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P4 (0x1 << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P5 (0x1 << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P6 (0x1 << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P7 (0x1 << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P8 (0x1 << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P9 (0x1 << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P10 (0x1 << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P11 (0x1 << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P12 (0x1 << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P13 (0x1 << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P14 (0x1 << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P15 (0x1 << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P16 (0x1 << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P17 (0x1 << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P18 (0x1 << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P19 (0x1 << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P20 (0x1 << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P21 (0x1 << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P22 (0x1 << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P23 (0x1 << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P24 (0x1 << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P25 (0x1 << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P26 (0x1 << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P27 (0x1 << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P28 (0x1 << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P29 (0x1 << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P30 (0x1 << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P31 (0x1 << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */
-#define PIO_AIMMR_P0 (0x1 << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P1 (0x1 << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P2 (0x1 << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P3 (0x1 << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P4 (0x1 << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P5 (0x1 << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P6 (0x1 << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P7 (0x1 << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P8 (0x1 << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P9 (0x1 << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P10 (0x1 << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P11 (0x1 << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P12 (0x1 << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P13 (0x1 << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P14 (0x1 << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P15 (0x1 << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P16 (0x1 << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P17 (0x1 << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P18 (0x1 << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P19 (0x1 << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P20 (0x1 << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P21 (0x1 << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P22 (0x1 << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P23 (0x1 << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P24 (0x1 << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P25 (0x1 << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P26 (0x1 << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P27 (0x1 << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P28 (0x1 << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P29 (0x1 << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P30 (0x1 << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P31 (0x1 << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */
-#define PIO_ESR_P0 (0x1 << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P1 (0x1 << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P2 (0x1 << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P3 (0x1 << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P4 (0x1 << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P5 (0x1 << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P6 (0x1 << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P7 (0x1 << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P8 (0x1 << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P9 (0x1 << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P10 (0x1 << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P11 (0x1 << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P12 (0x1 << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P13 (0x1 << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P14 (0x1 << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P15 (0x1 << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P16 (0x1 << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P17 (0x1 << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P18 (0x1 << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P19 (0x1 << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P20 (0x1 << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P21 (0x1 << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P22 (0x1 << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P23 (0x1 << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P24 (0x1 << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P25 (0x1 << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P26 (0x1 << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P27 (0x1 << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P28 (0x1 << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P29 (0x1 << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P30 (0x1 << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P31 (0x1 << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */
-#define PIO_LSR_P0 (0x1 << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P1 (0x1 << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P2 (0x1 << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P3 (0x1 << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P4 (0x1 << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P5 (0x1 << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P6 (0x1 << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P7 (0x1 << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P8 (0x1 << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P9 (0x1 << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P10 (0x1 << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P11 (0x1 << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P12 (0x1 << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P13 (0x1 << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P14 (0x1 << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P15 (0x1 << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P16 (0x1 << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P17 (0x1 << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P18 (0x1 << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P19 (0x1 << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P20 (0x1 << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P21 (0x1 << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P22 (0x1 << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P23 (0x1 << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P24 (0x1 << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P25 (0x1 << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P26 (0x1 << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P27 (0x1 << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P28 (0x1 << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P29 (0x1 << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P30 (0x1 << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P31 (0x1 << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */
-#define PIO_ELSR_P0 (0x1 << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P1 (0x1 << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P2 (0x1 << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P3 (0x1 << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P4 (0x1 << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P5 (0x1 << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P6 (0x1 << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P7 (0x1 << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P8 (0x1 << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P9 (0x1 << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P10 (0x1 << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P11 (0x1 << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P12 (0x1 << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P13 (0x1 << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P14 (0x1 << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P15 (0x1 << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P16 (0x1 << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P17 (0x1 << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P18 (0x1 << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P19 (0x1 << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P20 (0x1 << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P21 (0x1 << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P22 (0x1 << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P23 (0x1 << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P24 (0x1 << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P25 (0x1 << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P26 (0x1 << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P27 (0x1 << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P28 (0x1 << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P29 (0x1 << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P30 (0x1 << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P31 (0x1 << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */
-#define PIO_FELLSR_P0 (0x1 << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P1 (0x1 << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P2 (0x1 << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P3 (0x1 << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P4 (0x1 << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P5 (0x1 << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P6 (0x1 << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P7 (0x1 << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P8 (0x1 << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P9 (0x1 << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P10 (0x1 << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P11 (0x1 << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P12 (0x1 << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P13 (0x1 << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P14 (0x1 << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P15 (0x1 << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P16 (0x1 << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P17 (0x1 << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P18 (0x1 << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P19 (0x1 << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P20 (0x1 << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P21 (0x1 << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P22 (0x1 << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P23 (0x1 << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P24 (0x1 << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P25 (0x1 << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P26 (0x1 << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P27 (0x1 << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P28 (0x1 << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P29 (0x1 << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P30 (0x1 << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P31 (0x1 << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */
-#define PIO_REHLSR_P0 (0x1 << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P1 (0x1 << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P2 (0x1 << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P3 (0x1 << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P4 (0x1 << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P5 (0x1 << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P6 (0x1 << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P7 (0x1 << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P8 (0x1 << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P9 (0x1 << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P10 (0x1 << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P11 (0x1 << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P12 (0x1 << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P13 (0x1 << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P14 (0x1 << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P15 (0x1 << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P16 (0x1 << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P17 (0x1 << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P18 (0x1 << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P19 (0x1 << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P20 (0x1 << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P21 (0x1 << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P22 (0x1 << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P23 (0x1 << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P24 (0x1 << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P25 (0x1 << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P26 (0x1 << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P27 (0x1 << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P28 (0x1 << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P29 (0x1 << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P30 (0x1 << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P31 (0x1 << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */
-#define PIO_FRLHSR_P0 (0x1 << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P1 (0x1 << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P2 (0x1 << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P3 (0x1 << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P4 (0x1 << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P5 (0x1 << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P6 (0x1 << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P7 (0x1 << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P8 (0x1 << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P9 (0x1 << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P10 (0x1 << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P11 (0x1 << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P12 (0x1 << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P13 (0x1 << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P14 (0x1 << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P15 (0x1 << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P16 (0x1 << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P17 (0x1 << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P18 (0x1 << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P19 (0x1 << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P20 (0x1 << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P21 (0x1 << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P22 (0x1 << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P23 (0x1 << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P24 (0x1 << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P25 (0x1 << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P26 (0x1 << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P27 (0x1 << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P28 (0x1 << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P29 (0x1 << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P30 (0x1 << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P31 (0x1 << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */
-#define PIO_LOCKSR_P0 (0x1 << 0) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P1 (0x1 << 1) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P2 (0x1 << 2) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P3 (0x1 << 3) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P4 (0x1 << 4) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P5 (0x1 << 5) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P6 (0x1 << 6) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P7 (0x1 << 7) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P8 (0x1 << 8) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P9 (0x1 << 9) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P10 (0x1 << 10) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P11 (0x1 << 11) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P12 (0x1 << 12) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P13 (0x1 << 13) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P14 (0x1 << 14) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P15 (0x1 << 15) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P16 (0x1 << 16) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P17 (0x1 << 17) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P18 (0x1 << 18) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P19 (0x1 << 19) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P20 (0x1 << 20) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P21 (0x1 << 21) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P22 (0x1 << 22) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P23 (0x1 << 23) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P24 (0x1 << 24) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P25 (0x1 << 25) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P26 (0x1 << 26) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P27 (0x1 << 27) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P28 (0x1 << 28) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P29 (0x1 << 29) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P30 (0x1 << 30) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P31 (0x1 << 31) /**< \brief (PIO_LOCKSR) Lock Status. */
-/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */
-#define PIO_WPMR_WPEN (0x1 << 0) /**< \brief (PIO_WPMR) Write Protect Enable */
-#define PIO_WPMR_WPKEY (0xffffff << 8) /**< \brief (PIO_WPMR) Write Protect KEY */
-/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */
-#define PIO_WPSR_WPVS (0x1 << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */
-#define PIO_WPSR_WPVSRC (0xffff << 8) /**< \brief (PIO_WPSR) Write Protect Violation Source */
-/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */
-#define PIO_SCHMITT_SCHMITT0 (0x1 << 0) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT1 (0x1 << 1) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT2 (0x1 << 2) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT3 (0x1 << 3) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT4 (0x1 << 4) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT5 (0x1 << 5) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT6 (0x1 << 6) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT7 (0x1 << 7) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT8 (0x1 << 8) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT9 (0x1 << 9) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT10 (0x1 << 10) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT11 (0x1 << 11) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT12 (0x1 << 12) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT13 (0x1 << 13) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT14 (0x1 << 14) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT15 (0x1 << 15) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT16 (0x1 << 16) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT17 (0x1 << 17) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT18 (0x1 << 18) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT19 (0x1 << 19) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT20 (0x1 << 20) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT21 (0x1 << 21) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT22 (0x1 << 22) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT23 (0x1 << 23) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT24 (0x1 << 24) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT25 (0x1 << 25) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT26 (0x1 << 26) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT27 (0x1 << 27) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT28 (0x1 << 28) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT29 (0x1 << 29) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT30 (0x1 << 30) /**< \brief (PIO_SCHMITT) */
-#define PIO_SCHMITT_SCHMITT31 (0x1 << 31) /**< \brief (PIO_SCHMITT) */
-/* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */
-#define PIO_PCMR_PCEN (0x1 << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */
-#define PIO_PCMR_DSIZE (0x3 << 4) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */
-#define PIO_PCMR_ALWYS (0x1 << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */
-#define PIO_PCMR_HALFS (0x1 << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */
-#define PIO_PCMR_FRSTS (0x1 << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */
-/* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */
-#define PIO_PCIER_DRDY (0x1 << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */
-#define PIO_PCIER_OVRE (0x1 << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */
-#define PIO_PCIER_ENDRX (0x1 << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */
-#define PIO_PCIER_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */
-/* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */
-#define PIO_PCIDR_DRDY (0x1 << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */
-#define PIO_PCIDR_OVRE (0x1 << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */
-#define PIO_PCIDR_ENDRX (0x1 << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */
-#define PIO_PCIDR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */
-/* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */
-#define PIO_PCIMR_DRDY (0x1 << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */
-#define PIO_PCIMR_OVRE (0x1 << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */
-#define PIO_PCIMR_ENDRX (0x1 << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */
-#define PIO_PCIMR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */
-/* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */
-#define PIO_PCISR_DRDY (0x1 << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */
-#define PIO_PCISR_OVRE (0x1 << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */
-#define PIO_PCISR_ENDRX (0x1 << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */
-#define PIO_PCISR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */
-/* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */
-#define PIO_PCRHR_RDATA (0xffffffff << 0) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Power Management Controller */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_PMC Power Management Controller */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Pmc hardware registers */
-typedef struct {
- WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */
- WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */
- RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */
- RwReg Reserved1[1];
- WoReg PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */
- WoReg PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */
- RoReg PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */
- RwReg Reserved2[1];
- RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */
- RoReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */
- RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */
- RwReg CKGR_PLLBR; /**< \brief (Pmc Offset: 0x002C) PLLB Register */
- RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */
- RwReg Reserved3[1];
- RwReg PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */
- RwReg Reserved4[1];
- RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */
- RwReg Reserved5[5];
- WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */
- WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */
- RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */
- RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */
- RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */
- RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */
- WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */
- RwReg Reserved6[26];
- RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */
- RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */
- RwReg Reserved7[5];
- WoReg PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */
- WoReg PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */
- RoReg PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */
- RwReg Reserved8[1];
- RwReg PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */
-} Pmc;
-#endif /* __ASSEMBLY__ */
-/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
-#define PMC_SCER_UDP (0x1 << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */
-#define PMC_SCER_PCK0 (0x1 << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */
-#define PMC_SCER_PCK1 (0x1 << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */
-#define PMC_SCER_PCK2 (0x1 << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */
-/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
-#define PMC_SCDR_UDP (0x1 << 7) /**< \brief (PMC_SCDR) USB Device Port Clock Disable */
-#define PMC_SCDR_PCK0 (0x1 << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */
-#define PMC_SCDR_PCK1 (0x1 << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */
-#define PMC_SCDR_PCK2 (0x1 << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */
-/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
-#define PMC_SCSR_UDP (0x1 << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */
-#define PMC_SCSR_PCK0 (0x1 << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */
-#define PMC_SCSR_PCK1 (0x1 << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */
-#define PMC_SCSR_PCK2 (0x1 << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */
-/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
-#define PMC_PCER0_PID2 (0x1 << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */
-#define PMC_PCER0_PID3 (0x1 << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */
-#define PMC_PCER0_PID4 (0x1 << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */
-#define PMC_PCER0_PID5 (0x1 << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */
-#define PMC_PCER0_PID6 (0x1 << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */
-#define PMC_PCER0_PID7 (0x1 << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */
-#define PMC_PCER0_PID8 (0x1 << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */
-#define PMC_PCER0_PID9 (0x1 << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */
-#define PMC_PCER0_PID10 (0x1 << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */
-#define PMC_PCER0_PID11 (0x1 << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */
-#define PMC_PCER0_PID12 (0x1 << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */
-#define PMC_PCER0_PID13 (0x1 << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */
-#define PMC_PCER0_PID14 (0x1 << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */
-#define PMC_PCER0_PID15 (0x1 << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */
-#define PMC_PCER0_PID16 (0x1 << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */
-#define PMC_PCER0_PID17 (0x1 << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */
-#define PMC_PCER0_PID18 (0x1 << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */
-#define PMC_PCER0_PID19 (0x1 << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */
-#define PMC_PCER0_PID20 (0x1 << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */
-#define PMC_PCER0_PID21 (0x1 << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */
-#define PMC_PCER0_PID22 (0x1 << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */
-#define PMC_PCER0_PID23 (0x1 << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */
-#define PMC_PCER0_PID24 (0x1 << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */
-#define PMC_PCER0_PID25 (0x1 << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */
-#define PMC_PCER0_PID26 (0x1 << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */
-#define PMC_PCER0_PID27 (0x1 << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */
-#define PMC_PCER0_PID28 (0x1 << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */
-#define PMC_PCER0_PID29 (0x1 << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */
-#define PMC_PCER0_PID30 (0x1 << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */
-#define PMC_PCER0_PID31 (0x1 << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */
-/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
-#define PMC_PCDR0_PID2 (0x1 << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */
-#define PMC_PCDR0_PID3 (0x1 << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */
-#define PMC_PCDR0_PID4 (0x1 << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */
-#define PMC_PCDR0_PID5 (0x1 << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */
-#define PMC_PCDR0_PID6 (0x1 << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */
-#define PMC_PCDR0_PID7 (0x1 << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */
-#define PMC_PCDR0_PID8 (0x1 << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */
-#define PMC_PCDR0_PID9 (0x1 << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */
-#define PMC_PCDR0_PID10 (0x1 << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */
-#define PMC_PCDR0_PID11 (0x1 << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */
-#define PMC_PCDR0_PID12 (0x1 << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */
-#define PMC_PCDR0_PID13 (0x1 << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */
-#define PMC_PCDR0_PID14 (0x1 << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */
-#define PMC_PCDR0_PID15 (0x1 << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */
-#define PMC_PCDR0_PID16 (0x1 << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */
-#define PMC_PCDR0_PID17 (0x1 << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */
-#define PMC_PCDR0_PID18 (0x1 << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */
-#define PMC_PCDR0_PID19 (0x1 << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */
-#define PMC_PCDR0_PID20 (0x1 << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */
-#define PMC_PCDR0_PID21 (0x1 << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */
-#define PMC_PCDR0_PID22 (0x1 << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */
-#define PMC_PCDR0_PID23 (0x1 << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */
-#define PMC_PCDR0_PID24 (0x1 << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */
-#define PMC_PCDR0_PID25 (0x1 << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */
-#define PMC_PCDR0_PID26 (0x1 << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */
-#define PMC_PCDR0_PID27 (0x1 << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */
-#define PMC_PCDR0_PID28 (0x1 << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */
-#define PMC_PCDR0_PID29 (0x1 << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */
-#define PMC_PCDR0_PID30 (0x1 << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */
-#define PMC_PCDR0_PID31 (0x1 << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */
-/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
-#define PMC_PCSR0_PID2 (0x1 << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */
-#define PMC_PCSR0_PID3 (0x1 << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */
-#define PMC_PCSR0_PID4 (0x1 << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */
-#define PMC_PCSR0_PID5 (0x1 << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */
-#define PMC_PCSR0_PID6 (0x1 << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */
-#define PMC_PCSR0_PID7 (0x1 << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */
-#define PMC_PCSR0_PID8 (0x1 << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */
-#define PMC_PCSR0_PID9 (0x1 << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */
-#define PMC_PCSR0_PID10 (0x1 << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */
-#define PMC_PCSR0_PID11 (0x1 << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */
-#define PMC_PCSR0_PID12 (0x1 << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */
-#define PMC_PCSR0_PID13 (0x1 << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */
-#define PMC_PCSR0_PID14 (0x1 << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */
-#define PMC_PCSR0_PID15 (0x1 << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */
-#define PMC_PCSR0_PID16 (0x1 << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */
-#define PMC_PCSR0_PID17 (0x1 << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */
-#define PMC_PCSR0_PID18 (0x1 << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */
-#define PMC_PCSR0_PID19 (0x1 << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */
-#define PMC_PCSR0_PID20 (0x1 << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */
-#define PMC_PCSR0_PID21 (0x1 << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */
-#define PMC_PCSR0_PID22 (0x1 << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */
-#define PMC_PCSR0_PID23 (0x1 << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */
-#define PMC_PCSR0_PID24 (0x1 << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */
-#define PMC_PCSR0_PID25 (0x1 << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */
-#define PMC_PCSR0_PID26 (0x1 << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */
-#define PMC_PCSR0_PID27 (0x1 << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */
-#define PMC_PCSR0_PID28 (0x1 << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */
-#define PMC_PCSR0_PID29 (0x1 << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */
-#define PMC_PCSR0_PID30 (0x1 << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */
-#define PMC_PCSR0_PID31 (0x1 << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */
-/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
-#define CKGR_MOR_MOSCXTEN (0x1 << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */
-#define CKGR_MOR_MOSCXTBY (0x1 << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */
-#define CKGR_MOR_WAITMODE (0x1 << 2) /**< \brief (CKGR_MOR) Wait Mode Command */
-#define CKGR_MOR_MOSCRCEN (0x1 << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */
-#define CKGR_MOR_MOSCRCF (0x7 << 4) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */
-#define CKGR_MOR_MOSCXTST (0xff << 8) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */
-#define CKGR_MOR_KEY (0xff << 16) /**< \brief (CKGR_MOR) Password */
-#define CKGR_MOR_MOSCSEL (0x1 << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */
-#define CKGR_MOR_CFDEN (0x1 << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */
-/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
-#define CKGR_MCFR_MAINF (0xffff << 0) /**< \brief (CKGR_MCFR) Main Clock Frequency */
-#define CKGR_MCFR_MAINFRDY (0x1 << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */
-/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
-#define CKGR_PLLAR_DIVA (0xff << 0) /**< \brief (CKGR_PLLAR) Divider */
-#define CKGR_PLLAR_PLLACOUNT (0x3f << 8) /**< \brief (CKGR_PLLAR) PLLA Counter */
-#define CKGR_PLLAR_MULA (0x7ff << 16) /**< \brief (CKGR_PLLAR) PLLA Multiplier */
-#define CKGR_PLLAR_STUCKTO1 (0x1 << 29) /**< \brief (CKGR_PLLAR) */
-/* -------- CKGR_PLLBR : (PMC Offset: 0x002C) PLLB Register -------- */
-#define CKGR_PLLBR_DIVB (0xff << 0) /**< \brief (CKGR_PLLBR) Divider */
-#define CKGR_PLLBR_PLLBCOUNT (0x3f << 8) /**< \brief (CKGR_PLLBR) PLLB Counter */
-#define CKGR_PLLBR_MULB (0x7ff << 16) /**< \brief (CKGR_PLLBR) PLLB Multiplier */
-/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
-#define PMC_MCKR_CSS (0x3 << 0) /**< \brief (PMC_MCKR) Master Clock Source Selection */
-#define PMC_MCKR_CSS_SLOW_CLK (0x0 << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */
-#define PMC_MCKR_CSS_MAIN_CLK (0x1 << 0) /**< \brief (PMC_MCKR) Main Clock is selected */
-#define PMC_MCKR_CSS_PLLA_CLK (0x2 << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */
-#define PMC_MCKR_CSS_PLLB_CLK (0x3 << 0) /**< \brief (PMC_MCKR) PLLB Clock is selected */
-#define PMC_MCKR_PRES (0x7 << 4) /**< \brief (PMC_MCKR) Processor Clock Prescaler */
-#define PMC_MCKR_PRES_CLK (0x0 << 4) /**< \brief (PMC_MCKR) Selected clock */
-#define PMC_MCKR_PRES_CLK_2 (0x1 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */
-#define PMC_MCKR_PRES_CLK_4 (0x2 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */
-#define PMC_MCKR_PRES_CLK_8 (0x3 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */
-#define PMC_MCKR_PRES_CLK_16 (0x4 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */
-#define PMC_MCKR_PRES_CLK_32 (0x5 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */
-#define PMC_MCKR_PRES_CLK_64 (0x6 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */
-#define PMC_MCKR_PLLADIV2 (0x1 << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */
-#define PMC_MCKR_PLLBDIV2 (0x1 << 13) /**< \brief (PMC_MCKR) PLLB Divisor by 2 */
-/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */
-#define PMC_USB_USBS (0x1 << 0) /**< \brief (PMC_USB) USB Input Clock Selection */
-#define PMC_USB_USBDIV (0xf << 8) /**< \brief (PMC_USB) Divider for USB Clock. */
-/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
-#define PMC_PCK_CSS (0x7 << 0) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */
-#define PMC_PCK_PRES (0x7 << 4) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */
-/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
-#define PMC_IER_MOSCXTS (0x1 << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */
-#define PMC_IER_LOCKA (0x1 << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */
-#define PMC_IER_LOCKB (0x1 << 2) /**< \brief (PMC_IER) PLLB Lock Interrupt Enable */
-#define PMC_IER_MCKRDY (0x1 << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */
-#define PMC_IER_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */
-#define PMC_IER_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */
-#define PMC_IER_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */
-#define PMC_IER_MOSCSELS (0x1 << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */
-#define PMC_IER_MOSCRCS (0x1 << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */
-#define PMC_IER_CFDEV (0x1 << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */
-/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
-#define PMC_IDR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */
-#define PMC_IDR_LOCKA (0x1 << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */
-#define PMC_IDR_LOCKB (0x1 << 2) /**< \brief (PMC_IDR) PLLB Lock Interrupt Disable */
-#define PMC_IDR_MCKRDY (0x1 << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */
-#define PMC_IDR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */
-#define PMC_IDR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */
-#define PMC_IDR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */
-#define PMC_IDR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */
-#define PMC_IDR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */
-#define PMC_IDR_CFDEV (0x1 << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */
-/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
-#define PMC_SR_MOSCXTS (0x1 << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */
-#define PMC_SR_LOCKA (0x1 << 1) /**< \brief (PMC_SR) PLLA Lock Status */
-#define PMC_SR_LOCKB (0x1 << 2) /**< \brief (PMC_SR) PLLB Lock Status */
-#define PMC_SR_MCKRDY (0x1 << 3) /**< \brief (PMC_SR) Master Clock Status */
-#define PMC_SR_OSCSELS (0x1 << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */
-#define PMC_SR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */
-#define PMC_SR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */
-#define PMC_SR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */
-#define PMC_SR_MOSCSELS (0x1 << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */
-#define PMC_SR_MOSCRCS (0x1 << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */
-#define PMC_SR_CFDEV (0x1 << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */
-#define PMC_SR_CFDS (0x1 << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */
-#define PMC_SR_FOS (0x1 << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */
-/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
-#define PMC_IMR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */
-#define PMC_IMR_LOCKA (0x1 << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */
-#define PMC_IMR_LOCKB (0x1 << 2) /**< \brief (PMC_IMR) PLLB Lock Interrupt Mask */
-#define PMC_IMR_MCKRDY (0x1 << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */
-#define PMC_IMR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */
-#define PMC_IMR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */
-#define PMC_IMR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */
-#define PMC_IMR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */
-#define PMC_IMR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */
-#define PMC_IMR_CFDEV (0x1 << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */
-/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
-#define PMC_FSMR_FSTT0 (0x1 << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */
-#define PMC_FSMR_FSTT1 (0x1 << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */
-#define PMC_FSMR_FSTT2 (0x1 << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */
-#define PMC_FSMR_FSTT3 (0x1 << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */
-#define PMC_FSMR_FSTT4 (0x1 << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */
-#define PMC_FSMR_FSTT5 (0x1 << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */
-#define PMC_FSMR_FSTT6 (0x1 << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */
-#define PMC_FSMR_FSTT7 (0x1 << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */
-#define PMC_FSMR_FSTT8 (0x1 << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */
-#define PMC_FSMR_FSTT9 (0x1 << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */
-#define PMC_FSMR_FSTT10 (0x1 << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */
-#define PMC_FSMR_FSTT11 (0x1 << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */
-#define PMC_FSMR_FSTT12 (0x1 << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */
-#define PMC_FSMR_FSTT13 (0x1 << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */
-#define PMC_FSMR_FSTT14 (0x1 << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */
-#define PMC_FSMR_FSTT15 (0x1 << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */
-#define PMC_FSMR_RTTAL (0x1 << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */
-#define PMC_FSMR_RTCAL (0x1 << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */
-#define PMC_FSMR_USBAL (0x1 << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */
-#define PMC_FSMR_LPM (0x1 << 20) /**< \brief (PMC_FSMR) Low Power Mode */
-/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
-#define PMC_FSPR_FSTP0 (0x1 << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
-#define PMC_FSPR_FSTP1 (0x1 << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
-#define PMC_FSPR_FSTP2 (0x1 << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
-#define PMC_FSPR_FSTP3 (0x1 << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
-#define PMC_FSPR_FSTP4 (0x1 << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
-#define PMC_FSPR_FSTP5 (0x1 << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
-#define PMC_FSPR_FSTP6 (0x1 << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
-#define PMC_FSPR_FSTP7 (0x1 << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
-#define PMC_FSPR_FSTP8 (0x1 << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
-#define PMC_FSPR_FSTP9 (0x1 << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
-#define PMC_FSPR_FSTP10 (0x1 << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
-#define PMC_FSPR_FSTP11 (0x1 << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
-#define PMC_FSPR_FSTP12 (0x1 << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
-#define PMC_FSPR_FSTP13 (0x1 << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
-#define PMC_FSPR_FSTP14 (0x1 << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
-#define PMC_FSPR_FSTP15 (0x1 << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
-/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
-#define PMC_FOCR_FOCLR (0x1 << 0) /**< \brief (PMC_FOCR) Fault Output Clear */
-/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */
-#define PMC_WPMR_WPEN (0x1 << 0) /**< \brief (PMC_WPMR) Write Protect Enable */
-#define PMC_WPMR_WPKEY (0xffffff << 8) /**< \brief (PMC_WPMR) Write Protect KEY */
-/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */
-#define PMC_WPSR_WPVS (0x1 << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */
-#define PMC_WPSR_WPVSRC (0xffff << 8) /**< \brief (PMC_WPSR) Write Protect Violation Source */
-/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */
-#define PMC_PCER1_PID32 (0x1 << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */
-#define PMC_PCER1_PID33 (0x1 << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */
-#define PMC_PCER1_PID34 (0x1 << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */
-#define PMC_PCER1_PID35 (0x1 << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */
-#define PMC_PCER1_PID36 (0x1 << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */
-#define PMC_PCER1_PID37 (0x1 << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */
-#define PMC_PCER1_PID38 (0x1 << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */
-#define PMC_PCER1_PID39 (0x1 << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */
-#define PMC_PCER1_PID40 (0x1 << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */
-#define PMC_PCER1_PID41 (0x1 << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */
-#define PMC_PCER1_PID42 (0x1 << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */
-#define PMC_PCER1_PID43 (0x1 << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */
-#define PMC_PCER1_PID44 (0x1 << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */
-#define PMC_PCER1_PID45 (0x1 << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */
-#define PMC_PCER1_PID46 (0x1 << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */
-#define PMC_PCER1_PID47 (0x1 << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */
-#define PMC_PCER1_PID48 (0x1 << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */
-#define PMC_PCER1_PID49 (0x1 << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */
-#define PMC_PCER1_PID50 (0x1 << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */
-#define PMC_PCER1_PID51 (0x1 << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */
-#define PMC_PCER1_PID52 (0x1 << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */
-#define PMC_PCER1_PID53 (0x1 << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */
-#define PMC_PCER1_PID54 (0x1 << 22) /**< \brief (PMC_PCER1) Peripheral Clock 54 Enable */
-#define PMC_PCER1_PID55 (0x1 << 23) /**< \brief (PMC_PCER1) Peripheral Clock 55 Enable */
-#define PMC_PCER1_PID56 (0x1 << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */
-#define PMC_PCER1_PID57 (0x1 << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */
-#define PMC_PCER1_PID58 (0x1 << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */
-#define PMC_PCER1_PID59 (0x1 << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */
-#define PMC_PCER1_PID60 (0x1 << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */
-#define PMC_PCER1_PID61 (0x1 << 29) /**< \brief (PMC_PCER1) Peripheral Clock 61 Enable */
-#define PMC_PCER1_PID62 (0x1 << 30) /**< \brief (PMC_PCER1) Peripheral Clock 62 Enable */
-#define PMC_PCER1_PID63 (0x1 << 31) /**< \brief (PMC_PCER1) Peripheral Clock 63 Enable */
-/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */
-#define PMC_PCDR1_PID32 (0x1 << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */
-#define PMC_PCDR1_PID33 (0x1 << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */
-#define PMC_PCDR1_PID34 (0x1 << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */
-#define PMC_PCDR1_PID35 (0x1 << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */
-#define PMC_PCDR1_PID36 (0x1 << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */
-#define PMC_PCDR1_PID37 (0x1 << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */
-#define PMC_PCDR1_PID38 (0x1 << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */
-#define PMC_PCDR1_PID39 (0x1 << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */
-#define PMC_PCDR1_PID40 (0x1 << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */
-#define PMC_PCDR1_PID41 (0x1 << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */
-#define PMC_PCDR1_PID42 (0x1 << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */
-#define PMC_PCDR1_PID43 (0x1 << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */
-#define PMC_PCDR1_PID44 (0x1 << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */
-#define PMC_PCDR1_PID45 (0x1 << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */
-#define PMC_PCDR1_PID46 (0x1 << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */
-#define PMC_PCDR1_PID47 (0x1 << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */
-#define PMC_PCDR1_PID48 (0x1 << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */
-#define PMC_PCDR1_PID49 (0x1 << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */
-#define PMC_PCDR1_PID50 (0x1 << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */
-#define PMC_PCDR1_PID51 (0x1 << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */
-#define PMC_PCDR1_PID52 (0x1 << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */
-#define PMC_PCDR1_PID53 (0x1 << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */
-#define PMC_PCDR1_PID54 (0x1 << 22) /**< \brief (PMC_PCDR1) Peripheral Clock 54 Disable */
-#define PMC_PCDR1_PID55 (0x1 << 23) /**< \brief (PMC_PCDR1) Peripheral Clock 55 Disable */
-#define PMC_PCDR1_PID56 (0x1 << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */
-#define PMC_PCDR1_PID57 (0x1 << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */
-#define PMC_PCDR1_PID58 (0x1 << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */
-#define PMC_PCDR1_PID59 (0x1 << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */
-#define PMC_PCDR1_PID60 (0x1 << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */
-#define PMC_PCDR1_PID61 (0x1 << 29) /**< \brief (PMC_PCDR1) Peripheral Clock 61 Disable */
-#define PMC_PCDR1_PID62 (0x1 << 30) /**< \brief (PMC_PCDR1) Peripheral Clock 62 Disable */
-#define PMC_PCDR1_PID63 (0x1 << 31) /**< \brief (PMC_PCDR1) Peripheral Clock 63 Disable */
-/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */
-#define PMC_PCSR1_PID32 (0x1 << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */
-#define PMC_PCSR1_PID33 (0x1 << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */
-#define PMC_PCSR1_PID34 (0x1 << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */
-#define PMC_PCSR1_PID35 (0x1 << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */
-#define PMC_PCSR1_PID36 (0x1 << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */
-#define PMC_PCSR1_PID37 (0x1 << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */
-#define PMC_PCSR1_PID38 (0x1 << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */
-#define PMC_PCSR1_PID39 (0x1 << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */
-#define PMC_PCSR1_PID40 (0x1 << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */
-#define PMC_PCSR1_PID41 (0x1 << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */
-#define PMC_PCSR1_PID42 (0x1 << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */
-#define PMC_PCSR1_PID43 (0x1 << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */
-#define PMC_PCSR1_PID44 (0x1 << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */
-#define PMC_PCSR1_PID45 (0x1 << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */
-#define PMC_PCSR1_PID46 (0x1 << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */
-#define PMC_PCSR1_PID47 (0x1 << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */
-#define PMC_PCSR1_PID48 (0x1 << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */
-#define PMC_PCSR1_PID49 (0x1 << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */
-#define PMC_PCSR1_PID50 (0x1 << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */
-#define PMC_PCSR1_PID51 (0x1 << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */
-#define PMC_PCSR1_PID52 (0x1 << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */
-#define PMC_PCSR1_PID53 (0x1 << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */
-#define PMC_PCSR1_PID54 (0x1 << 22) /**< \brief (PMC_PCSR1) Peripheral Clock 54 Status */
-#define PMC_PCSR1_PID55 (0x1 << 23) /**< \brief (PMC_PCSR1) Peripheral Clock 55 Status */
-#define PMC_PCSR1_PID56 (0x1 << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */
-#define PMC_PCSR1_PID57 (0x1 << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */
-#define PMC_PCSR1_PID58 (0x1 << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */
-#define PMC_PCSR1_PID59 (0x1 << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */
-#define PMC_PCSR1_PID60 (0x1 << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */
-#define PMC_PCSR1_PID61 (0x1 << 29) /**< \brief (PMC_PCSR1) Peripheral Clock 61 Status */
-#define PMC_PCSR1_PID62 (0x1 << 30) /**< \brief (PMC_PCSR1) Peripheral Clock 62 Status */
-#define PMC_PCSR1_PID63 (0x1 << 31) /**< \brief (PMC_PCSR1) Peripheral Clock 63 Status */
-/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */
-#define PMC_OCR_CAL4 (0x7f << 0) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 Mhz */
-#define PMC_OCR_SEL4 (0x1 << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 Mhz */
-#define PMC_OCR_CAL8 (0x7f << 8) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 Mhz */
-#define PMC_OCR_SEL8 (0x1 << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 Mhz */
-#define PMC_OCR_CAL12 (0x7f << 16) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 Mhz */
-#define PMC_OCR_SEL12 (0x1 << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 Mhz */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_PWM Pulse Width Modulation Controller */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief PwmCh_num hardware registers */
-typedef struct {
- RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */
- RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */
- RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */
- RwReg PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */
- RwReg PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */
- RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */
- RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */
- RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */
-} PwmCh_num;
-/** \brief Pwm hardware registers */
-typedef struct {
- RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */
- WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */
- WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */
- RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */
- WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */
- WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */
- RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */
- RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */
- RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */
- RwReg Reserved1[1];
- RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */
- RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */
- WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */
- WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */
- WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */
- RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */
- RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */
- RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */
- RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */
- WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */
- WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */
- WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */
- WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */
- RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */
- RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */
- WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */
- RwReg PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */
- RwReg PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */
- RwReg Reserved2[3];
- RwReg PWM_ELxMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */
- RwReg Reserved3[11];
- RwReg PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */
- RwReg Reserved4[12];
- WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */
- RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */
- RwReg Reserved5[5];
- RwReg PWM_RPR; /**< \brief (Pwm Offset: 0x100) Receive Pointer Register */
- RwReg PWM_RCR; /**< \brief (Pwm Offset: 0x104) Receive Counter Register */
- RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */
- RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */
- RwReg PWM_RNPR; /**< \brief (Pwm Offset: 0x110) Receive Next Pointer Register */
- RwReg PWM_RNCR; /**< \brief (Pwm Offset: 0x114) Receive Next Counter Register */
- RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */
- RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */
- WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */
- RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */
- RwReg Reserved6[2];
- RwReg PWM_CMP0V; /**< \brief (Pwm Offset: 0x130) PWM Comparison 0 Value Register */
- WoReg PWM_CMP0VUPD; /**< \brief (Pwm Offset: 0x134) PWM Comparison 0 Value Update Register */
- RwReg PWM_CMP0M; /**< \brief (Pwm Offset: 0x138) PWM Comparison 0 Mode Register */
- WoReg PWM_CMP0MUPD; /**< \brief (Pwm Offset: 0x13C) PWM Comparison 0 Mode Update Register */
- RwReg PWM_CMP1V; /**< \brief (Pwm Offset: 0x140) PWM Comparison 1 Value Register */
- WoReg PWM_CMP1VUPD; /**< \brief (Pwm Offset: 0x144) PWM Comparison 1 Value Update Register */
- RwReg PWM_CMP1M; /**< \brief (Pwm Offset: 0x148) PWM Comparison 1 Mode Register */
- WoReg PWM_CMP1MUPD; /**< \brief (Pwm Offset: 0x14C) PWM Comparison 1 Mode Update Register */
- RwReg PWM_CMP2V; /**< \brief (Pwm Offset: 0x150) PWM Comparison 2 Value Register */
- WoReg PWM_CMP2VUPD; /**< \brief (Pwm Offset: 0x154) PWM Comparison 2 Value Update Register */
- RwReg PWM_CMP2M; /**< \brief (Pwm Offset: 0x158) PWM Comparison 2 Mode Register */
- WoReg PWM_CMP2MUPD; /**< \brief (Pwm Offset: 0x15C) PWM Comparison 2 Mode Update Register */
- RwReg PWM_CMP3V; /**< \brief (Pwm Offset: 0x160) PWM Comparison 3 Value Register */
- WoReg PWM_CMP3VUPD; /**< \brief (Pwm Offset: 0x164) PWM Comparison 3 Value Update Register */
- RwReg PWM_CMP3M; /**< \brief (Pwm Offset: 0x168) PWM Comparison 3 Mode Register */
- WoReg PWM_CMP3MUPD; /**< \brief (Pwm Offset: 0x16C) PWM Comparison 3 Mode Update Register */
- RwReg PWM_CMP4V; /**< \brief (Pwm Offset: 0x170) PWM Comparison 4 Value Register */
- WoReg PWM_CMP4VUPD; /**< \brief (Pwm Offset: 0x174) PWM Comparison 4 Value Update Register */
- RwReg PWM_CMP4M; /**< \brief (Pwm Offset: 0x178) PWM Comparison 4 Mode Register */
- WoReg PWM_CMP4MUPD; /**< \brief (Pwm Offset: 0x17C) PWM Comparison 4 Mode Update Register */
- RwReg PWM_CMP5V; /**< \brief (Pwm Offset: 0x180) PWM Comparison 5 Value Register */
- WoReg PWM_CMP5VUPD; /**< \brief (Pwm Offset: 0x184) PWM Comparison 5 Value Update Register */
- RwReg PWM_CMP5M; /**< \brief (Pwm Offset: 0x188) PWM Comparison 5 Mode Register */
- WoReg PWM_CMP5MUPD; /**< \brief (Pwm Offset: 0x18C) PWM Comparison 5 Mode Update Register */
- RwReg PWM_CMP6V; /**< \brief (Pwm Offset: 0x190) PWM Comparison 6 Value Register */
- WoReg PWM_CMP6VUPD; /**< \brief (Pwm Offset: 0x194) PWM Comparison 6 Value Update Register */
- RwReg PWM_CMP6M; /**< \brief (Pwm Offset: 0x198) PWM Comparison 6 Mode Register */
- WoReg PWM_CMP6MUPD; /**< \brief (Pwm Offset: 0x19C) PWM Comparison 6 Mode Update Register */
- RwReg PWM_CMP7V; /**< \brief (Pwm Offset: 0x1A0) PWM Comparison 7 Value Register */
- WoReg PWM_CMP7VUPD; /**< \brief (Pwm Offset: 0x1A4) PWM Comparison 7 Value Update Register */
- RwReg PWM_CMP7M; /**< \brief (Pwm Offset: 0x1A8) PWM Comparison 7 Mode Register */
- WoReg PWM_CMP7MUPD; /**< \brief (Pwm Offset: 0x1AC) PWM Comparison 7 Mode Update Register */
- RwReg Reserved7[20];
- PwmCh_num PWM_CH_NUM[4]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */
-} Pwm;
-#endif /* __ASSEMBLY__ */
-/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */
-#define PWM_CLK_DIVA (0xff << 0) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
-#define PWM_CLK_PREA (0xf << 8) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
-#define PWM_CLK_DIVB (0xff << 16) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
-#define PWM_CLK_PREB (0xf << 24) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
-/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
-#define PWM_ENA_CHID0 (0x1 << 0) /**< \brief (PWM_ENA) Channel ID */
-#define PWM_ENA_CHID1 (0x1 << 1) /**< \brief (PWM_ENA) Channel ID */
-#define PWM_ENA_CHID2 (0x1 << 2) /**< \brief (PWM_ENA) Channel ID */
-#define PWM_ENA_CHID3 (0x1 << 3) /**< \brief (PWM_ENA) Channel ID */
-/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
-#define PWM_DIS_CHID0 (0x1 << 0) /**< \brief (PWM_DIS) Channel ID */
-#define PWM_DIS_CHID1 (0x1 << 1) /**< \brief (PWM_DIS) Channel ID */
-#define PWM_DIS_CHID2 (0x1 << 2) /**< \brief (PWM_DIS) Channel ID */
-#define PWM_DIS_CHID3 (0x1 << 3) /**< \brief (PWM_DIS) Channel ID */
-/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
-#define PWM_SR_CHID0 (0x1 << 0) /**< \brief (PWM_SR) Channel ID */
-#define PWM_SR_CHID1 (0x1 << 1) /**< \brief (PWM_SR) Channel ID */
-#define PWM_SR_CHID2 (0x1 << 2) /**< \brief (PWM_SR) Channel ID */
-#define PWM_SR_CHID3 (0x1 << 3) /**< \brief (PWM_SR) Channel ID */
-/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */
-#define PWM_IER1_CHID0 (0x1 << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */
-#define PWM_IER1_CHID1 (0x1 << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */
-#define PWM_IER1_CHID2 (0x1 << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */
-#define PWM_IER1_CHID3 (0x1 << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */
-#define PWM_IER1_FCHID0 (0x1 << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */
-#define PWM_IER1_FCHID1 (0x1 << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */
-#define PWM_IER1_FCHID2 (0x1 << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */
-#define PWM_IER1_FCHID3 (0x1 << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */
-/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */
-#define PWM_IDR1_CHID0 (0x1 << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */
-#define PWM_IDR1_CHID1 (0x1 << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */
-#define PWM_IDR1_CHID2 (0x1 << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */
-#define PWM_IDR1_CHID3 (0x1 << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */
-#define PWM_IDR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */
-#define PWM_IDR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */
-#define PWM_IDR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */
-#define PWM_IDR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */
-/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */
-#define PWM_IMR1_CHID0 (0x1 << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */
-#define PWM_IMR1_CHID1 (0x1 << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */
-#define PWM_IMR1_CHID2 (0x1 << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */
-#define PWM_IMR1_CHID3 (0x1 << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */
-#define PWM_IMR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */
-#define PWM_IMR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */
-#define PWM_IMR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */
-#define PWM_IMR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */
-/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */
-#define PWM_ISR1_CHID0 (0x1 << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */
-#define PWM_ISR1_CHID1 (0x1 << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */
-#define PWM_ISR1_CHID2 (0x1 << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */
-#define PWM_ISR1_CHID3 (0x1 << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */
-#define PWM_ISR1_FCHID0 (0x1 << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */
-#define PWM_ISR1_FCHID1 (0x1 << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */
-#define PWM_ISR1_FCHID2 (0x1 << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */
-#define PWM_ISR1_FCHID3 (0x1 << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */
-/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */
-#define PWM_SCM_SYNC0 (0x1 << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */
-#define PWM_SCM_SYNC1 (0x1 << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */
-#define PWM_SCM_SYNC2 (0x1 << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */
-#define PWM_SCM_SYNC3 (0x1 << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */
-#define PWM_SCM_UPDM (0x3 << 16) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */
-#define PWM_SCM_PTRM (0x1 << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */
-#define PWM_SCM_PTRCS (0x7 << 21) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */
-/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */
-#define PWM_SCUC_UPDULOCK (0x1 << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */
-/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */
-#define PWM_SCUP_UPR (0xf << 0) /**< \brief (PWM_SCUP) Update Period */
-#define PWM_SCUP_UPRCNT (0xf << 4) /**< \brief (PWM_SCUP) Update Period Counter */
-/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */
-#define PWM_SCUPUPD_UPRUPD (0xf << 0) /**< \brief (PWM_SCUPUPD) Update Period Update */
-/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */
-#define PWM_IER2_WRDY (0x1 << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */
-#define PWM_IER2_ENDTX (0x1 << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */
-#define PWM_IER2_TXBUFE (0x1 << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */
-#define PWM_IER2_UNRE (0x1 << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */
-#define PWM_IER2_CMPM0 (0x1 << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */
-#define PWM_IER2_CMPM1 (0x1 << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */
-#define PWM_IER2_CMPM2 (0x1 << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */
-#define PWM_IER2_CMPM3 (0x1 << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */
-#define PWM_IER2_CMPM4 (0x1 << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */
-#define PWM_IER2_CMPM5 (0x1 << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */
-#define PWM_IER2_CMPM6 (0x1 << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */
-#define PWM_IER2_CMPM7 (0x1 << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */
-#define PWM_IER2_CMPU0 (0x1 << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */
-#define PWM_IER2_CMPU1 (0x1 << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */
-#define PWM_IER2_CMPU2 (0x1 << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */
-#define PWM_IER2_CMPU3 (0x1 << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */
-#define PWM_IER2_CMPU4 (0x1 << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */
-#define PWM_IER2_CMPU5 (0x1 << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */
-#define PWM_IER2_CMPU6 (0x1 << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */
-#define PWM_IER2_CMPU7 (0x1 << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */
-/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */
-#define PWM_IDR2_WRDY (0x1 << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */
-#define PWM_IDR2_ENDTX (0x1 << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */
-#define PWM_IDR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */
-#define PWM_IDR2_UNRE (0x1 << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */
-#define PWM_IDR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */
-#define PWM_IDR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */
-#define PWM_IDR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */
-#define PWM_IDR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */
-#define PWM_IDR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */
-#define PWM_IDR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */
-#define PWM_IDR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */
-#define PWM_IDR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */
-#define PWM_IDR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */
-#define PWM_IDR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */
-#define PWM_IDR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */
-#define PWM_IDR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */
-#define PWM_IDR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */
-#define PWM_IDR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */
-#define PWM_IDR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */
-#define PWM_IDR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */
-/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */
-#define PWM_IMR2_WRDY (0x1 << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */
-#define PWM_IMR2_ENDTX (0x1 << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */
-#define PWM_IMR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */
-#define PWM_IMR2_UNRE (0x1 << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */
-#define PWM_IMR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */
-#define PWM_IMR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */
-#define PWM_IMR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */
-#define PWM_IMR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */
-#define PWM_IMR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */
-#define PWM_IMR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */
-#define PWM_IMR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */
-#define PWM_IMR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */
-#define PWM_IMR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */
-#define PWM_IMR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */
-#define PWM_IMR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */
-#define PWM_IMR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */
-#define PWM_IMR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */
-#define PWM_IMR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */
-#define PWM_IMR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */
-#define PWM_IMR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */
-/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */
-#define PWM_ISR2_WRDY (0x1 << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */
-#define PWM_ISR2_ENDTX (0x1 << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */
-#define PWM_ISR2_TXBUFE (0x1 << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */
-#define PWM_ISR2_UNRE (0x1 << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */
-#define PWM_ISR2_CMPM0 (0x1 << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */
-#define PWM_ISR2_CMPM1 (0x1 << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */
-#define PWM_ISR2_CMPM2 (0x1 << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */
-#define PWM_ISR2_CMPM3 (0x1 << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */
-#define PWM_ISR2_CMPM4 (0x1 << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */
-#define PWM_ISR2_CMPM5 (0x1 << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */
-#define PWM_ISR2_CMPM6 (0x1 << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */
-#define PWM_ISR2_CMPM7 (0x1 << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */
-#define PWM_ISR2_CMPU0 (0x1 << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */
-#define PWM_ISR2_CMPU1 (0x1 << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */
-#define PWM_ISR2_CMPU2 (0x1 << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */
-#define PWM_ISR2_CMPU3 (0x1 << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */
-#define PWM_ISR2_CMPU4 (0x1 << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */
-#define PWM_ISR2_CMPU5 (0x1 << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */
-#define PWM_ISR2_CMPU6 (0x1 << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */
-#define PWM_ISR2_CMPU7 (0x1 << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */
-/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */
-#define PWM_OOV_OOVH0 (0x1 << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */
-#define PWM_OOV_OOVH1 (0x1 << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */
-#define PWM_OOV_OOVH2 (0x1 << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */
-#define PWM_OOV_OOVH3 (0x1 << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */
-#define PWM_OOV_OOVL0 (0x1 << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */
-#define PWM_OOV_OOVL1 (0x1 << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */
-#define PWM_OOV_OOVL2 (0x1 << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */
-#define PWM_OOV_OOVL3 (0x1 << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */
-/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */
-#define PWM_OS_OSH0 (0x1 << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */
-#define PWM_OS_OSH1 (0x1 << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */
-#define PWM_OS_OSH2 (0x1 << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */
-#define PWM_OS_OSH3 (0x1 << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */
-#define PWM_OS_OSL0 (0x1 << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */
-#define PWM_OS_OSL1 (0x1 << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */
-#define PWM_OS_OSL2 (0x1 << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */
-#define PWM_OS_OSL3 (0x1 << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */
-/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */
-#define PWM_OSS_OSSH0 (0x1 << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */
-#define PWM_OSS_OSSH1 (0x1 << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */
-#define PWM_OSS_OSSH2 (0x1 << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */
-#define PWM_OSS_OSSH3 (0x1 << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */
-#define PWM_OSS_OSSL0 (0x1 << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */
-#define PWM_OSS_OSSL1 (0x1 << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */
-#define PWM_OSS_OSSL2 (0x1 << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */
-#define PWM_OSS_OSSL3 (0x1 << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */
-/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */
-#define PWM_OSC_OSCH0 (0x1 << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */
-#define PWM_OSC_OSCH1 (0x1 << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */
-#define PWM_OSC_OSCH2 (0x1 << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */
-#define PWM_OSC_OSCH3 (0x1 << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */
-#define PWM_OSC_OSCL0 (0x1 << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */
-#define PWM_OSC_OSCL1 (0x1 << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */
-#define PWM_OSC_OSCL2 (0x1 << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */
-#define PWM_OSC_OSCL3 (0x1 << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */
-/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */
-#define PWM_OSSUPD_OSSUPH0 (0x1 << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */
-#define PWM_OSSUPD_OSSUPH1 (0x1 << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */
-#define PWM_OSSUPD_OSSUPH2 (0x1 << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */
-#define PWM_OSSUPD_OSSUPH3 (0x1 << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */
-#define PWM_OSSUPD_OSSUPL0 (0x1 << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */
-#define PWM_OSSUPD_OSSUPL1 (0x1 << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */
-#define PWM_OSSUPD_OSSUPL2 (0x1 << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */
-#define PWM_OSSUPD_OSSUPL3 (0x1 << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */
-/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */
-#define PWM_OSCUPD_OSCUPH0 (0x1 << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */
-#define PWM_OSCUPD_OSCUPH1 (0x1 << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */
-#define PWM_OSCUPD_OSCUPH2 (0x1 << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */
-#define PWM_OSCUPD_OSCUPH3 (0x1 << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */
-#define PWM_OSCUPD_OSCUPL0 (0x1 << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */
-#define PWM_OSCUPD_OSCUPL1 (0x1 << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */
-#define PWM_OSCUPD_OSCUPL2 (0x1 << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */
-#define PWM_OSCUPD_OSCUPL3 (0x1 << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */
-/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */
-#define PWM_FMR_FPOL0 (0x1 << 0) /**< \brief (PWM_FMR) Fault 0 Polarity */
-#define PWM_FMR_FPOL1 (0x1 << 1) /**< \brief (PWM_FMR) Fault 1 Polarity */
-#define PWM_FMR_FPOL2 (0x1 << 2) /**< \brief (PWM_FMR) Fault 2 Polarity */
-#define PWM_FMR_FPOL3 (0x1 << 3) /**< \brief (PWM_FMR) Fault 3 Polarity */
-#define PWM_FMR_FMOD0 (0x1 << 8) /**< \brief (PWM_FMR) Fault 0 Activation Mode */
-#define PWM_FMR_FMOD1 (0x1 << 9) /**< \brief (PWM_FMR) Fault 1 Activation Mode */
-#define PWM_FMR_FMOD2 (0x1 << 10) /**< \brief (PWM_FMR) Fault 2 Activation Mode */
-#define PWM_FMR_FMOD3 (0x1 << 11) /**< \brief (PWM_FMR) Fault 3 Activation Mode */
-#define PWM_FMR_FFIL0 (0x1 << 16) /**< \brief (PWM_FMR) Fault 0 Filtering */
-#define PWM_FMR_FFIL1 (0x1 << 17) /**< \brief (PWM_FMR) Fault 1 Filtering */
-#define PWM_FMR_FFIL2 (0x1 << 18) /**< \brief (PWM_FMR) Fault 2 Filtering */
-#define PWM_FMR_FFIL3 (0x1 << 19) /**< \brief (PWM_FMR) Fault 3 Filtering */
-/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */
-#define PWM_FSR_FIV0 (0x1 << 0) /**< \brief (PWM_FSR) Fault Input 0 Value */
-#define PWM_FSR_FIV1 (0x1 << 1) /**< \brief (PWM_FSR) Fault Input 1 Value */
-#define PWM_FSR_FIV2 (0x1 << 2) /**< \brief (PWM_FSR) Fault Input 2 Value */
-#define PWM_FSR_FIV3 (0x1 << 3) /**< \brief (PWM_FSR) Fault Input 3 Value */
-#define PWM_FSR_FS0 (0x1 << 8) /**< \brief (PWM_FSR) Fault 0 Status */
-#define PWM_FSR_FS1 (0x1 << 9) /**< \brief (PWM_FSR) Fault 1 Status */
-#define PWM_FSR_FS2 (0x1 << 10) /**< \brief (PWM_FSR) Fault 2 Status */
-#define PWM_FSR_FS3 (0x1 << 11) /**< \brief (PWM_FSR) Fault 3 Status */
-/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */
-#define PWM_FCR_FCLR0 (0x1 << 0) /**< \brief (PWM_FCR) Fault 0 Clear */
-#define PWM_FCR_FCLR1 (0x1 << 1) /**< \brief (PWM_FCR) Fault 1 Clear */
-#define PWM_FCR_FCLR2 (0x1 << 2) /**< \brief (PWM_FCR) Fault 2 Clear */
-#define PWM_FCR_FCLR3 (0x1 << 3) /**< \brief (PWM_FCR) Fault 3 Clear */
-/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */
-#define PWM_FPV_FPVH0 (0x1 << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */
-#define PWM_FPV_FPVH1 (0x1 << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */
-#define PWM_FPV_FPVH2 (0x1 << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */
-#define PWM_FPV_FPVH3 (0x1 << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */
-#define PWM_FPV_FPVL0 (0x1 << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */
-#define PWM_FPV_FPVL1 (0x1 << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */
-#define PWM_FPV_FPVL2 (0x1 << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */
-#define PWM_FPV_FPVL3 (0x1 << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */
-/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */
-#define PWM_FPE_FPE0 (0xff << 0) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 0 for channel x */
-#define PWM_FPE_FPE1 (0xff << 8) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 1 for channel x */
-#define PWM_FPE_FPE2 (0xff << 16) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 2 for channel x */
-#define PWM_FPE_FPE3 (0xff << 24) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 3 for channel x */
-/* -------- PWM_ELxMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */
-#define PWM_ELxMR_CSEL0 (0x1 << 0) /**< \brief (PWM_ELxMR[2]) Comparison 0 Selection */
-#define PWM_ELxMR_CSEL1 (0x1 << 1) /**< \brief (PWM_ELxMR[2]) Comparison 1 Selection */
-#define PWM_ELxMR_CSEL2 (0x1 << 2) /**< \brief (PWM_ELxMR[2]) Comparison 2 Selection */
-#define PWM_ELxMR_CSEL3 (0x1 << 3) /**< \brief (PWM_ELxMR[2]) Comparison 3 Selection */
-#define PWM_ELxMR_CSEL4 (0x1 << 4) /**< \brief (PWM_ELxMR[2]) Comparison 4 Selection */
-#define PWM_ELxMR_CSEL5 (0x1 << 5) /**< \brief (PWM_ELxMR[2]) Comparison 5 Selection */
-#define PWM_ELxMR_CSEL6 (0x1 << 6) /**< \brief (PWM_ELxMR[2]) Comparison 6 Selection */
-#define PWM_ELxMR_CSEL7 (0x1 << 7) /**< \brief (PWM_ELxMR[2]) Comparison 7 Selection */
-/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */
-#define PWM_SMMR_GCEN0 (0x1 << 0) /**< \brief (PWM_SMMR) Gray Count ENable */
-#define PWM_SMMR_GCEN1 (0x1 << 1) /**< \brief (PWM_SMMR) Gray Count ENable */
-#define PWM_SMMR_DOWN0 (0x1 << 16) /**< \brief (PWM_SMMR) DOWN Count */
-#define PWM_SMMR_DOWN1 (0x1 << 17) /**< \brief (PWM_SMMR) DOWN Count */
-/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */
-#define PWM_WPCR_WPCMD (0x3 << 0) /**< \brief (PWM_WPCR) Write Protect Command */
-#define PWM_WPCR_WPRG0 (0x1 << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */
-#define PWM_WPCR_WPRG1 (0x1 << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */
-#define PWM_WPCR_WPRG2 (0x1 << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */
-#define PWM_WPCR_WPRG3 (0x1 << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */
-#define PWM_WPCR_WPRG4 (0x1 << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */
-#define PWM_WPCR_WPRG5 (0x1 << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */
-#define PWM_WPCR_WPKEY (0xffffff << 8) /**< \brief (PWM_WPCR) Write Protect Key */
-/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */
-#define PWM_WPSR_WPSWS0 (0x1 << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */
-#define PWM_WPSR_WPSWS1 (0x1 << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */
-#define PWM_WPSR_WPSWS2 (0x1 << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */
-#define PWM_WPSR_WPSWS3 (0x1 << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */
-#define PWM_WPSR_WPSWS4 (0x1 << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */
-#define PWM_WPSR_WPSWS5 (0x1 << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */
-#define PWM_WPSR_WPVS (0x1 << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */
-#define PWM_WPSR_WPHWS0 (0x1 << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */
-#define PWM_WPSR_WPHWS1 (0x1 << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */
-#define PWM_WPSR_WPHWS2 (0x1 << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */
-#define PWM_WPSR_WPHWS3 (0x1 << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */
-#define PWM_WPSR_WPHWS4 (0x1 << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */
-#define PWM_WPSR_WPHWS5 (0x1 << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */
-#define PWM_WPSR_WPVSRC (0xffff << 16) /**< \brief (PWM_WPSR) Write Protect Violation Source */
-/* -------- PWM_RPR : (PWM Offset: 0x100) Receive Pointer Register -------- */
-#define PWM_RPR_RXPTR (0xffffffff << 0) /**< \brief (PWM_RPR) Receive Pointer Register */
-/* -------- PWM_RCR : (PWM Offset: 0x104) Receive Counter Register -------- */
-#define PWM_RCR_RXCTR (0xffff << 0) /**< \brief (PWM_RCR) Receive Counter Register */
-/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */
-#define PWM_TPR_TXPTR (0xffffffff << 0) /**< \brief (PWM_TPR) Transmit Counter Register */
-/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */
-#define PWM_TCR_TXCTR (0xffff << 0) /**< \brief (PWM_TCR) Transmit Counter Register */
-/* -------- PWM_RNPR : (PWM Offset: 0x110) Receive Next Pointer Register -------- */
-#define PWM_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PWM_RNPR) Receive Next Pointer */
-/* -------- PWM_RNCR : (PWM Offset: 0x114) Receive Next Counter Register -------- */
-#define PWM_RNCR_RXNCTR (0xffff << 0) /**< \brief (PWM_RNCR) Receive Next Counter */
-/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */
-#define PWM_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PWM_TNPR) Transmit Next Pointer */
-/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */
-#define PWM_TNCR_TXNCTR (0xffff << 0) /**< \brief (PWM_TNCR) Transmit Counter Next */
-/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */
-#define PWM_PTCR_RXTEN (0x1 << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */
-#define PWM_PTCR_RXTDIS (0x1 << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */
-#define PWM_PTCR_TXTEN (0x1 << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */
-#define PWM_PTCR_TXTDIS (0x1 << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */
-/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */
-#define PWM_PTSR_RXTEN (0x1 << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */
-#define PWM_PTSR_TXTEN (0x1 << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */
-/* -------- PWM_CMP0V : (PWM Offset: 0x130) PWM Comparison 0 Value Register -------- */
-#define PWM_CMP0V_CV (0xffffff << 0) /**< \brief (PWM_CMP0V) Comparison x Value */
-#define PWM_CMP0V_CVM (0x1 << 24) /**< \brief (PWM_CMP0V) Comparison x Value Mode */
-/* -------- PWM_CMP0VUPD : (PWM Offset: 0x134) PWM Comparison 0 Value Update Register -------- */
-#define PWM_CMP0VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP0VUPD) Comparison x Value Update */
-#define PWM_CMP0VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP0VUPD) Comparison x Value Mode Update */
-/* -------- PWM_CMP0M : (PWM Offset: 0x138) PWM Comparison 0 Mode Register -------- */
-#define PWM_CMP0M_CEN (0x1 << 0) /**< \brief (PWM_CMP0M) Comparison x Enable */
-#define PWM_CMP0M_CTR (0xf << 4) /**< \brief (PWM_CMP0M) Comparison x Trigger */
-#define PWM_CMP0M_CPR (0xf << 8) /**< \brief (PWM_CMP0M) Comparison x Period */
-#define PWM_CMP0M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP0M) Comparison x Period Counter */
-#define PWM_CMP0M_CUPR (0xf << 16) /**< \brief (PWM_CMP0M) Comparison x Update Period */
-#define PWM_CMP0M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP0M) Comparison x Update Period Counter */
-/* -------- PWM_CMP0MUPD : (PWM Offset: 0x13C) PWM Comparison 0 Mode Update Register -------- */
-#define PWM_CMP0MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP0MUPD) Comparison x Enable Update */
-#define PWM_CMP0MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP0MUPD) Comparison x Trigger Update */
-#define PWM_CMP0MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP0MUPD) Comparison x Period Update */
-#define PWM_CMP0MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP0MUPD) Comparison x Update Period Update */
-/* -------- PWM_CMP1V : (PWM Offset: 0x140) PWM Comparison 1 Value Register -------- */
-#define PWM_CMP1V_CV (0xffffff << 0) /**< \brief (PWM_CMP1V) Comparison x Value */
-#define PWM_CMP1V_CVM (0x1 << 24) /**< \brief (PWM_CMP1V) Comparison x Value Mode */
-/* -------- PWM_CMP1VUPD : (PWM Offset: 0x144) PWM Comparison 1 Value Update Register -------- */
-#define PWM_CMP1VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP1VUPD) Comparison x Value Update */
-#define PWM_CMP1VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP1VUPD) Comparison x Value Mode Update */
-/* -------- PWM_CMP1M : (PWM Offset: 0x148) PWM Comparison 1 Mode Register -------- */
-#define PWM_CMP1M_CEN (0x1 << 0) /**< \brief (PWM_CMP1M) Comparison x Enable */
-#define PWM_CMP1M_CTR (0xf << 4) /**< \brief (PWM_CMP1M) Comparison x Trigger */
-#define PWM_CMP1M_CPR (0xf << 8) /**< \brief (PWM_CMP1M) Comparison x Period */
-#define PWM_CMP1M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP1M) Comparison x Period Counter */
-#define PWM_CMP1M_CUPR (0xf << 16) /**< \brief (PWM_CMP1M) Comparison x Update Period */
-#define PWM_CMP1M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP1M) Comparison x Update Period Counter */
-/* -------- PWM_CMP1MUPD : (PWM Offset: 0x14C) PWM Comparison 1 Mode Update Register -------- */
-#define PWM_CMP1MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP1MUPD) Comparison x Enable Update */
-#define PWM_CMP1MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP1MUPD) Comparison x Trigger Update */
-#define PWM_CMP1MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP1MUPD) Comparison x Period Update */
-#define PWM_CMP1MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP1MUPD) Comparison x Update Period Update */
-/* -------- PWM_CMP2V : (PWM Offset: 0x150) PWM Comparison 2 Value Register -------- */
-#define PWM_CMP2V_CV (0xffffff << 0) /**< \brief (PWM_CMP2V) Comparison x Value */
-#define PWM_CMP2V_CVM (0x1 << 24) /**< \brief (PWM_CMP2V) Comparison x Value Mode */
-/* -------- PWM_CMP2VUPD : (PWM Offset: 0x154) PWM Comparison 2 Value Update Register -------- */
-#define PWM_CMP2VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP2VUPD) Comparison x Value Update */
-#define PWM_CMP2VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP2VUPD) Comparison x Value Mode Update */
-/* -------- PWM_CMP2M : (PWM Offset: 0x158) PWM Comparison 2 Mode Register -------- */
-#define PWM_CMP2M_CEN (0x1 << 0) /**< \brief (PWM_CMP2M) Comparison x Enable */
-#define PWM_CMP2M_CTR (0xf << 4) /**< \brief (PWM_CMP2M) Comparison x Trigger */
-#define PWM_CMP2M_CPR (0xf << 8) /**< \brief (PWM_CMP2M) Comparison x Period */
-#define PWM_CMP2M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP2M) Comparison x Period Counter */
-#define PWM_CMP2M_CUPR (0xf << 16) /**< \brief (PWM_CMP2M) Comparison x Update Period */
-#define PWM_CMP2M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP2M) Comparison x Update Period Counter */
-/* -------- PWM_CMP2MUPD : (PWM Offset: 0x15C) PWM Comparison 2 Mode Update Register -------- */
-#define PWM_CMP2MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP2MUPD) Comparison x Enable Update */
-#define PWM_CMP2MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP2MUPD) Comparison x Trigger Update */
-#define PWM_CMP2MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP2MUPD) Comparison x Period Update */
-#define PWM_CMP2MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP2MUPD) Comparison x Update Period Update */
-/* -------- PWM_CMP3V : (PWM Offset: 0x160) PWM Comparison 3 Value Register -------- */
-#define PWM_CMP3V_CV (0xffffff << 0) /**< \brief (PWM_CMP3V) Comparison x Value */
-#define PWM_CMP3V_CVM (0x1 << 24) /**< \brief (PWM_CMP3V) Comparison x Value Mode */
-/* -------- PWM_CMP3VUPD : (PWM Offset: 0x164) PWM Comparison 3 Value Update Register -------- */
-#define PWM_CMP3VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP3VUPD) Comparison x Value Update */
-#define PWM_CMP3VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP3VUPD) Comparison x Value Mode Update */
-/* -------- PWM_CMP3M : (PWM Offset: 0x168) PWM Comparison 3 Mode Register -------- */
-#define PWM_CMP3M_CEN (0x1 << 0) /**< \brief (PWM_CMP3M) Comparison x Enable */
-#define PWM_CMP3M_CTR (0xf << 4) /**< \brief (PWM_CMP3M) Comparison x Trigger */
-#define PWM_CMP3M_CPR (0xf << 8) /**< \brief (PWM_CMP3M) Comparison x Period */
-#define PWM_CMP3M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP3M) Comparison x Period Counter */
-#define PWM_CMP3M_CUPR (0xf << 16) /**< \brief (PWM_CMP3M) Comparison x Update Period */
-#define PWM_CMP3M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP3M) Comparison x Update Period Counter */
-/* -------- PWM_CMP3MUPD : (PWM Offset: 0x16C) PWM Comparison 3 Mode Update Register -------- */
-#define PWM_CMP3MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP3MUPD) Comparison x Enable Update */
-#define PWM_CMP3MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP3MUPD) Comparison x Trigger Update */
-#define PWM_CMP3MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP3MUPD) Comparison x Period Update */
-#define PWM_CMP3MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP3MUPD) Comparison x Update Period Update */
-/* -------- PWM_CMP4V : (PWM Offset: 0x170) PWM Comparison 4 Value Register -------- */
-#define PWM_CMP4V_CV (0xffffff << 0) /**< \brief (PWM_CMP4V) Comparison x Value */
-#define PWM_CMP4V_CVM (0x1 << 24) /**< \brief (PWM_CMP4V) Comparison x Value Mode */
-/* -------- PWM_CMP4VUPD : (PWM Offset: 0x174) PWM Comparison 4 Value Update Register -------- */
-#define PWM_CMP4VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP4VUPD) Comparison x Value Update */
-#define PWM_CMP4VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP4VUPD) Comparison x Value Mode Update */
-/* -------- PWM_CMP4M : (PWM Offset: 0x178) PWM Comparison 4 Mode Register -------- */
-#define PWM_CMP4M_CEN (0x1 << 0) /**< \brief (PWM_CMP4M) Comparison x Enable */
-#define PWM_CMP4M_CTR (0xf << 4) /**< \brief (PWM_CMP4M) Comparison x Trigger */
-#define PWM_CMP4M_CPR (0xf << 8) /**< \brief (PWM_CMP4M) Comparison x Period */
-#define PWM_CMP4M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP4M) Comparison x Period Counter */
-#define PWM_CMP4M_CUPR (0xf << 16) /**< \brief (PWM_CMP4M) Comparison x Update Period */
-#define PWM_CMP4M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP4M) Comparison x Update Period Counter */
-/* -------- PWM_CMP4MUPD : (PWM Offset: 0x17C) PWM Comparison 4 Mode Update Register -------- */
-#define PWM_CMP4MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP4MUPD) Comparison x Enable Update */
-#define PWM_CMP4MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP4MUPD) Comparison x Trigger Update */
-#define PWM_CMP4MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP4MUPD) Comparison x Period Update */
-#define PWM_CMP4MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP4MUPD) Comparison x Update Period Update */
-/* -------- PWM_CMP5V : (PWM Offset: 0x180) PWM Comparison 5 Value Register -------- */
-#define PWM_CMP5V_CV (0xffffff << 0) /**< \brief (PWM_CMP5V) Comparison x Value */
-#define PWM_CMP5V_CVM (0x1 << 24) /**< \brief (PWM_CMP5V) Comparison x Value Mode */
-/* -------- PWM_CMP5VUPD : (PWM Offset: 0x184) PWM Comparison 5 Value Update Register -------- */
-#define PWM_CMP5VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP5VUPD) Comparison x Value Update */
-#define PWM_CMP5VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP5VUPD) Comparison x Value Mode Update */
-/* -------- PWM_CMP5M : (PWM Offset: 0x188) PWM Comparison 5 Mode Register -------- */
-#define PWM_CMP5M_CEN (0x1 << 0) /**< \brief (PWM_CMP5M) Comparison x Enable */
-#define PWM_CMP5M_CTR (0xf << 4) /**< \brief (PWM_CMP5M) Comparison x Trigger */
-#define PWM_CMP5M_CPR (0xf << 8) /**< \brief (PWM_CMP5M) Comparison x Period */
-#define PWM_CMP5M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP5M) Comparison x Period Counter */
-#define PWM_CMP5M_CUPR (0xf << 16) /**< \brief (PWM_CMP5M) Comparison x Update Period */
-#define PWM_CMP5M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP5M) Comparison x Update Period Counter */
-/* -------- PWM_CMP5MUPD : (PWM Offset: 0x18C) PWM Comparison 5 Mode Update Register -------- */
-#define PWM_CMP5MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP5MUPD) Comparison x Enable Update */
-#define PWM_CMP5MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP5MUPD) Comparison x Trigger Update */
-#define PWM_CMP5MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP5MUPD) Comparison x Period Update */
-#define PWM_CMP5MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP5MUPD) Comparison x Update Period Update */
-/* -------- PWM_CMP6V : (PWM Offset: 0x190) PWM Comparison 6 Value Register -------- */
-#define PWM_CMP6V_CV (0xffffff << 0) /**< \brief (PWM_CMP6V) Comparison x Value */
-#define PWM_CMP6V_CVM (0x1 << 24) /**< \brief (PWM_CMP6V) Comparison x Value Mode */
-/* -------- PWM_CMP6VUPD : (PWM Offset: 0x194) PWM Comparison 6 Value Update Register -------- */
-#define PWM_CMP6VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP6VUPD) Comparison x Value Update */
-#define PWM_CMP6VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP6VUPD) Comparison x Value Mode Update */
-/* -------- PWM_CMP6M : (PWM Offset: 0x198) PWM Comparison 6 Mode Register -------- */
-#define PWM_CMP6M_CEN (0x1 << 0) /**< \brief (PWM_CMP6M) Comparison x Enable */
-#define PWM_CMP6M_CTR (0xf << 4) /**< \brief (PWM_CMP6M) Comparison x Trigger */
-#define PWM_CMP6M_CPR (0xf << 8) /**< \brief (PWM_CMP6M) Comparison x Period */
-#define PWM_CMP6M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP6M) Comparison x Period Counter */
-#define PWM_CMP6M_CUPR (0xf << 16) /**< \brief (PWM_CMP6M) Comparison x Update Period */
-#define PWM_CMP6M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP6M) Comparison x Update Period Counter */
-/* -------- PWM_CMP6MUPD : (PWM Offset: 0x19C) PWM Comparison 6 Mode Update Register -------- */
-#define PWM_CMP6MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP6MUPD) Comparison x Enable Update */
-#define PWM_CMP6MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP6MUPD) Comparison x Trigger Update */
-#define PWM_CMP6MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP6MUPD) Comparison x Period Update */
-#define PWM_CMP6MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP6MUPD) Comparison x Update Period Update */
-/* -------- PWM_CMP7V : (PWM Offset: 0x1A0) PWM Comparison 7 Value Register -------- */
-#define PWM_CMP7V_CV (0xffffff << 0) /**< \brief (PWM_CMP7V) Comparison x Value */
-#define PWM_CMP7V_CVM (0x1 << 24) /**< \brief (PWM_CMP7V) Comparison x Value Mode */
-/* -------- PWM_CMP7VUPD : (PWM Offset: 0x1A4) PWM Comparison 7 Value Update Register -------- */
-#define PWM_CMP7VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP7VUPD) Comparison x Value Update */
-#define PWM_CMP7VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP7VUPD) Comparison x Value Mode Update */
-/* -------- PWM_CMP7M : (PWM Offset: 0x1A8) PWM Comparison 7 Mode Register -------- */
-#define PWM_CMP7M_CEN (0x1 << 0) /**< \brief (PWM_CMP7M) Comparison x Enable */
-#define PWM_CMP7M_CTR (0xf << 4) /**< \brief (PWM_CMP7M) Comparison x Trigger */
-#define PWM_CMP7M_CPR (0xf << 8) /**< \brief (PWM_CMP7M) Comparison x Period */
-#define PWM_CMP7M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP7M) Comparison x Period Counter */
-#define PWM_CMP7M_CUPR (0xf << 16) /**< \brief (PWM_CMP7M) Comparison x Update Period */
-#define PWM_CMP7M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP7M) Comparison x Update Period Counter */
-/* -------- PWM_CMP7MUPD : (PWM Offset: 0x1AC) PWM Comparison 7 Mode Update Register -------- */
-#define PWM_CMP7MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP7MUPD) Comparison x Enable Update */
-#define PWM_CMP7MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP7MUPD) Comparison x Trigger Update */
-#define PWM_CMP7MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP7MUPD) Comparison x Period Update */
-#define PWM_CMP7MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP7MUPD) Comparison x Update Period Update */
-/* -------- PWM_CMR0 : (PWM Offset: 0x200) PWM Channel Mode Register (ch_num = 0) -------- */
-#define PWM_CMR0_CPRE (0xf << 0) /**< \brief (PWM_CMR0) Channel Pre-scaler */
-#define PWM_CMR0_CALG (0x1 << 8) /**< \brief (PWM_CMR0) Channel Alignment */
-#define PWM_CMR0_CPOL (0x1 << 9) /**< \brief (PWM_CMR0) Channel Polarity */
-#define PWM_CMR0_CES (0x1 << 10) /**< \brief (PWM_CMR0) Counter Event Selection */
-#define PWM_CMR0_DTE (0x1 << 16) /**< \brief (PWM_CMR0) Dead-Time Generator Enable */
-#define PWM_CMR0_DTHI (0x1 << 17) /**< \brief (PWM_CMR0) Dead-Time PWMHx Output Inverted */
-#define PWM_CMR0_DTLI (0x1 << 18) /**< \brief (PWM_CMR0) Dead-Time PWMLx Output Inverted */
-/* -------- PWM_CDTY0 : (PWM Offset: 0x204) PWM Channel Duty Cycle Register (ch_num = 0) -------- */
-#define PWM_CDTY0_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY0) Channel Duty-Cycle */
-/* -------- PWM_CDTYUPD0 : (PWM Offset: 0x208) PWM Channel Duty Cycle Update Register (ch_num = 0) -------- */
-#define PWM_CDTYUPD0_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD0) Channel Duty-Cycle Update */
-/* -------- PWM_CPRD0 : (PWM Offset: 0x20C) PWM Channel Period Register (ch_num = 0) -------- */
-#define PWM_CPRD0_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD0) Channel Period */
-/* -------- PWM_CPRDUPD0 : (PWM Offset: 0x210) PWM Channel Period Update Register (ch_num = 0) -------- */
-#define PWM_CPRDUPD0_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD0) Channel Period Update */
-/* -------- PWM_CCNT0 : (PWM Offset: 0x214) PWM Channel Counter Register (ch_num = 0) -------- */
-#define PWM_CCNT0_CNT (0xffffff << 0) /**< \brief (PWM_CCNT0) Channel Counter Register */
-/* -------- PWM_DT0 : (PWM Offset: 0x218) PWM Channel Dead Time Register (ch_num = 0) -------- */
-#define PWM_DT0_DTH (0xffff << 0) /**< \brief (PWM_DT0) Dead-Time Value for PWMHx Output */
-#define PWM_DT0_DTL (0xffff << 16) /**< \brief (PWM_DT0) Dead-Time Value for PWMLx Output */
-/* -------- PWM_DTUPD0 : (PWM Offset: 0x21C) PWM Channel Dead Time Update Register (ch_num = 0) -------- */
-#define PWM_DTUPD0_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMHx Output */
-#define PWM_DTUPD0_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMLx Output */
-/* -------- PWM_CMR1 : (PWM Offset: 0x220) PWM Channel Mode Register (ch_num = 1) -------- */
-#define PWM_CMR1_CPRE (0xf << 0) /**< \brief (PWM_CMR1) Channel Pre-scaler */
-#define PWM_CMR1_CALG (0x1 << 8) /**< \brief (PWM_CMR1) Channel Alignment */
-#define PWM_CMR1_CPOL (0x1 << 9) /**< \brief (PWM_CMR1) Channel Polarity */
-#define PWM_CMR1_CES (0x1 << 10) /**< \brief (PWM_CMR1) Counter Event Selection */
-#define PWM_CMR1_DTE (0x1 << 16) /**< \brief (PWM_CMR1) Dead-Time Generator Enable */
-#define PWM_CMR1_DTHI (0x1 << 17) /**< \brief (PWM_CMR1) Dead-Time PWMHx Output Inverted */
-#define PWM_CMR1_DTLI (0x1 << 18) /**< \brief (PWM_CMR1) Dead-Time PWMLx Output Inverted */
-/* -------- PWM_CDTY1 : (PWM Offset: 0x224) PWM Channel Duty Cycle Register (ch_num = 1) -------- */
-#define PWM_CDTY1_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY1) Channel Duty-Cycle */
-/* -------- PWM_CDTYUPD1 : (PWM Offset: 0x228) PWM Channel Duty Cycle Update Register (ch_num = 1) -------- */
-#define PWM_CDTYUPD1_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD1) Channel Duty-Cycle Update */
-/* -------- PWM_CPRD1 : (PWM Offset: 0x22C) PWM Channel Period Register (ch_num = 1) -------- */
-#define PWM_CPRD1_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD1) Channel Period */
-/* -------- PWM_CPRDUPD1 : (PWM Offset: 0x230) PWM Channel Period Update Register (ch_num = 1) -------- */
-#define PWM_CPRDUPD1_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD1) Channel Period Update */
-/* -------- PWM_CCNT1 : (PWM Offset: 0x234) PWM Channel Counter Register (ch_num = 1) -------- */
-#define PWM_CCNT1_CNT (0xffffff << 0) /**< \brief (PWM_CCNT1) Channel Counter Register */
-/* -------- PWM_DT1 : (PWM Offset: 0x238) PWM Channel Dead Time Register (ch_num = 1) -------- */
-#define PWM_DT1_DTH (0xffff << 0) /**< \brief (PWM_DT1) Dead-Time Value for PWMHx Output */
-#define PWM_DT1_DTL (0xffff << 16) /**< \brief (PWM_DT1) Dead-Time Value for PWMLx Output */
-/* -------- PWM_DTUPD1 : (PWM Offset: 0x23C) PWM Channel Dead Time Update Register (ch_num = 1) -------- */
-#define PWM_DTUPD1_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMHx Output */
-#define PWM_DTUPD1_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMLx Output */
-/* -------- PWM_CMR2 : (PWM Offset: 0x240) PWM Channel Mode Register (ch_num = 2) -------- */
-#define PWM_CMR2_CPRE (0xf << 0) /**< \brief (PWM_CMR2) Channel Pre-scaler */
-#define PWM_CMR2_CALG (0x1 << 8) /**< \brief (PWM_CMR2) Channel Alignment */
-#define PWM_CMR2_CPOL (0x1 << 9) /**< \brief (PWM_CMR2) Channel Polarity */
-#define PWM_CMR2_CES (0x1 << 10) /**< \brief (PWM_CMR2) Counter Event Selection */
-#define PWM_CMR2_DTE (0x1 << 16) /**< \brief (PWM_CMR2) Dead-Time Generator Enable */
-#define PWM_CMR2_DTHI (0x1 << 17) /**< \brief (PWM_CMR2) Dead-Time PWMHx Output Inverted */
-#define PWM_CMR2_DTLI (0x1 << 18) /**< \brief (PWM_CMR2) Dead-Time PWMLx Output Inverted */
-/* -------- PWM_CDTY2 : (PWM Offset: 0x244) PWM Channel Duty Cycle Register (ch_num = 2) -------- */
-#define PWM_CDTY2_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY2) Channel Duty-Cycle */
-/* -------- PWM_CDTYUPD2 : (PWM Offset: 0x248) PWM Channel Duty Cycle Update Register (ch_num = 2) -------- */
-#define PWM_CDTYUPD2_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD2) Channel Duty-Cycle Update */
-/* -------- PWM_CPRD2 : (PWM Offset: 0x24C) PWM Channel Period Register (ch_num = 2) -------- */
-#define PWM_CPRD2_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD2) Channel Period */
-/* -------- PWM_CPRDUPD2 : (PWM Offset: 0x250) PWM Channel Period Update Register (ch_num = 2) -------- */
-#define PWM_CPRDUPD2_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD2) Channel Period Update */
-/* -------- PWM_CCNT2 : (PWM Offset: 0x254) PWM Channel Counter Register (ch_num = 2) -------- */
-#define PWM_CCNT2_CNT (0xffffff << 0) /**< \brief (PWM_CCNT2) Channel Counter Register */
-/* -------- PWM_DT2 : (PWM Offset: 0x258) PWM Channel Dead Time Register (ch_num = 2) -------- */
-#define PWM_DT2_DTH (0xffff << 0) /**< \brief (PWM_DT2) Dead-Time Value for PWMHx Output */
-#define PWM_DT2_DTL (0xffff << 16) /**< \brief (PWM_DT2) Dead-Time Value for PWMLx Output */
-/* -------- PWM_DTUPD2 : (PWM Offset: 0x25C) PWM Channel Dead Time Update Register (ch_num = 2) -------- */
-#define PWM_DTUPD2_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMHx Output */
-#define PWM_DTUPD2_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMLx Output */
-/* -------- PWM_CMR3 : (PWM Offset: 0x260) PWM Channel Mode Register (ch_num = 3) -------- */
-#define PWM_CMR3_CPRE (0xf << 0) /**< \brief (PWM_CMR3) Channel Pre-scaler */
-#define PWM_CMR3_CALG (0x1 << 8) /**< \brief (PWM_CMR3) Channel Alignment */
-#define PWM_CMR3_CPOL (0x1 << 9) /**< \brief (PWM_CMR3) Channel Polarity */
-#define PWM_CMR3_CES (0x1 << 10) /**< \brief (PWM_CMR3) Counter Event Selection */
-#define PWM_CMR3_DTE (0x1 << 16) /**< \brief (PWM_CMR3) Dead-Time Generator Enable */
-#define PWM_CMR3_DTHI (0x1 << 17) /**< \brief (PWM_CMR3) Dead-Time PWMHx Output Inverted */
-#define PWM_CMR3_DTLI (0x1 << 18) /**< \brief (PWM_CMR3) Dead-Time PWMLx Output Inverted */
-/* -------- PWM_CDTY3 : (PWM Offset: 0x264) PWM Channel Duty Cycle Register (ch_num = 3) -------- */
-#define PWM_CDTY3_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY3) Channel Duty-Cycle */
-/* -------- PWM_CDTYUPD3 : (PWM Offset: 0x268) PWM Channel Duty Cycle Update Register (ch_num = 3) -------- */
-#define PWM_CDTYUPD3_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD3) Channel Duty-Cycle Update */
-/* -------- PWM_CPRD3 : (PWM Offset: 0x26C) PWM Channel Period Register (ch_num = 3) -------- */
-#define PWM_CPRD3_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD3) Channel Period */
-/* -------- PWM_CPRDUPD3 : (PWM Offset: 0x270) PWM Channel Period Update Register (ch_num = 3) -------- */
-#define PWM_CPRDUPD3_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD3) Channel Period Update */
-/* -------- PWM_CCNT3 : (PWM Offset: 0x274) PWM Channel Counter Register (ch_num = 3) -------- */
-#define PWM_CCNT3_CNT (0xffffff << 0) /**< \brief (PWM_CCNT3) Channel Counter Register */
-/* -------- PWM_DT3 : (PWM Offset: 0x278) PWM Channel Dead Time Register (ch_num = 3) -------- */
-#define PWM_DT3_DTH (0xffff << 0) /**< \brief (PWM_DT3) Dead-Time Value for PWMHx Output */
-#define PWM_DT3_DTL (0xffff << 16) /**< \brief (PWM_DT3) Dead-Time Value for PWMLx Output */
-/* -------- PWM_DTUPD3 : (PWM Offset: 0x27C) PWM Channel Dead Time Update Register (ch_num = 3) -------- */
-#define PWM_DTUPD3_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMHx Output */
-#define PWM_DTUPD3_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMLx Output */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Reset Controller */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_RSTC Reset Controller */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Rstc hardware registers */
-typedef struct {
- WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
- RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
- RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
-} Rstc;
-#endif /* __ASSEMBLY__ */
-/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
-#define RSTC_CR_PROCRST (0x1 << 0) /**< \brief (RSTC_CR) Processor Reset */
-#define RSTC_CR_PERRST (0x1 << 2) /**< \brief (RSTC_CR) Peripheral Reset */
-#define RSTC_CR_EXTRST (0x1 << 3) /**< \brief (RSTC_CR) External Reset */
-#define RSTC_CR_KEY (0xff << 24) /**< \brief (RSTC_CR) Password */
-/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
-#define RSTC_SR_URSTS (0x1 << 0) /**< \brief (RSTC_SR) User Reset Status */
-#define RSTC_SR_RSTTYP (0x7 << 8) /**< \brief (RSTC_SR) Reset Type */
-#define RSTC_SR_NRSTL (0x1 << 16) /**< \brief (RSTC_SR) NRST Pin Level */
-#define RSTC_SR_SRCMP (0x1 << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
-/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
-#define RSTC_MR_URSTEN (0x1 << 0) /**< \brief (RSTC_MR) User Reset Enable */
-#define RSTC_MR_URSTIEN (0x1 << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
-#define RSTC_MR_ERSTL (0xf << 8) /**< \brief (RSTC_MR) External Reset Length */
-#define RSTC_MR_KEY (0xff << 24) /**< \brief (RSTC_MR) Password */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Real-time Clock */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_RTC Real-time Clock */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Rtc hardware registers */
-typedef struct {
- RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */
- RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */
- RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */
- RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */
- RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
- RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
- RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */
- WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
- WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
- WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
- RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
- RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
-} Rtc;
-#endif /* __ASSEMBLY__ */
-/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
-#define RTC_CR_UPDTIM (0x1 << 0) /**< \brief (RTC_CR) Update Request Time Register */
-#define RTC_CR_UPDCAL (0x1 << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
-#define RTC_CR_TIMEVSEL (0x3 << 8) /**< \brief (RTC_CR) Time Event Selection */
-#define RTC_CR_TIMEVSEL_MINUTE (0x0 << 8) /**< \brief (RTC_CR) Minute change. */
-#define RTC_CR_TIMEVSEL_HOUR (0x1 << 8) /**< \brief (RTC_CR) Hour change. */
-#define RTC_CR_TIMEVSEL_DAY24 (0x2 << 8) /**< \brief (RTC_CR) Every day at midnight. */
-#define RTC_CR_TIMEVSEL_DAY12 (0x3 << 8) /**< \brief (RTC_CR) Every day at noon. */
-#define RTC_CR_CALEVSEL (0x3 << 16) /**< \brief (RTC_CR) Calendar Event Selection */
-#define RTC_CR_CALEVSEL_WEEK (0x0 << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00). */
-#define RTC_CR_CALEVSEL_MONTH (0x1 << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00). */
-/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
-#define RTC_MR_HRMOD (0x1 << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
-/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
-#define RTC_TIMR_SEC (0x7f << 0) /**< \brief (RTC_TIMR) Current Second */
-#define RTC_TIMR_MIN (0x7f << 8) /**< \brief (RTC_TIMR) Current Minute */
-#define RTC_TIMR_HOUR (0x3f << 16) /**< \brief (RTC_TIMR) Current Hour */
-#define RTC_TIMR_AMPM (0x1 << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
-/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
-#define RTC_CALR_CENT (0x7f << 0) /**< \brief (RTC_CALR) Current Century */
-#define RTC_CALR_YEAR (0xff << 8) /**< \brief (RTC_CALR) Current Year */
-#define RTC_CALR_MONTH (0x1f << 16) /**< \brief (RTC_CALR) Current Month */
-#define RTC_CALR_DAY (0x7 << 21) /**< \brief (RTC_CALR) Current Day in Current Week */
-#define RTC_CALR_DATE (0x3f << 24) /**< \brief (RTC_CALR) Current Day in Current Month */
-/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
-#define RTC_TIMALR_SEC (0x7f << 0) /**< \brief (RTC_TIMALR) Second Alarm */
-#define RTC_TIMALR_SECEN (0x1 << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
-#define RTC_TIMALR_MIN (0x7f << 8) /**< \brief (RTC_TIMALR) Minute Alarm */
-#define RTC_TIMALR_MINEN (0x1 << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
-#define RTC_TIMALR_HOUR (0x3f << 16) /**< \brief (RTC_TIMALR) Hour Alarm */
-#define RTC_TIMALR_AMPM (0x1 << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
-#define RTC_TIMALR_HOUREN (0x1 << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
-/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
-#define RTC_CALALR_MONTH (0x1f << 16) /**< \brief (RTC_CALALR) Month Alarm */
-#define RTC_CALALR_MTHEN (0x1 << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
-#define RTC_CALALR_DATE (0x3f << 24) /**< \brief (RTC_CALALR) Date Alarm */
-#define RTC_CALALR_DATEEN (0x1 << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
-/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
-#define RTC_SR_ACKUPD (0x1 << 0) /**< \brief (RTC_SR) Acknowledge for Update */
-#define RTC_SR_ALARM (0x1 << 1) /**< \brief (RTC_SR) Alarm Flag */
-#define RTC_SR_SEC (0x1 << 2) /**< \brief (RTC_SR) Second Event */
-#define RTC_SR_TIMEV (0x1 << 3) /**< \brief (RTC_SR) Time Event */
-#define RTC_SR_CALEV (0x1 << 4) /**< \brief (RTC_SR) Calendar Event */
-/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
-#define RTC_SCCR_ACKCLR (0x1 << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
-#define RTC_SCCR_ALRCLR (0x1 << 1) /**< \brief (RTC_SCCR) Alarm Clear */
-#define RTC_SCCR_SECCLR (0x1 << 2) /**< \brief (RTC_SCCR) Second Clear */
-#define RTC_SCCR_TIMCLR (0x1 << 3) /**< \brief (RTC_SCCR) Time Clear */
-#define RTC_SCCR_CALCLR (0x1 << 4) /**< \brief (RTC_SCCR) Calendar Clear */
-/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
-#define RTC_IER_ACKEN (0x1 << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
-#define RTC_IER_ALREN (0x1 << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
-#define RTC_IER_SECEN (0x1 << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
-#define RTC_IER_TIMEN (0x1 << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
-#define RTC_IER_CALEN (0x1 << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
-/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
-#define RTC_IDR_ACKDIS (0x1 << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
-#define RTC_IDR_ALRDIS (0x1 << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
-#define RTC_IDR_SECDIS (0x1 << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
-#define RTC_IDR_TIMDIS (0x1 << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
-#define RTC_IDR_CALDIS (0x1 << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
-/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
-#define RTC_IMR_ACK (0x1 << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
-#define RTC_IMR_ALR (0x1 << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
-#define RTC_IMR_SEC (0x1 << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
-#define RTC_IMR_TIM (0x1 << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
-#define RTC_IMR_CAL (0x1 << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
-/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
-#define RTC_VER_NVTIM (0x1 << 0) /**< \brief (RTC_VER) Non-valid Time */
-#define RTC_VER_NVCAL (0x1 << 1) /**< \brief (RTC_VER) Non-valid Calendar */
-#define RTC_VER_NVTIMALR (0x1 << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
-#define RTC_VER_NVCALALR (0x1 << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Real-time Timer */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_RTT Real-time Timer */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Rtt hardware registers */
-typedef struct {
- RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */
- RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */
- RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */
- RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */
-} Rtt;
-#endif /* __ASSEMBLY__ */
-/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */
-#define RTT_MR_RTPRES (0xffff << 0) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */
-#define RTT_MR_ALMIEN (0x1 << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */
-#define RTT_MR_RTTINCIEN (0x1 << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */
-#define RTT_MR_RTTRST (0x1 << 18) /**< \brief (RTT_MR) Real-time Timer Restart */
-/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */
-#define RTT_AR_ALMV (0xffffffff << 0) /**< \brief (RTT_AR) Alarm Value */
-/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */
-#define RTT_VR_CRTV (0xffffffff << 0) /**< \brief (RTT_VR) Current Real-time Value */
-/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */
-#define RTT_SR_ALMS (0x1 << 0) /**< \brief (RTT_SR) Real-time Alarm Status */
-#define RTT_SR_RTTINC (0x1 << 1) /**< \brief (RTT_SR) Real-time Timer Increment */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Static Memory Controller */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_SMC Static Memory Controller */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief SmcCs_number hardware registers */
-typedef struct {
- RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */
- RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */
- RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */
- RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */
-} SmcCs_number;
-/** \brief Smc hardware registers */
-typedef struct {
- SmcCs_number SMC_CS_NUMBER[5]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 4 */
- RwReg Reserved1[12];
- RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */
- WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */
- WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */
- RwReg Reserved2[22];
- RwReg SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */
- RoReg SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */
-} Smc;
-#endif /* __ASSEMBLY__ */
-/* -------- SMC_SETUP0 : (SMC Offset: 0x0) SMC Setup Register (CS_number = 0) -------- */
-#define SMC_SETUP0_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP0) NWE Setup Length */
-#define SMC_SETUP0_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP0) NCS Setup Length in WRITE Access */
-#define SMC_SETUP0_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP0) NRD Setup Length */
-#define SMC_SETUP0_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP0) NCS Setup Length in READ Access */
-/* -------- SMC_PULSE0 : (SMC Offset: 0x4) SMC Pulse Register (CS_number = 0) -------- */
-#define SMC_PULSE0_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE0) NWE Pulse Length */
-#define SMC_PULSE0_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE0) NCS Pulse Length in WRITE Access */
-#define SMC_PULSE0_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE0) NRD Pulse Length */
-#define SMC_PULSE0_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE0) NCS Pulse Length in READ Access */
-/* -------- SMC_CYCLE0 : (SMC Offset: 0x8) SMC Cycle Register (CS_number = 0) -------- */
-#define SMC_CYCLE0_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE0) Total Write Cycle Length */
-#define SMC_CYCLE0_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE0) Total Read Cycle Length */
-/* -------- SMC_MODE0 : (SMC Offset: 0xC) SMC Mode Register (CS_number = 0) -------- */
-#define SMC_MODE0_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE0) */
-#define SMC_MODE0_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE0) */
-#define SMC_MODE0_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE0) NWAIT Mode */
-#define SMC_MODE0_DBW (0x3 << 12) /**< \brief (SMC_MODE0) Data Bus Width */
-#define SMC_MODE0_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE0) Data Float Time */
-#define SMC_MODE0_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE0) TDF Optimization */
-#define SMC_MODE0_PMEN (0x1 << 24) /**< \brief (SMC_MODE0) Page Mode Enabled */
-#define SMC_MODE0_PS (0x3 << 28) /**< \brief (SMC_MODE0) Page Size */
-/* -------- SMC_SETUP1 : (SMC Offset: 0x10) SMC Setup Register (CS_number = 1) -------- */
-#define SMC_SETUP1_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP1) NWE Setup Length */
-#define SMC_SETUP1_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP1) NCS Setup Length in WRITE Access */
-#define SMC_SETUP1_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP1) NRD Setup Length */
-#define SMC_SETUP1_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP1) NCS Setup Length in READ Access */
-/* -------- SMC_PULSE1 : (SMC Offset: 0x14) SMC Pulse Register (CS_number = 1) -------- */
-#define SMC_PULSE1_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE1) NWE Pulse Length */
-#define SMC_PULSE1_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE1) NCS Pulse Length in WRITE Access */
-#define SMC_PULSE1_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE1) NRD Pulse Length */
-#define SMC_PULSE1_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE1) NCS Pulse Length in READ Access */
-/* -------- SMC_CYCLE1 : (SMC Offset: 0x18) SMC Cycle Register (CS_number = 1) -------- */
-#define SMC_CYCLE1_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE1) Total Write Cycle Length */
-#define SMC_CYCLE1_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE1) Total Read Cycle Length */
-/* -------- SMC_MODE1 : (SMC Offset: 0x1C) SMC Mode Register (CS_number = 1) -------- */
-#define SMC_MODE1_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE1) */
-#define SMC_MODE1_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE1) */
-#define SMC_MODE1_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE1) NWAIT Mode */
-#define SMC_MODE1_DBW (0x3 << 12) /**< \brief (SMC_MODE1) Data Bus Width */
-#define SMC_MODE1_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE1) Data Float Time */
-#define SMC_MODE1_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE1) TDF Optimization */
-#define SMC_MODE1_PMEN (0x1 << 24) /**< \brief (SMC_MODE1) Page Mode Enabled */
-#define SMC_MODE1_PS (0x3 << 28) /**< \brief (SMC_MODE1) Page Size */
-/* -------- SMC_SETUP2 : (SMC Offset: 0x20) SMC Setup Register (CS_number = 2) -------- */
-#define SMC_SETUP2_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP2) NWE Setup Length */
-#define SMC_SETUP2_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP2) NCS Setup Length in WRITE Access */
-#define SMC_SETUP2_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP2) NRD Setup Length */
-#define SMC_SETUP2_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP2) NCS Setup Length in READ Access */
-/* -------- SMC_PULSE2 : (SMC Offset: 0x24) SMC Pulse Register (CS_number = 2) -------- */
-#define SMC_PULSE2_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE2) NWE Pulse Length */
-#define SMC_PULSE2_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE2) NCS Pulse Length in WRITE Access */
-#define SMC_PULSE2_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE2) NRD Pulse Length */
-#define SMC_PULSE2_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE2) NCS Pulse Length in READ Access */
-/* -------- SMC_CYCLE2 : (SMC Offset: 0x28) SMC Cycle Register (CS_number = 2) -------- */
-#define SMC_CYCLE2_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE2) Total Write Cycle Length */
-#define SMC_CYCLE2_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE2) Total Read Cycle Length */
-/* -------- SMC_MODE2 : (SMC Offset: 0x2C) SMC Mode Register (CS_number = 2) -------- */
-#define SMC_MODE2_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE2) */
-#define SMC_MODE2_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE2) */
-#define SMC_MODE2_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE2) NWAIT Mode */
-#define SMC_MODE2_DBW (0x3 << 12) /**< \brief (SMC_MODE2) Data Bus Width */
-#define SMC_MODE2_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE2) Data Float Time */
-#define SMC_MODE2_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE2) TDF Optimization */
-#define SMC_MODE2_PMEN (0x1 << 24) /**< \brief (SMC_MODE2) Page Mode Enabled */
-#define SMC_MODE2_PS (0x3 << 28) /**< \brief (SMC_MODE2) Page Size */
-/* -------- SMC_SETUP3 : (SMC Offset: 0x30) SMC Setup Register (CS_number = 3) -------- */
-#define SMC_SETUP3_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP3) NWE Setup Length */
-#define SMC_SETUP3_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP3) NCS Setup Length in WRITE Access */
-#define SMC_SETUP3_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP3) NRD Setup Length */
-#define SMC_SETUP3_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP3) NCS Setup Length in READ Access */
-/* -------- SMC_PULSE3 : (SMC Offset: 0x34) SMC Pulse Register (CS_number = 3) -------- */
-#define SMC_PULSE3_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE3) NWE Pulse Length */
-#define SMC_PULSE3_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE3) NCS Pulse Length in WRITE Access */
-#define SMC_PULSE3_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE3) NRD Pulse Length */
-#define SMC_PULSE3_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE3) NCS Pulse Length in READ Access */
-/* -------- SMC_CYCLE3 : (SMC Offset: 0x38) SMC Cycle Register (CS_number = 3) -------- */
-#define SMC_CYCLE3_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE3) Total Write Cycle Length */
-#define SMC_CYCLE3_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE3) Total Read Cycle Length */
-/* -------- SMC_MODE3 : (SMC Offset: 0x3C) SMC Mode Register (CS_number = 3) -------- */
-#define SMC_MODE3_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE3) */
-#define SMC_MODE3_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE3) */
-#define SMC_MODE3_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE3) NWAIT Mode */
-#define SMC_MODE3_DBW (0x3 << 12) /**< \brief (SMC_MODE3) Data Bus Width */
-#define SMC_MODE3_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE3) Data Float Time */
-#define SMC_MODE3_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE3) TDF Optimization */
-#define SMC_MODE3_PMEN (0x1 << 24) /**< \brief (SMC_MODE3) Page Mode Enabled */
-#define SMC_MODE3_PS (0x3 << 28) /**< \brief (SMC_MODE3) Page Size */
-/* -------- SMC_SETUP4 : (SMC Offset: 0x40) SMC Setup Register (CS_number = 4) -------- */
-#define SMC_SETUP4_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP4) NWE Setup Length */
-#define SMC_SETUP4_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP4) NCS Setup Length in WRITE Access */
-#define SMC_SETUP4_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP4) NRD Setup Length */
-#define SMC_SETUP4_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP4) NCS Setup Length in READ Access */
-/* -------- SMC_PULSE4 : (SMC Offset: 0x44) SMC Pulse Register (CS_number = 4) -------- */
-#define SMC_PULSE4_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE4) NWE Pulse Length */
-#define SMC_PULSE4_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE4) NCS Pulse Length in WRITE Access */
-#define SMC_PULSE4_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE4) NRD Pulse Length */
-#define SMC_PULSE4_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE4) NCS Pulse Length in READ Access */
-/* -------- SMC_CYCLE4 : (SMC Offset: 0x48) SMC Cycle Register (CS_number = 4) -------- */
-#define SMC_CYCLE4_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE4) Total Write Cycle Length */
-#define SMC_CYCLE4_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE4) Total Read Cycle Length */
-/* -------- SMC_MODE4 : (SMC Offset: 0x4C) SMC Mode Register (CS_number = 4) -------- */
-#define SMC_MODE4_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE4) */
-#define SMC_MODE4_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE4) */
-#define SMC_MODE4_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE4) NWAIT Mode */
-#define SMC_MODE4_DBW (0x3 << 12) /**< \brief (SMC_MODE4) Data Bus Width */
-#define SMC_MODE4_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE4) Data Float Time */
-#define SMC_MODE4_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE4) TDF Optimization */
-#define SMC_MODE4_PMEN (0x1 << 24) /**< \brief (SMC_MODE4) Page Mode Enabled */
-#define SMC_MODE4_PS (0x3 << 28) /**< \brief (SMC_MODE4) Page Size */
-/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */
-#define SMC_OCMS_SMSE (0x1 << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */
-#define SMC_OCMS_CS0SE (0x1 << 16) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
-#define SMC_OCMS_CS1SE (0x1 << 17) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
-#define SMC_OCMS_CS2SE (0x1 << 18) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
-#define SMC_OCMS_CS3SE (0x1 << 19) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
-/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */
-#define SMC_KEY1_KEY1 (0xffffffff << 0) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */
-/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */
-#define SMC_KEY2_KEY2 (0xffffffff << 0) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */
-/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */
-#define SMC_WPMR_WPEN (0x1 << 0) /**< \brief (SMC_WPMR) Write Protect Enable */
-#define SMC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SMC_WPMR) Write Protect KEY */
-/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */
-#define SMC_WPSR_WPVS (0x1 << 0) /**< \brief (SMC_WPSR) Write Protect Enable */
-#define SMC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SMC_WPSR) Write Protect Violation Source */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_SPI Serial Peripheral Interface */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Spi hardware registers */
-typedef struct {
- WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */
- RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */
- RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */
- WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */
- RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */
- WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */
- WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */
- RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */
- RwReg Reserved1[4];
- RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */
- RwReg Reserved2[41];
- RwReg SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */
- RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */
- RwReg Reserved3[5];
- RwReg SPI_RPR; /**< \brief (Spi Offset: 0x100) Receive Pointer Register */
- RwReg SPI_RCR; /**< \brief (Spi Offset: 0x104) Receive Counter Register */
- RwReg SPI_TPR; /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */
- RwReg SPI_TCR; /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */
- RwReg SPI_RNPR; /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */
- RwReg SPI_RNCR; /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */
- RwReg SPI_TNPR; /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */
- RwReg SPI_TNCR; /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */
- WoReg SPI_PTCR; /**< \brief (Spi Offset: 0x120) Transfer Control Register */
- RoReg SPI_PTSR; /**< \brief (Spi Offset: 0x124) Transfer Status Register */
-} Spi;
-#endif /* __ASSEMBLY__ */
-/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
-#define SPI_CR_SPIEN (0x1 << 0) /**< \brief (SPI_CR) SPI Enable */
-#define SPI_CR_SPIDIS (0x1 << 1) /**< \brief (SPI_CR) SPI Disable */
-#define SPI_CR_SWRST (0x1 << 7) /**< \brief (SPI_CR) SPI Software Reset */
-#define SPI_CR_LASTXFER (0x1 << 24) /**< \brief (SPI_CR) Last Transfer */
-/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
-#define SPI_MR_MSTR (0x1 << 0) /**< \brief (SPI_MR) Master/Slave Mode */
-#define SPI_MR_PS (0x1 << 1) /**< \brief (SPI_MR) Peripheral Select */
-#define SPI_MR_PS_FIXED (0x0 << 1) /**< \brief (SPI_MR) Fixed Peripheral Select. */
-#define SPI_MR_PS_VARIABLE (0x1 << 1) /**< \brief (SPI_MR) Variable Peripheral Select. */
-#define SPI_MR_PCSDEC (0x1 << 2) /**< \brief (SPI_MR) Chip Select Decode */
-#define SPI_MR_MODFDIS (0x1 << 4) /**< \brief (SPI_MR) Mode Fault Detection */
-#define SPI_MR_WDRBT (0x1 << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
-#define SPI_MR_LLB (0x1 << 7) /**< \brief (SPI_MR) Local Loopback Enable */
-#define SPI_MR_PCS (0xf << 16) /**< \brief (SPI_MR) Peripheral Chip Select */
-#define SPI_MR_DLYBCS (0xff << 24) /**< \brief (SPI_MR) Delay Between Chip Selects */
-/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
-#define SPI_RDR_RD (0xffff << 0) /**< \brief (SPI_RDR) Receive Data */
-#define SPI_RDR_PCS (0xf << 16) /**< \brief (SPI_RDR) Peripheral Chip Select */
-/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
-#define SPI_TDR_TD (0xffff << 0) /**< \brief (SPI_TDR) Transmit Data */
-#define SPI_TDR_PCS (0xf << 16) /**< \brief (SPI_TDR) Peripheral Chip Select */
-#define SPI_TDR_LASTXFER (0x1 << 24) /**< \brief (SPI_TDR) Last Transfer */
-/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
-#define SPI_SR_RDRF (0x1 << 0) /**< \brief (SPI_SR) Receive Data Register Full */
-#define SPI_SR_TDRE (0x1 << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */
-#define SPI_SR_MODF (0x1 << 2) /**< \brief (SPI_SR) Mode Fault Error */
-#define SPI_SR_OVRES (0x1 << 3) /**< \brief (SPI_SR) Overrun Error Status */
-#define SPI_SR_ENDRX (0x1 << 4) /**< \brief (SPI_SR) End of RX buffer */
-#define SPI_SR_ENDTX (0x1 << 5) /**< \brief (SPI_SR) End of TX buffer */
-#define SPI_SR_RXBUFF (0x1 << 6) /**< \brief (SPI_SR) RX Buffer Full */
-#define SPI_SR_TXBUFE (0x1 << 7) /**< \brief (SPI_SR) TX Buffer Empty */
-#define SPI_SR_NSSR (0x1 << 8) /**< \brief (SPI_SR) NSS Rising */
-#define SPI_SR_TXEMPTY (0x1 << 9) /**< \brief (SPI_SR) Transmission Registers Empty */
-#define SPI_SR_UNDES (0x1 << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */
-#define SPI_SR_SPIENS (0x1 << 16) /**< \brief (SPI_SR) SPI Enable Status */
-/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
-#define SPI_IER_RDRF (0x1 << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
-#define SPI_IER_TDRE (0x1 << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
-#define SPI_IER_MODF (0x1 << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
-#define SPI_IER_OVRES (0x1 << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
-#define SPI_IER_ENDRX (0x1 << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */
-#define SPI_IER_ENDTX (0x1 << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */
-#define SPI_IER_RXBUFF (0x1 << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */
-#define SPI_IER_TXBUFE (0x1 << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */
-#define SPI_IER_NSSR (0x1 << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
-#define SPI_IER_TXEMPTY (0x1 << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
-#define SPI_IER_UNDES (0x1 << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
-/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
-#define SPI_IDR_RDRF (0x1 << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
-#define SPI_IDR_TDRE (0x1 << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
-#define SPI_IDR_MODF (0x1 << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
-#define SPI_IDR_OVRES (0x1 << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
-#define SPI_IDR_ENDRX (0x1 << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */
-#define SPI_IDR_ENDTX (0x1 << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */
-#define SPI_IDR_RXBUFF (0x1 << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */
-#define SPI_IDR_TXBUFE (0x1 << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */
-#define SPI_IDR_NSSR (0x1 << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
-#define SPI_IDR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
-#define SPI_IDR_UNDES (0x1 << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
-/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
-#define SPI_IMR_RDRF (0x1 << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
-#define SPI_IMR_TDRE (0x1 << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
-#define SPI_IMR_MODF (0x1 << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
-#define SPI_IMR_OVRES (0x1 << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
-#define SPI_IMR_ENDRX (0x1 << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */
-#define SPI_IMR_ENDTX (0x1 << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */
-#define SPI_IMR_RXBUFF (0x1 << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */
-#define SPI_IMR_TXBUFE (0x1 << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */
-#define SPI_IMR_NSSR (0x1 << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
-#define SPI_IMR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
-#define SPI_IMR_UNDES (0x1 << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
-/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
-#define SPI_CSR_CPOL (0x1 << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */
-#define SPI_CSR_NCPHA (0x1 << 1) /**< \brief (SPI_CSR[4]) Clock Phase */
-#define SPI_CSR_CSNAAT (0x1 << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
-#define SPI_CSR_CSAAT (0x1 << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
-#define SPI_CSR_BITS (0xf << 4) /**< \brief (SPI_CSR[4]) Bits Per Transfer (See the (Note:) below the register table; Section 9.9 "SPI Chip Select Register" on page 35.) */
-#define SPI_CSR_BITS_8 (0x0 << 4) /**< \brief (SPI_CSR[4]) 8 */
-#define SPI_CSR_BITS_9 (0x1 << 4) /**< \brief (SPI_CSR[4]) 9 */
-#define SPI_CSR_BITS_10 (0x2 << 4) /**< \brief (SPI_CSR[4]) 10 */
-#define SPI_CSR_BITS_11 (0x3 << 4) /**< \brief (SPI_CSR[4]) 11 */
-#define SPI_CSR_BITS_12 (0x4 << 4) /**< \brief (SPI_CSR[4]) 12 */
-#define SPI_CSR_BITS_13 (0x5 << 4) /**< \brief (SPI_CSR[4]) 13 */
-#define SPI_CSR_BITS_14 (0x6 << 4) /**< \brief (SPI_CSR[4]) 14 */
-#define SPI_CSR_BITS_15 (0x7 << 4) /**< \brief (SPI_CSR[4]) 15 */
-#define SPI_CSR_BITS_16 (0x8 << 4) /**< \brief (SPI_CSR[4]) 16 */
-#define SPI_CSR_SCBR (0xff << 8) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */
-#define SPI_CSR_DLYBS (0xff << 16) /**< \brief (SPI_CSR[4]) Delay Before SPCK */
-#define SPI_CSR_DLYBCT (0xff << 24) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */
-/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */
-#define SPI_WPMR_SPIWPEN (0x1 << 0) /**< \brief (SPI_WPMR) SPI Write Protection Enable */
-#define SPI_WPMR_SPIWPKEY (0xffffff << 8) /**< \brief (SPI_WPMR) SPI Write Protection Key Password */
-/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
-#define SPI_WPSR_SPIWPVS (0x7 << 0) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */
-#define SPI_WPSR_SPIWPVSRC (0xff << 8) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */
-/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */
-#define SPI_RPR_RXPTR (0xffffffff << 0) /**< \brief (SPI_RPR) Receive Pointer Register */
-/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */
-#define SPI_RCR_RXCTR (0xffff << 0) /**< \brief (SPI_RCR) Receive Counter Register */
-/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */
-#define SPI_TPR_TXPTR (0xffffffff << 0) /**< \brief (SPI_TPR) Transmit Counter Register */
-/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */
-#define SPI_TCR_TXCTR (0xffff << 0) /**< \brief (SPI_TCR) Transmit Counter Register */
-/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */
-#define SPI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (SPI_RNPR) Receive Next Pointer */
-/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */
-#define SPI_RNCR_RXNCTR (0xffff << 0) /**< \brief (SPI_RNCR) Receive Next Counter */
-/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */
-#define SPI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (SPI_TNPR) Transmit Next Pointer */
-/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */
-#define SPI_TNCR_TXNCTR (0xffff << 0) /**< \brief (SPI_TNCR) Transmit Counter Next */
-/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */
-#define SPI_PTCR_RXTEN (0x1 << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */
-#define SPI_PTCR_RXTDIS (0x1 << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */
-#define SPI_PTCR_TXTEN (0x1 << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */
-#define SPI_PTCR_TXTDIS (0x1 << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */
-/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */
-#define SPI_PTSR_RXTEN (0x1 << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */
-#define SPI_PTSR_TXTEN (0x1 << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_SSC Synchronous Serial Controller */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Ssc hardware registers */
-typedef struct {
- WoReg SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */
- RwReg SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */
- RwReg Reserved1[2];
- RwReg SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */
- RwReg SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */
- RwReg SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */
- RwReg SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */
- RoReg SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */
- WoReg SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */
- RwReg Reserved2[2];
- RoReg SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */
- RwReg SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */
- RwReg SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */
- RwReg SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */
- RoReg SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */
- WoReg SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */
- WoReg SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */
- RoReg SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */
- RwReg Reserved3[37];
- RwReg SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */
- RoReg SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */
- RwReg Reserved4[5];
- RwReg SSC_RPR; /**< \brief (Ssc Offset: 0x100) Receive Pointer Register */
- RwReg SSC_RCR; /**< \brief (Ssc Offset: 0x104) Receive Counter Register */
- RwReg SSC_TPR; /**< \brief (Ssc Offset: 0x108) Transmit Pointer Register */
- RwReg SSC_TCR; /**< \brief (Ssc Offset: 0x10C) Transmit Counter Register */
- RwReg SSC_RNPR; /**< \brief (Ssc Offset: 0x110) Receive Next Pointer Register */
- RwReg SSC_RNCR; /**< \brief (Ssc Offset: 0x114) Receive Next Counter Register */
- RwReg SSC_TNPR; /**< \brief (Ssc Offset: 0x118) Transmit Next Pointer Register */
- RwReg SSC_TNCR; /**< \brief (Ssc Offset: 0x11C) Transmit Next Counter Register */
- WoReg SSC_PTCR; /**< \brief (Ssc Offset: 0x120) Transfer Control Register */
- RoReg SSC_PTSR; /**< \brief (Ssc Offset: 0x124) Transfer Status Register */
-} Ssc;
-#endif /* __ASSEMBLY__ */
-/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */
-#define SSC_CR_RXEN (0x1 << 0) /**< \brief (SSC_CR) Receive Enable */
-#define SSC_CR_RXDIS (0x1 << 1) /**< \brief (SSC_CR) Receive Disable */
-#define SSC_CR_TXEN (0x1 << 8) /**< \brief (SSC_CR) Transmit Enable */
-#define SSC_CR_TXDIS (0x1 << 9) /**< \brief (SSC_CR) Transmit Disable */
-#define SSC_CR_SWRST (0x1 << 15) /**< \brief (SSC_CR) Software Reset */
-/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */
-#define SSC_CMR_DIV (0xfff << 0) /**< \brief (SSC_CMR) Clock Divider */
-/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */
-#define SSC_RCMR_CKS (0x3 << 0) /**< \brief (SSC_RCMR) Receive Clock Selection */
-#define SSC_RCMR_CKS_DIV (0x0 << 0) /**< \brief (SSC_RCMR) Divided Clock */
-#define SSC_RCMR_CKS_TK (0x1 << 0) /**< \brief (SSC_RCMR) TK Clock signal */
-#define SSC_RCMR_CKS_RK (0x2 << 0) /**< \brief (SSC_RCMR) RK pin */
-#define SSC_RCMR_CKO (0x7 << 2) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */
-#define SSC_RCMR_CKI (0x1 << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */
-#define SSC_RCMR_CKG (0x3 << 6) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */
-#define SSC_RCMR_CKG_NONE (0x0 << 6) /**< \brief (SSC_RCMR) None, continuous clock */
-#define SSC_RCMR_CKG_LOW (0x1 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */
-#define SSC_RCMR_CKG_HIGH (0x2 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */
-#define SSC_RCMR_START (0xf << 8) /**< \brief (SSC_RCMR) Receive Start Selection */
-#define SSC_RCMR_STOP (0x1 << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */
-#define SSC_RCMR_STTDLY (0xff << 16) /**< \brief (SSC_RCMR) Receive Start Delay */
-#define SSC_RCMR_PERIOD (0xff << 24) /**< \brief (SSC_RCMR) Receive Period Divider Selection */
-/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */
-#define SSC_RFMR_DATLEN (0x1f << 0) /**< \brief (SSC_RFMR) Data Length */
-#define SSC_RFMR_LOOP (0x1 << 5) /**< \brief (SSC_RFMR) Loop Mode */
-#define SSC_RFMR_MSBF (0x1 << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */
-#define SSC_RFMR_DATNB (0xf << 8) /**< \brief (SSC_RFMR) Data Number per Frame */
-#define SSC_RFMR_FSLEN (0xf << 16) /**< \brief (SSC_RFMR) Receive Frame Sync Length */
-#define SSC_RFMR_FSOS (0x7 << 20) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */
-#define SSC_RFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */
-#define SSC_RFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_RFMR) FSLEN Field Extension */
-/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */
-#define SSC_TCMR_CKS (0x3 << 0) /**< \brief (SSC_TCMR) Transmit Clock Selection */
-#define SSC_TCMR_CKO (0x7 << 2) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */
-#define SSC_TCMR_CKI (0x1 << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */
-#define SSC_TCMR_CKG (0x3 << 6) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */
-#define SSC_TCMR_START (0xf << 8) /**< \brief (SSC_TCMR) Transmit Start Selection */
-#define SSC_TCMR_STTDLY (0xff << 16) /**< \brief (SSC_TCMR) Transmit Start Delay */
-#define SSC_TCMR_PERIOD (0xff << 24) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */
-/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */
-#define SSC_TFMR_DATLEN (0x1f << 0) /**< \brief (SSC_TFMR) Data Length */
-#define SSC_TFMR_DATDEF (0x1 << 5) /**< \brief (SSC_TFMR) Data Default Value */
-#define SSC_TFMR_MSBF (0x1 << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */
-#define SSC_TFMR_DATNB (0xf << 8) /**< \brief (SSC_TFMR) Data Number per frame */
-#define SSC_TFMR_FSLEN (0xf << 16) /**< \brief (SSC_TFMR) Transmit Frame Syn Length */
-#define SSC_TFMR_FSOS (0x7 << 20) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */
-#define SSC_TFMR_FSDEN (0x1 << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */
-#define SSC_TFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */
-#define SSC_TFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_TFMR) FSLEN Field Extension */
-/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */
-#define SSC_RHR_RDAT (0xffffffff << 0) /**< \brief (SSC_RHR) Receive Data */
-/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */
-#define SSC_THR_TDAT (0xffffffff << 0) /**< \brief (SSC_THR) Transmit Data */
-/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */
-#define SSC_RSHR_RSDAT (0xffff << 0) /**< \brief (SSC_RSHR) Receive Synchronization Data */
-/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */
-#define SSC_TSHR_TSDAT (0xffff << 0) /**< \brief (SSC_TSHR) Transmit Synchronization Data */
-/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */
-#define SSC_RC0R_CP0 (0xffff << 0) /**< \brief (SSC_RC0R) Receive Compare Data 0 */
-/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */
-#define SSC_RC1R_CP1 (0xffff << 0) /**< \brief (SSC_RC1R) Receive Compare Data 1 */
-/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */
-#define SSC_SR_TXRDY (0x1 << 0) /**< \brief (SSC_SR) Transmit Ready */
-#define SSC_SR_TXEMPTY (0x1 << 1) /**< \brief (SSC_SR) Transmit Empty */
-#define SSC_SR_ENDTX (0x1 << 2) /**< \brief (SSC_SR) End of Transmission */
-#define SSC_SR_TXBUFE (0x1 << 3) /**< \brief (SSC_SR) Transmit Buffer Empty */
-#define SSC_SR_RXRDY (0x1 << 4) /**< \brief (SSC_SR) Receive Ready */
-#define SSC_SR_OVRUN (0x1 << 5) /**< \brief (SSC_SR) Receive Overrun */
-#define SSC_SR_ENDRX (0x1 << 6) /**< \brief (SSC_SR) End of Reception */
-#define SSC_SR_RXBUFF (0x1 << 7) /**< \brief (SSC_SR) Receive Buffer Full */
-#define SSC_SR_CP0 (0x1 << 8) /**< \brief (SSC_SR) Compare 0 */
-#define SSC_SR_CP1 (0x1 << 9) /**< \brief (SSC_SR) Compare 1 */
-#define SSC_SR_TXSYN (0x1 << 10) /**< \brief (SSC_SR) Transmit Sync */
-#define SSC_SR_RXSYN (0x1 << 11) /**< \brief (SSC_SR) Receive Sync */
-#define SSC_SR_TXEN (0x1 << 16) /**< \brief (SSC_SR) Transmit Enable */
-#define SSC_SR_RXEN (0x1 << 17) /**< \brief (SSC_SR) Receive Enable */
-/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */
-#define SSC_IER_TXRDY (0x1 << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */
-#define SSC_IER_TXEMPTY (0x1 << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */
-#define SSC_IER_ENDTX (0x1 << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */
-#define SSC_IER_TXBUFE (0x1 << 3) /**< \brief (SSC_IER) Transmit Buffer Empty Interrupt Enable */
-#define SSC_IER_RXRDY (0x1 << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */
-#define SSC_IER_OVRUN (0x1 << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */
-#define SSC_IER_ENDRX (0x1 << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */
-#define SSC_IER_RXBUFF (0x1 << 7) /**< \brief (SSC_IER) Receive Buffer Full Interrupt Enable */
-#define SSC_IER_CP0 (0x1 << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */
-#define SSC_IER_CP1 (0x1 << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */
-#define SSC_IER_TXSYN (0x1 << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */
-#define SSC_IER_RXSYN (0x1 << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */
-/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */
-#define SSC_IDR_TXRDY (0x1 << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */
-#define SSC_IDR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */
-#define SSC_IDR_ENDTX (0x1 << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */
-#define SSC_IDR_TXBUFE (0x1 << 3) /**< \brief (SSC_IDR) Transmit Buffer Empty Interrupt Disable */
-#define SSC_IDR_RXRDY (0x1 << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */
-#define SSC_IDR_OVRUN (0x1 << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */
-#define SSC_IDR_ENDRX (0x1 << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */
-#define SSC_IDR_RXBUFF (0x1 << 7) /**< \brief (SSC_IDR) Receive Buffer Full Interrupt Disable */
-#define SSC_IDR_CP0 (0x1 << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */
-#define SSC_IDR_CP1 (0x1 << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */
-#define SSC_IDR_TXSYN (0x1 << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */
-#define SSC_IDR_RXSYN (0x1 << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */
-/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */
-#define SSC_IMR_TXRDY (0x1 << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */
-#define SSC_IMR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */
-#define SSC_IMR_ENDTX (0x1 << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */
-#define SSC_IMR_TXBUFE (0x1 << 3) /**< \brief (SSC_IMR) Transmit Buffer Empty Interrupt Mask */
-#define SSC_IMR_RXRDY (0x1 << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */
-#define SSC_IMR_OVRUN (0x1 << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */
-#define SSC_IMR_ENDRX (0x1 << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */
-#define SSC_IMR_RXBUFF (0x1 << 7) /**< \brief (SSC_IMR) Receive Buffer Full Interrupt Mask */
-#define SSC_IMR_CP0 (0x1 << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */
-#define SSC_IMR_CP1 (0x1 << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */
-#define SSC_IMR_TXSYN (0x1 << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */
-#define SSC_IMR_RXSYN (0x1 << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */
-/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */
-#define SSC_WPMR_WPEN (0x1 << 0) /**< \brief (SSC_WPMR) Write Protect Enable */
-#define SSC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SSC_WPMR) Write Protect KEY */
-/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */
-#define SSC_WPSR_WPVS (0x1 << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */
-#define SSC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SSC_WPSR) Write Protect Violation Source */
-/* -------- SSC_RPR : (SSC Offset: 0x100) Receive Pointer Register -------- */
-#define SSC_RPR_RXPTR (0xffffffff << 0) /**< \brief (SSC_RPR) Receive Pointer Register */
-/* -------- SSC_RCR : (SSC Offset: 0x104) Receive Counter Register -------- */
-#define SSC_RCR_RXCTR (0xffff << 0) /**< \brief (SSC_RCR) Receive Counter Register */
-/* -------- SSC_TPR : (SSC Offset: 0x108) Transmit Pointer Register -------- */
-#define SSC_TPR_TXPTR (0xffffffff << 0) /**< \brief (SSC_TPR) Transmit Counter Register */
-/* -------- SSC_TCR : (SSC Offset: 0x10C) Transmit Counter Register -------- */
-#define SSC_TCR_TXCTR (0xffff << 0) /**< \brief (SSC_TCR) Transmit Counter Register */
-/* -------- SSC_RNPR : (SSC Offset: 0x110) Receive Next Pointer Register -------- */
-#define SSC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (SSC_RNPR) Receive Next Pointer */
-/* -------- SSC_RNCR : (SSC Offset: 0x114) Receive Next Counter Register -------- */
-#define SSC_RNCR_RXNCTR (0xffff << 0) /**< \brief (SSC_RNCR) Receive Next Counter */
-/* -------- SSC_TNPR : (SSC Offset: 0x118) Transmit Next Pointer Register -------- */
-#define SSC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (SSC_TNPR) Transmit Next Pointer */
-/* -------- SSC_TNCR : (SSC Offset: 0x11C) Transmit Next Counter Register -------- */
-#define SSC_TNCR_TXNCTR (0xffff << 0) /**< \brief (SSC_TNCR) Transmit Counter Next */
-/* -------- SSC_PTCR : (SSC Offset: 0x120) Transfer Control Register -------- */
-#define SSC_PTCR_RXTEN (0x1 << 0) /**< \brief (SSC_PTCR) Receiver Transfer Enable */
-#define SSC_PTCR_RXTDIS (0x1 << 1) /**< \brief (SSC_PTCR) Receiver Transfer Disable */
-#define SSC_PTCR_TXTEN (0x1 << 8) /**< \brief (SSC_PTCR) Transmitter Transfer Enable */
-#define SSC_PTCR_TXTDIS (0x1 << 9) /**< \brief (SSC_PTCR) Transmitter Transfer Disable */
-/* -------- SSC_PTSR : (SSC Offset: 0x124) Transfer Status Register -------- */
-#define SSC_PTSR_RXTEN (0x1 << 0) /**< \brief (SSC_PTSR) Receiver Transfer Enable */
-#define SSC_PTSR_TXTEN (0x1 << 8) /**< \brief (SSC_PTSR) Transmitter Transfer Enable */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Supply Controller */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_SUPC Supply Controller */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Supc hardware registers */
-typedef struct {
- WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */
- RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */
- RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */
- RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */
- RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */
- RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */
-} Supc;
-#endif /* __ASSEMBLY__ */
-/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
-#define SUPC_CR_VROFF (0x1 << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */
-#define SUPC_CR_VROFF_NO_EFFECT (0x0 << 2) /**< \brief (SUPC_CR) no effect. */
-#define SUPC_CR_VROFF_STOP_VREG (0x1 << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */
-#define SUPC_CR_XTALSEL (0x1 << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */
-#define SUPC_CR_XTALSEL_NO_EFFECT (0x0 << 3) /**< \brief (SUPC_CR) no effect. */
-#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1 << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */
-#define SUPC_CR_KEY (0xff << 24) /**< \brief (SUPC_CR) Password */
-/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
-#define SUPC_SMMR_SMTH (0xf << 0) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */
-#define SUPC_SMMR_SMTH_1_9V (0x0 << 0) /**< \brief (SUPC_SMMR) 1.9 V */
-#define SUPC_SMMR_SMTH_2_0V (0x1 << 0) /**< \brief (SUPC_SMMR) 2.0 V */
-#define SUPC_SMMR_SMTH_2_1V (0x2 << 0) /**< \brief (SUPC_SMMR) 2.1 V */
-#define SUPC_SMMR_SMTH_2_2V (0x3 << 0) /**< \brief (SUPC_SMMR) 2.2 V */
-#define SUPC_SMMR_SMTH_2_3V (0x4 << 0) /**< \brief (SUPC_SMMR) 2.3 V */
-#define SUPC_SMMR_SMTH_2_4V (0x5 << 0) /**< \brief (SUPC_SMMR) 2.4 V */
-#define SUPC_SMMR_SMTH_2_5V (0x6 << 0) /**< \brief (SUPC_SMMR) 2.5 V */
-#define SUPC_SMMR_SMTH_2_6V (0x7 << 0) /**< \brief (SUPC_SMMR) 2.6 V */
-#define SUPC_SMMR_SMTH_2_7V (0x8 << 0) /**< \brief (SUPC_SMMR) 2.7 V */
-#define SUPC_SMMR_SMTH_2_8V (0x9 << 0) /**< \brief (SUPC_SMMR) 2.8 V */
-#define SUPC_SMMR_SMTH_2_9V (0xA << 0) /**< \brief (SUPC_SMMR) 2.9 V */
-#define SUPC_SMMR_SMTH_3_0V (0xB << 0) /**< \brief (SUPC_SMMR) 3.0 V */
-#define SUPC_SMMR_SMTH_3_1V (0xC << 0) /**< \brief (SUPC_SMMR) 3.1 V */
-#define SUPC_SMMR_SMTH_3_2V (0xD << 0) /**< \brief (SUPC_SMMR) 3.2 V */
-#define SUPC_SMMR_SMTH_3_3V (0xE << 0) /**< \brief (SUPC_SMMR) 3.3 V */
-#define SUPC_SMMR_SMTH_3_4V (0xF << 0) /**< \brief (SUPC_SMMR) 3.4 V */
-#define SUPC_SMMR_SMSMPL (0x7 << 8) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */
-#define SUPC_SMMR_SMSMPL_SMD (0x0 << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */
-#define SUPC_SMMR_SMSMPL_CSM (0x1 << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */
-#define SUPC_SMMR_SMSMPL_32SLCK (0x2 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */
-#define SUPC_SMMR_SMSMPL_256SLCK (0x3 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */
-#define SUPC_SMMR_SMSMPL_2048SLCK (0x4 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */
-#define SUPC_SMMR_SMRSTEN (0x1 << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */
-#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */
-#define SUPC_SMMR_SMRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */
-#define SUPC_SMMR_SMIEN (0x1 << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */
-#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */
-#define SUPC_SMMR_SMIEN_ENABLE (0x1 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */
-/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
-#define SUPC_MR_BODRSTEN (0x1 << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */
-#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */
-#define SUPC_MR_BODRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */
-#define SUPC_MR_BODDIS (0x1 << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */
-#define SUPC_MR_BODDIS_ENABLE (0x0 << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */
-#define SUPC_MR_BODDIS_DISABLE (0x1 << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */
-#define SUPC_MR_ONREG (0x1 << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */
-#define SUPC_MR_ONREG_ONREG_UNUSED (0x0 << 14) /**< \brief (SUPC_MR) Voltage Regulator is not used */
-#define SUPC_MR_ONREG_ONREG_USED (0x1 << 14) /**< \brief (SUPC_MR) Voltage Regulator is used */
-#define SUPC_MR_OSCBYPASS (0x1 << 20) /**< \brief (SUPC_MR) Oscillator Bypass */
-#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0 << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */
-#define SUPC_MR_OSCBYPASS_BYPASS (0x1 << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */
-#define SUPC_MR_KEY (0xff << 24) /**< \brief (SUPC_MR) Password Key */
-/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */
-#define SUPC_WUMR_SMEN (0x1 << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */
-#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */
-#define SUPC_WUMR_SMEN_ENABLE (0x1 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */
-#define SUPC_WUMR_RTTEN (0x1 << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */
-#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */
-#define SUPC_WUMR_RTTEN_ENABLE (0x1 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */
-#define SUPC_WUMR_RTCEN (0x1 << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */
-#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */
-#define SUPC_WUMR_RTCEN_ENABLE (0x1 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */
-#define SUPC_WUMR_WKUPDBC (0x7 << 12) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer */
-#define SUPC_WUMR_WKUPDBC_1SCLK (0x0 << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
-#define SUPC_WUMR_WKUPDBC_3SCLK (0x1 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 3 SLCK periods */
-#define SUPC_WUMR_WKUPDBC_32SCLK (0x2 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32 SLCK periods */
-#define SUPC_WUMR_WKUPDBC_512SCLK (0x3 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 512 SLCK periods */
-#define SUPC_WUMR_WKUPDBC_4096SCLK (0x4 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 4,096 SLCK periods */
-#define SUPC_WUMR_WKUPDBC_32768SCLK (0x5 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32,768 SLCK periods */
-/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */
-#define SUPC_WUIR_WKUPEN0 (0x1 << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */
-#define SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN0_ENABLE (0x1 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN1 (0x1 << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */
-#define SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN1_ENABLE (0x1 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN2 (0x1 << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */
-#define SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN2_ENABLE (0x1 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN3 (0x1 << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */
-#define SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN3_ENABLE (0x1 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN4 (0x1 << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */
-#define SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN4_ENABLE (0x1 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN5 (0x1 << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */
-#define SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN5_ENABLE (0x1 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN6 (0x1 << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */
-#define SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN6_ENABLE (0x1 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN7 (0x1 << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */
-#define SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN7_ENABLE (0x1 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN8 (0x1 << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */
-#define SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN8_ENABLE (0x1 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN9 (0x1 << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */
-#define SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN9_ENABLE (0x1 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN10 (0x1 << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */
-#define SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN10_ENABLE (0x1 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN11 (0x1 << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */
-#define SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN11_ENABLE (0x1 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN12 (0x1 << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */
-#define SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN12_ENABLE (0x1 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN13 (0x1 << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */
-#define SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN13_ENABLE (0x1 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN14 (0x1 << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */
-#define SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN14_ENABLE (0x1 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN15 (0x1 << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */
-#define SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN15_ENABLE (0x1 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT0 (0x1 << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */
-#define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0 << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1 << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT1 (0x1 << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */
-#define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0 << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1 << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT2 (0x1 << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */
-#define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0 << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1 << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT3 (0x1 << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */
-#define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0 << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1 << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT4 (0x1 << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */
-#define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0 << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1 << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT5 (0x1 << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */
-#define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0 << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1 << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT6 (0x1 << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */
-#define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0 << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1 << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT7 (0x1 << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */
-#define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0 << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1 << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT8 (0x1 << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */
-#define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0 << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1 << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT9 (0x1 << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */
-#define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0 << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1 << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT10 (0x1 << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */
-#define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0 << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1 << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT11 (0x1 << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */
-#define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0 << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1 << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT12 (0x1 << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */
-#define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0 << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1 << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT13 (0x1 << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */
-#define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0 << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1 << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT14 (0x1 << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */
-#define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0 << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1 << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT15 (0x1 << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */
-#define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0 << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1 << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
-#define SUPC_SR_WKUPS (0x1 << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */
-#define SUPC_SR_WKUPS_NO (0x0 << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPS_PRESENT (0x1 << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_SMWS (0x1 << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */
-#define SUPC_SR_SMWS_NO (0x0 << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_SMWS_PRESENT (0x1 << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_BODRSTS (0x1 << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */
-#define SUPC_SR_BODRSTS_NO (0x0 << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */
-#define SUPC_SR_BODRSTS_PRESENT (0x1 << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */
-#define SUPC_SR_SMRSTS (0x1 << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */
-#define SUPC_SR_SMRSTS_NO (0x0 << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
-#define SUPC_SR_SMRSTS_PRESENT (0x1 << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
-#define SUPC_SR_SMS (0x1 << 5) /**< \brief (SUPC_SR) Supply Monitor Status */
-#define SUPC_SR_SMS_NO (0x0 << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */
-#define SUPC_SR_SMS_PRESENT (0x1 << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */
-#define SUPC_SR_SMOS (0x1 << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */
-#define SUPC_SR_SMOS_HIGH (0x0 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */
-#define SUPC_SR_SMOS_LOW (0x1 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */
-#define SUPC_SR_OSCSEL (0x1 << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */
-#define SUPC_SR_OSCSEL_RC (0x0 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */
-#define SUPC_SR_OSCSEL_CRYST (0x1 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */
-#define SUPC_SR_WKUPIS0 (0x1 << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */
-#define SUPC_SR_WKUPIS0_DIS (0x0 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS0_EN (0x1 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS1 (0x1 << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */
-#define SUPC_SR_WKUPIS1_DIS (0x0 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS1_EN (0x1 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS2 (0x1 << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */
-#define SUPC_SR_WKUPIS2_DIS (0x0 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS2_EN (0x1 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS3 (0x1 << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */
-#define SUPC_SR_WKUPIS3_DIS (0x0 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS3_EN (0x1 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS4 (0x1 << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */
-#define SUPC_SR_WKUPIS4_DIS (0x0 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS4_EN (0x1 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS5 (0x1 << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */
-#define SUPC_SR_WKUPIS5_DIS (0x0 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS5_EN (0x1 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS6 (0x1 << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */
-#define SUPC_SR_WKUPIS6_DIS (0x0 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS6_EN (0x1 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS7 (0x1 << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */
-#define SUPC_SR_WKUPIS7_DIS (0x0 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS7_EN (0x1 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS8 (0x1 << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */
-#define SUPC_SR_WKUPIS8_DIS (0x0 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS8_EN (0x1 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS9 (0x1 << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */
-#define SUPC_SR_WKUPIS9_DIS (0x0 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS9_EN (0x1 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS10 (0x1 << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */
-#define SUPC_SR_WKUPIS10_DIS (0x0 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS10_EN (0x1 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS11 (0x1 << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */
-#define SUPC_SR_WKUPIS11_DIS (0x0 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS11_EN (0x1 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS12 (0x1 << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */
-#define SUPC_SR_WKUPIS12_DIS (0x0 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS12_EN (0x1 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS13 (0x1 << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */
-#define SUPC_SR_WKUPIS13_DIS (0x0 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS13_EN (0x1 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS14 (0x1 << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */
-#define SUPC_SR_WKUPIS14_DIS (0x0 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS14_EN (0x1 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS15 (0x1 << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */
-#define SUPC_SR_WKUPIS15_DIS (0x0 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS15_EN (0x1 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Timer Counter */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_TC Timer Counter */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief TcChannel hardware registers */
-typedef struct {
- RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
- RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
- RwReg Reserved1[2];
- RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */
- RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */
- RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */
- RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */
- RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */
- RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
- RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
- RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
- RwReg Reserved2[4];
-} TcChannel;
-/** \brief Tc hardware registers */
-typedef struct {
- TcChannel TC_CHANNEL[3]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
- WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */
- RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */
- WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */
- WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */
- RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */
- RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */
- RwReg TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */
- RwReg Reserved1[2];
- RwReg TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */
- RwReg Reserved2[5];
- RoReg TC_VER; /**< \brief (Tc Offset: 0xFC) Version Register */
-} Tc;
-#endif /* __ASSEMBLY__ */
-/* -------- TC_CCR0 : (TC Offset: 0x0) Channel Control Register (channel = 0) -------- */
-#define TC_CCR0_CLKEN (0x1 << 0) /**< \brief (TC_CCR0) Counter Clock Enable Command */
-#define TC_CCR0_CLKDIS (0x1 << 1) /**< \brief (TC_CCR0) Counter Clock Disable Command */
-#define TC_CCR0_SWTRG (0x1 << 2) /**< \brief (TC_CCR0) Software Trigger Command */
-/* -------- TC_CMR0 : (TC Offset: 0x4) Channel Mode Register (channel = 0) -------- */
-#define TC_CMR0_TCCLKS (0x7 << 0) /**< \brief (TC_CMR0) Clock Selection */
-#define TC_CM0_TCCLKS_TIMER_DIV1_CLOCK (0x0 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV1_CLOCK*/
-#define TC_CM0_TCCLKS_TIMER_DIV2_CLOCK (0x1 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV2_CLOCK*/
-#define TC_CM0_TCCLKS_TIMER_DIV3_CLOCK (0x2 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV3_CLOCK*/
-#define TC_CM0_TCCLKS_TIMER_DIV4_CLOCK (0x3 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV4_CLOCK*/
-#define TC_CM0_TCCLKS_TIMER_DIV5_CLOCK (0x4 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV5_CLOCK*/
-#define TC_CM0_TCCLKS_XC0 (0x5 << 0) /**< (TC_CMR0) Clock selected: XC0*/
-#define TC_CM0_TCCLKS_XC1 (0x6 << 0) /**< (TC_CMR0) Clock selected: XC1*/
-#define TC_CM0_TCCLKS_XC2 (0x7 << 0) /**< (TC_CMR0) Clock selected: XC2*/
-#define TC_CMR0_CLKI (0x1 << 3) /**< \brief (TC_CMR0) Clock Invert */
-#define TC_CMR0_BURST (0x3 << 4) /**< \brief (TC_CMR0) Burst Signal Selection */
-#define TC_CMR0_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR0) The clock is not gated by an external signal. */
-#define TC_CMR0_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR0) XC0 is ANDed with the selected clock. */
-#define TC_CMR0_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR0) XC1 is ANDed with the selected clock. */
-#define TC_CMR0_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR0) XC2 is ANDed with the selected clock. */
-#define TC_CMR0_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR0) Counter Clock Stopped with RB Loading */
-#define TC_CMR0_LDBDIS (0x1 << 7) /**< \brief (TC_CMR0) Counter Clock Disable with RB Loading */
-#define TC_CMR0_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR0) External Trigger Edge Selection */
-#define TC_CMR0_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR0) none */
-#define TC_CMR0_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR0) rising edge */
-#define TC_CMR0_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR0) falling edge */
-#define TC_CMR0_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR0) each edge */
-#define TC_CMR0_ABETRG (0x1 << 10) /**< \brief (TC_CMR0) TIOA or TIOB External Trigger Selection */
-#define TC_CMR0_CPCTRG (0x1 << 14) /**< \brief (TC_CMR0) RC Compare Trigger Enable */
-#define TC_CMR0_WAVE (0x1 << 15) /**< \brief (TC_CMR0) */
-#define TC_CMR0_LDRA (0x3 << 16) /**< \brief (TC_CMR0) RA Loading Selection */
-#define TC_CMR0_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR0) none */
-#define TC_CMR0_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR0) rising edge of TIOA */
-#define TC_CMR0_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR0) falling edge of TIOA */
-#define TC_CMR0_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR0) each edge of TIOA */
-#define TC_CMR0_LDRB (0x3 << 18) /**< \brief (TC_CMR0) RB Loading Selection */
-#define TC_CMR0_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR0) none */
-#define TC_CMR0_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR0) rising edge of TIOA */
-#define TC_CMR0_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR0) falling edge of TIOA */
-#define TC_CMR0_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR0) each edge of TIOA */
-
-#define TC_CMR0_ACPA_NONE (0x0 << 16) // (TC) Effect: none
-#define TC_CMR0_ACPA_SET (0x1 << 16) // (TC) Effect: set
-#define TC_CMR0_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
-#define TC_CMR0_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
-
-#define TC_CMR0_ACPC_NONE (0x0 << 18) // (TC) Effect: none
-#define TC_CMR0_ACPC_SET (0x1 << 18) // (TC) Effect: set
-#define TC_CMR0_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
-#define TC_CMR0_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
-/* -------- TC_CV0 : (TC Offset: 0x10) Counter Value (channel = 0) -------- */
-#define TC_CV0_CV (0xffff << 0) /**< \brief (TC_CV0) Counter Value */
-/* -------- TC_RA0 : (TC Offset: 0x14) Register A (channel = 0) -------- */
-#define TC_RA0_RA (0xffff << 0) /**< \brief (TC_RA0) Register A */
-/* -------- TC_RB0 : (TC Offset: 0x18) Register B (channel = 0) -------- */
-#define TC_RB0_RB (0xffff << 0) /**< \brief (TC_RB0) Register B */
-/* -------- TC_RC0 : (TC Offset: 0x1C) Register C (channel = 0) -------- */
-#define TC_RC0_RC (0xffff << 0) /**< \brief (TC_RC0) Register C */
-/* -------- TC_SR0 : (TC Offset: 0x20) Status Register (channel = 0) -------- */
-#define TC_SR0_COVFS (0x1 << 0) /**< \brief (TC_SR0) Counter Overflow Status */
-#define TC_SR0_LOVRS (0x1 << 1) /**< \brief (TC_SR0) Load Overrun Status */
-#define TC_SR0_CPAS (0x1 << 2) /**< \brief (TC_SR0) RA Compare Status */
-#define TC_SR0_CPBS (0x1 << 3) /**< \brief (TC_SR0) RB Compare Status */
-#define TC_SR0_CPCS (0x1 << 4) /**< \brief (TC_SR0) RC Compare Status */
-#define TC_SR0_LDRAS (0x1 << 5) /**< \brief (TC_SR0) RA Loading Status */
-#define TC_SR0_LDRBS (0x1 << 6) /**< \brief (TC_SR0) RB Loading Status */
-#define TC_SR0_ETRGS (0x1 << 7) /**< \brief (TC_SR0) External Trigger Status */
-#define TC_SR0_CLKSTA (0x1 << 16) /**< \brief (TC_SR0) Clock Enabling Status */
-#define TC_SR0_MTIOA (0x1 << 17) /**< \brief (TC_SR0) TIOA Mirror */
-#define TC_SR0_MTIOB (0x1 << 18) /**< \brief (TC_SR0) TIOB Mirror */
-/* -------- TC_IER0 : (TC Offset: 0x24) Interrupt Enable Register (channel = 0) -------- */
-#define TC_IER0_COVFS (0x1 << 0) /**< \brief (TC_IER0) Counter Overflow */
-#define TC_IER0_LOVRS (0x1 << 1) /**< \brief (TC_IER0) Load Overrun */
-#define TC_IER0_CPAS (0x1 << 2) /**< \brief (TC_IER0) RA Compare */
-#define TC_IER0_CPBS (0x1 << 3) /**< \brief (TC_IER0) RB Compare */
-#define TC_IER0_CPCS (0x1 << 4) /**< \brief (TC_IER0) RC Compare */
-#define TC_IER0_LDRAS (0x1 << 5) /**< \brief (TC_IER0) RA Loading */
-#define TC_IER0_LDRBS (0x1 << 6) /**< \brief (TC_IER0) RB Loading */
-#define TC_IER0_ETRGS (0x1 << 7) /**< \brief (TC_IER0) External Trigger */
-/* -------- TC_IDR0 : (TC Offset: 0x28) Interrupt Disable Register (channel = 0) -------- */
-#define TC_IDR0_COVFS (0x1 << 0) /**< \brief (TC_IDR0) Counter Overflow */
-#define TC_IDR0_LOVRS (0x1 << 1) /**< \brief (TC_IDR0) Load Overrun */
-#define TC_IDR0_CPAS (0x1 << 2) /**< \brief (TC_IDR0) RA Compare */
-#define TC_IDR0_CPBS (0x1 << 3) /**< \brief (TC_IDR0) RB Compare */
-#define TC_IDR0_CPCS (0x1 << 4) /**< \brief (TC_IDR0) RC Compare */
-#define TC_IDR0_LDRAS (0x1 << 5) /**< \brief (TC_IDR0) RA Loading */
-#define TC_IDR0_LDRBS (0x1 << 6) /**< \brief (TC_IDR0) RB Loading */
-#define TC_IDR0_ETRGS (0x1 << 7) /**< \brief (TC_IDR0) External Trigger */
-/* -------- TC_IMR0 : (TC Offset: 0x2C) Interrupt Mask Register (channel = 0) -------- */
-#define TC_IMR0_COVFS (0x1 << 0) /**< \brief (TC_IMR0) Counter Overflow */
-#define TC_IMR0_LOVRS (0x1 << 1) /**< \brief (TC_IMR0) Load Overrun */
-#define TC_IMR0_CPAS (0x1 << 2) /**< \brief (TC_IMR0) RA Compare */
-#define TC_IMR0_CPBS (0x1 << 3) /**< \brief (TC_IMR0) RB Compare */
-#define TC_IMR0_CPCS (0x1 << 4) /**< \brief (TC_IMR0) RC Compare */
-#define TC_IMR0_LDRAS (0x1 << 5) /**< \brief (TC_IMR0) RA Loading */
-#define TC_IMR0_LDRBS (0x1 << 6) /**< \brief (TC_IMR0) RB Loading */
-#define TC_IMR0_ETRGS (0x1 << 7) /**< \brief (TC_IMR0) External Trigger */
-/* -------- TC_CCR1 : (TC Offset: 0x40) Channel Control Register (channel = 1) -------- */
-#define TC_CCR1_CLKEN (0x1 << 0) /**< \brief (TC_CCR1) Counter Clock Enable Command */
-#define TC_CCR1_CLKDIS (0x1 << 1) /**< \brief (TC_CCR1) Counter Clock Disable Command */
-#define TC_CCR1_SWTRG (0x1 << 2) /**< \brief (TC_CCR1) Software Trigger Command */
-/* -------- TC_CMR1 : (TC Offset: 0x44) Channel Mode Register (channel = 1) -------- */
-#define TC_CMR1_TCCLKS (0x7 << 0) /**< \brief (TC_CMR1) Clock Selection */
-#define TC_CMR1_CLKI (0x1 << 3) /**< \brief (TC_CMR1) Clock Invert */
-#define TC_CMR1_BURST (0x3 << 4) /**< \brief (TC_CMR1) Burst Signal Selection */
-#define TC_CMR1_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR1) The clock is not gated by an external signal. */
-#define TC_CMR1_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR1) XC0 is ANDed with the selected clock. */
-#define TC_CMR1_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR1) XC1 is ANDed with the selected clock. */
-#define TC_CMR1_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR1) XC2 is ANDed with the selected clock. */
-#define TC_CMR1_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR1) Counter Clock Stopped with RB Loading */
-#define TC_CMR1_LDBDIS (0x1 << 7) /**< \brief (TC_CMR1) Counter Clock Disable with RB Loading */
-#define TC_CMR1_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR1) External Trigger Edge Selection */
-#define TC_CMR1_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR1) none */
-#define TC_CMR1_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR1) rising edge */
-#define TC_CMR1_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR1) falling edge */
-#define TC_CMR1_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR1) each edge */
-#define TC_CMR1_ABETRG (0x1 << 10) /**< \brief (TC_CMR1) TIOA or TIOB External Trigger Selection */
-#define TC_CMR1_CPCTRG (0x1 << 14) /**< \brief (TC_CMR1) RC Compare Trigger Enable */
-#define TC_CMR1_WAVE (0x1 << 15) /**< \brief (TC_CMR1) */
-#define TC_CMR1_LDRA (0x3 << 16) /**< \brief (TC_CMR1) RA Loading Selection */
-#define TC_CMR1_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR1) none */
-#define TC_CMR1_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR1) rising edge of TIOA */
-#define TC_CMR1_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR1) falling edge of TIOA */
-#define TC_CMR1_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR1) each edge of TIOA */
-#define TC_CMR1_LDRB (0x3 << 18) /**< \brief (TC_CMR1) RB Loading Selection */
-#define TC_CMR1_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR1) none */
-#define TC_CMR1_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR1) rising edge of TIOA */
-#define TC_CMR1_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR1) falling edge of TIOA */
-#define TC_CMR1_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR1) each edge of TIOA */
-/* -------- TC_CV1 : (TC Offset: 0x50) Counter Value (channel = 1) -------- */
-#define TC_CV1_CV (0xffff << 0) /**< \brief (TC_CV1) Counter Value */
-/* -------- TC_RA1 : (TC Offset: 0x54) Register A (channel = 1) -------- */
-#define TC_RA1_RA (0xffff << 0) /**< \brief (TC_RA1) Register A */
-/* -------- TC_RB1 : (TC Offset: 0x58) Register B (channel = 1) -------- */
-#define TC_RB1_RB (0xffff << 0) /**< \brief (TC_RB1) Register B */
-/* -------- TC_RC1 : (TC Offset: 0x5C) Register C (channel = 1) -------- */
-#define TC_RC1_RC (0xffff << 0) /**< \brief (TC_RC1) Register C */
-/* -------- TC_SR1 : (TC Offset: 0x60) Status Register (channel = 1) -------- */
-#define TC_SR1_COVFS (0x1 << 0) /**< \brief (TC_SR1) Counter Overflow Status */
-#define TC_SR1_LOVRS (0x1 << 1) /**< \brief (TC_SR1) Load Overrun Status */
-#define TC_SR1_CPAS (0x1 << 2) /**< \brief (TC_SR1) RA Compare Status */
-#define TC_SR1_CPBS (0x1 << 3) /**< \brief (TC_SR1) RB Compare Status */
-#define TC_SR1_CPCS (0x1 << 4) /**< \brief (TC_SR1) RC Compare Status */
-#define TC_SR1_LDRAS (0x1 << 5) /**< \brief (TC_SR1) RA Loading Status */
-#define TC_SR1_LDRBS (0x1 << 6) /**< \brief (TC_SR1) RB Loading Status */
-#define TC_SR1_ETRGS (0x1 << 7) /**< \brief (TC_SR1) External Trigger Status */
-#define TC_SR1_CLKSTA (0x1 << 16) /**< \brief (TC_SR1) Clock Enabling Status */
-#define TC_SR1_MTIOA (0x1 << 17) /**< \brief (TC_SR1) TIOA Mirror */
-#define TC_SR1_MTIOB (0x1 << 18) /**< \brief (TC_SR1) TIOB Mirror */
-/* -------- TC_IER1 : (TC Offset: 0x64) Interrupt Enable Register (channel = 1) -------- */
-#define TC_IER1_COVFS (0x1 << 0) /**< \brief (TC_IER1) Counter Overflow */
-#define TC_IER1_LOVRS (0x1 << 1) /**< \brief (TC_IER1) Load Overrun */
-#define TC_IER1_CPAS (0x1 << 2) /**< \brief (TC_IER1) RA Compare */
-#define TC_IER1_CPBS (0x1 << 3) /**< \brief (TC_IER1) RB Compare */
-#define TC_IER1_CPCS (0x1 << 4) /**< \brief (TC_IER1) RC Compare */
-#define TC_IER1_LDRAS (0x1 << 5) /**< \brief (TC_IER1) RA Loading */
-#define TC_IER1_LDRBS (0x1 << 6) /**< \brief (TC_IER1) RB Loading */
-#define TC_IER1_ETRGS (0x1 << 7) /**< \brief (TC_IER1) External Trigger */
-/* -------- TC_IDR1 : (TC Offset: 0x68) Interrupt Disable Register (channel = 1) -------- */
-#define TC_IDR1_COVFS (0x1 << 0) /**< \brief (TC_IDR1) Counter Overflow */
-#define TC_IDR1_LOVRS (0x1 << 1) /**< \brief (TC_IDR1) Load Overrun */
-#define TC_IDR1_CPAS (0x1 << 2) /**< \brief (TC_IDR1) RA Compare */
-#define TC_IDR1_CPBS (0x1 << 3) /**< \brief (TC_IDR1) RB Compare */
-#define TC_IDR1_CPCS (0x1 << 4) /**< \brief (TC_IDR1) RC Compare */
-#define TC_IDR1_LDRAS (0x1 << 5) /**< \brief (TC_IDR1) RA Loading */
-#define TC_IDR1_LDRBS (0x1 << 6) /**< \brief (TC_IDR1) RB Loading */
-#define TC_IDR1_ETRGS (0x1 << 7) /**< \brief (TC_IDR1) External Trigger */
-/* -------- TC_IMR1 : (TC Offset: 0x6C) Interrupt Mask Register (channel = 1) -------- */
-#define TC_IMR1_COVFS (0x1 << 0) /**< \brief (TC_IMR1) Counter Overflow */
-#define TC_IMR1_LOVRS (0x1 << 1) /**< \brief (TC_IMR1) Load Overrun */
-#define TC_IMR1_CPAS (0x1 << 2) /**< \brief (TC_IMR1) RA Compare */
-#define TC_IMR1_CPBS (0x1 << 3) /**< \brief (TC_IMR1) RB Compare */
-#define TC_IMR1_CPCS (0x1 << 4) /**< \brief (TC_IMR1) RC Compare */
-#define TC_IMR1_LDRAS (0x1 << 5) /**< \brief (TC_IMR1) RA Loading */
-#define TC_IMR1_LDRBS (0x1 << 6) /**< \brief (TC_IMR1) RB Loading */
-#define TC_IMR1_ETRGS (0x1 << 7) /**< \brief (TC_IMR1) External Trigger */
-/* -------- TC_CCR2 : (TC Offset: 0x80) Channel Control Register (channel = 2) -------- */
-#define TC_CCR2_CLKEN (0x1 << 0) /**< \brief (TC_CCR2) Counter Clock Enable Command */
-#define TC_CCR2_CLKDIS (0x1 << 1) /**< \brief (TC_CCR2) Counter Clock Disable Command */
-#define TC_CCR2_SWTRG (0x1 << 2) /**< \brief (TC_CCR2) Software Trigger Command */
-/* -------- TC_CMR2 : (TC Offset: 0x84) Channel Mode Register (channel = 2) -------- */
-#define TC_CMR2_TCCLKS (0x7 << 0) /**< \brief (TC_CMR2) Clock Selection */
-#define TC_CMR2_CLKI (0x1 << 3) /**< \brief (TC_CMR2) Clock Invert */
-#define TC_CMR2_BURST (0x3 << 4) /**< \brief (TC_CMR2) Burst Signal Selection */
-#define TC_CMR2_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR2) The clock is not gated by an external signal. */
-#define TC_CMR2_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR2) XC0 is ANDed with the selected clock. */
-#define TC_CMR2_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR2) XC1 is ANDed with the selected clock. */
-#define TC_CMR2_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR2) XC2 is ANDed with the selected clock. */
-#define TC_CMR2_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR2) Counter Clock Stopped with RB Loading */
-#define TC_CMR2_LDBDIS (0x1 << 7) /**< \brief (TC_CMR2) Counter Clock Disable with RB Loading */
-#define TC_CMR2_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR2) External Trigger Edge Selection */
-#define TC_CMR2_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR2) none */
-#define TC_CMR2_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR2) rising edge */
-#define TC_CMR2_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR2) falling edge */
-#define TC_CMR2_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR2) each edge */
-#define TC_CMR2_ABETRG (0x1 << 10) /**< \brief (TC_CMR2) TIOA or TIOB External Trigger Selection */
-#define TC_CMR2_CPCTRG (0x1 << 14) /**< \brief (TC_CMR2) RC Compare Trigger Enable */
-#define TC_CMR2_WAVE (0x1 << 15) /**< \brief (TC_CMR2) */
-#define TC_CMR2_LDRA (0x3 << 16) /**< \brief (TC_CMR2) RA Loading Selection */
-#define TC_CMR2_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR2) none */
-#define TC_CMR2_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR2) rising edge of TIOA */
-#define TC_CMR2_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR2) falling edge of TIOA */
-#define TC_CMR2_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR2) each edge of TIOA */
-#define TC_CMR2_LDRB (0x3 << 18) /**< \brief (TC_CMR2) RB Loading Selection */
-#define TC_CMR2_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR2) none */
-#define TC_CMR2_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR2) rising edge of TIOA */
-#define TC_CMR2_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR2) falling edge of TIOA */
-#define TC_CMR2_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR2) each edge of TIOA */
-/* -------- TC_CV2 : (TC Offset: 0x90) Counter Value (channel = 2) -------- */
-#define TC_CV2_CV (0xffff << 0) /**< \brief (TC_CV2) Counter Value */
-/* -------- TC_RA2 : (TC Offset: 0x94) Register A (channel = 2) -------- */
-#define TC_RA2_RA (0xffff << 0) /**< \brief (TC_RA2) Register A */
-/* -------- TC_RB2 : (TC Offset: 0x98) Register B (channel = 2) -------- */
-#define TC_RB2_RB (0xffff << 0) /**< \brief (TC_RB2) Register B */
-/* -------- TC_RC2 : (TC Offset: 0x9C) Register C (channel = 2) -------- */
-#define TC_RC2_RC (0xffff << 0) /**< \brief (TC_RC2) Register C */
-/* -------- TC_SR2 : (TC Offset: 0xA0) Status Register (channel = 2) -------- */
-#define TC_SR2_COVFS (0x1 << 0) /**< \brief (TC_SR2) Counter Overflow Status */
-#define TC_SR2_LOVRS (0x1 << 1) /**< \brief (TC_SR2) Load Overrun Status */
-#define TC_SR2_CPAS (0x1 << 2) /**< \brief (TC_SR2) RA Compare Status */
-#define TC_SR2_CPBS (0x1 << 3) /**< \brief (TC_SR2) RB Compare Status */
-#define TC_SR2_CPCS (0x1 << 4) /**< \brief (TC_SR2) RC Compare Status */
-#define TC_SR2_LDRAS (0x1 << 5) /**< \brief (TC_SR2) RA Loading Status */
-#define TC_SR2_LDRBS (0x1 << 6) /**< \brief (TC_SR2) RB Loading Status */
-#define TC_SR2_ETRGS (0x1 << 7) /**< \brief (TC_SR2) External Trigger Status */
-#define TC_SR2_CLKSTA (0x1 << 16) /**< \brief (TC_SR2) Clock Enabling Status */
-#define TC_SR2_MTIOA (0x1 << 17) /**< \brief (TC_SR2) TIOA Mirror */
-#define TC_SR2_MTIOB (0x1 << 18) /**< \brief (TC_SR2) TIOB Mirror */
-/* -------- TC_IER2 : (TC Offset: 0xA4) Interrupt Enable Register (channel = 2) -------- */
-#define TC_IER2_COVFS (0x1 << 0) /**< \brief (TC_IER2) Counter Overflow */
-#define TC_IER2_LOVRS (0x1 << 1) /**< \brief (TC_IER2) Load Overrun */
-#define TC_IER2_CPAS (0x1 << 2) /**< \brief (TC_IER2) RA Compare */
-#define TC_IER2_CPBS (0x1 << 3) /**< \brief (TC_IER2) RB Compare */
-#define TC_IER2_CPCS (0x1 << 4) /**< \brief (TC_IER2) RC Compare */
-#define TC_IER2_LDRAS (0x1 << 5) /**< \brief (TC_IER2) RA Loading */
-#define TC_IER2_LDRBS (0x1 << 6) /**< \brief (TC_IER2) RB Loading */
-#define TC_IER2_ETRGS (0x1 << 7) /**< \brief (TC_IER2) External Trigger */
-/* -------- TC_IDR2 : (TC Offset: 0xA8) Interrupt Disable Register (channel = 2) -------- */
-#define TC_IDR2_COVFS (0x1 << 0) /**< \brief (TC_IDR2) Counter Overflow */
-#define TC_IDR2_LOVRS (0x1 << 1) /**< \brief (TC_IDR2) Load Overrun */
-#define TC_IDR2_CPAS (0x1 << 2) /**< \brief (TC_IDR2) RA Compare */
-#define TC_IDR2_CPBS (0x1 << 3) /**< \brief (TC_IDR2) RB Compare */
-#define TC_IDR2_CPCS (0x1 << 4) /**< \brief (TC_IDR2) RC Compare */
-#define TC_IDR2_LDRAS (0x1 << 5) /**< \brief (TC_IDR2) RA Loading */
-#define TC_IDR2_LDRBS (0x1 << 6) /**< \brief (TC_IDR2) RB Loading */
-#define TC_IDR2_ETRGS (0x1 << 7) /**< \brief (TC_IDR2) External Trigger */
-/* -------- TC_IMR2 : (TC Offset: 0xAC) Interrupt Mask Register (channel = 2) -------- */
-#define TC_IMR2_COVFS (0x1 << 0) /**< \brief (TC_IMR2) Counter Overflow */
-#define TC_IMR2_LOVRS (0x1 << 1) /**< \brief (TC_IMR2) Load Overrun */
-#define TC_IMR2_CPAS (0x1 << 2) /**< \brief (TC_IMR2) RA Compare */
-#define TC_IMR2_CPBS (0x1 << 3) /**< \brief (TC_IMR2) RB Compare */
-#define TC_IMR2_CPCS (0x1 << 4) /**< \brief (TC_IMR2) RC Compare */
-#define TC_IMR2_LDRAS (0x1 << 5) /**< \brief (TC_IMR2) RA Loading */
-#define TC_IMR2_LDRBS (0x1 << 6) /**< \brief (TC_IMR2) RB Loading */
-#define TC_IMR2_ETRGS (0x1 << 7) /**< \brief (TC_IMR2) External Trigger */
-/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
-#define TC_BCR_SYNC (0x1 << 0) /**< \brief (TC_BCR) Synchro Command */
-/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
-#define TC_BMR_TC0XC0S (0x3 << 0) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
-#define TC_BMR_TC0XC0S_TCLK0 (0x0 << 0) /**< \brief (TC_BMR) TCLK0 */
-#define TC_BMR_TC0XC0S_NONE (0x1 << 0) /**< \brief (TC_BMR) none */
-#define TC_BMR_TC0XC0S_TIOA1 (0x2 << 0) /**< \brief (TC_BMR) TIOA1 */
-#define TC_BMR_TC0XC0S_TIOA2 (0x3 << 0) /**< \brief (TC_BMR) TIOA2 */
-#define TC_BMR_TC1XC1S (0x3 << 2) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
-#define TC_BMR_TC1XC1S_TCLK1 (0x0 << 2) /**< \brief (TC_BMR) TCLK1 */
-#define TC_BMR_TC1XC1S_NONE (0x1 << 2) /**< \brief (TC_BMR) none */
-#define TC_BMR_TC1XC1S_TIOA0 (0x2 << 2) /**< \brief (TC_BMR) TIOA0 */
-#define TC_BMR_TC1XC1S_TIOA2 (0x3 << 2) /**< \brief (TC_BMR) TIOA2 */
-#define TC_BMR_TC2XC2S (0x3 << 4) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
-#define TC_BMR_TC2XC2S_TCLK2 (0x0 << 4) /**< \brief (TC_BMR) TCLK2 */
-#define TC_BMR_TC2XC2S_NONE (0x1 << 4) /**< \brief (TC_BMR) none */
-#define TC_BMR_TC2XC2S_TIOA0 (0x2 << 4) /**< \brief (TC_BMR) TIOA0 */
-#define TC_BMR_TC2XC2S_TIOA1 (0x3 << 4) /**< \brief (TC_BMR) TIOA1 */
-#define TC_BMR_QDEN (0x1 << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */
-#define TC_BMR_POSEN (0x1 << 9) /**< \brief (TC_BMR) POSition ENabled */
-#define TC_BMR_SPEEDEN (0x1 << 10) /**< \brief (TC_BMR) SPEED ENabled */
-#define TC_BMR_QDTRANS (0x1 << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */
-#define TC_BMR_EDGPHA (0x1 << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */
-#define TC_BMR_INVA (0x1 << 13) /**< \brief (TC_BMR) INVerted phA */
-#define TC_BMR_INVB (0x1 << 14) /**< \brief (TC_BMR) INVerted phB */
-#define TC_BMR_INVIDX (0x1 << 15) /**< \brief (TC_BMR) INVerted InDeX */
-#define TC_BMR_SWAP (0x1 << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */
-#define TC_BMR_IDXPHB (0x1 << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */
-#define TC_BMR_FILTER (0x1 << 19) /**< \brief (TC_BMR) */
-#define TC_BMR_MAXFILT (0x3f << 20) /**< \brief (TC_BMR) MAXimum FILTer */
-/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
-#define TC_QIER_IDX (0x1 << 0) /**< \brief (TC_QIER) InDeX */
-#define TC_QIER_DIRCHG (0x1 << 1) /**< \brief (TC_QIER) DIRection CHanGe */
-#define TC_QIER_QERR (0x1 << 2) /**< \brief (TC_QIER) Quadrature ERRor */
-/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
-#define TC_QIDR_IDX (0x1 << 0) /**< \brief (TC_QIDR) InDeX */
-#define TC_QIDR_DIRCHG (0x1 << 1) /**< \brief (TC_QIDR) DIRection CHanGe */
-#define TC_QIDR_QERR (0x1 << 2) /**< \brief (TC_QIDR) Quadrature ERRor */
-/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
-#define TC_QIMR_IDX (0x1 << 0) /**< \brief (TC_QIMR) InDeX */
-#define TC_QIMR_DIRCHG (0x1 << 1) /**< \brief (TC_QIMR) DIRection CHanGe */
-#define TC_QIMR_QERR (0x1 << 2) /**< \brief (TC_QIMR) Quadrature ERRor */
-/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
-#define TC_QISR_IDX (0x1 << 0) /**< \brief (TC_QISR) InDeX */
-#define TC_QISR_DIRCHG (0x1 << 1) /**< \brief (TC_QISR) DIRection CHanGe */
-#define TC_QISR_QERR (0x1 << 2) /**< \brief (TC_QISR) Quadrature ERRor */
-#define TC_QISR_DIR (0x1 << 8) /**< \brief (TC_QISR) Direction */
-/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */
-#define TC_FMR_ENCF0 (0x1 << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */
-#define TC_FMR_ENCF1 (0x1 << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */
-/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */
-#define TC_WPMR_WPEN (0x1 << 0) /**< \brief (TC_WPMR) Write Protect Enable */
-#define TC_WPMR_WPKEY (0xffffff << 8) /**< \brief (TC_WPMR) Write Protect KEY */
-/* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */
-#define TC_VER_VERSION (0xfff << 0) /**< \brief (TC_VER) */
-#define TC_VER_MFN (0x7 << 16) /**< \brief (TC_VER) */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Two-wire Interface */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_TWI Two-wire Interface */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Twi hardware registers */
-typedef struct {
- WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */
- RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */
- RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */
- RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */
- RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */
- RwReg Reserved1[3];
- RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */
- WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */
- WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */
- RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */
- RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */
- WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */
- RwReg Reserved2[50];
- RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */
- RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */
- RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */
- RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */
- RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */
- RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */
- RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */
- RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */
- WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */
- RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */
-} Twi;
-#endif /* __ASSEMBLY__ */
-/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
-#define TWI_CR_START (0x1 << 0) /**< \brief (TWI_CR) Send a START Condition */
-#define TWI_CR_STOP (0x1 << 1) /**< \brief (TWI_CR) Send a STOP Condition */
-#define TWI_CR_MSEN (0x1 << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */
-#define TWI_CR_MSDIS (0x1 << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */
-#define TWI_CR_SVEN (0x1 << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */
-#define TWI_CR_SVDIS (0x1 << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */
-#define TWI_CR_QUICK (0x1 << 6) /**< \brief (TWI_CR) SMBUS Quick Command */
-#define TWI_CR_SWRST (0x1 << 7) /**< \brief (TWI_CR) Software Reset */
-/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
-#define TWI_MMR_IADRSZ (0x3 << 8) /**< \brief (TWI_MMR) Internal Device Address Size */
-#define TWI_MMR_IADRSZ_NO (0x0 << 8) /**< \brief (TWI_MMR) No internal device address */
-#define TWI_MMR_IADRSZ_1_BYTE (0x1 << 8) /**< \brief (TWI_MMR) One-byte internal device address */
-#define TWI_MMR_IADRSZ_2_BYTE (0x2 << 8) /**< \brief (TWI_MMR) Two-byte internal device address */
-#define TWI_MMR_IADRSZ_3_BYTE (0x3 << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
-#define TWI_MMR_MREAD (0x1 << 12) /**< \brief (TWI_MMR) Master Read Direction */
-#define TWI_MMR_DADR (0x7f << 16) /**< \brief (TWI_MMR) Device Address */
-/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
-#define TWI_SMR_SADR (0x7f << 16) /**< \brief (TWI_SMR) Slave Address */
-/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
-#define TWI_IADR_IADR (0xffffff << 0) /**< \brief (TWI_IADR) Internal Address */
-/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
-#define TWI_CWGR_CLDIV (0xff << 0) /**< \brief (TWI_CWGR) Clock Low Divider */
-#define TWI_CWGR_CHDIV (0xff << 8) /**< \brief (TWI_CWGR) Clock High Divider */
-#define TWI_CWGR_CKDIV (0x7 << 16) /**< \brief (TWI_CWGR) Clock Divider */
-/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
-#define TWI_SR_TXCOMP (0x1 << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */
-#define TWI_SR_RXRDY (0x1 << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */
-#define TWI_SR_TXRDY (0x1 << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */
-#define TWI_SR_SVREAD (0x1 << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */
-#define TWI_SR_SVACC (0x1 << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */
-#define TWI_SR_GACC (0x1 << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */
-#define TWI_SR_OVRE (0x1 << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */
-#define TWI_SR_NACK (0x1 << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */
-#define TWI_SR_ARBLST (0x1 << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */
-#define TWI_SR_SCLWS (0x1 << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */
-#define TWI_SR_EOSACC (0x1 << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */
-#define TWI_SR_ENDRX (0x1 << 12) /**< \brief (TWI_SR) End of RX buffer */
-#define TWI_SR_ENDTX (0x1 << 13) /**< \brief (TWI_SR) End of TX buffer */
-#define TWI_SR_RXBUFF (0x1 << 14) /**< \brief (TWI_SR) RX Buffer Full */
-#define TWI_SR_TXBUFE (0x1 << 15) /**< \brief (TWI_SR) TX Buffer Empty */
-/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
-#define TWI_IER_TXCOMP (0x1 << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */
-#define TWI_IER_RXRDY (0x1 << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */
-#define TWI_IER_TXRDY (0x1 << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */
-#define TWI_IER_SVACC (0x1 << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */
-#define TWI_IER_GACC (0x1 << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */
-#define TWI_IER_OVRE (0x1 << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */
-#define TWI_IER_NACK (0x1 << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */
-#define TWI_IER_ARBLST (0x1 << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */
-#define TWI_IER_SCL_WS (0x1 << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */
-#define TWI_IER_EOSACC (0x1 << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */
-#define TWI_IER_ENDRX (0x1 << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */
-#define TWI_IER_ENDTX (0x1 << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */
-#define TWI_IER_RXBUFF (0x1 << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */
-#define TWI_IER_TXBUFE (0x1 << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */
-/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
-#define TWI_IDR_TXCOMP (0x1 << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */
-#define TWI_IDR_RXRDY (0x1 << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */
-#define TWI_IDR_TXRDY (0x1 << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */
-#define TWI_IDR_SVACC (0x1 << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */
-#define TWI_IDR_GACC (0x1 << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */
-#define TWI_IDR_OVRE (0x1 << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */
-#define TWI_IDR_NACK (0x1 << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */
-#define TWI_IDR_ARBLST (0x1 << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */
-#define TWI_IDR_SCL_WS (0x1 << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */
-#define TWI_IDR_EOSACC (0x1 << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */
-#define TWI_IDR_ENDRX (0x1 << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */
-#define TWI_IDR_ENDTX (0x1 << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */
-#define TWI_IDR_RXBUFF (0x1 << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */
-#define TWI_IDR_TXBUFE (0x1 << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */
-/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
-#define TWI_IMR_TXCOMP (0x1 << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */
-#define TWI_IMR_RXRDY (0x1 << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */
-#define TWI_IMR_TXRDY (0x1 << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */
-#define TWI_IMR_SVACC (0x1 << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */
-#define TWI_IMR_GACC (0x1 << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */
-#define TWI_IMR_OVRE (0x1 << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */
-#define TWI_IMR_NACK (0x1 << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */
-#define TWI_IMR_ARBLST (0x1 << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */
-#define TWI_IMR_SCL_WS (0x1 << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */
-#define TWI_IMR_EOSACC (0x1 << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */
-#define TWI_IMR_ENDRX (0x1 << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */
-#define TWI_IMR_ENDTX (0x1 << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */
-#define TWI_IMR_RXBUFF (0x1 << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */
-#define TWI_IMR_TXBUFE (0x1 << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */
-/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
-#define TWI_RHR_RXDATA (0xff << 0) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */
-/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
-#define TWI_THR_TXDATA (0xff << 0) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */
-/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */
-#define TWI_RPR_RXPTR (0xffffffff << 0) /**< \brief (TWI_RPR) Receive Pointer Register */
-/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */
-#define TWI_RCR_RXCTR (0xffff << 0) /**< \brief (TWI_RCR) Receive Counter Register */
-/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */
-#define TWI_TPR_TXPTR (0xffffffff << 0) /**< \brief (TWI_TPR) Transmit Counter Register */
-/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */
-#define TWI_TCR_TXCTR (0xffff << 0) /**< \brief (TWI_TCR) Transmit Counter Register */
-/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */
-#define TWI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (TWI_RNPR) Receive Next Pointer */
-/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */
-#define TWI_RNCR_RXNCTR (0xffff << 0) /**< \brief (TWI_RNCR) Receive Next Counter */
-/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */
-#define TWI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (TWI_TNPR) Transmit Next Pointer */
-/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */
-#define TWI_TNCR_TXNCTR (0xffff << 0) /**< \brief (TWI_TNCR) Transmit Counter Next */
-/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */
-#define TWI_PTCR_RXTEN (0x1 << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */
-#define TWI_PTCR_RXTDIS (0x1 << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */
-#define TWI_PTCR_TXTEN (0x1 << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */
-#define TWI_PTCR_TXTDIS (0x1 << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */
-/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */
-#define TWI_PTSR_RXTEN (0x1 << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */
-#define TWI_PTSR_TXTEN (0x1 << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_UART Universal Asynchronous Receiver Transmitter */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Uart hardware registers */
-typedef struct {
- WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */
- RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */
- WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
- WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
- RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
- RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */
- RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
- WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
- RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
- RwReg Reserved1[55];
- RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */
- RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */
- RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */
- RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */
- RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */
- RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */
- RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */
- RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */
- WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */
- RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */
-} Uart;
-#endif /* __ASSEMBLY__ */
-/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
-#define UART_CR_RSTRX (0x1 << 2) /**< \brief (UART_CR) Reset Receiver */
-#define UART_CR_RSTTX (0x1 << 3) /**< \brief (UART_CR) Reset Transmitter */
-#define UART_CR_RXEN (0x1 << 4) /**< \brief (UART_CR) Receiver Enable */
-#define UART_CR_RXDIS (0x1 << 5) /**< \brief (UART_CR) Receiver Disable */
-#define UART_CR_TXEN (0x1 << 6) /**< \brief (UART_CR) Transmitter Enable */
-#define UART_CR_TXDIS (0x1 << 7) /**< \brief (UART_CR) Transmitter Disable */
-#define UART_CR_RSTSTA (0x1 << 8) /**< \brief (UART_CR) Reset Status Bits */
-/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
-#define UART_MR_PAR (0x7 << 9) /**< \brief (UART_MR) Parity Type */
-#define UART_MR_CHMODE (0x3 << 14) /**< \brief (UART_MR) Channel Mode */
-/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
-#define UART_IER_RXRDY (0x1 << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
-#define UART_IER_TXRDY (0x1 << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
-#define UART_IER_ENDRX (0x1 << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */
-#define UART_IER_ENDTX (0x1 << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */
-#define UART_IER_OVRE (0x1 << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
-#define UART_IER_FRAME (0x1 << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
-#define UART_IER_PARE (0x1 << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
-#define UART_IER_TXEMPTY (0x1 << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
-#define UART_IER_TXBUFE (0x1 << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */
-#define UART_IER_RXBUFF (0x1 << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */
-/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
-#define UART_IDR_RXRDY (0x1 << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
-#define UART_IDR_TXRDY (0x1 << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
-#define UART_IDR_ENDRX (0x1 << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */
-#define UART_IDR_ENDTX (0x1 << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */
-#define UART_IDR_OVRE (0x1 << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
-#define UART_IDR_FRAME (0x1 << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
-#define UART_IDR_PARE (0x1 << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
-#define UART_IDR_TXEMPTY (0x1 << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
-#define UART_IDR_TXBUFE (0x1 << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */
-#define UART_IDR_RXBUFF (0x1 << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */
-/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
-#define UART_IMR_RXRDY (0x1 << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
-#define UART_IMR_TXRDY (0x1 << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
-#define UART_IMR_ENDRX (0x1 << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */
-#define UART_IMR_ENDTX (0x1 << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */
-#define UART_IMR_OVRE (0x1 << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
-#define UART_IMR_FRAME (0x1 << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
-#define UART_IMR_PARE (0x1 << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
-#define UART_IMR_TXEMPTY (0x1 << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
-#define UART_IMR_TXBUFE (0x1 << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */
-#define UART_IMR_RXBUFF (0x1 << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */
-/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
-#define UART_SR_RXRDY (0x1 << 0) /**< \brief (UART_SR) Receiver Ready */
-#define UART_SR_TXRDY (0x1 << 1) /**< \brief (UART_SR) Transmitter Ready */
-#define UART_SR_ENDRX (0x1 << 3) /**< \brief (UART_SR) End of Receiver Transfer */
-#define UART_SR_ENDTX (0x1 << 4) /**< \brief (UART_SR) End of Transmitter Transfer */
-#define UART_SR_OVRE (0x1 << 5) /**< \brief (UART_SR) Overrun Error */
-#define UART_SR_FRAME (0x1 << 6) /**< \brief (UART_SR) Framing Error */
-#define UART_SR_PARE (0x1 << 7) /**< \brief (UART_SR) Parity Error */
-#define UART_SR_TXEMPTY (0x1 << 9) /**< \brief (UART_SR) Transmitter Empty */
-#define UART_SR_TXBUFE (0x1 << 11) /**< \brief (UART_SR) Transmission Buffer Empty */
-#define UART_SR_RXBUFF (0x1 << 12) /**< \brief (UART_SR) Receive Buffer Full */
-/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
-#define UART_RHR_RXCHR (0xff << 0) /**< \brief (UART_RHR) Received Character */
-/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
-#define UART_THR_TXCHR (0xff << 0) /**< \brief (UART_THR) Character to be Transmitted */
-/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
-#define UART_BRGR_CD (0xffff << 0) /**< \brief (UART_BRGR) Clock Divisor */
-/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */
-#define UART_RPR_RXPTR (0xffffffff << 0) /**< \brief (UART_RPR) Receive Pointer Register */
-/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */
-#define UART_RCR_RXCTR (0xffff << 0) /**< \brief (UART_RCR) Receive Counter Register */
-/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */
-#define UART_TPR_TXPTR (0xffffffff << 0) /**< \brief (UART_TPR) Transmit Counter Register */
-/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */
-#define UART_TCR_TXCTR (0xffff << 0) /**< \brief (UART_TCR) Transmit Counter Register */
-/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */
-#define UART_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (UART_RNPR) Receive Next Pointer */
-/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */
-#define UART_RNCR_RXNCTR (0xffff << 0) /**< \brief (UART_RNCR) Receive Next Counter */
-/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */
-#define UART_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (UART_TNPR) Transmit Next Pointer */
-/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */
-#define UART_TNCR_TXNCTR (0xffff << 0) /**< \brief (UART_TNCR) Transmit Counter Next */
-/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */
-#define UART_PTCR_RXTEN (0x1 << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */
-#define UART_PTCR_RXTDIS (0x1 << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */
-#define UART_PTCR_TXTEN (0x1 << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */
-#define UART_PTCR_TXTDIS (0x1 << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */
-/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */
-#define UART_PTSR_RXTEN (0x1 << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */
-#define UART_PTSR_TXTEN (0x1 << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR USB Device Port */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_UDP USB Device Port */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Udp hardware registers */
-typedef struct {
- RoReg UDP_FRM_NUM; /**< \brief (Udp Offset: 0x000) Frame Number Register */
- RwReg UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */
- RwReg UDP_FADDR; /**< \brief (Udp Offset: 0x008) Function Address Register */
- RwReg Reserved1[1];
- WoReg UDP_IER; /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */
- WoReg UDP_IDR; /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */
- RoReg UDP_IMR; /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */
- RoReg UDP_ISR; /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */
- WoReg UDP_ICR; /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */
- RwReg Reserved2[1];
- RwReg UDP_RST_EP; /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */
- RwReg Reserved3[1];
- RwReg UDP_CSR[8]; /**< \brief (Udp Offset: 0x30) Endpoint Control and Status Register (ept_num = 0) */
- RwReg UDP_FDR[8]; /**< \brief (Udp Offset: 0x50) Endpoint FIFO Data Register (ept_num = 0) */
- RwReg Reserved4[1];
- RwReg UDP_TXVC; /**< \brief (Udp Offset: 0x074) Transceiver Control Register */
-} Udp;
-#endif /* __ASSEMBLY__ */
-/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */
-#define UDP_FRM_NUM_FRM_NUM (0x7ff << 0) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */
-#define UDP_FRM_NUM_FRM_ERR (0x1 << 16) /**< \brief (UDP_FRM_NUM) Frame Error */
-#define UDP_FRM_NUM_FRM_OK (0x1 << 17) /**< \brief (UDP_FRM_NUM) Frame OK */
-/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */
-#define UDP_GLB_STAT_FADDEN (0x1 << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */
-#define UDP_GLB_STAT_CONFG (0x1 << 1) /**< \brief (UDP_GLB_STAT) Configured */
-#define UDP_GLB_STAT_ESR (0x1 << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */
-#define UDP_GLB_STAT_RSMINPR (0x1 << 3) /**< \brief (UDP_GLB_STAT) */
-#define UDP_GLB_STAT_RMWUPE (0x1 << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */
-/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */
-#define UDP_FADDR_FADD (0x7f << 0) /**< \brief (UDP_FADDR) Function Address Value */
-#define UDP_FADDR_FEN (0x1 << 8) /**< \brief (UDP_FADDR) Function Enable */
-/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */
-#define UDP_IER_EP0INT (0x1 << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */
-#define UDP_IER_EP1INT (0x1 << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */
-#define UDP_IER_EP2INT (0x1 << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */
-#define UDP_IER_EP3INT (0x1 << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */
-#define UDP_IER_EP4INT (0x1 << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */
-#define UDP_IER_EP5INT (0x1 << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */
-#define UDP_IER_EP6INT (0x1 << 6) /**< \brief (UDP_IER) Enable Endpoint 6 Interrupt */
-#define UDP_IER_EP7INT (0x1 << 7) /**< \brief (UDP_IER) Enable Endpoint 7 Interrupt */
-#define UDP_IER_RXSUSP (0x1 << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */
-#define UDP_IER_RXRSM (0x1 << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */
-#define UDP_IER_EXTRSM (0x1 << 10) /**< \brief (UDP_IER) */
-#define UDP_IER_SOFINT (0x1 << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */
-#define UDP_IER_WAKEUP (0x1 << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */
-/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */
-#define UDP_IDR_EP0INT (0x1 << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */
-#define UDP_IDR_EP1INT (0x1 << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */
-#define UDP_IDR_EP2INT (0x1 << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */
-#define UDP_IDR_EP3INT (0x1 << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */
-#define UDP_IDR_EP4INT (0x1 << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */
-#define UDP_IDR_EP5INT (0x1 << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */
-#define UDP_IDR_EP6INT (0x1 << 6) /**< \brief (UDP_IDR) Disable Endpoint 6 Interrupt */
-#define UDP_IDR_EP7INT (0x1 << 7) /**< \brief (UDP_IDR) Disable Endpoint 7 Interrupt */
-#define UDP_IDR_RXSUSP (0x1 << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */
-#define UDP_IDR_RXRSM (0x1 << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */
-#define UDP_IDR_EXTRSM (0x1 << 10) /**< \brief (UDP_IDR) */
-#define UDP_IDR_SOFINT (0x1 << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */
-#define UDP_IDR_WAKEUP (0x1 << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */
-/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */
-#define UDP_IMR_EP0INT (0x1 << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */
-#define UDP_IMR_EP1INT (0x1 << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */
-#define UDP_IMR_EP2INT (0x1 << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */
-#define UDP_IMR_EP3INT (0x1 << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */
-#define UDP_IMR_EP4INT (0x1 << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */
-#define UDP_IMR_EP5INT (0x1 << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */
-#define UDP_IMR_EP6INT (0x1 << 6) /**< \brief (UDP_IMR) Mask Endpoint 6 Interrupt */
-#define UDP_IMR_EP7INT (0x1 << 7) /**< \brief (UDP_IMR) Mask Endpoint 7 Interrupt */
-#define UDP_IMR_RXSUSP (0x1 << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */
-#define UDP_IMR_RXRSM (0x1 << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */
-#define UDP_IMR_EXTRSM (0x1 << 10) /**< \brief (UDP_IMR) */
-#define UDP_IMR_SOFINT (0x1 << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */
-#define UDP_IMR_BIT12 (0x1 << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */
-#define UDP_IMR_WAKEUP (0x1 << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */
-/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */
-#define UDP_ISR_EP0INT (0x1 << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */
-#define UDP_ISR_EP1INT (0x1 << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */
-#define UDP_ISR_EP2INT (0x1 << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */
-#define UDP_ISR_EP3INT (0x1 << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */
-#define UDP_ISR_EP4INT (0x1 << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */
-#define UDP_ISR_EP5INT (0x1 << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */
-#define UDP_ISR_EP6INT (0x1 << 6) /**< \brief (UDP_ISR) Endpoint 6 Interrupt Status */
-#define UDP_ISR_EP7INT (0x1 << 7) /**< \brief (UDP_ISR) Endpoint 7Interrupt Status */
-#define UDP_ISR_RXSUSP (0x1 << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */
-#define UDP_ISR_RXRSM (0x1 << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */
-#define UDP_ISR_EXTRSM (0x1 << 10) /**< \brief (UDP_ISR) */
-#define UDP_ISR_SOFINT (0x1 << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */
-#define UDP_ISR_ENDBUSRES (0x1 << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */
-#define UDP_ISR_WAKEUP (0x1 << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */
-/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */
-#define UDP_ICR_RXSUSP (0x1 << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */
-#define UDP_ICR_RXRSM (0x1 << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */
-#define UDP_ICR_EXTRSM (0x1 << 10) /**< \brief (UDP_ICR) */
-#define UDP_ICR_SOFINT (0x1 << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */
-#define UDP_ICR_ENDBUSRES (0x1 << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */
-#define UDP_ICR_WAKEUP (0x1 << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */
-/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */
-#define UDP_RST_EP_EP0 (0x1 << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */
-#define UDP_RST_EP_EP1 (0x1 << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */
-#define UDP_RST_EP_EP2 (0x1 << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */
-#define UDP_RST_EP_EP3 (0x1 << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */
-#define UDP_RST_EP_EP4 (0x1 << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */
-#define UDP_RST_EP_EP5 (0x1 << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */
-#define UDP_RST_EP_EP6 (0x1 << 6) /**< \brief (UDP_RST_EP) Reset Endpoint 6 */
-#define UDP_RST_EP_EP7 (0x1 << 7) /**< \brief (UDP_RST_EP) Reset Endpoint 7 */
-/* -------- UDP_CSR[8] : (UDP Offset: 0x2C) Endpoint Control and Status Register (ept_num = 0) -------- */
-#define UDP_CSR_TXCOMP (0x1 << 0) /**< \brief (UDP_CSR[8]) Generates an IN Packet with Data Previously Written in the DPR */
-#define UDP_CSR_RX_DATA_BK0 (0x1 << 1) /**< \brief (UDP_CSR[8]) Receive Data Bank 0 */
-#define UDP_CSR_RXSETUP (0x1 << 2) /**< \brief (UDP_CSR[8]) Received Setup */
-#define UDP_CSR_STALLSENTISOERROR (0x1 << 3) /**< \brief (UDP_CSR[8]) */
-#define UDP_CSR_TXPKTRDY (0x1 << 4) /**< \brief (UDP_CSR[8]) Transmit Packet Ready */
-#define UDP_CSR_FORCESTALL (0x1 << 5) /**< \brief (UDP_CSR[8]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */
-#define UDP_CSR_RX_DATA_BK1 (0x1 << 6) /**< \brief (UDP_CSR[8]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */
-#define UDP_CSR_DIR (0x1 << 7) /**< \brief (UDP_CSR[8]) Transfer Direction (only available for control endpoints) */
-#define UDP_CSR_EPTYPE (0x7 << 8) /**< \brief (UDP_CSR[8]) Endpoint Type */
-#define UDP_CSR_EPTYPE_CTRL (0x0 << 8) /**< \brief (UDP_CSR[8]) Control */
-#define UDP_CSR_EPTYPE_ISO_OUT (0x1 << 8) /**< \brief (UDP_CSR[8]) Isochronous OUT */
-#define UDP_CSR_EPTYPE_BULK_OUT (0x2 << 8) /**< \brief (UDP_CSR[8]) Bulk OUT */
-#define UDP_CSR_EPTYPE_INT_OUT (0x3 << 8) /**< \brief (UDP_CSR[8]) Interrupt OUT */
-#define UDP_CSR_EPTYPE_ISO_IN (0x5 << 8) /**< \brief (UDP_CSR[8]) Isochronous IN */
-#define UDP_CSR_EPTYPE_BULK_IN (0x6 << 8) /**< \brief (UDP_CSR[8]) Bulk IN */
-#define UDP_CSR_EPTYPE_INT_IN (0x7 << 8) /**< \brief (UDP_CSR[8]) Interrupt IN */
-#define UDP_CSR_DTGLE (0x1 << 11) /**< \brief (UDP_CSR[8]) Data Toggle */
-#define UDP_CSR_EPEDS (0x1 << 15) /**< \brief (UDP_CSR[8]) Endpoint Enable Disable */
-#define UDP_CSR_RXBYTECNT (0x7ff << 16) /**< \brief (UDP_CSR[8]) Number of Bytes Available in the FIFO */
-/* -------- UDP_FDR[8] : (UDP Offset: 0x4C) Endpoint FIFO Data Register (ept_num = 0) -------- */
-#define UDP_FDR_FIFO_DATA (0xff << 0) /**< \brief (UDP_FDR[8]) FIFO Data Value */
-/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */
-#define UDP_TXVC_TXVDIS (0x1 << 8) /**< \brief (UDP_TXVC) Transceiver Disable */
-#define UDP_TXVC_PUON (0x1 << 9) /**< \brief (UDP_TXVC) Pullup On */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_USART Universal Synchronous Asynchronous Receiver Transmitter */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Usart hardware registers */
-typedef struct {
- WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */
- RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */
- WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
- WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
- RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
- RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */
- RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */
- WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */
- RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
- RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */
- RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
- RwReg Reserved1[5];
- RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */
- RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */
- RwReg Reserved2[1];
- RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */
- RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */
- RwReg Reserved3[36];
- RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */
- RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */
- RwReg Reserved4[4];
- RoReg US_VERSION; /**< \brief (Usart Offset: 0xFC) Version Register */
- RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */
- RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */
- RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */
- RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */
- RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */
- RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */
- RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */
- RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */
- WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */
- RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */
-} Usart;
-#endif /* __ASSEMBLY__ */
-/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
-#define US_CR_RSTRX (0x1 << 2) /**< \brief (US_CR) Reset Receiver */
-#define US_CR_RSTTX (0x1 << 3) /**< \brief (US_CR) Reset Transmitter */
-#define US_CR_RXEN (0x1 << 4) /**< \brief (US_CR) Receiver Enable */
-#define US_CR_RXDIS (0x1 << 5) /**< \brief (US_CR) Receiver Disable */
-#define US_CR_TXEN (0x1 << 6) /**< \brief (US_CR) Transmitter Enable */
-#define US_CR_TXDIS (0x1 << 7) /**< \brief (US_CR) Transmitter Disable */
-#define US_CR_RSTSTA (0x1 << 8) /**< \brief (US_CR) Reset Status Bits */
-#define US_CR_STTBRK (0x1 << 9) /**< \brief (US_CR) Start Break */
-#define US_CR_STPBRK (0x1 << 10) /**< \brief (US_CR) Stop Break */
-#define US_CR_STTTO (0x1 << 11) /**< \brief (US_CR) Start Time-out */
-#define US_CR_SENDA (0x1 << 12) /**< \brief (US_CR) Send Address */
-#define US_CR_RSTIT (0x1 << 13) /**< \brief (US_CR) Reset Iterations */
-#define US_CR_RSTNACK (0x1 << 14) /**< \brief (US_CR) Reset Non Acknowledge */
-#define US_CR_RETTO (0x1 << 15) /**< \brief (US_CR) Rearm Time-out */
-#define US_CR_DTREN (0x1 << 16) /**< \brief (US_CR) Data Terminal Ready Enable */
-#define US_CR_DTRDIS (0x1 << 17) /**< \brief (US_CR) Data Terminal Ready Disable */
-#define US_CR_RTSEN__FCS (0x1 << 18) /**< \brief (US_CR) Request to Send Enable/Force SPI Chip Select */
-#define US_CR_RTSDIS__RCS (0x1 << 19) /**< \brief (US_CR) Request to Send Disable/Release SPI Chip Select */
-/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
-#define US_MR_USART_MODE (0xf << 0) /**< \brief (US_MR) */
-#define US_MR_USART_MODE_NORMAL (0x0) /**< (USART) Normal*/
-#define US_MR_USART_MODE_RS485 (0x1) /**< (USART) RS485*/
-#define US_MR_USART_MODE_HWHSH (0x2) /**< (USART) Hardware Handshaking*/
-#define US_MR_USART_MODE_ISO7816_0 (0x4) /**< (USART) ISO7816 protocol: T = 0*/
-#define US_MR_USART_MODE_ISO7816_1 (0x6) /**< (USART) ISO7816 protocol: T = 1*/
-#define US_MR_USART_MODE_IRDA (0x8) /**< (USART) IrDA*/
-#define US_MR_USART_MODE_SPIM (0xE) /**< (USART) SPI Master*/
-#define US_MR_USART_MODE_SPIS (0xF) /**< (USART) SPI Slave*/
-#define US_MR_USCLKS (0x3 << 4) /**< \brief (US_MR) Clock Selection */
-#define US_MR_USCLKS_CLOCK (0x0 << 4) /**< (USART) MCK*/
-#define US_MR_USCLKS_FDIV1 (0x1 << 4) /**< (USART) MCK/DIV(DIV=8)*/
-#define US_MR_USCLKS_SLOW (0x2 << 4) /**< (USART) Reserved*/
-#define US_MR_USCLKS_EXT (0x3 << 4) /**< (USART) SCK*/
-#define US_MR_CHRL (0x3 << 6) /**< \brief (US_MR) Character Length. */
-#define US_MR_CHRL_5_BITS (0x0 << 6) /**< (USART) Character Length: 5 bits*/
-#define US_MR_CHRL_6_BITS (0x1 << 6) /**< (USART) Character Length: 6 bits*/
-#define US_MR_CHRL_7_BITS (0x2 << 6) /**< (USART) Character Length: 7 bits*/
-#define US_MR_CHRL_8_BITS (0x3 << 6) /**< (USART) Character Length: 8 bits*/
-#define US_MR_SYNC__CPHA (0x1 << 8) /**< \brief (US_MR) Synchronous Mode Select or SPI Clock Phase */
-#define US_MR_PAR (0x7 << 9) /**< \brief (US_MR) Parity Type */
-#define US_MR_PAR_EVEN (0x0 << 9) /**< (USART) Even Parity*/
-#define US_MR_PAR_ODD (0x1 << 9) /**< (USART) Odd Parity*/
-#define US_MR_PAR_SPACE (0x2 << 9) /**< (USART) Parity forced to 0 (Space)*/
-#define US_MR_PAR_MARK (0x3 << 9) /**< (USART) Parity forced to 1 (Mark)*/
-#define US_MR_PAR_NONE (0x4 << 9) /**< (USART) No Parity*/
-#define US_MR_PAR_MULTI_DROP (0x6 << 9) /**< (USART) Multi-drop mode*/
-#define US_MR_NBSTOP (0x3 << 12) /**< \brief (US_MR) Number of Stop Bits */
-#define US_MR_NBSTOP_1_BIT (0x0 << 12) /**< (USART) 1 stop bit*/
-#define US_MR_NBSTOP_15_BIT (0x1 << 12) /**< (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits*/
-#define US_MR_NBSTOP_2_BIT (0x2 << 12) /**< (USART) 2 stop bits*/
-#define US_MR_CHMODE (0x3 << 14) /**< \brief (US_MR) Channel Mode */
-#define US_MR_CHMODE_NORMAL (0x0 << 14) /**< (USART) Normal Mode: The USART channel operates as an RX/TX USART.*/
-#define US_MR_CHMODE_AUTO (0x1 << 14) /**< (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin.*/
-#define US_MR_CHMODE_LOCAL (0x2 << 14) /**< (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.*/
-#define US_MR_CHMODE_REMOTE (0x3 << 14) /**< (USART) Remote Loopback: RXD pin is internally connected to TXD pin.*/
-#define US_MR_MSBF__CPOL (0x1 << 16) /**< \brief (US_MR) Bit Order or SPI Clock Polarity */
-#define US_MR_MODE9 (0x1 << 17) /**< \brief (US_MR) 9-bit Character Length */
-#define US_MR_CLKO (0x1 << 18) /**< \brief (US_MR) Clock Output Select */
-#define US_MR_OVER (0x1 << 19) /**< \brief (US_MR) Oversampling Mode */
-#define US_MR_INACK (0x1 << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */
-#define US_MR_DSNACK (0x1 << 21) /**< \brief (US_MR) Disable Successive NACK */
-#define US_MR_VAR_SYNC (0x1 << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */
-#define US_MR_INVDATA (0x1 << 23) /**< \brief (US_MR) INverted Data */
-#define US_MR_MAX_ITERATION (0x7 << 24) /**< \brief (US_MR) */
-#define US_MR_FILTER (0x1 << 28) /**< \brief (US_MR) Infrared Receive Line Filter */
-#define US_MR_MAN (0x1 << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */
-#define US_MR_MODSYNC_ (0x1 << 30) /**< \brief (US_MR) */
-#define US_MR_ONEBIT (0x1 << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */
-/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
-#define US_IER_RXRDY (0x1 << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
-#define US_IER_TXRDY (0x1 << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
-#define US_IER_RXBRK (0x1 << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
-#define US_IER_ENDRX (0x1 << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */
-#define US_IER_ENDTX (0x1 << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */
-#define US_IER_OVRE (0x1 << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
-#define US_IER_FRAME (0x1 << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
-#define US_IER_PARE (0x1 << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
-#define US_IER_TIMEOUT (0x1 << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
-#define US_IER_TXEMPTY (0x1 << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
-#define US_IER_ITER__UNRE (0x1 << 10) /**< \brief (US_IER) Iteration or SPI Underrun Error Interrupt Enable */
-#define US_IER_TXBUFE (0x1 << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */
-#define US_IER_RXBUFF (0x1 << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */
-#define US_IER_NACK (0x1 << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */
-#define US_IER_RIIC (0x1 << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */
-#define US_IER_DSRIC (0x1 << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */
-#define US_IER_DCDIC (0x1 << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */
-#define US_IER_CTSIC (0x1 << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
-#define US_IER_MANE (0x1 << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */
-/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
-#define US_IDR_RXRDY (0x1 << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
-#define US_IDR_TXRDY (0x1 << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
-#define US_IDR_RXBRK (0x1 << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
-#define US_IDR_ENDRX (0x1 << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */
-#define US_IDR_ENDTX (0x1 << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */
-#define US_IDR_OVRE (0x1 << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */
-#define US_IDR_FRAME (0x1 << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
-#define US_IDR_PARE (0x1 << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
-#define US_IDR_TIMEOUT (0x1 << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
-#define US_IDR_TXEMPTY (0x1 << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
-#define US_IDR_ITER__UNRE (0x1 << 10) /**< \brief (US_IDR) Iteration or SPI Underrun Error Interrupt Enable */
-#define US_IDR_TXBUFE (0x1 << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */
-#define US_IDR_RXBUFF (0x1 << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */
-#define US_IDR_NACK (0x1 << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */
-#define US_IDR_RIIC (0x1 << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */
-#define US_IDR_DSRIC (0x1 << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */
-#define US_IDR_DCDIC (0x1 << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */
-#define US_IDR_CTSIC (0x1 << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
-#define US_IDR_MANE (0x1 << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */
-/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
-#define US_IMR_RXRDY (0x1 << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
-#define US_IMR_TXRDY (0x1 << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
-#define US_IMR_RXBRK (0x1 << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
-#define US_IMR_ENDRX (0x1 << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */
-#define US_IMR_ENDTX (0x1 << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */
-#define US_IMR_OVRE (0x1 << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
-#define US_IMR_FRAME (0x1 << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
-#define US_IMR_PARE (0x1 << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
-#define US_IMR_TIMEOUT (0x1 << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
-#define US_IMR_TXEMPTY (0x1 << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
-#define US_IMR_ITER__UNRE (0x1 << 10) /**< \brief (US_IMR) Iteration or SPI Underrun Error Interrupt Enable */
-#define US_IMR_TXBUFE (0x1 << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */
-#define US_IMR_RXBUFF (0x1 << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */
-#define US_IMR_NACK (0x1 << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */
-#define US_IMR_RIIC (0x1 << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */
-#define US_IMR_DSRIC (0x1 << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */
-#define US_IMR_DCDIC (0x1 << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */
-#define US_IMR_CTSIC (0x1 << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
-#define US_IMR_MANE (0x1 << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */
-/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
-#define US_CSR_RXRDY (0x1 << 0) /**< \brief (US_CSR) Receiver Ready */
-#define US_CSR_TXRDY (0x1 << 1) /**< \brief (US_CSR) Transmitter Ready */
-#define US_CSR_RXBRK (0x1 << 2) /**< \brief (US_CSR) Break Received/End of Break */
-#define US_CSR_ENDRX (0x1 << 3) /**< \brief (US_CSR) End of Receiver Transfer */
-#define US_CSR_ENDTX (0x1 << 4) /**< \brief (US_CSR) End of Transmitter Transfer */
-#define US_CSR_OVRE (0x1 << 5) /**< \brief (US_CSR) Overrun Error */
-#define US_CSR_FRAME (0x1 << 6) /**< \brief (US_CSR) Framing Error */
-#define US_CSR_PARE (0x1 << 7) /**< \brief (US_CSR) Parity Error */
-#define US_CSR_TIMEOUT (0x1 << 8) /**< \brief (US_CSR) Receiver Time-out */
-#define US_CSR_TXEMPTY (0x1 << 9) /**< \brief (US_CSR) Transmitter Empty */
-#define US_CSR_ITER__UNRE (0x1 << 10) /**< \brief (US_CSR) Max number of Repetitions Reached or SPI Underrun Error */
-#define US_CSR_TXBUFE (0x1 << 11) /**< \brief (US_CSR) Transmission Buffer Empty */
-#define US_CSR_RXBUFF (0x1 << 12) /**< \brief (US_CSR) Reception Buffer Full */
-#define US_CSR_NACK (0x1 << 13) /**< \brief (US_CSR) */
-#define US_CSR_RIIC (0x1 << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */
-#define US_CSR_DSRIC (0x1 << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */
-#define US_CSR_DCDIC (0x1 << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */
-#define US_CSR_CTSIC (0x1 << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */
-#define US_CSR_RI (0x1 << 20) /**< \brief (US_CSR) Image of RI Input */
-#define US_CSR_DSR (0x1 << 21) /**< \brief (US_CSR) Image of DSR Input */
-#define US_CSR_DCD (0x1 << 22) /**< \brief (US_CSR) Image of DCD Input */
-#define US_CSR_CTS (0x1 << 23) /**< \brief (US_CSR) Image of CTS Input */
-#define US_CSR_MANERR (0x1 << 24) /**< \brief (US_CSR) Manchester Error */
-/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */
-#define US_RHR_RXCHR (0x1ff << 0) /**< \brief (US_RHR) Received Character */
-#define US_RHR_RXSYNH (0x1 << 15) /**< \brief (US_RHR) Received Sync */
-/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */
-#define US_THR_TXCHR (0x1ff << 0) /**< \brief (US_THR) Character to be Transmitted */
-#define US_THR_TXSYNH (0x1 << 15) /**< \brief (US_THR) Sync Field to be transmitted */
-/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
-#define US_BRGR_CD (0xffff << 0) /**< \brief (US_BRGR) Clock Divider */
-#define US_BRGR_FP (0x7 << 16) /**< \brief (US_BRGR) Fractional Part */
-/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
-#define US_RTOR_TO (0xffff << 0) /**< \brief (US_RTOR) Time-out Value */
-/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
-#define US_TTGR_TG (0xff << 0) /**< \brief (US_TTGR) Timeguard Value */
-/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
-#define US_FIDI_FI_DI_RATIO (0x7ff << 0) /**< \brief (US_FIDI) FI Over DI Ratio Value */
-/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
-#define US_NER_NB_ERRORS (0xff << 0) /**< \brief (US_NER) Number of Errors */
-/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
-#define US_IF_IRDA_FILTER (0xff << 0) /**< \brief (US_IF) IrDA Filter */
-/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */
-#define US_MAN_TX_PL (0xf << 0) /**< \brief (US_MAN) Transmitter Preamble Length */
-#define US_MAN_TX_PP (0x3 << 8) /**< \brief (US_MAN) Transmitter Preamble Pattern */
-#define US_MAN_TX_MPOL (0x1 << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */
-#define US_MAN_RX_PL (0xf << 16) /**< \brief (US_MAN) Receiver Preamble Length */
-#define US_MAN_RX_PP (0x3 << 24) /**< \brief (US_MAN) Receiver Preamble Pattern detected */
-#define US_MAN_RX_MPOL (0x1 << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */
-#define US_MAN_STUCKTO1 (0x1 << 29) /**< \brief (US_MAN) */
-#define US_MAN_DRIFT (0x1 << 30) /**< \brief (US_MAN) Drift compensation */
-/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */
-#define US_WPMR_WPEN (0x1 << 0) /**< \brief (US_WPMR) Write Protect Enable */
-#define US_WPMR_WPKEY (0xffffff << 8) /**< \brief (US_WPMR) Write Protect KEY */
-/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */
-#define US_WPSR_WPVS (0x1 << 0) /**< \brief (US_WPSR) Write Protect Violation Status */
-#define US_WPSR_WPVSRC (0xffff << 8) /**< \brief (US_WPSR) Write Protect Violation Source */
-/* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */
-#define US_VERSION_VERSION (0xfff << 0) /**< \brief (US_VERSION) */
-#define US_VERSION_MFN (0x7 << 16) /**< \brief (US_VERSION) */
-/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */
-#define US_RPR_RXPTR (0xffffffff << 0) /**< \brief (US_RPR) Receive Pointer Register */
-/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */
-#define US_RCR_RXCTR (0xffff << 0) /**< \brief (US_RCR) Receive Counter Register */
-/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */
-#define US_TPR_TXPTR (0xffffffff << 0) /**< \brief (US_TPR) Transmit Counter Register */
-/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */
-#define US_TCR_TXCTR (0xffff << 0) /**< \brief (US_TCR) Transmit Counter Register */
-/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */
-#define US_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (US_RNPR) Receive Next Pointer */
-/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */
-#define US_RNCR_RXNCTR (0xffff << 0) /**< \brief (US_RNCR) Receive Next Counter */
-/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */
-#define US_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (US_TNPR) Transmit Next Pointer */
-/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */
-#define US_TNCR_TXNCTR (0xffff << 0) /**< \brief (US_TNCR) Transmit Counter Next */
-/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */
-#define US_PTCR_RXTEN (0x1 << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */
-#define US_PTCR_RXTDIS (0x1 << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */
-#define US_PTCR_TXTEN (0x1 << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */
-#define US_PTCR_TXTDIS (0x1 << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */
-/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */
-#define US_PTSR_RXTEN (0x1 << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */
-#define US_PTSR_TXTEN (0x1 << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Watchdog Timer */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3S_WDT Watchdog Timer */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Wdt hardware registers */
-typedef struct {
- WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
- RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
- RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
-} Wdt;
-#endif /* __ASSEMBLY__ */
-/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
-#define WDT_CR_WDRSTT (0x1 << 0) /**< \brief (WDT_CR) Watchdog Restart */
-#define WDT_CR_KEY (0xff << 24) /**< \brief (WDT_CR) Password */
-/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
-#define WDT_MR_WDV (0xfff << 0) /**< \brief (WDT_MR) Watchdog Counter Value */
-#define WDT_MR_WDFIEN (0x1 << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
-#define WDT_MR_WDRSTEN (0x1 << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
-#define WDT_MR_WDRPROC (0x1 << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */
-#define WDT_MR_WDDIS (0x1 << 15) /**< \brief (WDT_MR) Watchdog Disable */
-#define WDT_MR_WDD (0xfff << 16) /**< \brief (WDT_MR) Watchdog Delta Value */
-#define WDT_MR_WDDBGHLT (0x1 << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
-#define WDT_MR_WDIDLEHLT (0x1 << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
-/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
-#define WDT_SR_WDUNF (0x1 << 0) /**< \brief (WDT_SR) Watchdog Underflow */
-#define WDT_SR_WDERR (0x1 << 1) /**< \brief (WDT_SR) Watchdog Error */
-
-/*@}*/
-
-/*@}*/
-
-/* ***************************************************************************** */
-/* REGISTER ACCESS DEFINITIONS FOR AT91SAM3S */
-/* ***************************************************************************** */
-/** \addtogroup AT91SAM3S_reg Registers Access Definitions */
-/*@{*/
-
-/* ========== Register definition for HSMCI peripheral ========== */
-#define REG_HSMCI_CR REG_ACCESS(WoReg, 0x40000000U) /**< \brief (HSMCI) Control Register */
-#define REG_HSMCI_MR REG_ACCESS(RwReg, 0x40000004U) /**< \brief (HSMCI) Mode Register */
-#define REG_HSMCI_DTOR REG_ACCESS(RwReg, 0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
-#define REG_HSMCI_SDCR REG_ACCESS(RwReg, 0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
-#define REG_HSMCI_ARGR REG_ACCESS(RwReg, 0x40000010U) /**< \brief (HSMCI) Argument Register */
-#define REG_HSMCI_CMDR REG_ACCESS(WoReg, 0x40000014U) /**< \brief (HSMCI) Command Register */
-#define REG_HSMCI_BLKR REG_ACCESS(RwReg, 0x40000018U) /**< \brief (HSMCI) Block Register */
-#define REG_HSMCI_CSTOR REG_ACCESS(RwReg, 0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
-#define REG_HSMCI_RSPR REG_ACCESS(RoReg, 0x40000020U) /**< \brief (HSMCI) Response Register */
-#define REG_HSMCI_RDR REG_ACCESS(RoReg, 0x40000030U) /**< \brief (HSMCI) Receive Data Register */
-#define REG_HSMCI_TDR REG_ACCESS(WoReg, 0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
-#define REG_HSMCI_SR REG_ACCESS(RoReg, 0x40000040U) /**< \brief (HSMCI) Status Register */
-#define REG_HSMCI_IER REG_ACCESS(WoReg, 0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
-#define REG_HSMCI_IDR REG_ACCESS(WoReg, 0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
-#define REG_HSMCI_IMR REG_ACCESS(RoReg, 0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
-#define REG_HSMCI_CFG REG_ACCESS(RwReg, 0x40000054U) /**< \brief (HSMCI) Configuration Register */
-#define REG_HSMCI_WPMR REG_ACCESS(RwReg, 0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
-#define REG_HSMCI_WPSR REG_ACCESS(RoReg, 0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
-#define REG_HSMCI_RPR REG_ACCESS(RwReg, 0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */
-#define REG_HSMCI_RCR REG_ACCESS(RwReg, 0x40000104U) /**< \brief (HSMCI) Receive Counter Register */
-#define REG_HSMCI_TPR REG_ACCESS(RwReg, 0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */
-#define REG_HSMCI_TCR REG_ACCESS(RwReg, 0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */
-#define REG_HSMCI_RNPR REG_ACCESS(RwReg, 0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */
-#define REG_HSMCI_RNCR REG_ACCESS(RwReg, 0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */
-#define REG_HSMCI_TNPR REG_ACCESS(RwReg, 0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */
-#define REG_HSMCI_TNCR REG_ACCESS(RwReg, 0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */
-#define REG_HSMCI_PTCR REG_ACCESS(WoReg, 0x40000120U) /**< \brief (HSMCI) Transfer Control Register */
-#define REG_HSMCI_PTSR REG_ACCESS(RoReg, 0x40000124U) /**< \brief (HSMCI) Transfer Status Register */
-/* ========== Register definition for SSC peripheral ========== */
-#define REG_SSC_CR REG_ACCESS(WoReg, 0x40004000U) /**< \brief (SSC) Control Register */
-#define REG_SSC_CMR REG_ACCESS(RwReg, 0x40004004U) /**< \brief (SSC) Clock Mode Register */
-#define REG_SSC_RCMR REG_ACCESS(RwReg, 0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
-#define REG_SSC_RFMR REG_ACCESS(RwReg, 0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
-#define REG_SSC_TCMR REG_ACCESS(RwReg, 0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
-#define REG_SSC_TFMR REG_ACCESS(RwReg, 0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
-#define REG_SSC_RHR REG_ACCESS(RoReg, 0x40004020U) /**< \brief (SSC) Receive Holding Register */
-#define REG_SSC_THR REG_ACCESS(WoReg, 0x40004024U) /**< \brief (SSC) Transmit Holding Register */
-#define REG_SSC_RSHR REG_ACCESS(RoReg, 0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
-#define REG_SSC_TSHR REG_ACCESS(RwReg, 0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
-#define REG_SSC_RC0R REG_ACCESS(RwReg, 0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
-#define REG_SSC_RC1R REG_ACCESS(RwReg, 0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
-#define REG_SSC_SR REG_ACCESS(RoReg, 0x40004040U) /**< \brief (SSC) Status Register */
-#define REG_SSC_IER REG_ACCESS(WoReg, 0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
-#define REG_SSC_IDR REG_ACCESS(WoReg, 0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
-#define REG_SSC_IMR REG_ACCESS(RoReg, 0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
-#define REG_SSC_WPMR REG_ACCESS(RwReg, 0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
-#define REG_SSC_WPSR REG_ACCESS(RoReg, 0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
-#define REG_SSC_RPR REG_ACCESS(RwReg, 0x40004100U) /**< \brief (SSC) Receive Pointer Register */
-#define REG_SSC_RCR REG_ACCESS(RwReg, 0x40004104U) /**< \brief (SSC) Receive Counter Register */
-#define REG_SSC_TPR REG_ACCESS(RwReg, 0x40004108U) /**< \brief (SSC) Transmit Pointer Register */
-#define REG_SSC_TCR REG_ACCESS(RwReg, 0x4000410CU) /**< \brief (SSC) Transmit Counter Register */
-#define REG_SSC_RNPR REG_ACCESS(RwReg, 0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */
-#define REG_SSC_RNCR REG_ACCESS(RwReg, 0x40004114U) /**< \brief (SSC) Receive Next Counter Register */
-#define REG_SSC_TNPR REG_ACCESS(RwReg, 0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */
-#define REG_SSC_TNCR REG_ACCESS(RwReg, 0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */
-#define REG_SSC_PTCR REG_ACCESS(WoReg, 0x40004120U) /**< \brief (SSC) Transfer Control Register */
-#define REG_SSC_PTSR REG_ACCESS(RoReg, 0x40004124U) /**< \brief (SSC) Transfer Status Register */
-/* ========== Register definition for SPI peripheral ========== */
-#define REG_SPI_CR REG_ACCESS(WoReg, 0x40008000U) /**< \brief (SPI) Control Register */
-#define REG_SPI_MR REG_ACCESS(RwReg, 0x40008004U) /**< \brief (SPI) Mode Register */
-#define REG_SPI_RDR REG_ACCESS(RoReg, 0x40008008U) /**< \brief (SPI) Receive Data Register */
-#define REG_SPI_TDR REG_ACCESS(WoReg, 0x4000800CU) /**< \brief (SPI) Transmit Data Register */
-#define REG_SPI_SR REG_ACCESS(RoReg, 0x40008010U) /**< \brief (SPI) Status Register */
-#define REG_SPI_IER REG_ACCESS(WoReg, 0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
-#define REG_SPI_IDR REG_ACCESS(WoReg, 0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
-#define REG_SPI_IMR REG_ACCESS(RoReg, 0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
-#define REG_SPI_CSR REG_ACCESS(RwReg, 0x40008030U) /**< \brief (SPI) Chip Select Register */
-#define REG_SPI_WPMR REG_ACCESS(RwReg, 0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
-#define REG_SPI_WPSR REG_ACCESS(RoReg, 0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
-#define REG_SPI_RPR REG_ACCESS(RwReg, 0x40008100U) /**< \brief (SPI) Receive Pointer Register */
-#define REG_SPI_RCR REG_ACCESS(RwReg, 0x40008104U) /**< \brief (SPI) Receive Counter Register */
-#define REG_SPI_TPR REG_ACCESS(RwReg, 0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
-#define REG_SPI_TCR REG_ACCESS(RwReg, 0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
-#define REG_SPI_RNPR REG_ACCESS(RwReg, 0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
-#define REG_SPI_RNCR REG_ACCESS(RwReg, 0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
-#define REG_SPI_TNPR REG_ACCESS(RwReg, 0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
-#define REG_SPI_TNCR REG_ACCESS(RwReg, 0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
-#define REG_SPI_PTCR REG_ACCESS(WoReg, 0x40008120U) /**< \brief (SPI) Transfer Control Register */
-#define REG_SPI_PTSR REG_ACCESS(RoReg, 0x40008124U) /**< \brief (SPI) Transfer Status Register */
-/* ========== Register definition for TC0 peripheral ========== */
-#define REG_TC0_CCR0 REG_ACCESS(WoReg, 0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
-#define REG_TC0_CMR0 REG_ACCESS(RwReg, 0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
-#define REG_TC0_CV0 REG_ACCESS(RoReg, 0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */
-#define REG_TC0_RA0 REG_ACCESS(RwReg, 0x40010014U) /**< \brief (TC0) Register A (channel = 0) */
-#define REG_TC0_RB0 REG_ACCESS(RwReg, 0x40010018U) /**< \brief (TC0) Register B (channel = 0) */
-#define REG_TC0_RC0 REG_ACCESS(RwReg, 0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */
-#define REG_TC0_SR0 REG_ACCESS(RoReg, 0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */
-#define REG_TC0_IER0 REG_ACCESS(WoReg, 0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
-#define REG_TC0_IDR0 REG_ACCESS(WoReg, 0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
-#define REG_TC0_IMR0 REG_ACCESS(RoReg, 0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
-#define REG_TC0_CCR1 REG_ACCESS(WoReg, 0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
-#define REG_TC0_CMR1 REG_ACCESS(RwReg, 0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
-#define REG_TC0_CV1 REG_ACCESS(RoReg, 0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */
-#define REG_TC0_RA1 REG_ACCESS(RwReg, 0x40010054U) /**< \brief (TC0) Register A (channel = 1) */
-#define REG_TC0_RB1 REG_ACCESS(RwReg, 0x40010058U) /**< \brief (TC0) Register B (channel = 1) */
-#define REG_TC0_RC1 REG_ACCESS(RwReg, 0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */
-#define REG_TC0_SR1 REG_ACCESS(RoReg, 0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */
-#define REG_TC0_IER1 REG_ACCESS(WoReg, 0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
-#define REG_TC0_IDR1 REG_ACCESS(WoReg, 0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
-#define REG_TC0_IMR1 REG_ACCESS(RoReg, 0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
-#define REG_TC0_CCR2 REG_ACCESS(WoReg, 0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
-#define REG_TC0_CMR2 REG_ACCESS(RwReg, 0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
-#define REG_TC0_CV2 REG_ACCESS(RoReg, 0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */
-#define REG_TC0_RA2 REG_ACCESS(RwReg, 0x40010094U) /**< \brief (TC0) Register A (channel = 2) */
-#define REG_TC0_RB2 REG_ACCESS(RwReg, 0x40010098U) /**< \brief (TC0) Register B (channel = 2) */
-#define REG_TC0_RC2 REG_ACCESS(RwReg, 0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */
-#define REG_TC0_SR2 REG_ACCESS(RoReg, 0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */
-#define REG_TC0_IER2 REG_ACCESS(WoReg, 0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
-#define REG_TC0_IDR2 REG_ACCESS(WoReg, 0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
-#define REG_TC0_IMR2 REG_ACCESS(RoReg, 0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
-#define REG_TC0_BCR REG_ACCESS(WoReg, 0x400100C0U) /**< \brief (TC0) Block Control Register */
-#define REG_TC0_BMR REG_ACCESS(RwReg, 0x400100C4U) /**< \brief (TC0) Block Mode Register */
-#define REG_TC0_QIER REG_ACCESS(WoReg, 0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
-#define REG_TC0_QIDR REG_ACCESS(WoReg, 0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
-#define REG_TC0_QIMR REG_ACCESS(RoReg, 0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
-#define REG_TC0_QISR REG_ACCESS(RoReg, 0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
-#define REG_TC0_FMR REG_ACCESS(RwReg, 0x400100D8U) /**< \brief (TC0) Fault Mode Register */
-#define REG_TC0_WPMR REG_ACCESS(RwReg, 0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */
-#define REG_TC0_VER REG_ACCESS(RoReg, 0x400100FCU) /**< \brief (TC0) Version Register */
-/* ========== Register definition for TC1 peripheral ========== */
-#define REG_TC1_CCR0 REG_ACCESS(WoReg, 0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
-#define REG_TC1_CMR0 REG_ACCESS(RwReg, 0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
-#define REG_TC1_CV0 REG_ACCESS(RoReg, 0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */
-#define REG_TC1_RA0 REG_ACCESS(RwReg, 0x40014014U) /**< \brief (TC1) Register A (channel = 0) */
-#define REG_TC1_RB0 REG_ACCESS(RwReg, 0x40014018U) /**< \brief (TC1) Register B (channel = 0) */
-#define REG_TC1_RC0 REG_ACCESS(RwReg, 0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */
-#define REG_TC1_SR0 REG_ACCESS(RoReg, 0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */
-#define REG_TC1_IER0 REG_ACCESS(WoReg, 0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
-#define REG_TC1_IDR0 REG_ACCESS(WoReg, 0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
-#define REG_TC1_IMR0 REG_ACCESS(RoReg, 0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
-#define REG_TC1_CCR1 REG_ACCESS(WoReg, 0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
-#define REG_TC1_CMR1 REG_ACCESS(RwReg, 0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
-#define REG_TC1_CV1 REG_ACCESS(RoReg, 0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */
-#define REG_TC1_RA1 REG_ACCESS(RwReg, 0x40014054U) /**< \brief (TC1) Register A (channel = 1) */
-#define REG_TC1_RB1 REG_ACCESS(RwReg, 0x40014058U) /**< \brief (TC1) Register B (channel = 1) */
-#define REG_TC1_RC1 REG_ACCESS(RwReg, 0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */
-#define REG_TC1_SR1 REG_ACCESS(RoReg, 0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */
-#define REG_TC1_IER1 REG_ACCESS(WoReg, 0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
-#define REG_TC1_IDR1 REG_ACCESS(WoReg, 0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
-#define REG_TC1_IMR1 REG_ACCESS(RoReg, 0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
-#define REG_TC1_CCR2 REG_ACCESS(WoReg, 0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
-#define REG_TC1_CMR2 REG_ACCESS(RwReg, 0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
-#define REG_TC1_CV2 REG_ACCESS(RoReg, 0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */
-#define REG_TC1_RA2 REG_ACCESS(RwReg, 0x40014094U) /**< \brief (TC1) Register A (channel = 2) */
-#define REG_TC1_RB2 REG_ACCESS(RwReg, 0x40014098U) /**< \brief (TC1) Register B (channel = 2) */
-#define REG_TC1_RC2 REG_ACCESS(RwReg, 0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */
-#define REG_TC1_SR2 REG_ACCESS(RoReg, 0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */
-#define REG_TC1_IER2 REG_ACCESS(WoReg, 0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
-#define REG_TC1_IDR2 REG_ACCESS(WoReg, 0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
-#define REG_TC1_IMR2 REG_ACCESS(RoReg, 0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
-#define REG_TC1_BCR REG_ACCESS(WoReg, 0x400140C0U) /**< \brief (TC1) Block Control Register */
-#define REG_TC1_BMR REG_ACCESS(RwReg, 0x400140C4U) /**< \brief (TC1) Block Mode Register */
-#define REG_TC1_QIER REG_ACCESS(WoReg, 0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
-#define REG_TC1_QIDR REG_ACCESS(WoReg, 0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
-#define REG_TC1_QIMR REG_ACCESS(RoReg, 0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
-#define REG_TC1_QISR REG_ACCESS(RoReg, 0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
-#define REG_TC1_FMR REG_ACCESS(RwReg, 0x400140D8U) /**< \brief (TC1) Fault Mode Register */
-#define REG_TC1_WPMR REG_ACCESS(RwReg, 0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */
-#define REG_TC1_VER REG_ACCESS(RoReg, 0x400140FCU) /**< \brief (TC1) Version Register */
-/* ========== Register definition for TWI0 peripheral ========== */
-#define REG_TWI0_CR REG_ACCESS(WoReg, 0x40018000U) /**< \brief (TWI0) Control Register */
-#define REG_TWI0_MMR REG_ACCESS(RwReg, 0x40018004U) /**< \brief (TWI0) Master Mode Register */
-#define REG_TWI0_SMR REG_ACCESS(RwReg, 0x40018008U) /**< \brief (TWI0) Slave Mode Register */
-#define REG_TWI0_IADR REG_ACCESS(RwReg, 0x4001800CU) /**< \brief (TWI0) Internal Address Register */
-#define REG_TWI0_CWGR REG_ACCESS(RwReg, 0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */
-#define REG_TWI0_SR REG_ACCESS(RoReg, 0x40018020U) /**< \brief (TWI0) Status Register */
-#define REG_TWI0_IER REG_ACCESS(WoReg, 0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */
-#define REG_TWI0_IDR REG_ACCESS(WoReg, 0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */
-#define REG_TWI0_IMR REG_ACCESS(RoReg, 0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */
-#define REG_TWI0_RHR REG_ACCESS(RoReg, 0x40018030U) /**< \brief (TWI0) Receive Holding Register */
-#define REG_TWI0_THR REG_ACCESS(WoReg, 0x40018034U) /**< \brief (TWI0) Transmit Holding Register */
-#define REG_TWI0_RPR REG_ACCESS(RwReg, 0x40018100U) /**< \brief (TWI0) Receive Pointer Register */
-#define REG_TWI0_RCR REG_ACCESS(RwReg, 0x40018104U) /**< \brief (TWI0) Receive Counter Register */
-#define REG_TWI0_TPR REG_ACCESS(RwReg, 0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */
-#define REG_TWI0_TCR REG_ACCESS(RwReg, 0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */
-#define REG_TWI0_RNPR REG_ACCESS(RwReg, 0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */
-#define REG_TWI0_RNCR REG_ACCESS(RwReg, 0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */
-#define REG_TWI0_TNPR REG_ACCESS(RwReg, 0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */
-#define REG_TWI0_TNCR REG_ACCESS(RwReg, 0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */
-#define REG_TWI0_PTCR REG_ACCESS(WoReg, 0x40018120U) /**< \brief (TWI0) Transfer Control Register */
-#define REG_TWI0_PTSR REG_ACCESS(RoReg, 0x40018124U) /**< \brief (TWI0) Transfer Status Register */
-/* ========== Register definition for TWI1 peripheral ========== */
-#define REG_TWI1_CR REG_ACCESS(WoReg, 0x4001C000U) /**< \brief (TWI1) Control Register */
-#define REG_TWI1_MMR REG_ACCESS(RwReg, 0x4001C004U) /**< \brief (TWI1) Master Mode Register */
-#define REG_TWI1_SMR REG_ACCESS(RwReg, 0x4001C008U) /**< \brief (TWI1) Slave Mode Register */
-#define REG_TWI1_IADR REG_ACCESS(RwReg, 0x4001C00CU) /**< \brief (TWI1) Internal Address Register */
-#define REG_TWI1_CWGR REG_ACCESS(RwReg, 0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */
-#define REG_TWI1_SR REG_ACCESS(RoReg, 0x4001C020U) /**< \brief (TWI1) Status Register */
-#define REG_TWI1_IER REG_ACCESS(WoReg, 0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */
-#define REG_TWI1_IDR REG_ACCESS(WoReg, 0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */
-#define REG_TWI1_IMR REG_ACCESS(RoReg, 0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */
-#define REG_TWI1_RHR REG_ACCESS(RoReg, 0x4001C030U) /**< \brief (TWI1) Receive Holding Register */
-#define REG_TWI1_THR REG_ACCESS(WoReg, 0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */
-#define REG_TWI1_RPR REG_ACCESS(RwReg, 0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */
-#define REG_TWI1_RCR REG_ACCESS(RwReg, 0x4001C104U) /**< \brief (TWI1) Receive Counter Register */
-#define REG_TWI1_TPR REG_ACCESS(RwReg, 0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */
-#define REG_TWI1_TCR REG_ACCESS(RwReg, 0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */
-#define REG_TWI1_RNPR REG_ACCESS(RwReg, 0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */
-#define REG_TWI1_RNCR REG_ACCESS(RwReg, 0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */
-#define REG_TWI1_TNPR REG_ACCESS(RwReg, 0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */
-#define REG_TWI1_TNCR REG_ACCESS(RwReg, 0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */
-#define REG_TWI1_PTCR REG_ACCESS(WoReg, 0x4001C120U) /**< \brief (TWI1) Transfer Control Register */
-#define REG_TWI1_PTSR REG_ACCESS(RoReg, 0x4001C124U) /**< \brief (TWI1) Transfer Status Register */
-/* ========== Register definition for PWM peripheral ========== */
-#define REG_PWM_CLK REG_ACCESS(RwReg, 0x40020000U) /**< \brief (PWM) PWM Clock Register */
-#define REG_PWM_ENA REG_ACCESS(WoReg, 0x40020004U) /**< \brief (PWM) PWM Enable Register */
-#define REG_PWM_DIS REG_ACCESS(WoReg, 0x40020008U) /**< \brief (PWM) PWM Disable Register */
-#define REG_PWM_SR REG_ACCESS(RoReg, 0x4002000CU) /**< \brief (PWM) PWM Status Register */
-#define REG_PWM_IER1 REG_ACCESS(WoReg, 0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
-#define REG_PWM_IDR1 REG_ACCESS(WoReg, 0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
-#define REG_PWM_IMR1 REG_ACCESS(RoReg, 0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
-#define REG_PWM_ISR1 REG_ACCESS(RoReg, 0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
-#define REG_PWM_SCM REG_ACCESS(RwReg, 0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
-#define REG_PWM_SCUC REG_ACCESS(RwReg, 0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
-#define REG_PWM_SCUP REG_ACCESS(RwReg, 0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
-#define REG_PWM_SCUPUPD REG_ACCESS(WoReg, 0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
-#define REG_PWM_IER2 REG_ACCESS(WoReg, 0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
-#define REG_PWM_IDR2 REG_ACCESS(WoReg, 0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
-#define REG_PWM_IMR2 REG_ACCESS(RoReg, 0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
-#define REG_PWM_ISR2 REG_ACCESS(RoReg, 0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
-#define REG_PWM_OOV REG_ACCESS(RwReg, 0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */
-#define REG_PWM_OS REG_ACCESS(RwReg, 0x40020048U) /**< \brief (PWM) PWM Output Selection Register */
-#define REG_PWM_OSS REG_ACCESS(WoReg, 0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */
-#define REG_PWM_OSC REG_ACCESS(WoReg, 0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */
-#define REG_PWM_OSSUPD REG_ACCESS(WoReg, 0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
-#define REG_PWM_OSCUPD REG_ACCESS(WoReg, 0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
-#define REG_PWM_FMR REG_ACCESS(RwReg, 0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */
-#define REG_PWM_FSR REG_ACCESS(RoReg, 0x40020060U) /**< \brief (PWM) PWM Fault Status Register */
-#define REG_PWM_FCR REG_ACCESS(WoReg, 0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */
-#define REG_PWM_FPV REG_ACCESS(RwReg, 0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */
-#define REG_PWM_FPE REG_ACCESS(RwReg, 0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
-#define REG_PWM_ELxMR REG_ACCESS(RwReg, 0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
-#define REG_PWM_SMMR REG_ACCESS(RwReg, 0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
-#define REG_PWM_WPCR REG_ACCESS(WoReg, 0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */
-#define REG_PWM_WPSR REG_ACCESS(RoReg, 0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */
-#define REG_PWM_RPR REG_ACCESS(RwReg, 0x40020100U) /**< \brief (PWM) Receive Pointer Register */
-#define REG_PWM_RCR REG_ACCESS(RwReg, 0x40020104U) /**< \brief (PWM) Receive Counter Register */
-#define REG_PWM_TPR REG_ACCESS(RwReg, 0x40020108U) /**< \brief (PWM) Transmit Pointer Register */
-#define REG_PWM_TCR REG_ACCESS(RwReg, 0x4002010CU) /**< \brief (PWM) Transmit Counter Register */
-#define REG_PWM_RNPR REG_ACCESS(RwReg, 0x40020110U) /**< \brief (PWM) Receive Next Pointer Register */
-#define REG_PWM_RNCR REG_ACCESS(RwReg, 0x40020114U) /**< \brief (PWM) Receive Next Counter Register */
-#define REG_PWM_TNPR REG_ACCESS(RwReg, 0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */
-#define REG_PWM_TNCR REG_ACCESS(RwReg, 0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */
-#define REG_PWM_PTCR REG_ACCESS(WoReg, 0x40020120U) /**< \brief (PWM) Transfer Control Register */
-#define REG_PWM_PTSR REG_ACCESS(RoReg, 0x40020124U) /**< \brief (PWM) Transfer Status Register */
-#define REG_PWM_CMP0V REG_ACCESS(RwReg, 0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
-#define REG_PWM_CMP0VUPD REG_ACCESS(WoReg, 0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
-#define REG_PWM_CMP0M REG_ACCESS(RwReg, 0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
-#define REG_PWM_CMP0MUPD REG_ACCESS(WoReg, 0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
-#define REG_PWM_CMP1V REG_ACCESS(RwReg, 0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
-#define REG_PWM_CMP1VUPD REG_ACCESS(WoReg, 0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
-#define REG_PWM_CMP1M REG_ACCESS(RwReg, 0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
-#define REG_PWM_CMP1MUPD REG_ACCESS(WoReg, 0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
-#define REG_PWM_CMP2V REG_ACCESS(RwReg, 0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
-#define REG_PWM_CMP2VUPD REG_ACCESS(WoReg, 0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
-#define REG_PWM_CMP2M REG_ACCESS(RwReg, 0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
-#define REG_PWM_CMP2MUPD REG_ACCESS(WoReg, 0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
-#define REG_PWM_CMP3V REG_ACCESS(RwReg, 0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
-#define REG_PWM_CMP3VUPD REG_ACCESS(WoReg, 0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
-#define REG_PWM_CMP3M REG_ACCESS(RwReg, 0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
-#define REG_PWM_CMP3MUPD REG_ACCESS(WoReg, 0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
-#define REG_PWM_CMP4V REG_ACCESS(RwReg, 0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
-#define REG_PWM_CMP4VUPD REG_ACCESS(WoReg, 0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
-#define REG_PWM_CMP4M REG_ACCESS(RwReg, 0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
-#define REG_PWM_CMP4MUPD REG_ACCESS(WoReg, 0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
-#define REG_PWM_CMP5V REG_ACCESS(RwReg, 0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
-#define REG_PWM_CMP5VUPD REG_ACCESS(WoReg, 0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
-#define REG_PWM_CMP5M REG_ACCESS(RwReg, 0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
-#define REG_PWM_CMP5MUPD REG_ACCESS(WoReg, 0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
-#define REG_PWM_CMP6V REG_ACCESS(RwReg, 0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
-#define REG_PWM_CMP6VUPD REG_ACCESS(WoReg, 0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
-#define REG_PWM_CMP6M REG_ACCESS(RwReg, 0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
-#define REG_PWM_CMP6MUPD REG_ACCESS(WoReg, 0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
-#define REG_PWM_CMP7V REG_ACCESS(RwReg, 0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
-#define REG_PWM_CMP7VUPD REG_ACCESS(WoReg, 0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
-#define REG_PWM_CMP7M REG_ACCESS(RwReg, 0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
-#define REG_PWM_CMP7MUPD REG_ACCESS(WoReg, 0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
-#define REG_PWM_CMR0 REG_ACCESS(RwReg, 0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
-#define REG_PWM_CDTY0 REG_ACCESS(RwReg, 0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
-#define REG_PWM_CDTYUPD0 REG_ACCESS(WoReg, 0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
-#define REG_PWM_CPRD0 REG_ACCESS(RwReg, 0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
-#define REG_PWM_CPRDUPD0 REG_ACCESS(WoReg, 0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
-#define REG_PWM_CCNT0 REG_ACCESS(RoReg, 0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
-#define REG_PWM_DT0 REG_ACCESS(RwReg, 0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
-#define REG_PWM_DTUPD0 REG_ACCESS(WoReg, 0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
-#define REG_PWM_CMR1 REG_ACCESS(RwReg, 0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
-#define REG_PWM_CDTY1 REG_ACCESS(RwReg, 0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
-#define REG_PWM_CDTYUPD1 REG_ACCESS(WoReg, 0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
-#define REG_PWM_CPRD1 REG_ACCESS(RwReg, 0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
-#define REG_PWM_CPRDUPD1 REG_ACCESS(WoReg, 0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
-#define REG_PWM_CCNT1 REG_ACCESS(RoReg, 0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
-#define REG_PWM_DT1 REG_ACCESS(RwReg, 0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
-#define REG_PWM_DTUPD1 REG_ACCESS(WoReg, 0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
-#define REG_PWM_CMR2 REG_ACCESS(RwReg, 0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
-#define REG_PWM_CDTY2 REG_ACCESS(RwReg, 0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
-#define REG_PWM_CDTYUPD2 REG_ACCESS(WoReg, 0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
-#define REG_PWM_CPRD2 REG_ACCESS(RwReg, 0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
-#define REG_PWM_CPRDUPD2 REG_ACCESS(WoReg, 0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
-#define REG_PWM_CCNT2 REG_ACCESS(RoReg, 0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
-#define REG_PWM_DT2 REG_ACCESS(RwReg, 0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
-#define REG_PWM_DTUPD2 REG_ACCESS(WoReg, 0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
-#define REG_PWM_CMR3 REG_ACCESS(RwReg, 0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
-#define REG_PWM_CDTY3 REG_ACCESS(RwReg, 0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
-#define REG_PWM_CDTYUPD3 REG_ACCESS(WoReg, 0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
-#define REG_PWM_CPRD3 REG_ACCESS(RwReg, 0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
-#define REG_PWM_CPRDUPD3 REG_ACCESS(WoReg, 0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
-#define REG_PWM_CCNT3 REG_ACCESS(RoReg, 0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
-#define REG_PWM_DT3 REG_ACCESS(RwReg, 0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
-#define REG_PWM_DTUPD3 REG_ACCESS(WoReg, 0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
-/* ========== Register definition for USART0 peripheral ========== */
-#define REG_USART0_CR REG_ACCESS(WoReg, 0x40024000U) /**< \brief (USART0) Control Register */
-#define REG_USART0_MR REG_ACCESS(RwReg, 0x40024004U) /**< \brief (USART0) Mode Register */
-#define REG_USART0_IER REG_ACCESS(WoReg, 0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
-#define REG_USART0_IDR REG_ACCESS(WoReg, 0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
-#define REG_USART0_IMR REG_ACCESS(RoReg, 0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
-#define REG_USART0_CSR REG_ACCESS(RoReg, 0x40024014U) /**< \brief (USART0) Channel Status Register */
-#define REG_USART0_RHR REG_ACCESS(RoReg, 0x40024018U) /**< \brief (USART0) Receiver Holding Register */
-#define REG_USART0_THR REG_ACCESS(WoReg, 0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */
-#define REG_USART0_BRGR REG_ACCESS(RwReg, 0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
-#define REG_USART0_RTOR REG_ACCESS(RwReg, 0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
-#define REG_USART0_TTGR REG_ACCESS(RwReg, 0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
-#define REG_USART0_FIDI REG_ACCESS(RwReg, 0x40024040U) /**< \brief (USART0) FI DI Ratio Register */
-#define REG_USART0_NER REG_ACCESS(RoReg, 0x40024044U) /**< \brief (USART0) Number of Errors Register */
-#define REG_USART0_IF REG_ACCESS(RwReg, 0x4002404CU) /**< \brief (USART0) IrDA Filter Register */
-#define REG_USART0_MAN REG_ACCESS(RwReg, 0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
-#define REG_USART0_WPMR REG_ACCESS(RwReg, 0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */
-#define REG_USART0_WPSR REG_ACCESS(RoReg, 0x400240E8U) /**< \brief (USART0) Write Protect Status Register */
-#define REG_USART0_VERSION REG_ACCESS(RoReg, 0x400240FCU) /**< \brief (USART0) Version Register */
-#define REG_USART0_RPR REG_ACCESS(RwReg, 0x40024100U) /**< \brief (USART0) Receive Pointer Register */
-#define REG_USART0_RCR REG_ACCESS(RwReg, 0x40024104U) /**< \brief (USART0) Receive Counter Register */
-#define REG_USART0_TPR REG_ACCESS(RwReg, 0x40024108U) /**< \brief (USART0) Transmit Pointer Register */
-#define REG_USART0_TCR REG_ACCESS(RwReg, 0x4002410CU) /**< \brief (USART0) Transmit Counter Register */
-#define REG_USART0_RNPR REG_ACCESS(RwReg, 0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */
-#define REG_USART0_RNCR REG_ACCESS(RwReg, 0x40024114U) /**< \brief (USART0) Receive Next Counter Register */
-#define REG_USART0_TNPR REG_ACCESS(RwReg, 0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */
-#define REG_USART0_TNCR REG_ACCESS(RwReg, 0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */
-#define REG_USART0_PTCR REG_ACCESS(WoReg, 0x40024120U) /**< \brief (USART0) Transfer Control Register */
-#define REG_USART0_PTSR REG_ACCESS(RoReg, 0x40024124U) /**< \brief (USART0) Transfer Status Register */
-/* ========== Register definition for USART1 peripheral ========== */
-#define REG_USART1_CR REG_ACCESS(WoReg, 0x40028000U) /**< \brief (USART1) Control Register */
-#define REG_USART1_MR REG_ACCESS(RwReg, 0x40028004U) /**< \brief (USART1) Mode Register */
-#define REG_USART1_IER REG_ACCESS(WoReg, 0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
-#define REG_USART1_IDR REG_ACCESS(WoReg, 0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
-#define REG_USART1_IMR REG_ACCESS(RoReg, 0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
-#define REG_USART1_CSR REG_ACCESS(RoReg, 0x40028014U) /**< \brief (USART1) Channel Status Register */
-#define REG_USART1_RHR REG_ACCESS(RoReg, 0x40028018U) /**< \brief (USART1) Receiver Holding Register */
-#define REG_USART1_THR REG_ACCESS(WoReg, 0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */
-#define REG_USART1_BRGR REG_ACCESS(RwReg, 0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
-#define REG_USART1_RTOR REG_ACCESS(RwReg, 0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
-#define REG_USART1_TTGR REG_ACCESS(RwReg, 0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
-#define REG_USART1_FIDI REG_ACCESS(RwReg, 0x40028040U) /**< \brief (USART1) FI DI Ratio Register */
-#define REG_USART1_NER REG_ACCESS(RoReg, 0x40028044U) /**< \brief (USART1) Number of Errors Register */
-#define REG_USART1_IF REG_ACCESS(RwReg, 0x4002804CU) /**< \brief (USART1) IrDA Filter Register */
-#define REG_USART1_MAN REG_ACCESS(RwReg, 0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
-#define REG_USART1_WPMR REG_ACCESS(RwReg, 0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */
-#define REG_USART1_WPSR REG_ACCESS(RoReg, 0x400280E8U) /**< \brief (USART1) Write Protect Status Register */
-#define REG_USART1_VERSION REG_ACCESS(RoReg, 0x400280FCU) /**< \brief (USART1) Version Register */
-#define REG_USART1_RPR REG_ACCESS(RwReg, 0x40028100U) /**< \brief (USART1) Receive Pointer Register */
-#define REG_USART1_RCR REG_ACCESS(RwReg, 0x40028104U) /**< \brief (USART1) Receive Counter Register */
-#define REG_USART1_TPR REG_ACCESS(RwReg, 0x40028108U) /**< \brief (USART1) Transmit Pointer Register */
-#define REG_USART1_TCR REG_ACCESS(RwReg, 0x4002810CU) /**< \brief (USART1) Transmit Counter Register */
-#define REG_USART1_RNPR REG_ACCESS(RwReg, 0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */
-#define REG_USART1_RNCR REG_ACCESS(RwReg, 0x40028114U) /**< \brief (USART1) Receive Next Counter Register */
-#define REG_USART1_TNPR REG_ACCESS(RwReg, 0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */
-#define REG_USART1_TNCR REG_ACCESS(RwReg, 0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */
-#define REG_USART1_PTCR REG_ACCESS(WoReg, 0x40028120U) /**< \brief (USART1) Transfer Control Register */
-#define REG_USART1_PTSR REG_ACCESS(RoReg, 0x40028124U) /**< \brief (USART1) Transfer Status Register */
-/* ========== Register definition for UDP peripheral ========== */
-#define REG_UDP_FRM_NUM REG_ACCESS(RoReg, 0x40034000U) /**< \brief (UDP) Frame Number Register */
-#define REG_UDP_GLB_STAT REG_ACCESS(RwReg, 0x40034004U) /**< \brief (UDP) Global State Register */
-#define REG_UDP_FADDR REG_ACCESS(RwReg, 0x40034008U) /**< \brief (UDP) Function Address Register */
-#define REG_UDP_IER REG_ACCESS(WoReg, 0x40034010U) /**< \brief (UDP) Interrupt Enable Register */
-#define REG_UDP_IDR REG_ACCESS(WoReg, 0x40034014U) /**< \brief (UDP) Interrupt Disable Register */
-#define REG_UDP_IMR REG_ACCESS(RoReg, 0x40034018U) /**< \brief (UDP) Interrupt Mask Register */
-#define REG_UDP_ISR REG_ACCESS(RoReg, 0x4003401CU) /**< \brief (UDP) Interrupt Status Register */
-#define REG_UDP_ICR REG_ACCESS(WoReg, 0x40034020U) /**< \brief (UDP) Interrupt Clear Register */
-#define REG_UDP_RST_EP REG_ACCESS(RwReg, 0x40034028U) /**< \brief (UDP) Reset Endpoint Register */
-#define REG_UDP_CSR REG_ACCESS(RwReg, 0x4003402CU) /**< \brief (UDP) Endpoint Control and Status Register (ept_num = 0) */
-#define REG_UDP_FDR REG_ACCESS(RwReg, 0x4003404CU) /**< \brief (UDP) Endpoint FIFO Data Register (ept_num = 0) */
-#define REG_UDP_TXVC REG_ACCESS(RwReg, 0x40034074U) /**< \brief (UDP) Transceiver Control Register */
-/* ========== Register definition for ADC peripheral ========== */
-#define REG_ADC_CR REG_ACCESS(WoReg, 0x40038000U) /**< \brief (ADC) Control Register */
-#define REG_ADC_MR REG_ACCESS(RwReg, 0x40038004U) /**< \brief (ADC) Mode Register */
-#define REG_ADC_SEQ1R REG_ACCESS(RwReg, 0x40038008U) /**< \brief (ADC) Channel Sequence 1Register */
-#define REG_ADC_SEQ2R REG_ACCESS(RwReg, 0x4003800CU) /**< \brief (ADC) Channel Sequence 2 Register */
-#define REG_ADC_CHER REG_ACCESS(WoReg, 0x40038010U) /**< \brief (ADC) Channel Enable Register */
-#define REG_ADC_CHDR REG_ACCESS(WoReg, 0x40038014U) /**< \brief (ADC) Channel Disable Register */
-#define REG_ADC_CHSR REG_ACCESS(RoReg, 0x40038018U) /**< \brief (ADC) Channel Status Register */
-#define REG_ADC_LCDR REG_ACCESS(RoReg, 0x40038020U) /**< \brief (ADC) Last Converted Data Register */
-#define REG_ADC_IER REG_ACCESS(WoReg, 0x40038024U) /**< \brief (ADC) Interrupt Enable Register */
-#define REG_ADC_IDR REG_ACCESS(WoReg, 0x40038028U) /**< \brief (ADC) Interrupt Disable Register */
-#define REG_ADC_IMR REG_ACCESS(RoReg, 0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */
-#define REG_ADC_ISR REG_ACCESS(RoReg, 0x40038030U) /**< \brief (ADC) Interrupt Status Register */
-#define REG_ADC_OVER REG_ACCESS(RoReg, 0x4003803CU) /**< \brief (ADC) Overrun Status Register */
-#define REG_ADC_EMR REG_ACCESS(RwReg, 0x40038040U) /**< \brief (ADC) Extended Mode Register */
-#define REG_ADC_CWR REG_ACCESS(RwReg, 0x40038044U) /**< \brief (ADC) Compare Window Register */
-#define REG_ADC_CGR REG_ACCESS(RwReg, 0x40038048U) /**< \brief (ADC) Channel Gain Register */
-#define REG_ADC_COR REG_ACCESS(RwReg, 0x4003804CU) /**< \brief (ADC) Channel Offset Register */
-#define REG_ADC_CDR0 REG_ACCESS(RoReg, 0x40038050U) /**< \brief (ADC) Channel Data Register 0 */
-#define REG_ADC_CDR1 REG_ACCESS(RoReg, 0x40038054U) /**< \brief (ADC) Channel Data Register 1 */
-#define REG_ADC_CDR2 REG_ACCESS(RoReg, 0x40038058U) /**< \brief (ADC) Channel Data Register 2 */
-#define REG_ADC_CDR3 REG_ACCESS(RoReg, 0x4003805CU) /**< \brief (ADC) Channel Data Register 3 */
-#define REG_ADC_CDR4 REG_ACCESS(RoReg, 0x40038060U) /**< \brief (ADC) Channel Data Register 4 */
-#define REG_ADC_CDR5 REG_ACCESS(RoReg, 0x40038064U) /**< \brief (ADC) Channel Data Register 5 */
-#define REG_ADC_CDR6 REG_ACCESS(RoReg, 0x40038068U) /**< \brief (ADC) Channel Data Register 6 */
-#define REG_ADC_CDR15 REG_ACCESS(RoReg, 0x4003806CU) /**< \brief (ADC) Channel Data Register 15 */
-#define REG_ADC_ACR REG_ACCESS(RwReg, 0x40038094U) /**< \brief (ADC) Analog Control Register */
-#define REG_ADC_WPMR REG_ACCESS(RwReg, 0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */
-#define REG_ADC_WPSR REG_ACCESS(RoReg, 0x400380E8U) /**< \brief (ADC) Write Protect Status Register */
-#define REG_ADC_RPR REG_ACCESS(RwReg, 0x40038100U) /**< \brief (ADC) Receive Pointer Register */
-#define REG_ADC_RCR REG_ACCESS(RwReg, 0x40038104U) /**< \brief (ADC) Receive Counter Register */
-#define REG_ADC_TPR REG_ACCESS(RwReg, 0x40038108U) /**< \brief (ADC) Transmit Pointer Register */
-#define REG_ADC_TCR REG_ACCESS(RwReg, 0x4003810CU) /**< \brief (ADC) Transmit Counter Register */
-#define REG_ADC_RNPR REG_ACCESS(RwReg, 0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */
-#define REG_ADC_RNCR REG_ACCESS(RwReg, 0x40038114U) /**< \brief (ADC) Receive Next Counter Register */
-#define REG_ADC_TNPR REG_ACCESS(RwReg, 0x40038118U) /**< \brief (ADC) Transmit Next Pointer Register */
-#define REG_ADC_TNCR REG_ACCESS(RwReg, 0x4003811CU) /**< \brief (ADC) Transmit Next Counter Register */
-#define REG_ADC_PTCR REG_ACCESS(WoReg, 0x40038120U) /**< \brief (ADC) Transfer Control Register */
-#define REG_ADC_PTSR REG_ACCESS(RoReg, 0x40038124U) /**< \brief (ADC) Transfer Status Register */
-/* ========== Register definition for DACC peripheral ========== */
-#define REG_DACC_CR REG_ACCESS(WoReg, 0x4003C000U) /**< \brief (DACC) Control Register */
-#define REG_DACC_MR REG_ACCESS(RwReg, 0x4003C004U) /**< \brief (DACC) Mode Register */
-#define REG_DACC_CHER REG_ACCESS(WoReg, 0x4003C010U) /**< \brief (DACC) Channel Enable Register */
-#define REG_DACC_CHDR REG_ACCESS(WoReg, 0x4003C014U) /**< \brief (DACC) Channel Disable Register */
-#define REG_DACC_CHSR REG_ACCESS(RoReg, 0x4003C018U) /**< \brief (DACC) Channel Status Register */
-#define REG_DACC_CDR REG_ACCESS(WoReg, 0x4003C020U) /**< \brief (DACC) Conversion Data Register */
-#define REG_DACC_IER REG_ACCESS(WoReg, 0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */
-#define REG_DACC_IDR REG_ACCESS(WoReg, 0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */
-#define REG_DACC_IMR REG_ACCESS(RoReg, 0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */
-#define REG_DACC_ISR REG_ACCESS(RoReg, 0x4003C030U) /**< \brief (DACC) Interrupt Status Register */
-#define REG_DACC_ACR REG_ACCESS(RwReg, 0x4003C094U) /**< \brief (DACC) Analog Current Register */
-#define REG_DACC_WPMR REG_ACCESS(RwReg, 0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */
-#define REG_DACC_WPSR REG_ACCESS(RoReg, 0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */
-#define REG_DACC_RPR REG_ACCESS(RwReg, 0x4003C100U) /**< \brief (DACC) Receive Pointer Register */
-#define REG_DACC_RCR REG_ACCESS(RwReg, 0x4003C104U) /**< \brief (DACC) Receive Counter Register */
-#define REG_DACC_TPR REG_ACCESS(RwReg, 0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */
-#define REG_DACC_TCR REG_ACCESS(RwReg, 0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */
-#define REG_DACC_RNPR REG_ACCESS(RwReg, 0x4003C110U) /**< \brief (DACC) Receive Next Pointer Register */
-#define REG_DACC_RNCR REG_ACCESS(RwReg, 0x4003C114U) /**< \brief (DACC) Receive Next Counter Register */
-#define REG_DACC_TNPR REG_ACCESS(RwReg, 0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */
-#define REG_DACC_TNCR REG_ACCESS(RwReg, 0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */
-#define REG_DACC_PTCR REG_ACCESS(WoReg, 0x4003C120U) /**< \brief (DACC) Transfer Control Register */
-#define REG_DACC_PTSR REG_ACCESS(RoReg, 0x4003C124U) /**< \brief (DACC) Transfer Status Register */
-/* ========== Register definition for ACC peripheral ========== */
-#define REG_ACC_CR REG_ACCESS(WoReg, 0x40040000U) /**< \brief (ACC) Control Register */
-#define REG_ACC_MR REG_ACCESS(RwReg, 0x40040004U) /**< \brief (ACC) Mode Register */
-#define REG_ACC_IER REG_ACCESS(WoReg, 0x40040024U) /**< \brief (ACC) Interrupt Enable Register */
-#define REG_ACC_IDR REG_ACCESS(WoReg, 0x40040028U) /**< \brief (ACC) Interrupt Disable Register */
-#define REG_ACC_IMR REG_ACCESS(RoReg, 0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */
-#define REG_ACC_ISR REG_ACCESS(RoReg, 0x40040030U) /**< \brief (ACC) Interrupt Status Register */
-#define REG_ACC_ACR REG_ACCESS(RwReg, 0x40040094U) /**< \brief (ACC) Analog Control Register */
-#define REG_ACC_WPMR REG_ACCESS(RwReg, 0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */
-#define REG_ACC_WPSR REG_ACCESS(RoReg, 0x400400E8U) /**< \brief (ACC) Write Protect Status Register */
-/* ========== Register definition for CRCCU peripheral ========== */
-#define REG_CRCCU_DSCR REG_ACCESS(RwReg, 0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */
-#define REG_CRCCU_DMA_EN REG_ACCESS(WoReg, 0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */
-#define REG_CRCCU_DMA_DIS REG_ACCESS(WoReg, 0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */
-#define REG_CRCCU_DMA_SR REG_ACCESS(RoReg, 0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */
-#define REG_CRCCU_DMA_IER REG_ACCESS(WoReg, 0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */
-#define REG_CRCCU_DMA_IDR REG_ACCESS(WoReg, 0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */
-#define REG_CRCCU_DMA_IMR REG_ACCESS(RoReg, 0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */
-#define REG_CRCCU_DMA_ISR REG_ACCESS(RoReg, 0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */
-#define REG_CRCCU_CR REG_ACCESS(WoReg, 0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */
-#define REG_CRCCU_MR REG_ACCESS(RwReg, 0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */
-#define REG_CRCCU_SR REG_ACCESS(RoReg, 0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */
-#define REG_CRCCU_IER REG_ACCESS(WoReg, 0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */
-#define REG_CRCCU_IDR REG_ACCESS(WoReg, 0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */
-#define REG_CRCCU_IMR REG_ACCESS(RoReg, 0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */
-#define REG_CRCCU_ISR REG_ACCESS(RoReg, 0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */
-/* ========== Register definition for SMC peripheral ========== */
-#define REG_SMC_SETUP0 REG_ACCESS(RwReg, 0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
-#define REG_SMC_PULSE0 REG_ACCESS(RwReg, 0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
-#define REG_SMC_CYCLE0 REG_ACCESS(RwReg, 0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
-#define REG_SMC_MODE0 REG_ACCESS(RwReg, 0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
-#define REG_SMC_SETUP1 REG_ACCESS(RwReg, 0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
-#define REG_SMC_PULSE1 REG_ACCESS(RwReg, 0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
-#define REG_SMC_CYCLE1 REG_ACCESS(RwReg, 0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
-#define REG_SMC_MODE1 REG_ACCESS(RwReg, 0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
-#define REG_SMC_SETUP2 REG_ACCESS(RwReg, 0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
-#define REG_SMC_PULSE2 REG_ACCESS(RwReg, 0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
-#define REG_SMC_CYCLE2 REG_ACCESS(RwReg, 0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
-#define REG_SMC_MODE2 REG_ACCESS(RwReg, 0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
-#define REG_SMC_SETUP3 REG_ACCESS(RwReg, 0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
-#define REG_SMC_PULSE3 REG_ACCESS(RwReg, 0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
-#define REG_SMC_CYCLE3 REG_ACCESS(RwReg, 0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
-#define REG_SMC_MODE3 REG_ACCESS(RwReg, 0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
-#define REG_SMC_SETUP4 REG_ACCESS(RwReg, 0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */
-#define REG_SMC_PULSE4 REG_ACCESS(RwReg, 0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */
-#define REG_SMC_CYCLE4 REG_ACCESS(RwReg, 0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */
-#define REG_SMC_MODE4 REG_ACCESS(RwReg, 0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */
-#define REG_SMC_OCMS REG_ACCESS(RwReg, 0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */
-#define REG_SMC_KEY1 REG_ACCESS(WoReg, 0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */
-#define REG_SMC_KEY2 REG_ACCESS(WoReg, 0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */
-#define REG_SMC_WPMR REG_ACCESS(RwReg, 0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */
-#define REG_SMC_WPSR REG_ACCESS(RoReg, 0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */
-/* ========== Register definition for MATRIX peripheral ========== */
-#define REG_MATRIX_MCFG REG_ACCESS(RwReg, 0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
-#define REG_MATRIX_SCFG REG_ACCESS(RwReg, 0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
-#define REG_MATRIX_PRAS0 REG_ACCESS(RwReg, 0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
-#define REG_MATRIX_PRAS1 REG_ACCESS(RwReg, 0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
-#define REG_MATRIX_PRAS2 REG_ACCESS(RwReg, 0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
-#define REG_MATRIX_PRAS3 REG_ACCESS(RwReg, 0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
-#define REG_MATRIX_PRAS4 REG_ACCESS(RwReg, 0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
-#define REG_MATRIX_SYSIO REG_ACCESS(RwReg, 0x400E0314U) /**< \brief (MATRIX) System IO Configuration register */
-#define REG_MATRIX_SMCNFCS REG_ACCESS(RwReg, 0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */
-#define REG_MATRIX_WPMR REG_ACCESS(RwReg, 0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
-#define REG_MATRIX_WPSR REG_ACCESS(RoReg, 0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
-/* ========== Register definition for PMC peripheral ========== */
-#define REG_PMC_SCER REG_ACCESS(WoReg, 0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
-#define REG_PMC_SCDR REG_ACCESS(WoReg, 0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
-#define REG_PMC_SCSR REG_ACCESS(RoReg, 0x400E0408U) /**< \brief (PMC) System Clock Status Register */
-#define REG_PMC_PCER0 REG_ACCESS(WoReg, 0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
-#define REG_PMC_PCDR0 REG_ACCESS(WoReg, 0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
-#define REG_PMC_PCSR0 REG_ACCESS(RoReg, 0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
-#define REG_PMC_MOR REG_ACCESS(RwReg, 0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
-#define REG_PMC_MCFR REG_ACCESS(RoReg, 0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
-#define REG_PMC_PLLAR REG_ACCESS(RwReg, 0x400E0428U) /**< \brief (PMC) PLLA Register */
-#define REG_PMC_PLLBR REG_ACCESS(RwReg, 0x400E042CU) /**< \brief (PMC) PLLB Register */
-#define REG_PMC_MCKR REG_ACCESS(RwReg, 0x400E0430U) /**< \brief (PMC) Master Clock Register */
-#define REG_PMC_USB REG_ACCESS(RwReg, 0x400E0438U) /**< \brief (PMC) USB Clock Register */
-#define REG_PMC_PCK REG_ACCESS(RwReg, 0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
-#define REG_PMC_IER REG_ACCESS(WoReg, 0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
-#define REG_PMC_IDR REG_ACCESS(WoReg, 0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
-#define REG_PMC_SR REG_ACCESS(RoReg, 0x400E0468U) /**< \brief (PMC) Status Register */
-#define REG_PMC_IMR REG_ACCESS(RoReg, 0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
-#define REG_PMC_FSMR REG_ACCESS(RwReg, 0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
-#define REG_PMC_FSPR REG_ACCESS(RwReg, 0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
-#define REG_PMC_FOCR REG_ACCESS(WoReg, 0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
-#define REG_PMC_WPMR REG_ACCESS(RwReg, 0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
-#define REG_PMC_WPSR REG_ACCESS(RoReg, 0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
-#define REG_PMC_PCER1 REG_ACCESS(WoReg, 0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
-#define REG_PMC_PCDR1 REG_ACCESS(WoReg, 0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
-#define REG_PMC_PCSR1 REG_ACCESS(RoReg, 0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
-#define REG_PMC_OCR REG_ACCESS(RwReg, 0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */
-/* ========== Register definition for UART0 peripheral ========== */
-#define REG_UART0_CR REG_ACCESS(WoReg, 0x400E0600U) /**< \brief (UART0) Control Register */
-#define REG_UART0_MR REG_ACCESS(RwReg, 0x400E0604U) /**< \brief (UART0) Mode Register */
-#define REG_UART0_IER REG_ACCESS(WoReg, 0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */
-#define REG_UART0_IDR REG_ACCESS(WoReg, 0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */
-#define REG_UART0_IMR REG_ACCESS(RoReg, 0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */
-#define REG_UART0_SR REG_ACCESS(RoReg, 0x400E0614U) /**< \brief (UART0) Status Register */
-#define REG_UART0_RHR REG_ACCESS(RoReg, 0x400E0618U) /**< \brief (UART0) Receive Holding Register */
-#define REG_UART0_THR REG_ACCESS(WoReg, 0x400E061CU) /**< \brief (UART0) Transmit Holding Register */
-#define REG_UART0_BRGR REG_ACCESS(RwReg, 0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */
-#define REG_UART0_RPR REG_ACCESS(RwReg, 0x400E0700U) /**< \brief (UART0) Receive Pointer Register */
-#define REG_UART0_RCR REG_ACCESS(RwReg, 0x400E0704U) /**< \brief (UART0) Receive Counter Register */
-#define REG_UART0_TPR REG_ACCESS(RwReg, 0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */
-#define REG_UART0_TCR REG_ACCESS(RwReg, 0x400E070CU) /**< \brief (UART0) Transmit Counter Register */
-#define REG_UART0_RNPR REG_ACCESS(RwReg, 0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */
-#define REG_UART0_RNCR REG_ACCESS(RwReg, 0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */
-#define REG_UART0_TNPR REG_ACCESS(RwReg, 0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */
-#define REG_UART0_TNCR REG_ACCESS(RwReg, 0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */
-#define REG_UART0_PTCR REG_ACCESS(WoReg, 0x400E0720U) /**< \brief (UART0) Transfer Control Register */
-#define REG_UART0_PTSR REG_ACCESS(RoReg, 0x400E0724U) /**< \brief (UART0) Transfer Status Register */
-/* ========== Register definition for CHIPID peripheral ========== */
-#define REG_CHIPID_CIDR REG_ACCESS(RoReg, 0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
-#define REG_CHIPID_EXID REG_ACCESS(RoReg, 0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
-/* ========== Register definition for UART1 peripheral ========== */
-#define REG_UART1_CR REG_ACCESS(WoReg, 0x400E0800U) /**< \brief (UART1) Control Register */
-#define REG_UART1_MR REG_ACCESS(RwReg, 0x400E0804U) /**< \brief (UART1) Mode Register */
-#define REG_UART1_IER REG_ACCESS(WoReg, 0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */
-#define REG_UART1_IDR REG_ACCESS(WoReg, 0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */
-#define REG_UART1_IMR REG_ACCESS(RoReg, 0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */
-#define REG_UART1_SR REG_ACCESS(RoReg, 0x400E0814U) /**< \brief (UART1) Status Register */
-#define REG_UART1_RHR REG_ACCESS(RoReg, 0x400E0818U) /**< \brief (UART1) Receive Holding Register */
-#define REG_UART1_THR REG_ACCESS(WoReg, 0x400E081CU) /**< \brief (UART1) Transmit Holding Register */
-#define REG_UART1_BRGR REG_ACCESS(RwReg, 0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */
-#define REG_UART1_RPR REG_ACCESS(RwReg, 0x400E0900U) /**< \brief (UART1) Receive Pointer Register */
-#define REG_UART1_RCR REG_ACCESS(RwReg, 0x400E0904U) /**< \brief (UART1) Receive Counter Register */
-#define REG_UART1_TPR REG_ACCESS(RwReg, 0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */
-#define REG_UART1_TCR REG_ACCESS(RwReg, 0x400E090CU) /**< \brief (UART1) Transmit Counter Register */
-#define REG_UART1_RNPR REG_ACCESS(RwReg, 0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */
-#define REG_UART1_RNCR REG_ACCESS(RwReg, 0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */
-#define REG_UART1_TNPR REG_ACCESS(RwReg, 0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */
-#define REG_UART1_TNCR REG_ACCESS(RwReg, 0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */
-#define REG_UART1_PTCR REG_ACCESS(WoReg, 0x400E0920U) /**< \brief (UART1) Transfer Control Register */
-#define REG_UART1_PTSR REG_ACCESS(RoReg, 0x400E0924U) /**< \brief (UART1) Transfer Status Register */
-/* ========== Register definition for EFC peripheral ========== */
-#define REG_EFC_FMR REG_ACCESS(RwReg, 0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */
-#define REG_EFC_FCR REG_ACCESS(WoReg, 0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */
-#define REG_EFC_FSR REG_ACCESS(RoReg, 0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */
-#define REG_EFC_FRR REG_ACCESS(RoReg, 0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */
-/* ========== Register definition for PIOA peripheral ========== */
-#define REG_PIOA_PER REG_ACCESS(WoReg, 0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
-#define REG_PIOA_PDR REG_ACCESS(WoReg, 0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
-#define REG_PIOA_PSR REG_ACCESS(RoReg, 0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
-#define REG_PIOA_OER REG_ACCESS(WoReg, 0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
-#define REG_PIOA_ODR REG_ACCESS(WoReg, 0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
-#define REG_PIOA_OSR REG_ACCESS(RoReg, 0x400E0E18U) /**< \brief (PIOA) Output Status Register */
-#define REG_PIOA_IFER REG_ACCESS(WoReg, 0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
-#define REG_PIOA_IFDR REG_ACCESS(WoReg, 0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
-#define REG_PIOA_IFSR REG_ACCESS(RoReg, 0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
-#define REG_PIOA_SODR REG_ACCESS(WoReg, 0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
-#define REG_PIOA_CODR REG_ACCESS(WoReg, 0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
-#define REG_PIOA_ODSR REG_ACCESS(RwReg, 0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
-#define REG_PIOA_PDSR REG_ACCESS(RoReg, 0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
-#define REG_PIOA_IER REG_ACCESS(WoReg, 0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
-#define REG_PIOA_IDR REG_ACCESS(WoReg, 0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
-#define REG_PIOA_IMR REG_ACCESS(RoReg, 0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
-#define REG_PIOA_ISR REG_ACCESS(RoReg, 0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
-#define REG_PIOA_MDER REG_ACCESS(WoReg, 0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
-#define REG_PIOA_MDDR REG_ACCESS(WoReg, 0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
-#define REG_PIOA_MDSR REG_ACCESS(RoReg, 0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
-#define REG_PIOA_PUDR REG_ACCESS(WoReg, 0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
-#define REG_PIOA_PUER REG_ACCESS(WoReg, 0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
-#define REG_PIOA_PUSR REG_ACCESS(RoReg, 0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
-#define REG_PIOA_ABCDSR REG_ACCESS(RwReg, 0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
-#define REG_PIOA_SCIFSR REG_ACCESS(WoReg, 0x400E0E80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */
-#define REG_PIOA_DIFSR REG_ACCESS(WoReg, 0x400E0E84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */
-#define REG_PIOA_IFDGSR REG_ACCESS(RoReg, 0x400E0E88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */
-#define REG_PIOA_SCDR REG_ACCESS(RwReg, 0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
-#define REG_PIOA_PPDDR REG_ACCESS(WoReg, 0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
-#define REG_PIOA_PPDER REG_ACCESS(WoReg, 0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
-#define REG_PIOA_PPDSR REG_ACCESS(RoReg, 0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
-#define REG_PIOA_OWER REG_ACCESS(WoReg, 0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
-#define REG_PIOA_OWDR REG_ACCESS(WoReg, 0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
-#define REG_PIOA_OWSR REG_ACCESS(RoReg, 0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
-#define REG_PIOA_AIMER REG_ACCESS(WoReg, 0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
-#define REG_PIOA_AIMDR REG_ACCESS(WoReg, 0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
-#define REG_PIOA_AIMMR REG_ACCESS(RoReg, 0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
-#define REG_PIOA_ESR REG_ACCESS(WoReg, 0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
-#define REG_PIOA_LSR REG_ACCESS(WoReg, 0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
-#define REG_PIOA_ELSR REG_ACCESS(RoReg, 0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
-#define REG_PIOA_FELLSR REG_ACCESS(WoReg, 0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
-#define REG_PIOA_REHLSR REG_ACCESS(WoReg, 0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
-#define REG_PIOA_FRLHSR REG_ACCESS(RoReg, 0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
-#define REG_PIOA_LOCKSR REG_ACCESS(RoReg, 0x400E0EE0U) /**< \brief (PIOA) Lock Status */
-#define REG_PIOA_WPMR REG_ACCESS(RwReg, 0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
-#define REG_PIOA_WPSR REG_ACCESS(RoReg, 0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
-#define REG_PIOA_SCHMITT REG_ACCESS(RwReg, 0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
-#define REG_PIOA_PCMR REG_ACCESS(RwReg, 0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */
-#define REG_PIOA_PCIER REG_ACCESS(WoReg, 0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */
-#define REG_PIOA_PCIDR REG_ACCESS(WoReg, 0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */
-#define REG_PIOA_PCIMR REG_ACCESS(RoReg, 0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */
-#define REG_PIOA_PCISR REG_ACCESS(RoReg, 0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */
-#define REG_PIOA_PCRHR REG_ACCESS(RoReg, 0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */
-/* ========== Register definition for PIOB peripheral ========== */
-#define REG_PIOB_PER REG_ACCESS(WoReg, 0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
-#define REG_PIOB_PDR REG_ACCESS(WoReg, 0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
-#define REG_PIOB_PSR REG_ACCESS(RoReg, 0x400E1008U) /**< \brief (PIOB) PIO Status Register */
-#define REG_PIOB_OER REG_ACCESS(WoReg, 0x400E1010U) /**< \brief (PIOB) Output Enable Register */
-#define REG_PIOB_ODR REG_ACCESS(WoReg, 0x400E1014U) /**< \brief (PIOB) Output Disable Register */
-#define REG_PIOB_OSR REG_ACCESS(RoReg, 0x400E1018U) /**< \brief (PIOB) Output Status Register */
-#define REG_PIOB_IFER REG_ACCESS(WoReg, 0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
-#define REG_PIOB_IFDR REG_ACCESS(WoReg, 0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
-#define REG_PIOB_IFSR REG_ACCESS(RoReg, 0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
-#define REG_PIOB_SODR REG_ACCESS(WoReg, 0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
-#define REG_PIOB_CODR REG_ACCESS(WoReg, 0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
-#define REG_PIOB_ODSR REG_ACCESS(RwReg, 0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
-#define REG_PIOB_PDSR REG_ACCESS(RoReg, 0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
-#define REG_PIOB_IER REG_ACCESS(WoReg, 0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
-#define REG_PIOB_IDR REG_ACCESS(WoReg, 0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
-#define REG_PIOB_IMR REG_ACCESS(RoReg, 0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
-#define REG_PIOB_ISR REG_ACCESS(RoReg, 0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
-#define REG_PIOB_MDER REG_ACCESS(WoReg, 0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
-#define REG_PIOB_MDDR REG_ACCESS(WoReg, 0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
-#define REG_PIOB_MDSR REG_ACCESS(RoReg, 0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
-#define REG_PIOB_PUDR REG_ACCESS(WoReg, 0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
-#define REG_PIOB_PUER REG_ACCESS(WoReg, 0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
-#define REG_PIOB_PUSR REG_ACCESS(RoReg, 0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
-#define REG_PIOB_ABCDSR REG_ACCESS(RwReg, 0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
-#define REG_PIOB_SCIFSR REG_ACCESS(WoReg, 0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */
-#define REG_PIOB_DIFSR REG_ACCESS(WoReg, 0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */
-#define REG_PIOB_IFDGSR REG_ACCESS(RoReg, 0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */
-#define REG_PIOB_SCDR REG_ACCESS(RwReg, 0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
-#define REG_PIOB_PPDDR REG_ACCESS(WoReg, 0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
-#define REG_PIOB_PPDER REG_ACCESS(WoReg, 0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
-#define REG_PIOB_PPDSR REG_ACCESS(RoReg, 0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
-#define REG_PIOB_OWER REG_ACCESS(WoReg, 0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
-#define REG_PIOB_OWDR REG_ACCESS(WoReg, 0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
-#define REG_PIOB_OWSR REG_ACCESS(RoReg, 0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
-#define REG_PIOB_AIMER REG_ACCESS(WoReg, 0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
-#define REG_PIOB_AIMDR REG_ACCESS(WoReg, 0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
-#define REG_PIOB_AIMMR REG_ACCESS(RoReg, 0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
-#define REG_PIOB_ESR REG_ACCESS(WoReg, 0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
-#define REG_PIOB_LSR REG_ACCESS(WoReg, 0x400E10C4U) /**< \brief (PIOB) Level Select Register */
-#define REG_PIOB_ELSR REG_ACCESS(RoReg, 0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
-#define REG_PIOB_FELLSR REG_ACCESS(WoReg, 0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
-#define REG_PIOB_REHLSR REG_ACCESS(WoReg, 0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
-#define REG_PIOB_FRLHSR REG_ACCESS(RoReg, 0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
-#define REG_PIOB_LOCKSR REG_ACCESS(RoReg, 0x400E10E0U) /**< \brief (PIOB) Lock Status */
-#define REG_PIOB_WPMR REG_ACCESS(RwReg, 0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
-#define REG_PIOB_WPSR REG_ACCESS(RoReg, 0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
-#define REG_PIOB_SCHMITT REG_ACCESS(RwReg, 0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
-#define REG_PIOB_PCMR REG_ACCESS(RwReg, 0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */
-#define REG_PIOB_PCIER REG_ACCESS(WoReg, 0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */
-#define REG_PIOB_PCIDR REG_ACCESS(WoReg, 0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */
-#define REG_PIOB_PCIMR REG_ACCESS(RoReg, 0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */
-#define REG_PIOB_PCISR REG_ACCESS(RoReg, 0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */
-#define REG_PIOB_PCRHR REG_ACCESS(RoReg, 0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */
-/* ========== Register definition for PIOC peripheral ========== */
-#define REG_PIOC_PER REG_ACCESS(WoReg, 0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
-#define REG_PIOC_PDR REG_ACCESS(WoReg, 0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
-#define REG_PIOC_PSR REG_ACCESS(RoReg, 0x400E1208U) /**< \brief (PIOC) PIO Status Register */
-#define REG_PIOC_OER REG_ACCESS(WoReg, 0x400E1210U) /**< \brief (PIOC) Output Enable Register */
-#define REG_PIOC_ODR REG_ACCESS(WoReg, 0x400E1214U) /**< \brief (PIOC) Output Disable Register */
-#define REG_PIOC_OSR REG_ACCESS(RoReg, 0x400E1218U) /**< \brief (PIOC) Output Status Register */
-#define REG_PIOC_IFER REG_ACCESS(WoReg, 0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
-#define REG_PIOC_IFDR REG_ACCESS(WoReg, 0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
-#define REG_PIOC_IFSR REG_ACCESS(RoReg, 0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
-#define REG_PIOC_SODR REG_ACCESS(WoReg, 0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
-#define REG_PIOC_CODR REG_ACCESS(WoReg, 0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
-#define REG_PIOC_ODSR REG_ACCESS(RwReg, 0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
-#define REG_PIOC_PDSR REG_ACCESS(RoReg, 0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
-#define REG_PIOC_IER REG_ACCESS(WoReg, 0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
-#define REG_PIOC_IDR REG_ACCESS(WoReg, 0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
-#define REG_PIOC_IMR REG_ACCESS(RoReg, 0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
-#define REG_PIOC_ISR REG_ACCESS(RoReg, 0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
-#define REG_PIOC_MDER REG_ACCESS(WoReg, 0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
-#define REG_PIOC_MDDR REG_ACCESS(WoReg, 0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
-#define REG_PIOC_MDSR REG_ACCESS(RoReg, 0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
-#define REG_PIOC_PUDR REG_ACCESS(WoReg, 0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
-#define REG_PIOC_PUER REG_ACCESS(WoReg, 0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
-#define REG_PIOC_PUSR REG_ACCESS(RoReg, 0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
-#define REG_PIOC_ABCDSR REG_ACCESS(RwReg, 0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
-#define REG_PIOC_SCIFSR REG_ACCESS(WoReg, 0x400E1280U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */
-#define REG_PIOC_DIFSR REG_ACCESS(WoReg, 0x400E1284U) /**< \brief (PIOC) Debouncing Input Filter Select Register */
-#define REG_PIOC_IFDGSR REG_ACCESS(RoReg, 0x400E1288U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */
-#define REG_PIOC_SCDR REG_ACCESS(RwReg, 0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
-#define REG_PIOC_PPDDR REG_ACCESS(WoReg, 0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
-#define REG_PIOC_PPDER REG_ACCESS(WoReg, 0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
-#define REG_PIOC_PPDSR REG_ACCESS(RoReg, 0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
-#define REG_PIOC_OWER REG_ACCESS(WoReg, 0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
-#define REG_PIOC_OWDR REG_ACCESS(WoReg, 0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
-#define REG_PIOC_OWSR REG_ACCESS(RoReg, 0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
-#define REG_PIOC_AIMER REG_ACCESS(WoReg, 0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
-#define REG_PIOC_AIMDR REG_ACCESS(WoReg, 0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
-#define REG_PIOC_AIMMR REG_ACCESS(RoReg, 0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
-#define REG_PIOC_ESR REG_ACCESS(WoReg, 0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
-#define REG_PIOC_LSR REG_ACCESS(WoReg, 0x400E12C4U) /**< \brief (PIOC) Level Select Register */
-#define REG_PIOC_ELSR REG_ACCESS(RoReg, 0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
-#define REG_PIOC_FELLSR REG_ACCESS(WoReg, 0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
-#define REG_PIOC_REHLSR REG_ACCESS(WoReg, 0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
-#define REG_PIOC_FRLHSR REG_ACCESS(RoReg, 0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
-#define REG_PIOC_LOCKSR REG_ACCESS(RoReg, 0x400E12E0U) /**< \brief (PIOC) Lock Status */
-#define REG_PIOC_WPMR REG_ACCESS(RwReg, 0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
-#define REG_PIOC_WPSR REG_ACCESS(RoReg, 0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
-#define REG_PIOC_SCHMITT REG_ACCESS(RwReg, 0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
-#define REG_PIOC_PCMR REG_ACCESS(RwReg, 0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */
-#define REG_PIOC_PCIER REG_ACCESS(WoReg, 0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */
-#define REG_PIOC_PCIDR REG_ACCESS(WoReg, 0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */
-#define REG_PIOC_PCIMR REG_ACCESS(RoReg, 0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */
-#define REG_PIOC_PCISR REG_ACCESS(RoReg, 0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */
-#define REG_PIOC_PCRHR REG_ACCESS(RoReg, 0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */
-/* ========== Register definition for RSTC peripheral ========== */
-#define REG_RSTC_CR REG_ACCESS(WoReg, 0x400E1400U) /**< \brief (RSTC) Control Register */
-#define REG_RSTC_SR REG_ACCESS(RoReg, 0x400E1404U) /**< \brief (RSTC) Status Register */
-#define REG_RSTC_MR REG_ACCESS(RwReg, 0x400E1408U) /**< \brief (RSTC) Mode Register */
-/* ========== Register definition for SUPC peripheral ========== */
-#define REG_SUPC_CR REG_ACCESS(WoReg, 0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */
-#define REG_SUPC_SMMR REG_ACCESS(RwReg, 0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
-#define REG_SUPC_MR REG_ACCESS(RwReg, 0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */
-#define REG_SUPC_WUMR REG_ACCESS(RwReg, 0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
-#define REG_SUPC_WUIR REG_ACCESS(RwReg, 0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
-#define REG_SUPC_SR REG_ACCESS(RoReg, 0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */
-/* ========== Register definition for RTT peripheral ========== */
-#define REG_RTT_MR REG_ACCESS(RwReg, 0x400E1430U) /**< \brief (RTT) Mode Register */
-#define REG_RTT_AR REG_ACCESS(RwReg, 0x400E1434U) /**< \brief (RTT) Alarm Register */
-#define REG_RTT_VR REG_ACCESS(RoReg, 0x400E1438U) /**< \brief (RTT) Value Register */
-#define REG_RTT_SR REG_ACCESS(RoReg, 0x400E143CU) /**< \brief (RTT) Status Register */
-/* ========== Register definition for WDT peripheral ========== */
-#define REG_WDT_CR REG_ACCESS(WoReg, 0x400E1450U) /**< \brief (WDT) Control Register */
-#define REG_WDT_MR REG_ACCESS(RwReg, 0x400E1454U) /**< \brief (WDT) Mode Register */
-#define REG_WDT_SR REG_ACCESS(RoReg, 0x400E1458U) /**< \brief (WDT) Status Register */
-/* ========== Register definition for RTC peripheral ========== */
-#define REG_RTC_CR REG_ACCESS(RwReg, 0x400E1460U) /**< \brief (RTC) Control Register */
-#define REG_RTC_MR REG_ACCESS(RwReg, 0x400E1464U) /**< \brief (RTC) Mode Register */
-#define REG_RTC_TIMR REG_ACCESS(RwReg, 0x400E1468U) /**< \brief (RTC) Time Register */
-#define REG_RTC_CALR REG_ACCESS(RwReg, 0x400E146CU) /**< \brief (RTC) Calendar Register */
-#define REG_RTC_TIMALR REG_ACCESS(RwReg, 0x400E1470U) /**< \brief (RTC) Time Alarm Register */
-#define REG_RTC_CALALR REG_ACCESS(RwReg, 0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */
-#define REG_RTC_SR REG_ACCESS(RoReg, 0x400E1478U) /**< \brief (RTC) Status Register */
-#define REG_RTC_SCCR REG_ACCESS(WoReg, 0x400E147CU) /**< \brief (RTC) Status Clear Command Register */
-#define REG_RTC_IER REG_ACCESS(WoReg, 0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */
-#define REG_RTC_IDR REG_ACCESS(WoReg, 0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */
-#define REG_RTC_IMR REG_ACCESS(RoReg, 0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */
-#define REG_RTC_VER REG_ACCESS(RoReg, 0x400E148CU) /**< \brief (RTC) Valid Entry Register */
-/* ========== Register definition for GPBR peripheral ========== */
-#define REG_GPBR_GPBR0 REG_ACCESS(RwReg, 0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register 0 */
-#define REG_GPBR_GPBR1 REG_ACCESS(RwReg, 0x400E1494U) /**< \brief (GPBR) General Purpose Backup Register 1 */
-#define REG_GPBR_GPBR2 REG_ACCESS(RwReg, 0x400E1498U) /**< \brief (GPBR) General Purpose Backup Register 2 */
-#define REG_GPBR_GPBR3 REG_ACCESS(RwReg, 0x400E149CU) /**< \brief (GPBR) General Purpose Backup Register 3 */
-/*@}*/
-
-/* ***************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR AT91SAM3S */
-/* ***************************************************************************** */
-/** \addtogroup AT91SAM3S_id Peripheral Ids Definitions */
-/*@{*/
-
-#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
-#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
-#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
-#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
-#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
-#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
-#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */
-#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */
-#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */
-#define ID_SMC (10) /**< \brief Static Memory Controller (SMC) */
-#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */
-#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */
-#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */
-#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
-#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
-#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
-#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */
-#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */
-#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */
-#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */
-#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
-#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
-#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
-#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */
-#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */
-#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */
-#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */
-#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
-#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */
-#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */
-#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
-#define ID_UDP (34) /**< \brief USB Device Port (UDP) */
-/*@}*/
-
-/* ***************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR AT91SAM3S */
-/* ***************************************************************************** */
-/** \addtogroup AT91SAM3S_base Peripheral Base Address Definitions */
-/*@{*/
-
-#define HSMCI CAST(Hsmci , 0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define PDC_HSMCI CAST(Pdc , 0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
-#define SSC CAST(Ssc , 0x40004000U) /**< \brief (SSC ) Base Address */
-#define PDC_SSC CAST(Pdc , 0x40004100U) /**< \brief (PDC_SSC ) Base Address */
-#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */
-#define PDC_SPI CAST(Pdc , 0x40008100U) /**< \brief (PDC_SPI ) Base Address */
-#define TC0 CAST(Tc , 0x40010000U) /**< \brief (TC0 ) Base Address */
-#define TC1 CAST(Tc , 0x40014000U) /**< \brief (TC1 ) Base Address */
-#define TWI0 CAST(Twi , 0x40018000U) /**< \brief (TWI0 ) Base Address */
-#define PDC_TWI0 CAST(Pdc , 0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */
-#define TWI1 CAST(Twi , 0x4001C000U) /**< \brief (TWI1 ) Base Address */
-#define PDC_TWI1 CAST(Pdc , 0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */
-#define PWM CAST(Pwm , 0x40020000U) /**< \brief (PWM ) Base Address */
-#define PDC_PWM CAST(Pdc , 0x40020100U) /**< \brief (PDC_PWM ) Base Address */
-#define USART0 CAST(Usart , 0x40024000U) /**< \brief (USART0 ) Base Address */
-#define PDC_USART0 CAST(Pdc , 0x40024100U) /**< \brief (PDC_USART0) Base Address */
-#define USART1 CAST(Usart , 0x40028000U) /**< \brief (USART1 ) Base Address */
-#define PDC_USART1 CAST(Pdc , 0x40028100U) /**< \brief (PDC_USART1) Base Address */
-#define UDP CAST(Udp , 0x40034000U) /**< \brief (UDP ) Base Address */
-#define ADC CAST(Adc , 0x40038000U) /**< \brief (ADC ) Base Address */
-#define PDC_ADC CAST(Pdc , 0x40038100U) /**< \brief (PDC_ADC ) Base Address */
-#define DACC CAST(Dacc , 0x4003C000U) /**< \brief (DACC ) Base Address */
-#define PDC_DACC CAST(Pdc , 0x4003C100U) /**< \brief (PDC_DACC ) Base Address */
-#define ACC CAST(Acc , 0x40040000U) /**< \brief (ACC ) Base Address */
-#define CRCCU CAST(Crccu , 0x40044000U) /**< \brief (CRCCU ) Base Address */
-#define SMC CAST(Smc , 0x400E0000U) /**< \brief (SMC ) Base Address */
-#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */
-#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */
-#define UART0 CAST(Uart , 0x400E0600U) /**< \brief (UART0 ) Base Address */
-#define PDC_UART0 CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
-#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */
-#define UART1 CAST(Uart , 0x400E0800U) /**< \brief (UART1 ) Base Address */
-#define PDC_UART1 CAST(Pdc , 0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
-#define EFC CAST(Efc , 0x400E0A00U) /**< \brief (EFC ) Base Address */
-#define PIOA CAST(Pio , 0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB CAST(Pio , 0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOC CAST(Pio , 0x400E1200U) /**< \brief (PIOC ) Base Address */
-#define RSTC CAST(Rstc , 0x400E1400U) /**< \brief (RSTC ) Base Address */
-#define SUPC CAST(Supc , 0x400E1410U) /**< \brief (SUPC ) Base Address */
-#define RTT CAST(Rtt , 0x400E1430U) /**< \brief (RTT ) Base Address */
-#define WDT CAST(Wdt , 0x400E1450U) /**< \brief (WDT ) Base Address */
-#define RTC CAST(Rtc , 0x400E1460U) /**< \brief (RTC ) Base Address */
-#define GPBR CAST(Gpbr , 0x400E1490U) /**< \brief (GPBR ) Base Address */
-/*@}*/
-
-/* ***************************************************************************** */
-/* PIO DEFINITIONS FOR AT91SAM3S */
-/* ***************************************************************************** */
-/** \addtogroup AT91SAM3S_pio Peripheral Pio Definitions */
-/*@{*/
-
-#define PIO_PA0 (1 << 0) /**< \brief Pin Controlled by PA0 */
-#define PIO_PA1 (1 << 1) /**< \brief Pin Controlled by PA1 */
-#define PIO_PA2 (1 << 2) /**< \brief Pin Controlled by PA2 */
-#define PIO_PA3 (1 << 3) /**< \brief Pin Controlled by PA3 */
-#define PIO_PA4 (1 << 4) /**< \brief Pin Controlled by PA4 */
-#define PIO_PA5 (1 << 5) /**< \brief Pin Controlled by PA5 */
-#define PIO_PA6 (1 << 6) /**< \brief Pin Controlled by PA6 */
-#define PIO_PA7 (1 << 7) /**< \brief Pin Controlled by PA7 */
-#define PIO_PA8 (1 << 8) /**< \brief Pin Controlled by PA8 */
-#define PIO_PA9 (1 << 9) /**< \brief Pin Controlled by PA9 */
-#define PIO_PA10 (1 << 10) /**< \brief Pin Controlled by PA10 */
-#define PIO_PA11 (1 << 11) /**< \brief Pin Controlled by PA11 */
-#define PIO_PA12 (1 << 12) /**< \brief Pin Controlled by PA12 */
-#define PIO_PA13 (1 << 13) /**< \brief Pin Controlled by PA13 */
-#define PIO_PA14 (1 << 14) /**< \brief Pin Controlled by PA14 */
-#define PIO_PA15 (1 << 15) /**< \brief Pin Controlled by PA15 */
-#define PIO_PA16 (1 << 16) /**< \brief Pin Controlled by PA16 */
-#define PIO_PA17 (1 << 17) /**< \brief Pin Controlled by PA17 */
-#define PIO_PA18 (1 << 18) /**< \brief Pin Controlled by PA18 */
-#define PIO_PA19 (1 << 19) /**< \brief Pin Controlled by PA19 */
-#define PIO_PA20 (1 << 20) /**< \brief Pin Controlled by PA20 */
-#define PIO_PA21 (1 << 21) /**< \brief Pin Controlled by PA21 */
-#define PIO_PA22 (1 << 22) /**< \brief Pin Controlled by PA22 */
-#define PIO_PA23 (1 << 23) /**< \brief Pin Controlled by PA23 */
-#define PIO_PA24 (1 << 24) /**< \brief Pin Controlled by PA24 */
-#define PIO_PA25 (1 << 25) /**< \brief Pin Controlled by PA25 */
-#define PIO_PA26 (1 << 26) /**< \brief Pin Controlled by PA26 */
-#define PIO_PA27 (1 << 27) /**< \brief Pin Controlled by PA27 */
-#define PIO_PA28 (1 << 28) /**< \brief Pin Controlled by PA28 */
-#define PIO_PA29 (1 << 29) /**< \brief Pin Controlled by PA29 */
-#define PIO_PA30 (1 << 30) /**< \brief Pin Controlled by PA30 */
-#define PIO_PA31 (1 << 31) /**< \brief Pin Controlled by PA31 */
-#define PIO_PB0 (1 << 0) /**< \brief Pin Controlled by PB0 */
-#define PIO_PB1 (1 << 1) /**< \brief Pin Controlled by PB1 */
-#define PIO_PB2 (1 << 2) /**< \brief Pin Controlled by PB2 */
-#define PIO_PB3 (1 << 3) /**< \brief Pin Controlled by PB3 */
-#define PIO_PB4 (1 << 4) /**< \brief Pin Controlled by PB4 */
-#define PIO_PB5 (1 << 5) /**< \brief Pin Controlled by PB5 */
-#define PIO_PB6 (1 << 6) /**< \brief Pin Controlled by PB6 */
-#define PIO_PB7 (1 << 7) /**< \brief Pin Controlled by PB7 */
-#define PIO_PB8 (1 << 8) /**< \brief Pin Controlled by PB8 */
-#define PIO_PB9 (1 << 9) /**< \brief Pin Controlled by PB9 */
-#define PIO_PB10 (1 << 10) /**< \brief Pin Controlled by PB10 */
-#define PIO_PB11 (1 << 11) /**< \brief Pin Controlled by PB11 */
-#define PIO_PB12 (1 << 12) /**< \brief Pin Controlled by PB12 */
-#define PIO_PB13 (1 << 13) /**< \brief Pin Controlled by PB13 */
-#define PIO_PB14 (1 << 14) /**< \brief Pin Controlled by PB14 */
-#define PIO_PC0 (1 << 0) /**< \brief Pin Controlled by PC0 */
-#define PIO_PC1 (1 << 1) /**< \brief Pin Controlled by PC1 */
-#define PIO_PC2 (1 << 2) /**< \brief Pin Controlled by PC2 */
-#define PIO_PC3 (1 << 3) /**< \brief Pin Controlled by PC3 */
-#define PIO_PC4 (1 << 4) /**< \brief Pin Controlled by PC4 */
-#define PIO_PC5 (1 << 5) /**< \brief Pin Controlled by PC5 */
-#define PIO_PC6 (1 << 6) /**< \brief Pin Controlled by PC6 */
-#define PIO_PC7 (1 << 7) /**< \brief Pin Controlled by PC7 */
-#define PIO_PC8 (1 << 8) /**< \brief Pin Controlled by PC8 */
-#define PIO_PC9 (1 << 9) /**< \brief Pin Controlled by PC9 */
-#define PIO_PC10 (1 << 10) /**< \brief Pin Controlled by PC10 */
-#define PIO_PC11 (1 << 11) /**< \brief Pin Controlled by PC11 */
-#define PIO_PC12 (1 << 12) /**< \brief Pin Controlled by PC12 */
-#define PIO_PC13 (1 << 13) /**< \brief Pin Controlled by PC13 */
-#define PIO_PC14 (1 << 14) /**< \brief Pin Controlled by PC14 */
-#define PIO_PC15 (1 << 15) /**< \brief Pin Controlled by PC15 */
-#define PIO_PC16 (1 << 16) /**< \brief Pin Controlled by PC16 */
-#define PIO_PC17 (1 << 17) /**< \brief Pin Controlled by PC17 */
-#define PIO_PC18 (1 << 18) /**< \brief Pin Controlled by PC18 */
-#define PIO_PC19 (1 << 19) /**< \brief Pin Controlled by PC19 */
-#define PIO_PC20 (1 << 20) /**< \brief Pin Controlled by PC20 */
-#define PIO_PC21 (1 << 21) /**< \brief Pin Controlled by PC21 */
-#define PIO_PC22 (1 << 22) /**< \brief Pin Controlled by PC22 */
-#define PIO_PC23 (1 << 23) /**< \brief Pin Controlled by PC23 */
-#define PIO_PC24 (1 << 24) /**< \brief Pin Controlled by PC24 */
-#define PIO_PC25 (1 << 25) /**< \brief Pin Controlled by PC25 */
-#define PIO_PC26 (1 << 26) /**< \brief Pin Controlled by PC26 */
-#define PIO_PC27 (1 << 27) /**< \brief Pin Controlled by PC27 */
-#define PIO_PC28 (1 << 28) /**< \brief Pin Controlled by PC28 */
-#define PIO_PC29 (1 << 29) /**< \brief Pin Controlled by PC29 */
-#define PIO_PC30 (1 << 30) /**< \brief Pin Controlled by PC30 */
-#define PIO_PC31 (1 << 31) /**< \brief Pin Controlled by PC31 */
-/* ========== Pio definition for HSMCI peripheral ========== */
-#define PIO_PA28C_MCCDA (1 << 28) /**< \brief Hsmci signal: MCCDA */
-#define PIO_PA29C_MCCK (1 << 29) /**< \brief Hsmci signal: MCCK */
-#define PIO_PA30C_MCDA0 (1 << 30) /**< \brief Hsmci signal: MCDA0 */
-#define PIO_PA31C_MCDA1 (1 << 31) /**< \brief Hsmci signal: MCDA1 */
-#define PIO_PA26C_MCDA2 (1 << 26) /**< \brief Hsmci signal: MCDA2 */
-#define PIO_PA27C_MCDA3 (1 << 27) /**< \brief Hsmci signal: MCDA3 */
-/* ========== Pio definition for SSC peripheral ========== */
-#define PIO_PA18A_RD (1 << 18) /**< \brief Ssc signal: RD */
-#define PIO_PA20A_RF (1 << 20) /**< \brief Ssc signal: RF */
-#define PIO_PA19A_RK (1 << 19) /**< \brief Ssc signal: RK */
-#define PIO_PA17A_TD (1 << 17) /**< \brief Ssc signal: TD */
-#define PIO_PA15A_TF (1 << 15) /**< \brief Ssc signal: TF */
-#define PIO_PA16A_TK (1 << 16) /**< \brief Ssc signal: TK */
-/* ========== Pio definition for SPI peripheral ========== */
-#define PIO_PA12A_MISO (1 << 12) /**< \brief Spi signal: MISO */
-#define PIO_PA13A_MOSI (1 << 13) /**< \brief Spi signal: MOSI */
-#define PIO_PA11A_NPCS0 (1 << 11) /**< \brief Spi signal: NPCS0 */
-#define PIO_PA31A_NPCS1 (1 << 31) /**< \brief Spi signal: NPCS1 */
-#define PIO_PA9B_NPCS1 (1 << 9) /**< \brief Spi signal: NPCS1 */
-#define PIO_PB14A_NPCS1 (1 << 14) /**< \brief Spi signal: NPCS1 */
-#define PIO_PC4B_NPCS1 (1 << 4) /**< \brief Spi signal: NPCS1 */
-#define PIO_PA10B_NPCS2 (1 << 10) /**< \brief Spi signal: NPCS2 */
-#define PIO_PA30B_NPCS2 (1 << 30) /**< \brief Spi signal: NPCS2 */
-#define PIO_PB2B_NPCS2 (1 << 2) /**< \brief Spi signal: NPCS2 */
-#define PIO_PA22B_NPCS3 (1 << 22) /**< \brief Spi signal: NPCS3 */
-#define PIO_PA3B_NPCS3 (1 << 3) /**< \brief Spi signal: NPCS3 */
-#define PIO_PA5B_NPCS3 (1 << 5) /**< \brief Spi signal: NPCS3 */
-#define PIO_PA14A_SPCK (1 << 14) /**< \brief Spi signal: SPCK */
-/* ========== Pio definition for TC0 peripheral ========== */
-#define PIO_PA4B_TCLK0 (1 << 4) /**< \brief Tc0 signal: TCLK0 */
-#define PIO_PA28B_TCLK1 (1 << 28) /**< \brief Tc0 signal: TCLK1 */
-#define PIO_PA29B_TCLK2 (1 << 29) /**< \brief Tc0 signal: TCLK2 */
-#define PIO_PA0B_TIOA0 (1 << 0) /**< \brief Tc0 signal: TIOA0 */
-#define PIO_PA15B_TIOA1 (1 << 15) /**< \brief Tc0 signal: TIOA1 */
-#define PIO_PA26B_TIOA2 (1 << 26) /**< \brief Tc0 signal: TIOA2 */
-#define PIO_PA1B_TIOB0 (1 << 1) /**< \brief Tc0 signal: TIOB0 */
-#define PIO_PA16B_TIOB1 (1 << 16) /**< \brief Tc0 signal: TIOB1 */
-#define PIO_PA27B_TIOB2 (1 << 27) /**< \brief Tc0 signal: TIOB2 */
-/* ========== Pio definition for TC1 peripheral ========== */
-#define PIO_PC25B_TCLK3 (1 << 25) /**< \brief Tc1 signal: TCLK3 */
-#define PIO_PC28B_TCLK4 (1 << 28) /**< \brief Tc1 signal: TCLK4 */
-#define PIO_PC31B_TCLK5 (1 << 31) /**< \brief Tc1 signal: TCLK5 */
-#define PIO_PC23B_TIOA3 (1 << 23) /**< \brief Tc1 signal: TIOA3 */
-#define PIO_PC26B_TIOA4 (1 << 26) /**< \brief Tc1 signal: TIOA4 */
-#define PIO_PC29B_TIOA5 (1 << 29) /**< \brief Tc1 signal: TIOA5 */
-#define PIO_PC24B_TIOB3 (1 << 24) /**< \brief Tc1 signal: TIOB3 */
-#define PIO_PC27B_TIOB4 (1 << 27) /**< \brief Tc1 signal: TIOB4 */
-#define PIO_PC30B_TIOB5 (1 << 30) /**< \brief Tc1 signal: TIOB5 */
-/* ========== Pio definition for TWI0 peripheral ========== */
-#define PIO_PA4A_TWCK0 (1 << 4) /**< \brief Twi0 signal: TWCK0 */
-#define PIO_PA3A_TWD0 (1 << 3) /**< \brief Twi0 signal: TWD0 */
-/* ========== Pio definition for TWI1 peripheral ========== */
-#define PIO_PB5A_TWCK1 (1 << 5) /**< \brief Twi1 signal: TWCK1 */
-#define PIO_PB4A_TWD1 (1 << 4) /**< \brief Twi1 signal: TWD1 */
-/* ========== Pio definition for PWM peripheral ========== */
-#define PIO_PA9C_PWMFI0 (1 << 9) /**< \brief Pwm signal: PWMFI0 */
-#define PIO_PA0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */
-#define PIO_PA11B_PWMH0 (1 << 11) /**< \brief Pwm signal: PWMH0 */
-#define PIO_PA23B_PWMH0 (1 << 23) /**< \brief Pwm signal: PWMH0 */
-#define PIO_PB0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */
-#define PIO_PC18B_PWMH0 (1 << 18) /**< \brief Pwm signal: PWMH0 */
-#define PIO_PA1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */
-#define PIO_PA12B_PWMH1 (1 << 12) /**< \brief Pwm signal: PWMH1 */
-#define PIO_PA24B_PWMH1 (1 << 24) /**< \brief Pwm signal: PWMH1 */
-#define PIO_PB1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */
-#define PIO_PC19B_PWMH1 (1 << 19) /**< \brief Pwm signal: PWMH1 */
-#define PIO_PA13B_PWMH2 (1 << 13) /**< \brief Pwm signal: PWMH2 */
-#define PIO_PA2A_PWMH2 (1 << 2) /**< \brief Pwm signal: PWMH2 */
-#define PIO_PA25B_PWMH2 (1 << 25) /**< \brief Pwm signal: PWMH2 */
-#define PIO_PB4B_PWMH2 (1 << 4) /**< \brief Pwm signal: PWMH2 */
-#define PIO_PC20B_PWMH2 (1 << 20) /**< \brief Pwm signal: PWMH2 */
-#define PIO_PA14B_PWMH3 (1 << 14) /**< \brief Pwm signal: PWMH3 */
-#define PIO_PA17C_PWMH3 (1 << 17) /**< \brief Pwm signal: PWMH3 */
-#define PIO_PA7B_PWMH3 (1 << 7) /**< \brief Pwm signal: PWMH3 */
-#define PIO_PB14B_PWMH3 (1 << 14) /**< \brief Pwm signal: PWMH3 */
-#define PIO_PC21B_PWMH3 (1 << 21) /**< \brief Pwm signal: PWMH3 */
-#define PIO_PA19B_PWML0 (1 << 19) /**< \brief Pwm signal: PWML0 */
-#define PIO_PB5B_PWML0 (1 << 5) /**< \brief Pwm signal: PWML0 */
-#define PIO_PC0B_PWML0 (1 << 0) /**< \brief Pwm signal: PWML0 */
-#define PIO_PC13B_PWML0 (1 << 13) /**< \brief Pwm signal: PWML0 */
-#define PIO_PA20B_PWML1 (1 << 20) /**< \brief Pwm signal: PWML1 */
-#define PIO_PB12A_PWML1 (1 << 12) /**< \brief Pwm signal: PWML1 */
-#define PIO_PC1B_PWML1 (1 << 1) /**< \brief Pwm signal: PWML1 */
-#define PIO_PC15B_PWML1 (1 << 15) /**< \brief Pwm signal: PWML1 */
-#define PIO_PA16C_PWML2 (1 << 16) /**< \brief Pwm signal: PWML2 */
-#define PIO_PA30A_PWML2 (1 << 30) /**< \brief Pwm signal: PWML2 */
-#define PIO_PB13A_PWML2 (1 << 13) /**< \brief Pwm signal: PWML2 */
-#define PIO_PC2B_PWML2 (1 << 2) /**< \brief Pwm signal: PWML2 */
-#define PIO_PA15C_PWML3 (1 << 15) /**< \brief Pwm signal: PWML3 */
-#define PIO_PC22B_PWML3 (1 << 22) /**< \brief Pwm signal: PWML3 */
-#define PIO_PC3B_PWML3 (1 << 3) /**< \brief Pwm signal: PWML3 */
-/* ========== Pio definition for USART0 peripheral ========== */
-#define PIO_PA8A_CTS0 (1 << 8) /**< \brief Usart0 signal: CTS0 */
-#define PIO_PA7A_RTS0 (1 << 7) /**< \brief Usart0 signal: RTS0 */
-#define PIO_PA5A_RXD0 (1 << 5) /**< \brief Usart0 signal: RXD0 */
-#define PIO_PA2B_SCK0 (1 << 2) /**< \brief Usart0 signal: SCK0 */
-#define PIO_PA6A_TXD0 (1 << 6) /**< \brief Usart0 signal: TXD0 */
-/* ========== Pio definition for USART1 peripheral ========== */
-#define PIO_PA25A_CTS1 (1 << 25) /**< \brief Usart1 signal: CTS1 */
-#define PIO_PA26A_DCD1 (1 << 26) /**< \brief Usart1 signal: DCD1 */
-#define PIO_PA28A_DSR1 (1 << 28) /**< \brief Usart1 signal: DSR1 */
-#define PIO_PA27A_DTR1 (1 << 27) /**< \brief Usart1 signal: DTR1 */
-#define PIO_PA29A_RI1 (1 << 29) /**< \brief Usart1 signal: RI1 */
-#define PIO_PA24A_RTS1 (1 << 24) /**< \brief Usart1 signal: RTS1 */
-#define PIO_PA21A_RXD1 (1 << 21) /**< \brief Usart1 signal: RXD1 */
-#define PIO_PA23A_SCK1 (1 << 23) /**< \brief Usart1 signal: SCK1 */
-#define PIO_PA22A_TXD1 (1 << 22) /**< \brief Usart1 signal: TXD1 */
-/* ========== Pio definition for ADC peripheral ========== */
-#define PIO_PA17X1_AD0 (1 << 17) /**< \brief Adc signal: AD0 */
-#define PIO_PA18X1_AD1 (1 << 18) /**< \brief Adc signal: AD1 */
-#define PIO_PC13X1_AD10 (1 << 13) /**< \brief Adc signal: AD10 */
-#define PIO_PC15X1_AD11 (1 << 15) /**< \brief Adc signal: AD11 */
-#define PIO_PC12X1_AD12 (1 << 12) /**< \brief Adc signal: AD12 */
-#define PIO_PC29X1_AD13 (1 << 29) /**< \brief Adc signal: AD13 */
-#define PIO_PC30X1_AD14 (1 << 30) /**< \brief Adc signal: AD14 */
-#define PIO_PA19X1_AD2 (1 << 19) /**< \brief Adc signal: AD2 */
-#define PIO_PA20X1_AD3 (1 << 20) /**< \brief Adc signal: AD3 */
-#define PIO_PB0X1_AD4 (1 << 0) /**< \brief Adc signal: AD4 */
-#define PIO_PB1X1_AD5 (1 << 1) /**< \brief Adc signal: AD5 */
-#define PIO_PB2X1_AD6 (1 << 2) /**< \brief Adc signal: AD6 */
-#define PIO_PB3X1_AD7 (1 << 3) /**< \brief Adc signal: AD7 */
-#define PIO_PA21X1_AD8 (1 << 21) /**< \brief Adc signal: AD8 */
-#define PIO_PA22X1_AD9 (1 << 22) /**< \brief Adc signal: AD9 */
-#define PIO_PA8B_ADTRG (1 << 8) /**< \brief Adc signal: ADTRG */
-/* ========== Pio definition for DACC peripheral ========== */
-#define PIO_PB13X1_DAC0 (1 << 13) /**< \brief Dacc signal: DAC0 */
-#define PIO_PB14X1_DAC1 (1 << 14) /**< \brief Dacc signal: DAC1 */
-#define PIO_PA2C_DATRG (1 << 2) /**< \brief Dacc signal: DATRG */
-/* ========== Pio definition for PMC peripheral ========== */
-#define PIO_PA6B_PCK0 (1 << 6) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB13B_PCK0 (1 << 13) /**< \brief Pmc signal: PCK0 */
-#define PIO_PA17B_PCK1 (1 << 17) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA21B_PCK1 (1 << 21) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA18B_PCK2 (1 << 18) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA31B_PCK2 (1 << 31) /**< \brief Pmc signal: PCK2 */
-#define PIO_PB3B_PCK2 (1 << 3) /**< \brief Pmc signal: PCK2 */
-/* ========== Pio definition for UART0 peripheral ========== */
-#define PIO_PA9A_URXD0 (1 << 9) /**< \brief Uart0 signal: URXD0 */
-#define PIO_PA10A_UTXD0 (1 << 10) /**< \brief Uart0 signal: UTXD0 */
-/* ========== Pio definition for UART1 peripheral ========== */
-#define PIO_PB2A_URXD1 (1 << 2) /**< \brief Uart1 signal: URXD1 */
-#define PIO_PB3A_UTXD1 (1 << 3) /**< \brief Uart1 signal: UTXD1 */
-/* ========== Pio definition for PIOA peripheral ========== */
-#define PIO_PA24X1_PIODC0 (1 << 24) /**< \brief Pioa signal: PIODC0 */
-#define PIO_PA25X1_PIODC1 (1 << 25) /**< \brief Pioa signal: PIODC1 */
-#define PIO_PA26X1_PIODC2 (1 << 26) /**< \brief Pioa signal: PIODC2 */
-#define PIO_PA27X1_PIODC3 (1 << 27) /**< \brief Pioa signal: PIODC3 */
-#define PIO_PA28X1_PIODC4 (1 << 28) /**< \brief Pioa signal: PIODC4 */
-#define PIO_PA29X1_PIODC5 (1 << 29) /**< \brief Pioa signal: PIODC5 */
-#define PIO_PA30X1_PIODC6 (1 << 30) /**< \brief Pioa signal: PIODC6 */
-#define PIO_PA31X1_PIODC7 (1 << 31) /**< \brief Pioa signal: PIODC7 */
-#define PIO_PA23X1_PIODCCLK (1 << 23) /**< \brief Pioa signal: PIODCCLK */
-#define PIO_PA15X1_PIODCEN1 (1 << 15) /**< \brief Pioa signal: PIODCEN1 */
-#define PIO_PA16X1_PIODCEN2 (1 << 16) /**< \brief Pioa signal: PIODCEN2 */
-/*@}*/
-
-/* ***************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR AT91SAM3S */
-/* ***************************************************************************** */
-
-#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */
-#define AT91C_IFLASH (0x00400000) /**< Internal Flash base address */
-#define AT91C_IROM (0x00800000) /**< Internal ROM base address */
-#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */
-#define AT91C_EBI_CS0 (0x60000000) /**< EBI Chip Select 0 base address */
-#define AT91C_EBI_CS1 (0x61000000) /**< EBI Chip Select 1 base address */
-#define AT91C_EBI_CS2 (0x62000000) /**< EBI Chip Select 2 base address */
-#define AT91C_EBI_CS3 (0x63000000) /**< EBI Chip Select 3 base address */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* AT91SAM3S_H */
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/chip.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/chip.h
deleted file mode 100644
index 8b698408..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/chip.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-/// \unit
-/// !Purpose
-///
-/// Definition of AT91SAM3S4 characteristics and features
-///
-/// !Usage
-/// -# For ARM core feature, see "AT91SAM3S4 - ARM core features".
-/// -# For IP features, see "AT91SAM3S4 - IP features".
-/// -# For misc, see "AT91SAM3S4 - Misc".
-//------------------------------------------------------------------------------
-
-#ifndef CHIP_H
-#define CHIP_H
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Definitions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// \page "AT91SAM3S4 - ARM core features"
-/// This page lists several characteristics related to the ARM core
-///
-
-//ARM core features
-
-/// ARM core definition.
-#define cortexm3
-
-/// family definition.
-#define at91sam3s
-
-//------------------------------------------------------------------------------
-/// \page "AT91SAM3S4 - IP features"
-/// This page lists several characteristics related to the embedded IP
-///
-
-//IP FEATURES
-
-// EFC GPNVM number
-#define CHIP_EFC_NUM_GPNVMS 3
-
-/// Indicates chip has an Enhanced EFC.
-#define CHIP_FLASH_EEFC
-
-// DMA channels number
-#define CHIP_DMA_CHANNEL_NUM 4
-
-// Indicate chip's MCI interface.
-#define MCI2_INTERFACE
-
-// Indicate chip SSC has DMA interface.
-#define CHIP_SSC_DMA
-
-// Indicate chip SPI has DMA interface.
-#define CHIP_SPI_DMA
-
-/// Indicates chip has an UDP Full Speed.
-#define CHIP_USB_UDP
-
-/// Indicates chip has an internal pull-up.
-#define CHIP_USB_PULLUP_INTERNAL
-
-/// Number of USB endpoints
-#define CHIP_USB_NUMENDPOINTS 8
-
-/// Endpoints max paxcket size
-#define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(i) \
- ((i == 0) ? 64 : \
- ((i == 1) ? 64 : \
- ((i == 2) ? 64 : \
- ((i == 3) ? 64 : \
- ((i == 4) ? 512 : \
- ((i == 5) ? 512 : \
- ((i == 6) ? 64 : \
- ((i == 7) ? 64 : 0 ))))))))
-
-/// Endpoints Number of Bank
-#define CHIP_USB_ENDPOINTS_BANKS(i) \
- ((i == 0) ? 1 : \
- ((i == 1) ? 2 : \
- ((i == 2) ? 2 : \
- ((i == 3) ? 1 : \
- ((i == 4) ? 2 : \
- ((i == 5) ? 2 : \
- ((i == 6) ? 2 : \
- ((i == 7) ? 2 : 0 ))))))))
-
-//------------------------------------------------------------------------------
-/// \page "AT91SAM3S4 - Misc "
-/// This page lists misc features
-///
-
-//Misc
-
-#endif //#ifndef CHIP_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/flash.icf b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/flash.icf
deleted file mode 100644
index 65ac3312..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/flash.icf
+++ /dev/null
@@ -1,30 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
-/*-Vector table start*/
-define symbol __ICFEDIT_vector_start__ = 0x000400000; /*Add for CMSIS*/
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2000BFFF;
-define symbol __ICFEDIT_region_ROM_start__ = 0x00400000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0043FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x800;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-
-export symbol __ICFEDIT_vector_start__; /*Add for CMSIS*/
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_vector_start__ { readonly section .vectors }; /*Add for CMSIS*/
-place in ROM_region { readonly };
-place in RAM_region { readwrite,,block CSTACK, block HEAP };
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/flash.lds b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/flash.lds
deleted file mode 100644
index 9d01841e..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/flash.lds
+++ /dev/null
@@ -1,81 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/*------------------------------------------------------------------------------
- * Linker script for running in internal FLASH on the AT91SAM3S4
- *----------------------------------------------------------------------------*/
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(ResetException)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
- sram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x0000C000 /* sram, 48K */
- flash (W!RX) : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* Flash, 256K */
-}
-
-SECTIONS
-{
- .fixed :
- {
- . = ALIGN(4);
- _sfixed = .;
- KEEP(*(.vectors))
- *(.text*)
- *(.rodata*)
- *(.glue_7)
- *(.glue_7t)
- . = ALIGN(4);
- _efixed = .; /* End of text section */
- } >flash
-
- .relocate : AT (_efixed)
- {
- . = ALIGN(4);
- _srelocate = .;
- *(.ramfunc);
- *(.data);
- . = ALIGN(4);
- _erelocate = .;
- } >sram
-
- .bss (NOLOAD) : {
- . = ALIGN(4);
- _szero = .;
- *(.bss)
- . = ALIGN(4);
- _ezero = .;
- } >sram
-
- /* Stack in the end of SRAM */
- _estack = 0x2000BFFC;
-}
-end = .;
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/sram.icf b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/sram.icf
deleted file mode 100644
index 22eb374b..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/sram.icf
+++ /dev/null
@@ -1,27 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
-/*-Vector table start*/
-define symbol __ICFEDIT_vector_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2000BFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x900;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/*-Exports-*/
-export symbol __ICFEDIT_vector_start__;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-/* define block RamVect with alignment = 8, size = __ICFEDIT_size_vectors__ { }; */
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_vector_start__ { readonly section .vectors };
-place in RAM_region { readonly, readwrite, block CSTACK, block HEAP };
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/sram.lds b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/sram.lds
deleted file mode 100644
index 2d38cfcc..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/sram.lds
+++ /dev/null
@@ -1,81 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/*------------------------------------------------------------------------------
- * Linker script for running in internal SRAM on the AT91SAM3S4
- *----------------------------------------------------------------------------*/
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(ResetException)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
- sram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x0000C000 /* sram, 48K */
-}
-
-SECTIONS
-{
- .fixed :
- {
- . = ALIGN(4);
- _sfixed = .;
- KEEP(*(.vectors))
- *(.text*)
- *(.ramfunc)
- *(.rodata*)
- *(.glue_7)
- *(.glue_7t)
- . = ALIGN(4);
- _efixed = .; /* End of text section */
- } > sram
-
- .relocate : AT (_efixed)
- {
- . = ALIGN(4);
- _srelocate = .;
- *(.data)
- . = ALIGN(4);
- _erelocate = .;
- } >sram
-
- .bss (NOLOAD) : {
- . = ALIGN(4);
- _szero = .;
- *(.bss)
- . = ALIGN(4);
- _ezero = .;
- } >sram
-
- /* Stack in the end of SRAM */
- _estack = 0x2000BFFC;
-
-}
-end = .;
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/sram_flashloader.icf b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/sram_flashloader.icf
deleted file mode 100644
index a954d2cb..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/sram_flashloader.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x0;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000040;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2000BFFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x0200;
-define symbol __ICFEDIT_size_heap__ = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-//initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { section .intvec };
-
-place at start of RAM_region { block RamTop with fixed order {readonly, section LOWEND}};
-place at end of RAM_region { block RamBottom with fixed order {section HIGHSTART, readwrite, section .init,
- block CSTACK, block HEAP}};
-
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/sram_samba.lds b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/sram_samba.lds
deleted file mode 100644
index 16b1dc96..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/sram_samba.lds
+++ /dev/null
@@ -1,91 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/*------------------------------------------------------------------------------
- * Linker script for running in internal SRAM on the AT91SAM3S4
- *----------------------------------------------------------------------------*/
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(entry)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
- romcodesram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x01000
- sram (W!RX) : ORIGIN = 0x20001000, LENGTH = 0x0000B000 /* sram, 48K - sizeof(romcodesram) */
-}
-
-/* Entry point */
-/*ENTRY (ResetException)*/
-
-SECTIONS
-{
- /* startup code in the .isr_vector */
- .text :
- {
- . = ALIGN(4);
- _stext = .;
- KEEP(*(.isr_vector .isr_vector.*))
- *(.mailbox)
- *(.text .text.*)
- *(.rodata .rodata.*)
- *(.glue_7)
- *(.glue_7t)
- *(.gcc_except_table)
- *(.rodata .rodata*)
- *(.gnu.linkonce.r.*)
- . = ALIGN(4);
- _etext = .;
- } > sram
-
- /* data */
- .data :
- {
- . = ALIGN(4);
- _sidata = .;
- _sdata = .;
-
- *(.data)
- *(.data.*)
- . = ALIGN(4);
- _edata = .;
- } > sram
-
- .bss (NOLOAD) : {
- _szero = .;
- *(.bss)
- . = ALIGN(4);
- _ezero = .;
- } >sram
-
- /* Stack in SRAM */
- _sstack = 0x2000BFFC;
-}
-end = .;
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/AT91SAM3U4.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/AT91SAM3U4.h
deleted file mode 100644
index 64101aa0..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/AT91SAM3U4.h
+++ /dev/null
@@ -1,7439 +0,0 @@
-/* ---------------------------------------------------------------------------- */
-/* Atmel Microcontroller Software Support */
-/* ---------------------------------------------------------------------------- */
-/* Copyright (c) 2009, Atmel Corporation */
-/* */
-/* All rights reserved. */
-/* */
-/* Redistribution and use in source and binary forms, with or without */
-/* modification, are permitted provided that the following condition is met: */
-/* */
-/* - Redistributions of source code must retain the above copyright notice, */
-/* this list of conditions and the disclaimer below. */
-/* */
-/* Atmel's name may not be used to endorse or promote products derived from */
-/* this software without specific prior written permission. */
-/* */
-/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
-/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
-/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
-/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
-/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
-/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
-/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
-/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
-/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
-/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
-/* ---------------------------------------------------------------------------- */
-/* */
-/* File Name : AT91SAM3U.h */
-/* Object : AT91SAM3U definitions */
-/* Generated by : AT91 SW Application Group */
-/* Generated on : 2009-09-10 */
-
-#ifndef AT91SAM3U_H
-#define AT91SAM3U_H
-
-/** \addtogroup AT91SAM3U_definitions AT91SAM3U definitions
- This file defines all structures and symbols for AT91SAM3U:
- - registers and bitfields
- - peripheral base address
- - peripheral ID
- - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __ASSEMBLY__
-#include
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
-#else
-typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
-#endif
-typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
-#define CAST(type, value) ((type *) value)
-#define REG_ACCESS(type, address) (*(type*)address) /**< C code: Register value */
-#else
-#define CAST(type, value) (value)
-#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
-#endif
-
-/* ***************************************************************************** */
-/* CMSIS DEFINITIONS FOR AT91SAM3U */
-/* ***************************************************************************** */
-/** \addtogroup AT91SAM3U_cmsis CMSIS Definitions */
-
-/*@{*/
-
-/**
- * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
- */
-#define __MPU_PRESENT 0 /**< AT91SAM3U does not provide a MPU present or not */
-#define __NVIC_PRIO_BITS 4 /**< AT91SAM3U uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
-
-/**< Interrupt Number Definition */
-typedef enum IRQn
-{
-/****** Cortex-M3 Processor Exceptions Numbers ***************************************/
- NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
- MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */
-/****** AT91SAM3U specific Interrupt Numbers *****************************************/
-
- SUPC_IRQn = 0, /**< 0 AT91SAM3U Supply Controller (SUPC) */
- RSTC_IRQn = 1, /**< 1 AT91SAM3U Reset Controller (RSTC) */
- RTC_IRQn = 2, /**< 2 AT91SAM3U Real Time Clock (RTC) */
- RTT_IRQn = 3, /**< 3 AT91SAM3U Real Time Timer (RTT) */
- WDT_IRQn = 4, /**< 4 AT91SAM3U Watchdog Timer (WDT) */
- PMC_IRQn = 5, /**< 5 AT91SAM3U Power Management Controller (PMC) */
- EFC0_IRQn = 6, /**< 6 AT91SAM3U Enhanced Embedded Flash Controller 0 (EFC0) */
- EFC1_IRQn = 7, /**< 7 AT91SAM3U Enhanced Embedded Flash Controller 1 (EFC1) */
- UART_IRQn = 8, /**< 8 AT91SAM3U Universal Asynchronous Receiver Transmitter (UART) */
- SMC_IRQn = 9, /**< 9 AT91SAM3U Static Memory Controller (SMC) */
- PIOA_IRQn = 10, /**< 10 AT91SAM3U Parallel I/O Controller A, (PIOA) */
- PIOB_IRQn = 11, /**< 11 AT91SAM3U Parallel I/O Controller B (PIOB) */
- PIOC_IRQn = 12, /**< 12 AT91SAM3U Parallel I/O Controller C (PIOC) */
- USART0_IRQn = 13, /**< 13 AT91SAM3U USART 0 (USART0) */
- USART1_IRQn = 14, /**< 14 AT91SAM3U USART 1 (USART1) */
- USART2_IRQn = 15, /**< 15 AT91SAM3U USART 2 (USART2) */
- USART3_IRQn = 16, /**< 16 AT91SAM3U USART 3 (USART3) */
- HSMCI_IRQn = 17, /**< 17 AT91SAM3U High Speed Multimedia Card Interface (HSMCI) */
- TWI0_IRQn = 18, /**< 18 AT91SAM3U Two-Wire Interface 0 (TWI0) */
- TWI1_IRQn = 19, /**< 19 AT91SAM3U Two-Wire Interface 1 (TWI1) */
- SPI_IRQn = 20, /**< 20 AT91SAM3U Serial Peripheral Interface (SPI) */
- SSC_IRQn = 21, /**< 21 AT91SAM3U Synchronous Serial Controller (SSC) */
- TC0_IRQn = 22, /**< 22 AT91SAM3U Timer Counter 0 (TC0) */
- TC1_IRQn = 23, /**< 23 AT91SAM3U Timer Counter 1 (TC1) */
- TC2_IRQn = 24, /**< 24 AT91SAM3U Timer Counter 2 (TC2) */
- PWM_IRQn = 25, /**< 25 AT91SAM3U Pulse Width Modulation Controller (PWM) */
- ADC12B_IRQn = 26, /**< 26 AT91SAM3U 12-bit ADC Controller (ADC12B) */
- ADC_IRQn = 27, /**< 27 AT91SAM3U 10-bit ADC Controller (ADC) */
- DMAC_IRQn = 28, /**< 28 AT91SAM3U DMA Controller (DMAC) */
- UDPHS_IRQn = 29, /**< 29 AT91SAM3U USB Device High Speed (UDPHS) */
-} IRQn_Type;
-/*@}*/
-
-/* ***************************************************************************** */
-/** SOFTWARE PERIPHERAL API DEFINITION FOR AT91SAM3U */
-/* ***************************************************************************** */
-/** \addtogroup AT91SAM3U_api Peripheral Software API */
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Analog-to-digital Converter */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3U_ADC12B Analog-to-digital Converter */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Adc12b hardware registers */
-typedef struct {
- WoReg ADC_CR; /**< \brief (Adc12b Offset: 0x00) Control Register */
- RwReg ADC_MR; /**< \brief (Adc12b Offset: 0x04) Mode Register */
- RwReg Reserved1[2];
- WoReg ADC_CHER; /**< \brief (Adc12b Offset: 0x10) Channel Enable Register */
- WoReg ADC_CHDR; /**< \brief (Adc12b Offset: 0x14) Channel Disable Register */
- RoReg ADC_CHSR; /**< \brief (Adc12b Offset: 0x18) Channel Status Register */
- RoReg ADC_SR; /**< \brief (Adc12b Offset: 0x1C) Status Register */
- RoReg ADC_LCDR; /**< \brief (Adc12b Offset: 0x20) Last Converted Data Register */
- WoReg ADC_IER; /**< \brief (Adc12b Offset: 0x24) Interrupt Enable Register */
- WoReg ADC_IDR; /**< \brief (Adc12b Offset: 0x28) Interrupt Disable Register */
- RoReg ADC_IMR; /**< \brief (Adc12b Offset: 0x2C) Interrupt Mask Register */
- RoReg ADC_CDR[8]; /**< \brief (Adc12b Offset: 0x30) Channel Data Register */
- RwReg Reserved2[5];
- RwReg ADC_ACR; /**< \brief (Adc12b Offset: 0x64) Analog Control Register */
- RwReg ADC_EMR; /**< \brief (Adc12b Offset: 0x68) Extended Mode Register */
- RwReg Reserved3[37];
- RwReg ADC_RPR; /**< \brief (Adc12b Offset: 0x100) Receive Pointer Register */
- RwReg ADC_RCR; /**< \brief (Adc12b Offset: 0x104) Receive Counter Register */
- RwReg ADC_TPR; /**< \brief (Adc12b Offset: 0x108) Transmit Pointer Register */
- RwReg ADC_TCR; /**< \brief (Adc12b Offset: 0x10C) Transmit Counter Register */
- RwReg ADC_RNPR; /**< \brief (Adc12b Offset: 0x110) Receive Next Pointer Register */
- RwReg ADC_RNCR; /**< \brief (Adc12b Offset: 0x114) Receive Next Counter Register */
- RwReg ADC_TNPR; /**< \brief (Adc12b Offset: 0x118) Transmit Next Pointer Register */
- RwReg ADC_TNCR; /**< \brief (Adc12b Offset: 0x11C) Transmit Next Counter Register */
- WoReg ADC_PTCR; /**< \brief (Adc12b Offset: 0x120) Transfer Control Register */
- RoReg ADC_PTSR; /**< \brief (Adc12b Offset: 0x124) Transfer Status Register */
-} Adc12b;
-#endif /* __ASSEMBLY__ */
-/* -------- ADC_CR : (ADC12B Offset: 0x00) Control Register -------- */
-#define ADC_CR_SWRST (0x1 << 0) /**< \brief (ADC_CR) Software Reset */
-#define ADC_CR_START (0x1 << 1) /**< \brief (ADC_CR) Start Conversion */
-/* -------- ADC_MR : (ADC12B Offset: 0x04) Mode Register -------- */
-#define ADC_MR_TRGEN (0x1 << 0) /**< \brief (ADC_MR) Trigger Enable */
-#define ADC_MR_TRGSEL (0x7 << 1) /**< \brief (ADC_MR) Trigger Selection */
-#define ADC_MR_LOWRES (0x1 << 4) /**< \brief (ADC_MR) Resolution */
-#define ADC_MR_SLEEP (0x1 << 5) /**< \brief (ADC_MR) Sleep Mode */
-#define ADC_MR_PRESCAL (0xff << 8) /**< \brief (ADC_MR) Prescaler Rate Selection */
-#define ADC_MR_STARTUP (0xff << 16) /**< \brief (ADC_MR) Start Up Time */
-#define ADC_MR_SHTIM (0xf << 24) /**< \brief (ADC_MR) Sample & Hold Time */
-/* -------- ADC_CHER : (ADC12B Offset: 0x10) Channel Enable Register -------- */
-#define ADC_CHER_CH0 (0x1 << 0) /**< \brief (ADC_CHER) Channel 0 Enable */
-#define ADC_CHER_CH1 (0x1 << 1) /**< \brief (ADC_CHER) Channel 1 Enable */
-#define ADC_CHER_CH2 (0x1 << 2) /**< \brief (ADC_CHER) Channel 2 Enable */
-#define ADC_CHER_CH3 (0x1 << 3) /**< \brief (ADC_CHER) Channel 3 Enable */
-#define ADC_CHER_CH4 (0x1 << 4) /**< \brief (ADC_CHER) Channel 4 Enable */
-#define ADC_CHER_CH5 (0x1 << 5) /**< \brief (ADC_CHER) Channel 5 Enable */
-#define ADC_CHER_CH6 (0x1 << 6) /**< \brief (ADC_CHER) Channel 6 Enable */
-#define ADC_CHER_CH7 (0x1 << 7) /**< \brief (ADC_CHER) Channel 7 Enable */
-/* -------- ADC_CHDR : (ADC12B Offset: 0x14) Channel Disable Register -------- */
-#define ADC_CHDR_CH0 (0x1 << 0) /**< \brief (ADC_CHDR) */
-#define ADC_CHDR_CH1 (0x1 << 1) /**< \brief (ADC_CHDR) */
-#define ADC_CHDR_CH2 (0x1 << 2) /**< \brief (ADC_CHDR) */
-#define ADC_CHDR_CH3 (0x1 << 3) /**< \brief (ADC_CHDR) */
-#define ADC_CHDR_CH4 (0x1 << 4) /**< \brief (ADC_CHDR) */
-#define ADC_CHDR_CH5 (0x1 << 5) /**< \brief (ADC_CHDR) */
-#define ADC_CHDR_CH6 (0x1 << 6) /**< \brief (ADC_CHDR) */
-#define ADC_CHDR_CH7 (0x1 << 7) /**< \brief (ADC_CHDR) */
-/* -------- ADC_CHSR : (ADC12B Offset: 0x18) Channel Status Register -------- */
-#define ADC_CHSR_CH0 (0x1 << 0) /**< \brief (ADC_CHSR) Channel 0 Status */
-#define ADC_CHSR_CH1 (0x1 << 1) /**< \brief (ADC_CHSR) Channel 1 Status */
-#define ADC_CHSR_CH2 (0x1 << 2) /**< \brief (ADC_CHSR) Channel 2 Status */
-#define ADC_CHSR_CH3 (0x1 << 3) /**< \brief (ADC_CHSR) Channel 3 Status */
-#define ADC_CHSR_CH4 (0x1 << 4) /**< \brief (ADC_CHSR) Channel 4 Status */
-#define ADC_CHSR_CH5 (0x1 << 5) /**< \brief (ADC_CHSR) Channel 5 Status */
-#define ADC_CHSR_CH6 (0x1 << 6) /**< \brief (ADC_CHSR) Channel 6 Status */
-#define ADC_CHSR_CH7 (0x1 << 7) /**< \brief (ADC_CHSR) Channel 7 Status */
-/* -------- ADC_SR : (ADC12B Offset: 0x1C) Status Register -------- */
-#define ADC_SR_EOC0 (0x1 << 0) /**< \brief (ADC_SR) End of Conversion 0 */
-#define ADC_SR_EOC1 (0x1 << 1) /**< \brief (ADC_SR) End of Conversion 1 */
-#define ADC_SR_EOC2 (0x1 << 2) /**< \brief (ADC_SR) End of Conversion 2 */
-#define ADC_SR_EOC3 (0x1 << 3) /**< \brief (ADC_SR) End of Conversion 3 */
-#define ADC_SR_EOC4 (0x1 << 4) /**< \brief (ADC_SR) End of Conversion 4 */
-#define ADC_SR_EOC5 (0x1 << 5) /**< \brief (ADC_SR) End of Conversion 5 */
-#define ADC_SR_EOC6 (0x1 << 6) /**< \brief (ADC_SR) End of Conversion 6 */
-#define ADC_SR_EOC7 (0x1 << 7) /**< \brief (ADC_SR) End of Conversion 7 */
-#define ADC_SR_OVRE0 (0x1 << 8) /**< \brief (ADC_SR) Overrun Error 0 */
-#define ADC_SR_OVRE1 (0x1 << 9) /**< \brief (ADC_SR) Overrun Error 1 */
-#define ADC_SR_OVRE2 (0x1 << 10) /**< \brief (ADC_SR) Overrun Error 2 */
-#define ADC_SR_OVRE3 (0x1 << 11) /**< \brief (ADC_SR) Overrun Error 3 */
-#define ADC_SR_OVRE4 (0x1 << 12) /**< \brief (ADC_SR) Overrun Error 4 */
-#define ADC_SR_OVRE5 (0x1 << 13) /**< \brief (ADC_SR) Overrun Error 5 */
-#define ADC_SR_OVRE6 (0x1 << 14) /**< \brief (ADC_SR) Overrun Error 6 */
-#define ADC_SR_OVRE7 (0x1 << 15) /**< \brief (ADC_SR) Overrun Error 7 */
-#define ADC_SR_DRDY (0x1 << 16) /**< \brief (ADC_SR) Data Ready */
-#define ADC_SR_GOVRE (0x1 << 17) /**< \brief (ADC_SR) General Overrun Error */
-#define ADC_SR_ENDRX (0x1 << 18) /**< \brief (ADC_SR) End of RX Buffer */
-#define ADC_SR_RXBUFF (0x1 << 19) /**< \brief (ADC_SR) RX Buffer Full */
-/* -------- ADC_LCDR : (ADC12B Offset: 0x20) Last Converted Data Register -------- */
-#define ADC_LCDR_LDATA (0xfff << 0) /**< \brief (ADC_LCDR) Last Data Converted */
-/* -------- ADC_IER : (ADC12B Offset: 0x24) Interrupt Enable Register -------- */
-#define ADC_IER_EOC0 (0x1 << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */
-#define ADC_IER_EOC1 (0x1 << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */
-#define ADC_IER_EOC2 (0x1 << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */
-#define ADC_IER_EOC3 (0x1 << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */
-#define ADC_IER_EOC4 (0x1 << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */
-#define ADC_IER_EOC5 (0x1 << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */
-#define ADC_IER_EOC6 (0x1 << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */
-#define ADC_IER_EOC7 (0x1 << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */
-#define ADC_IER_OVRE0 (0x1 << 8) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 0 */
-#define ADC_IER_OVRE1 (0x1 << 9) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 1 */
-#define ADC_IER_OVRE2 (0x1 << 10) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 2 */
-#define ADC_IER_OVRE3 (0x1 << 11) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 3 */
-#define ADC_IER_OVRE4 (0x1 << 12) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 4 */
-#define ADC_IER_OVRE5 (0x1 << 13) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 5 */
-#define ADC_IER_OVRE6 (0x1 << 14) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 6 */
-#define ADC_IER_OVRE7 (0x1 << 15) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 7 */
-#define ADC_IER_DRDY (0x1 << 16) /**< \brief (ADC_IER) Data Ready Interrupt Enable */
-#define ADC_IER_GOVRE (0x1 << 17) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */
-#define ADC_IER_ENDRX (0x1 << 18) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */
-#define ADC_IER_RXBUFF (0x1 << 19) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */
-/* -------- ADC_IDR : (ADC12B Offset: 0x28) Interrupt Disable Register -------- */
-#define ADC_IDR_EOC0 (0x1 << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */
-#define ADC_IDR_EOC1 (0x1 << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */
-#define ADC_IDR_EOC2 (0x1 << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */
-#define ADC_IDR_EOC3 (0x1 << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */
-#define ADC_IDR_EOC4 (0x1 << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */
-#define ADC_IDR_EOC5 (0x1 << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */
-#define ADC_IDR_EOC6 (0x1 << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */
-#define ADC_IDR_EOC7 (0x1 << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */
-#define ADC_IDR_OVRE0 (0x1 << 8) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 0 */
-#define ADC_IDR_OVRE1 (0x1 << 9) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 1 */
-#define ADC_IDR_OVRE2 (0x1 << 10) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 2 */
-#define ADC_IDR_OVRE3 (0x1 << 11) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 3 */
-#define ADC_IDR_OVRE4 (0x1 << 12) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 4 */
-#define ADC_IDR_OVRE5 (0x1 << 13) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 5 */
-#define ADC_IDR_OVRE6 (0x1 << 14) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 6 */
-#define ADC_IDR_OVRE7 (0x1 << 15) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 7 */
-#define ADC_IDR_DRDY (0x1 << 16) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */
-#define ADC_IDR_GOVRE (0x1 << 17) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */
-#define ADC_IDR_ENDRX (0x1 << 18) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */
-#define ADC_IDR_RXBUFF (0x1 << 19) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */
-/* -------- ADC_IMR : (ADC12B Offset: 0x2C) Interrupt Mask Register -------- */
-#define ADC_IMR_EOC0 (0x1 << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */
-#define ADC_IMR_EOC1 (0x1 << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */
-#define ADC_IMR_EOC2 (0x1 << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */
-#define ADC_IMR_EOC3 (0x1 << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */
-#define ADC_IMR_EOC4 (0x1 << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */
-#define ADC_IMR_EOC5 (0x1 << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */
-#define ADC_IMR_EOC6 (0x1 << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */
-#define ADC_IMR_EOC7 (0x1 << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */
-#define ADC_IMR_OVRE0 (0x1 << 8) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 0 */
-#define ADC_IMR_OVRE1 (0x1 << 9) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 1 */
-#define ADC_IMR_OVRE2 (0x1 << 10) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 2 */
-#define ADC_IMR_OVRE3 (0x1 << 11) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 3 */
-#define ADC_IMR_OVRE4 (0x1 << 12) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 4 */
-#define ADC_IMR_OVRE5 (0x1 << 13) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 5 */
-#define ADC_IMR_OVRE6 (0x1 << 14) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 6 */
-#define ADC_IMR_OVRE7 (0x1 << 15) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 7 */
-#define ADC_IMR_DRDY (0x1 << 16) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */
-#define ADC_IMR_GOVRE (0x1 << 17) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */
-#define ADC_IMR_ENDRX (0x1 << 18) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */
-#define ADC_IMR_RXBUFF (0x1 << 19) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */
-/* -------- ADC_CDR[8] : (ADC12B Offset: 0x30) Channel Data Register -------- */
-#define ADC_CDR_DATA (0xfff << 0) /**< \brief (ADC_CDR[8]) Converted Data */
-/* -------- ADC_ACR : (ADC12B Offset: 0x64) Analog Control Register -------- */
-#define ADC_ACR_GAIN (0x3 << 0) /**< \brief (ADC_ACR) Input Gain */
-#define ADC_ACR_IBCTL (0x3 << 6) /**< \brief (ADC_ACR) Bias Current Control */
-#define ADC_ACR_DIFF (0x1 << 16) /**< \brief (ADC_ACR) Differential Mode */
-#define ADC_ACR_OFFSET (0x1 << 17) /**< \brief (ADC_ACR) Input OFFSET */
-/* -------- ADC_EMR : (ADC12B Offset: 0x68) Extended Mode Register -------- */
-#define ADC_EMR_OFFMODES (0x1 << 0) /**< \brief (ADC_EMR) Off Mode if Sleep Bit (ADC_MR) = 1 */
-#define ADC_EMR_OFF_MODE_STARTUP_TIME (0xff << 16) /**< \brief (ADC_EMR) Startup Time */
-/* -------- ADC_RPR : (ADC12B Offset: 0x100) Receive Pointer Register -------- */
-#define ADC_RPR_RXPTR (0xffffffff << 0) /**< \brief (ADC_RPR) Receive Pointer Register */
-/* -------- ADC_RCR : (ADC12B Offset: 0x104) Receive Counter Register -------- */
-#define ADC_RCR_RXCTR (0xffff << 0) /**< \brief (ADC_RCR) Receive Counter Register */
-/* -------- ADC_TPR : (ADC12B Offset: 0x108) Transmit Pointer Register -------- */
-#define ADC_TPR_TXPTR (0xffffffff << 0) /**< \brief (ADC_TPR) Transmit Counter Register */
-/* -------- ADC_TCR : (ADC12B Offset: 0x10C) Transmit Counter Register -------- */
-#define ADC_TCR_TXCTR (0xffff << 0) /**< \brief (ADC_TCR) Transmit Counter Register */
-/* -------- ADC_RNPR : (ADC12B Offset: 0x110) Receive Next Pointer Register -------- */
-#define ADC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (ADC_RNPR) Receive Next Pointer */
-/* -------- ADC_RNCR : (ADC12B Offset: 0x114) Receive Next Counter Register -------- */
-#define ADC_RNCR_RXNCTR (0xffff << 0) /**< \brief (ADC_RNCR) Receive Next Counter */
-/* -------- ADC_TNPR : (ADC12B Offset: 0x118) Transmit Next Pointer Register -------- */
-#define ADC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (ADC_TNPR) Transmit Next Pointer */
-/* -------- ADC_TNCR : (ADC12B Offset: 0x11C) Transmit Next Counter Register -------- */
-#define ADC_TNCR_TXNCTR (0xffff << 0) /**< \brief (ADC_TNCR) Transmit Counter Next */
-/* -------- ADC_PTCR : (ADC12B Offset: 0x120) Transfer Control Register -------- */
-#define ADC_PTCR_RXTEN (0x1 << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */
-#define ADC_PTCR_RXTDIS (0x1 << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */
-#define ADC_PTCR_TXTEN (0x1 << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */
-#define ADC_PTCR_TXTDIS (0x1 << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */
-/* -------- ADC_PTSR : (ADC12B Offset: 0x124) Transfer Status Register -------- */
-#define ADC_PTSR_RXTEN (0x1 << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */
-#define ADC_PTSR_TXTEN (0x1 << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Chip Identifier */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3U_CHIPID Chip Identifier */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Chipid hardware registers */
-typedef struct {
- RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */
- RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */
-} Chipid;
-#endif /* __ASSEMBLY__ */
-/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
-#define CHIPID_CIDR_VERSION (0x1f << 0) /**< \brief (CHIPID_CIDR) Version of the Device */
-#define CHIPID_CIDR_EPROC (0x7 << 5) /**< \brief (CHIPID_CIDR) Embedded Processor */
-#define CHIPID_CIDR_NVPSIZ (0xf << 8) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */
-#define CHIPID_CIDR_NVPSIZ2 (0xf << 12) /**< \brief (CHIPID_CIDR) */
-#define CHIPID_CIDR_SRAMSIZ (0xf << 16) /**< \brief (CHIPID_CIDR) Internal SRAM Size */
-#define CHIPID_CIDR_ARCH (0xff << 20) /**< \brief (CHIPID_CIDR) Architecture Identifier */
-#define CHIPID_CIDR_NVPTYP (0x7 << 28) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */
-#define CHIPID_CIDR_EXT (0x1 << 31) /**< \brief (CHIPID_CIDR) Extension Flag */
-/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
-#define CHIPID_EXID_EXID (0xffffffff << 0) /**< \brief (CHIPID_EXID) Chip ID Extension */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR DMA Controller */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3U_DMAC DMA Controller */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief DmacCh_num hardware registers */
-typedef struct {
- RwReg DMAC_SADDR; /**< \brief (DmacCh_num Offset: 0x0) DMAC Channel Source Address Register */
- RwReg DMAC_DADDR; /**< \brief (DmacCh_num Offset: 0x4) DMAC Channel Destination Address Register */
- RwReg DMAC_DSCR; /**< \brief (DmacCh_num Offset: 0x8) DMAC Channel Descriptor Address Register */
- RwReg DMAC_CTRLA; /**< \brief (DmacCh_num Offset: 0xC) DMAC Channel Control A Register */
- RwReg DMAC_CTRLB; /**< \brief (DmacCh_num Offset: 0x10) DMAC Channel Control B Register */
- RwReg DMAC_CFG; /**< \brief (DmacCh_num Offset: 0x14) DMAC Channel Configuration Register */
- RwReg Reserved1[4];
-} DmacCh_num;
-/** \brief Dmac hardware registers */
-typedef struct {
- RwReg DMAC_GCFG; /**< \brief (Dmac Offset: 0x000) DMAC Global Configuration Register */
- RwReg DMAC_EN; /**< \brief (Dmac Offset: 0x004) DMAC Enable Register */
- RwReg DMAC_SREQ; /**< \brief (Dmac Offset: 0x008) DMAC Software Single Request Register */
- RwReg DMAC_CREQ; /**< \brief (Dmac Offset: 0x00C) DMAC Software Chunk Transfer Request Register */
- RwReg DMAC_LAST; /**< \brief (Dmac Offset: 0x010) DMAC Software Last Transfer Flag Register */
- RwReg Reserved1[1];
- WoReg DMAC_EBCIER; /**< \brief (Dmac Offset: 0x018) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. */
- WoReg DMAC_EBCIDR; /**< \brief (Dmac Offset: 0x01C) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register. */
- RoReg DMAC_EBCIMR; /**< \brief (Dmac Offset: 0x020) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register. */
- RoReg DMAC_EBCISR; /**< \brief (Dmac Offset: 0x024) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Status Register. */
- WoReg DMAC_CHER; /**< \brief (Dmac Offset: 0x028) DMAC Channel Handler Enable Register */
- WoReg DMAC_CHDR; /**< \brief (Dmac Offset: 0x02C) DMAC Channel Handler Disable Register */
- RoReg DMAC_CHSR; /**< \brief (Dmac Offset: 0x030) DMAC Channel Handler Status Register */
- RwReg Reserved2[2];
- DmacCh_num DMAC_CH_NUM[4]; /**< \brief (Dmac Offset: 0x3C) ch_num = 0 .. 3 */
-} Dmac;
-#endif /* __ASSEMBLY__ */
-/* -------- DMAC_GCFG : (DMAC Offset: 0x000) DMAC Global Configuration Register -------- */
-#define DMAC_GCFG_ARB_CFG (0x1 << 4) /**< \brief (DMAC_GCFG) */
-/* -------- DMAC_EN : (DMAC Offset: 0x004) DMAC Enable Register -------- */
-#define DMAC_EN_ENABLE (0x1 << 0) /**< \brief (DMAC_EN) */
-/* -------- DMAC_SREQ : (DMAC Offset: 0x008) DMAC Software Single Request Register -------- */
-#define DMAC_SREQ_SSREQ0 (0x1 << 0) /**< \brief (DMAC_SREQ) */
-#define DMAC_SREQ_DSREQ0 (0x1 << 1) /**< \brief (DMAC_SREQ) */
-#define DMAC_SREQ_SSREQ1 (0x1 << 2) /**< \brief (DMAC_SREQ) */
-#define DMAC_SREQ_DSREQ1 (0x1 << 3) /**< \brief (DMAC_SREQ) */
-#define DMAC_SREQ_SSREQ2_ (0x1 << 4) /**< \brief (DMAC_SREQ) */
-#define DMAC_SREQ_DSREQ2_ (0x1 << 5) /**< \brief (DMAC_SREQ) */
-#define DMAC_SREQ_SSREQ3 (0x1 << 6) /**< \brief (DMAC_SREQ) */
-#define DMAC_SREQ_DSREQ3 (0x1 << 7) /**< \brief (DMAC_SREQ) */
-/* -------- DMAC_CREQ : (DMAC Offset: 0x00C) DMAC Software Chunk Transfer Request Register -------- */
-#define DMAC_CREQ_SCREQ0 (0x1 << 0) /**< \brief (DMAC_CREQ) */
-#define DMAC_CREQ_DCREQ0 (0x1 << 1) /**< \brief (DMAC_CREQ) */
-#define DMAC_CREQ_SCREQ1 (0x1 << 2) /**< \brief (DMAC_CREQ) */
-#define DMAC_CREQ_DCREQ1 (0x1 << 3) /**< \brief (DMAC_CREQ) */
-#define DMAC_CREQ_SCREQ2_ (0x1 << 4) /**< \brief (DMAC_CREQ) */
-#define DMAC_CREQ_DCREQ2_ (0x1 << 5) /**< \brief (DMAC_CREQ) */
-#define DMAC_CREQ_SCREQ3 (0x1 << 6) /**< \brief (DMAC_CREQ) */
-#define DMAC_CREQ_DCREQ3 (0x1 << 7) /**< \brief (DMAC_CREQ) */
-/* -------- DMAC_LAST : (DMAC Offset: 0x010) DMAC Software Last Transfer Flag Register -------- */
-#define DMAC_LAST_SLAST0 (0x1 << 0) /**< \brief (DMAC_LAST) */
-#define DMAC_LAST_DLAST0 (0x1 << 1) /**< \brief (DMAC_LAST) */
-#define DMAC_LAST_SLAST1 (0x1 << 2) /**< \brief (DMAC_LAST) */
-#define DMAC_LAST_DLAST1 (0x1 << 3) /**< \brief (DMAC_LAST) */
-#define DMAC_LAST_SLAST2 (0x1 << 4) /**< \brief (DMAC_LAST) */
-#define DMAC_LAST_DLAST2 (0x1 << 5) /**< \brief (DMAC_LAST) */
-#define DMAC_LAST_SLAST3 (0x1 << 6) /**< \brief (DMAC_LAST) */
-#define DMAC_LAST_DLAST3 (0x1 << 7) /**< \brief (DMAC_LAST) */
-/* -------- DMAC_EBCIER : (DMAC Offset: 0x018) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. -------- */
-#define DMAC_EBCIER_BTC0 (0x1 << 0) /**< \brief (DMAC_EBCIER) */
-#define DMAC_EBCIER_BTC1 (0x1 << 1) /**< \brief (DMAC_EBCIER) */
-#define DMAC_EBCIER_BTC2 (0x1 << 2) /**< \brief (DMAC_EBCIER) */
-#define DMAC_EBCIER_BTC3 (0x1 << 3) /**< \brief (DMAC_EBCIER) */
-#define DMAC_EBCIER_CBTC0 (0x1 << 8) /**< \brief (DMAC_EBCIER) */
-#define DMAC_EBCIER_CBTC1 (0x1 << 9) /**< \brief (DMAC_EBCIER) */
-#define DMAC_EBCIER_CBTC2 (0x1 << 10) /**< \brief (DMAC_EBCIER) */
-#define DMAC_EBCIER_CBTC3 (0x1 << 11) /**< \brief (DMAC_EBCIER) */
-#define DMAC_EBCIER_ERR0 (0x1 << 16) /**< \brief (DMAC_EBCIER) */
-#define DMAC_EBCIER_ERR1 (0x1 << 17) /**< \brief (DMAC_EBCIER) */
-#define DMAC_EBCIER_ERR2 (0x1 << 18) /**< \brief (DMAC_EBCIER) */
-#define DMAC_EBCIER_ERR3 (0x1 << 19) /**< \brief (DMAC_EBCIER) */
-/* -------- DMAC_EBCIDR : (DMAC Offset: 0x01C) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register. -------- */
-#define DMAC_EBCIDR_BTC0 (0x1 << 0) /**< \brief (DMAC_EBCIDR) */
-#define DMAC_EBCIDR_BTC1 (0x1 << 1) /**< \brief (DMAC_EBCIDR) */
-#define DMAC_EBCIDR_BTC2 (0x1 << 2) /**< \brief (DMAC_EBCIDR) */
-#define DMAC_EBCIDR_BTC3 (0x1 << 3) /**< \brief (DMAC_EBCIDR) */
-#define DMAC_EBCIDR_CBTC0 (0x1 << 8) /**< \brief (DMAC_EBCIDR) */
-#define DMAC_EBCIDR_CBTC1 (0x1 << 9) /**< \brief (DMAC_EBCIDR) */
-#define DMAC_EBCIDR_CBTC2 (0x1 << 10) /**< \brief (DMAC_EBCIDR) */
-#define DMAC_EBCIDR_CBTC3 (0x1 << 11) /**< \brief (DMAC_EBCIDR) */
-#define DMAC_EBCIDR_ERR0 (0x1 << 16) /**< \brief (DMAC_EBCIDR) */
-#define DMAC_EBCIDR_ERR1 (0x1 << 17) /**< \brief (DMAC_EBCIDR) */
-#define DMAC_EBCIDR_ERR2 (0x1 << 18) /**< \brief (DMAC_EBCIDR) */
-#define DMAC_EBCIDR_ERR3 (0x1 << 19) /**< \brief (DMAC_EBCIDR) */
-/* -------- DMAC_EBCIMR : (DMAC Offset: 0x020) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register. -------- */
-#define DMAC_EBCIMR_BTC0 (0x1 << 0) /**< \brief (DMAC_EBCIMR) */
-#define DMAC_EBCIMR_BTC1 (0x1 << 1) /**< \brief (DMAC_EBCIMR) */
-#define DMAC_EBCIMR_BTC2 (0x1 << 2) /**< \brief (DMAC_EBCIMR) */
-#define DMAC_EBCIMR_BTC3 (0x1 << 3) /**< \brief (DMAC_EBCIMR) */
-#define DMAC_EBCIMR_CBTC0 (0x1 << 8) /**< \brief (DMAC_EBCIMR) */
-#define DMAC_EBCIMR_CBTC1 (0x1 << 9) /**< \brief (DMAC_EBCIMR) */
-#define DMAC_EBCIMR_CBTC2 (0x1 << 10) /**< \brief (DMAC_EBCIMR) */
-#define DMAC_EBCIMR_CBTC3 (0x1 << 11) /**< \brief (DMAC_EBCIMR) */
-#define DMAC_EBCIMR_ERR0 (0x1 << 16) /**< \brief (DMAC_EBCIMR) */
-#define DMAC_EBCIMR_ERR1 (0x1 << 17) /**< \brief (DMAC_EBCIMR) */
-#define DMAC_EBCIMR_ERR2 (0x1 << 18) /**< \brief (DMAC_EBCIMR) */
-#define DMAC_EBCIMR_ERR3 (0x1 << 19) /**< \brief (DMAC_EBCIMR) */
-/* -------- DMAC_EBCISR : (DMAC Offset: 0x024) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Status Register. -------- */
-#define DMAC_EBCISR_BTC0 (0x1 << 0) /**< \brief (DMAC_EBCISR) */
-#define DMAC_EBCISR_BTC1 (0x1 << 1) /**< \brief (DMAC_EBCISR) */
-#define DMAC_EBCISR_BTC2 (0x1 << 2) /**< \brief (DMAC_EBCISR) */
-#define DMAC_EBCISR_BTC3 (0x1 << 3) /**< \brief (DMAC_EBCISR) */
-#define DMAC_EBCISR_CBTC0 (0x1 << 8) /**< \brief (DMAC_EBCISR) */
-#define DMAC_EBCISR_CBTC1 (0x1 << 9) /**< \brief (DMAC_EBCISR) */
-#define DMAC_EBCISR_CBTC2 (0x1 << 10) /**< \brief (DMAC_EBCISR) */
-#define DMAC_EBCISR_CBTC3 (0x1 << 11) /**< \brief (DMAC_EBCISR) */
-#define DMAC_EBCISR_ERR0 (0x1 << 16) /**< \brief (DMAC_EBCISR) */
-#define DMAC_EBCISR_ERR1 (0x1 << 17) /**< \brief (DMAC_EBCISR) */
-#define DMAC_EBCISR_ERR2 (0x1 << 18) /**< \brief (DMAC_EBCISR) */
-#define DMAC_EBCISR_ERR3 (0x1 << 19) /**< \brief (DMAC_EBCISR) */
-/* -------- DMAC_CHER : (DMAC Offset: 0x028) DMAC Channel Handler Enable Register -------- */
-#define DMAC_CHER_ENA0 (0x1 << 0) /**< \brief (DMAC_CHER) */
-#define DMAC_CHER_ENA1 (0x1 << 1) /**< \brief (DMAC_CHER) */
-#define DMAC_CHER_ENA2 (0x1 << 2) /**< \brief (DMAC_CHER) */
-#define DMAC_CHER_ENA3 (0x1 << 3) /**< \brief (DMAC_CHER) */
-#define DMAC_CHER_SUSP0 (0x1 << 8) /**< \brief (DMAC_CHER) */
-#define DMAC_CHER_SUSP1 (0x1 << 9) /**< \brief (DMAC_CHER) */
-#define DMAC_CHER_SUSP2 (0x1 << 10) /**< \brief (DMAC_CHER) */
-#define DMAC_CHER_SUSP3 (0x1 << 11) /**< \brief (DMAC_CHER) */
-#define DMAC_CHER_KEEP0 (0x1 << 24) /**< \brief (DMAC_CHER) */
-#define DMAC_CHER_KEEP1 (0x1 << 25) /**< \brief (DMAC_CHER) */
-#define DMAC_CHER_KEEP2 (0x1 << 26) /**< \brief (DMAC_CHER) */
-#define DMAC_CHER_KEEP3 (0x1 << 27) /**< \brief (DMAC_CHER) */
-/* -------- DMAC_CHDR : (DMAC Offset: 0x02C) DMAC Channel Handler Disable Register -------- */
-#define DMAC_CHDR_DIS0 (0x1 << 0) /**< \brief (DMAC_CHDR) */
-#define DMAC_CHDR_DIS1 (0x1 << 1) /**< \brief (DMAC_CHDR) */
-#define DMAC_CHDR_DIS2 (0x1 << 2) /**< \brief (DMAC_CHDR) */
-#define DMAC_CHDR_DIS3 (0x1 << 3) /**< \brief (DMAC_CHDR) */
-#define DMAC_CHDR_RES0 (0x1 << 8) /**< \brief (DMAC_CHDR) */
-#define DMAC_CHDR_RES1 (0x1 << 9) /**< \brief (DMAC_CHDR) */
-#define DMAC_CHDR_RES2 (0x1 << 10) /**< \brief (DMAC_CHDR) */
-#define DMAC_CHDR_RES3 (0x1 << 11) /**< \brief (DMAC_CHDR) */
-/* -------- DMAC_CHSR : (DMAC Offset: 0x030) DMAC Channel Handler Status Register -------- */
-#define DMAC_CHSR_ENA0 (0x1 << 0) /**< \brief (DMAC_CHSR) */
-#define DMAC_CHSR_ENA1 (0x1 << 1) /**< \brief (DMAC_CHSR) */
-#define DMAC_CHSR_ENA2 (0x1 << 2) /**< \brief (DMAC_CHSR) */
-#define DMAC_CHSR_ENA3 (0x1 << 3) /**< \brief (DMAC_CHSR) */
-#define DMAC_CHSR_SUSP0 (0x1 << 8) /**< \brief (DMAC_CHSR) */
-#define DMAC_CHSR_SUSP1 (0x1 << 9) /**< \brief (DMAC_CHSR) */
-#define DMAC_CHSR_SUSP2 (0x1 << 10) /**< \brief (DMAC_CHSR) */
-#define DMAC_CHSR_SUSP3 (0x1 << 11) /**< \brief (DMAC_CHSR) */
-#define DMAC_CHSR_EMPT0 (0x1 << 16) /**< \brief (DMAC_CHSR) */
-#define DMAC_CHSR_EMPT1 (0x1 << 17) /**< \brief (DMAC_CHSR) */
-#define DMAC_CHSR_EMPT2 (0x1 << 18) /**< \brief (DMAC_CHSR) */
-#define DMAC_CHSR_EMPT3 (0x1 << 19) /**< \brief (DMAC_CHSR) */
-#define DMAC_CHSR_STAL0 (0x1 << 24) /**< \brief (DMAC_CHSR) */
-#define DMAC_CHSR_STAL1 (0x1 << 25) /**< \brief (DMAC_CHSR) */
-#define DMAC_CHSR_STAL2 (0x1 << 26) /**< \brief (DMAC_CHSR) */
-#define DMAC_CHSR_STAL3 (0x1 << 27) /**< \brief (DMAC_CHSR) */
-/* -------- DMAC_SADDR0 : (DMAC Offset: 0x3C) DMAC Channel Source Address Register (ch_num = 0) -------- */
-#define DMAC_SADDR0_SADDRx (0xffffffff << 0) /**< \brief (DMAC_SADDR0) */
-/* -------- DMAC_DADDR0 : (DMAC Offset: 0x40) DMAC Channel Destination Address Register (ch_num = 0) -------- */
-#define DMAC_DADDR0_DADDRx (0xffffffff << 0) /**< \brief (DMAC_DADDR0) */
-/* -------- DMAC_DSCR0 : (DMAC Offset: 0x44) DMAC Channel Descriptor Address Register (ch_num = 0) -------- */
-#define DMAC_DSCR0_DSCRx (0x3fffffff << 2) /**< \brief (DMAC_DSCR0) */
-/* -------- DMAC_CTRLA0 : (DMAC Offset: 0x48) DMAC Channel Control A Register (ch_num = 0) -------- */
-#define DMAC_CTRLA0_BTSIZE (0xfff << 0) /**< \brief (DMAC_CTRLA0) */
-#define DMAC_CTRLA0_SCSIZE (0x1 << 16) /**< \brief (DMAC_CTRLA0) */
-#define DMAC_CTRLA0_DCSIZE (0x1 << 20) /**< \brief (DMAC_CTRLA0) */
-#define DMAC_CTRLA0_SRC_WIDTH (0x3 << 24) /**< \brief (DMAC_CTRLA0) */
-#define DMAC_CTRLA0_DST_WIDTH (0x3 << 28) /**< \brief (DMAC_CTRLA0) */
-#define DMAC_CTRLA0_DONE (0x1 << 31) /**< \brief (DMAC_CTRLA0) */
-/* -------- DMAC_CTRLB0 : (DMAC Offset: 0x4C) DMAC Channel Control B Register (ch_num = 0) -------- */
-#define DMAC_CTRLB0_SRC_DSCR (0x1 << 16) /**< \brief (DMAC_CTRLB0) */
-#define DMAC_CTRLB0_DST_DSCR (0x1 << 20) /**< \brief (DMAC_CTRLB0) */
-#define DMAC_CTRLB0_FC (0x3 << 21) /**< \brief (DMAC_CTRLB0) */
-#define DMAC_CTRLB0_SRC_INCR (0x3 << 24) /**< \brief (DMAC_CTRLB0) */
-#define DMAC_CTRLB0_DST_INCR (0x3 << 28) /**< \brief (DMAC_CTRLB0) */
-#define DMAC_CTRLB0_IEN (0x1 << 30) /**< \brief (DMAC_CTRLB0) */
-/* -------- DMAC_CFG0 : (DMAC Offset: 0x50) DMAC Channel Configuration Register (ch_num = 0) -------- */
-#define DMAC_CFG0_SRC_PER (0xf << 0) /**< \brief (DMAC_CFG0) */
-#define DMAC_CFG0_DST_PER (0xf << 4) /**< \brief (DMAC_CFG0) */
-#define DMAC_CFG0_SRC_H2SEL (0x1 << 9) /**< \brief (DMAC_CFG0) */
-#define DMAC_CFG0_DST_H2SEL (0x1 << 13) /**< \brief (DMAC_CFG0) */
-#define DMAC_CFG0_SOD (0x1 << 16) /**< \brief (DMAC_CFG0) */
-#define DMAC_CFG0_LOCK_IF (0x1 << 20) /**< \brief (DMAC_CFG0) */
-#define DMAC_CFG0_LOCK_B (0x1 << 21) /**< \brief (DMAC_CFG0) */
-#define DMAC_CFG0_LOCK_IF_L (0x1 << 22) /**< \brief (DMAC_CFG0) */
-#define DMAC_CFG0_AHB_PROT (0x7 << 24) /**< \brief (DMAC_CFG0) */
-#define DMAC_CFG0_FIFOCFG (0x3 << 28) /**< \brief (DMAC_CFG0) */
-/* -------- DMAC_SADDR1 : (DMAC Offset: 0x64) DMAC Channel Source Address Register (ch_num = 1) -------- */
-#define DMAC_SADDR1_SADDRx (0xffffffff << 0) /**< \brief (DMAC_SADDR1) */
-/* -------- DMAC_DADDR1 : (DMAC Offset: 0x68) DMAC Channel Destination Address Register (ch_num = 1) -------- */
-#define DMAC_DADDR1_DADDRx (0xffffffff << 0) /**< \brief (DMAC_DADDR1) */
-/* -------- DMAC_DSCR1 : (DMAC Offset: 0x6C) DMAC Channel Descriptor Address Register (ch_num = 1) -------- */
-#define DMAC_DSCR1_DSCRx (0x3fffffff << 2) /**< \brief (DMAC_DSCR1) */
-/* -------- DMAC_CTRLA1 : (DMAC Offset: 0x70) DMAC Channel Control A Register (ch_num = 1) -------- */
-#define DMAC_CTRLA1_BTSIZE (0xfff << 0) /**< \brief (DMAC_CTRLA1) */
-#define DMAC_CTRLA1_SCSIZE (0x1 << 16) /**< \brief (DMAC_CTRLA1) */
-#define DMAC_CTRLA1_DCSIZE (0x1 << 20) /**< \brief (DMAC_CTRLA1) */
-#define DMAC_CTRLA1_SRC_WIDTH (0x3 << 24) /**< \brief (DMAC_CTRLA1) */
-#define DMAC_CTRLA1_DST_WIDTH (0x3 << 28) /**< \brief (DMAC_CTRLA1) */
-#define DMAC_CTRLA1_DONE (0x1 << 31) /**< \brief (DMAC_CTRLA1) */
-/* -------- DMAC_CTRLB1 : (DMAC Offset: 0x74) DMAC Channel Control B Register (ch_num = 1) -------- */
-#define DMAC_CTRLB1_SRC_DSCR (0x1 << 16) /**< \brief (DMAC_CTRLB1) */
-#define DMAC_CTRLB1_DST_DSCR (0x1 << 20) /**< \brief (DMAC_CTRLB1) */
-#define DMAC_CTRLB1_FC (0x3 << 21) /**< \brief (DMAC_CTRLB1) */
-#define DMAC_CTRLB1_SRC_INCR (0x3 << 24) /**< \brief (DMAC_CTRLB1) */
-#define DMAC_CTRLB1_DST_INCR (0x3 << 28) /**< \brief (DMAC_CTRLB1) */
-#define DMAC_CTRLB1_IEN (0x1 << 30) /**< \brief (DMAC_CTRLB1) */
-/* -------- DMAC_CFG1 : (DMAC Offset: 0x78) DMAC Channel Configuration Register (ch_num = 1) -------- */
-#define DMAC_CFG1_SRC_PER (0xf << 0) /**< \brief (DMAC_CFG1) */
-#define DMAC_CFG1_DST_PER (0xf << 4) /**< \brief (DMAC_CFG1) */
-#define DMAC_CFG1_SRC_H2SEL (0x1 << 9) /**< \brief (DMAC_CFG1) */
-#define DMAC_CFG1_DST_H2SEL (0x1 << 13) /**< \brief (DMAC_CFG1) */
-#define DMAC_CFG1_SOD (0x1 << 16) /**< \brief (DMAC_CFG1) */
-#define DMAC_CFG1_LOCK_IF (0x1 << 20) /**< \brief (DMAC_CFG1) */
-#define DMAC_CFG1_LOCK_B (0x1 << 21) /**< \brief (DMAC_CFG1) */
-#define DMAC_CFG1_LOCK_IF_L (0x1 << 22) /**< \brief (DMAC_CFG1) */
-#define DMAC_CFG1_AHB_PROT (0x7 << 24) /**< \brief (DMAC_CFG1) */
-#define DMAC_CFG1_FIFOCFG (0x3 << 28) /**< \brief (DMAC_CFG1) */
-/* -------- DMAC_SADDR2 : (DMAC Offset: 0x8C) DMAC Channel Source Address Register (ch_num = 2) -------- */
-#define DMAC_SADDR2_SADDRx (0xffffffff << 0) /**< \brief (DMAC_SADDR2) */
-/* -------- DMAC_DADDR2 : (DMAC Offset: 0x90) DMAC Channel Destination Address Register (ch_num = 2) -------- */
-#define DMAC_DADDR2_DADDRx (0xffffffff << 0) /**< \brief (DMAC_DADDR2) */
-/* -------- DMAC_DSCR2 : (DMAC Offset: 0x94) DMAC Channel Descriptor Address Register (ch_num = 2) -------- */
-#define DMAC_DSCR2_DSCRx (0x3fffffff << 2) /**< \brief (DMAC_DSCR2) */
-/* -------- DMAC_CTRLA2 : (DMAC Offset: 0x98) DMAC Channel Control A Register (ch_num = 2) -------- */
-#define DMAC_CTRLA2_BTSIZE (0xfff << 0) /**< \brief (DMAC_CTRLA2) */
-#define DMAC_CTRLA2_SCSIZE (0x1 << 16) /**< \brief (DMAC_CTRLA2) */
-#define DMAC_CTRLA2_DCSIZE (0x1 << 20) /**< \brief (DMAC_CTRLA2) */
-#define DMAC_CTRLA2_SRC_WIDTH (0x3 << 24) /**< \brief (DMAC_CTRLA2) */
-#define DMAC_CTRLA2_DST_WIDTH (0x3 << 28) /**< \brief (DMAC_CTRLA2) */
-#define DMAC_CTRLA2_DONE (0x1 << 31) /**< \brief (DMAC_CTRLA2) */
-/* -------- DMAC_CTRLB2 : (DMAC Offset: 0x9C) DMAC Channel Control B Register (ch_num = 2) -------- */
-#define DMAC_CTRLB2_SRC_DSCR (0x1 << 16) /**< \brief (DMAC_CTRLB2) */
-#define DMAC_CTRLB2_DST_DSCR (0x1 << 20) /**< \brief (DMAC_CTRLB2) */
-#define DMAC_CTRLB2_FC (0x3 << 21) /**< \brief (DMAC_CTRLB2) */
-#define DMAC_CTRLB2_SRC_INCR (0x3 << 24) /**< \brief (DMAC_CTRLB2) */
-#define DMAC_CTRLB2_DST_INCR (0x3 << 28) /**< \brief (DMAC_CTRLB2) */
-#define DMAC_CTRLB2_IEN (0x1 << 30) /**< \brief (DMAC_CTRLB2) */
-/* -------- DMAC_CFG2 : (DMAC Offset: 0xA0) DMAC Channel Configuration Register (ch_num = 2) -------- */
-#define DMAC_CFG2_SRC_PER (0xf << 0) /**< \brief (DMAC_CFG2) */
-#define DMAC_CFG2_DST_PER (0xf << 4) /**< \brief (DMAC_CFG2) */
-#define DMAC_CFG2_SRC_H2SEL (0x1 << 9) /**< \brief (DMAC_CFG2) */
-#define DMAC_CFG2_DST_H2SEL (0x1 << 13) /**< \brief (DMAC_CFG2) */
-#define DMAC_CFG2_SOD (0x1 << 16) /**< \brief (DMAC_CFG2) */
-#define DMAC_CFG2_LOCK_IF (0x1 << 20) /**< \brief (DMAC_CFG2) */
-#define DMAC_CFG2_LOCK_B (0x1 << 21) /**< \brief (DMAC_CFG2) */
-#define DMAC_CFG2_LOCK_IF_L (0x1 << 22) /**< \brief (DMAC_CFG2) */
-#define DMAC_CFG2_AHB_PROT (0x7 << 24) /**< \brief (DMAC_CFG2) */
-#define DMAC_CFG2_FIFOCFG (0x3 << 28) /**< \brief (DMAC_CFG2) */
-/* -------- DMAC_SADDR3 : (DMAC Offset: 0xB4) DMAC Channel Source Address Register (ch_num = 3) -------- */
-#define DMAC_SADDR3_SADDRx (0xffffffff << 0) /**< \brief (DMAC_SADDR3) */
-/* -------- DMAC_DADDR3 : (DMAC Offset: 0xB8) DMAC Channel Destination Address Register (ch_num = 3) -------- */
-#define DMAC_DADDR3_DADDRx (0xffffffff << 0) /**< \brief (DMAC_DADDR3) */
-/* -------- DMAC_DSCR3 : (DMAC Offset: 0xBC) DMAC Channel Descriptor Address Register (ch_num = 3) -------- */
-#define DMAC_DSCR3_DSCRx (0x3fffffff << 2) /**< \brief (DMAC_DSCR3) */
-/* -------- DMAC_CTRLA3 : (DMAC Offset: 0xC0) DMAC Channel Control A Register (ch_num = 3) -------- */
-#define DMAC_CTRLA3_BTSIZE (0xfff << 0) /**< \brief (DMAC_CTRLA3) */
-#define DMAC_CTRLA3_SCSIZE (0x1 << 16) /**< \brief (DMAC_CTRLA3) */
-#define DMAC_CTRLA3_DCSIZE (0x1 << 20) /**< \brief (DMAC_CTRLA3) */
-#define DMAC_CTRLA3_SRC_WIDTH (0x3 << 24) /**< \brief (DMAC_CTRLA3) */
-#define DMAC_CTRLA3_DST_WIDTH (0x3 << 28) /**< \brief (DMAC_CTRLA3) */
-#define DMAC_CTRLA3_DONE (0x1 << 31) /**< \brief (DMAC_CTRLA3) */
-/* -------- DMAC_CTRLB3 : (DMAC Offset: 0xC4) DMAC Channel Control B Register (ch_num = 3) -------- */
-#define DMAC_CTRLB3_SRC_DSCR (0x1 << 16) /**< \brief (DMAC_CTRLB3) */
-#define DMAC_CTRLB3_DST_DSCR (0x1 << 20) /**< \brief (DMAC_CTRLB3) */
-#define DMAC_CTRLB3_FC (0x3 << 21) /**< \brief (DMAC_CTRLB3) */
-#define DMAC_CTRLB3_SRC_INCR (0x3 << 24) /**< \brief (DMAC_CTRLB3) */
-#define DMAC_CTRLB3_DST_INCR (0x3 << 28) /**< \brief (DMAC_CTRLB3) */
-#define DMAC_CTRLB3_IEN (0x1 << 30) /**< \brief (DMAC_CTRLB3) */
-/* -------- DMAC_CFG3 : (DMAC Offset: 0xC8) DMAC Channel Configuration Register (ch_num = 3) -------- */
-#define DMAC_CFG3_SRC_PER (0xf << 0) /**< \brief (DMAC_CFG3) */
-#define DMAC_CFG3_DST_PER (0xf << 4) /**< \brief (DMAC_CFG3) */
-#define DMAC_CFG3_SRC_H2SEL (0x1 << 9) /**< \brief (DMAC_CFG3) */
-#define DMAC_CFG3_DST_H2SEL (0x1 << 13) /**< \brief (DMAC_CFG3) */
-#define DMAC_CFG3_SOD (0x1 << 16) /**< \brief (DMAC_CFG3) */
-#define DMAC_CFG3_LOCK_IF (0x1 << 20) /**< \brief (DMAC_CFG3) */
-#define DMAC_CFG3_LOCK_B (0x1 << 21) /**< \brief (DMAC_CFG3) */
-#define DMAC_CFG3_LOCK_IF_L (0x1 << 22) /**< \brief (DMAC_CFG3) */
-#define DMAC_CFG3_AHB_PROT (0x7 << 24) /**< \brief (DMAC_CFG3) */
-#define DMAC_CFG3_FIFOCFG (0x3 << 28) /**< \brief (DMAC_CFG3) */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3U_EFC Embedded Flash Controller */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Efc hardware registers */
-typedef struct {
- RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */
- WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */
- RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */
- RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */
-} Efc;
-#endif /* __ASSEMBLY__ */
-/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
-#define EEFC_FMR_FRDY (0x1 << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */
-#define EEFC_FMR_FWS (0xf << 8) /**< \brief (EEFC_FMR) Flash Wait State */
-#define EEFC_FMR_FAM (0x1 << 24) /**< \brief (EEFC_FMR) Flash Access Mode */
-/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
-#define EEFC_FCR_FCMD (0xff << 0) /**< \brief (EEFC_FCR) Flash Command */
-#define EEFC_FCR_FARG (0xffff << 8) /**< \brief (EEFC_FCR) Flash Command Argument */
-#define EEFC_FCR_FKEY (0xff << 24) /**< \brief (EEFC_FCR) Flash Writing Protection Key */
-/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
-#define EEFC_FSR_FRDY (0x1 << 0) /**< \brief (EEFC_FSR) Flash Ready Status */
-#define EEFC_FSR_FCMDE (0x1 << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */
-#define EEFC_FSR_FLOCKE (0x1 << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */
-/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
-#define EEFC_FRR_FVALUE (0xffffffff << 0) /**< \brief (EEFC_FRR) Flash Result Value */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3U_GPBR General Purpose Backup Register */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Gpbr hardware registers */
-typedef struct {
- RwReg SYS_GPBR0; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register 0 */
- RwReg SYS_GPBR1; /**< \brief (Gpbr Offset: 0x4) General Purpose Backup Register 1 */
- RwReg SYS_GPBR2; /**< \brief (Gpbr Offset: 0x8) General Purpose Backup Register 2 */
- RwReg SYS_GPBR3; /**< \brief (Gpbr Offset: 0xC) General Purpose Backup Register 3 */
-} Gpbr;
-#endif /* __ASSEMBLY__ */
-/* -------- SYS_GPBR0 : (GPBR Offset: 0x0) General Purpose Backup Register 0 -------- */
-#define SYS_GPBR0_GPBR_VALUE0 (0xffffffff << 0) /**< \brief (SYS_GPBR0) Value of GPBR x */
-/* -------- SYS_GPBR1 : (GPBR Offset: 0x4) General Purpose Backup Register 1 -------- */
-#define SYS_GPBR1_GPBR_VALUE1 (0xffffffff << 0) /**< \brief (SYS_GPBR1) Value of GPBR x */
-/* -------- SYS_GPBR2 : (GPBR Offset: 0x8) General Purpose Backup Register 2 -------- */
-#define SYS_GPBR2_GPBR_VALUE2 (0xffffffff << 0) /**< \brief (SYS_GPBR2) Value of GPBR x */
-/* -------- SYS_GPBR3 : (GPBR Offset: 0xC) General Purpose Backup Register 3 -------- */
-#define SYS_GPBR3_GPBR_VALUE3 (0xffffffff << 0) /**< \brief (SYS_GPBR3) Value of GPBR x */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR MultiMedia Card Interface */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3U_HSMCI MultiMedia Card Interface */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Hsmci hardware registers */
-typedef struct {
- WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */
- RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */
- RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */
- RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */
- RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */
- WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */
- RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */
- RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */
- RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */
- RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */
- WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */
- RwReg Reserved1[2];
- RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */
- WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */
- WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */
- RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */
- RwReg HSMCI_DMA; /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */
- RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */
- RwReg Reserved2[35];
- RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */
- RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */
-} Hsmci;
-#endif /* __ASSEMBLY__ */
-/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */
-#define HSMCI_CR_MCIEN (0x1 << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */
-#define HSMCI_CR_HSMCIDIS (0x1 << 1) /**< \brief (HSMCI_CR) */
-#define HSMCI_CR_PWSEN (0x1 << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */
-#define HSMCI_CR_PWSDIS (0x1 << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */
-#define HSMCI_CR_SWRST (0x1 << 7) /**< \brief (HSMCI_CR) Software Reset */
-/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */
-#define HSMCI_MR_CLKDIV (0xff << 0) /**< \brief (HSMCI_MR) Clock Divider */
-#define HSMCI_MR_PWSDIV (0x7 << 8) /**< \brief (HSMCI_MR) Power Saving Divider */
-#define HSMCI_MR_RDPROOF (0x1 << 11) /**< \brief (HSMCI_MR) */
-#define HSMCI_MR_WRPROOF (0x1 << 12) /**< \brief (HSMCI_MR) */
-#define HSMCI_MR_FBYTE (0x1 << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */
-#define HSMCI_MR_PADV (0x1 << 14) /**< \brief (HSMCI_MR) Padding Value */
-#define HSMCI_MR_BLKLEN (0xffff << 16) /**< \brief (HSMCI_MR) Data Block Length */
-/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */
-#define HSMCI_DTOR_DTOCYC (0xf << 0) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */
-#define HSMCI_DTOR_DTOMUL (0x7 << 4) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */
-/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */
-#define HSMCI_SDCR_SDCSEL (0x3 << 0) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */
-#define HSMCI_SDCR_SDCBUS (0x3 << 6) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */
-/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */
-#define HSMCI_ARGR_ARG (0xffffffff << 0) /**< \brief (HSMCI_ARGR) Command Argument */
-/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */
-#define HSMCI_CMDR_CMDNB (0x3f << 0) /**< \brief (HSMCI_CMDR) Command Number */
-#define HSMCI_CMDR_RSPTYP (0x3 << 6) /**< \brief (HSMCI_CMDR) Response Type */
-#define HSMCI_CMDR_SPCMD (0x7 << 8) /**< \brief (HSMCI_CMDR) Special Command */
-#define HSMCI_CMDR_OPDCMD (0x1 << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */
-#define HSMCI_CMDR_MAXLAT (0x1 << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */
-#define HSMCI_CMDR_TRCMD (0x3 << 16) /**< \brief (HSMCI_CMDR) Transfer Command */
-#define HSMCI_CMDR_TRDIR (0x1 << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */
-#define HSMCI_CMDR_TRTYP (0x7 << 19) /**< \brief (HSMCI_CMDR) Transfer Type */
-#define HSMCI_CMDR_IOSPCMD (0x3 << 24) /**< \brief (HSMCI_CMDR) SDIO Special Command */
-#define HSMCI_CMDR_ATACS (0x1 << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */
-#define HSMCI_CMDR_BOOT_ACK (0x1 << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */
-/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */
-#define HSMCI_BLKR_BCNT (0xffff << 0) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */
-#define HSMCI_BLKR_BLKLEN (0xffff << 16) /**< \brief (HSMCI_BLKR) Data Block Length */
-/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */
-#define HSMCI_CSTOR_CSTOCYC (0xf << 0) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */
-#define HSMCI_CSTOR_CSTOMUL (0x7 << 4) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */
-/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */
-#define HSMCI_RSPR_RSP (0xffffffff << 0) /**< \brief (HSMCI_RSPR[4]) Response */
-/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */
-#define HSMCI_RDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_RDR) Data to Read */
-/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */
-#define HSMCI_TDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_TDR) Data to Write */
-/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */
-#define HSMCI_SR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_SR) Command Ready */
-#define HSMCI_SR_RXRDY (0x1 << 1) /**< \brief (HSMCI_SR) Receiver Ready */
-#define HSMCI_SR_TXRDY (0x1 << 2) /**< \brief (HSMCI_SR) Transmit Ready */
-#define HSMCI_SR_BLKE (0x1 << 3) /**< \brief (HSMCI_SR) Data Block Ended */
-#define HSMCI_SR_DTIP (0x1 << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */
-#define HSMCI_SR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */
-#define HSMCI_SR_MCI_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_SR) */
-#define HSMCI_SR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */
-#define HSMCI_SR_CSRCV (0x1 << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */
-#define HSMCI_SR_RINDE (0x1 << 16) /**< \brief (HSMCI_SR) Response Index Error */
-#define HSMCI_SR_RDIRE (0x1 << 17) /**< \brief (HSMCI_SR) Response Direction Error */
-#define HSMCI_SR_RCRCE (0x1 << 18) /**< \brief (HSMCI_SR) Response CRC Error */
-#define HSMCI_SR_RENDE (0x1 << 19) /**< \brief (HSMCI_SR) Response End Bit Error */
-#define HSMCI_SR_RTOE (0x1 << 20) /**< \brief (HSMCI_SR) Response Time-out Error */
-#define HSMCI_SR_DCRCE (0x1 << 21) /**< \brief (HSMCI_SR) Data CRC Error */
-#define HSMCI_SR_DTOE (0x1 << 22) /**< \brief (HSMCI_SR) Data Time-out Error */
-#define HSMCI_SR_CSTOE (0x1 << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */
-#define HSMCI_SR_BLKOVRE (0x1 << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error */
-#define HSMCI_SR_DMADONE (0x1 << 25) /**< \brief (HSMCI_SR) DMA Transfer done */
-#define HSMCI_SR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_SR) FIFO empty flag */
-#define HSMCI_SR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_SR) Transfer Done flag */
-#define HSMCI_SR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */
-#define HSMCI_SR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */
-#define HSMCI_SR_OVRE (0x1 << 30) /**< \brief (HSMCI_SR) Overrun */
-#define HSMCI_SR_UNRE (0x1 << 31) /**< \brief (HSMCI_SR) Underrun */
-/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */
-#define HSMCI_IER_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */
-#define HSMCI_IER_RXRDY (0x1 << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */
-#define HSMCI_IER_TXRDY (0x1 << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */
-#define HSMCI_IER_BLKE (0x1 << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */
-#define HSMCI_IER_DTIP (0x1 << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */
-#define HSMCI_IER_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */
-#define HSMCI_IER_MCI_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IER) */
-#define HSMCI_IER_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */
-#define HSMCI_IER_CSRCV (0x1 << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */
-#define HSMCI_IER_RINDE (0x1 << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */
-#define HSMCI_IER_RDIRE (0x1 << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */
-#define HSMCI_IER_RCRCE (0x1 << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */
-#define HSMCI_IER_RENDE (0x1 << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */
-#define HSMCI_IER_RTOE (0x1 << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */
-#define HSMCI_IER_DCRCE (0x1 << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */
-#define HSMCI_IER_DTOE (0x1 << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */
-#define HSMCI_IER_CSTOE (0x1 << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */
-#define HSMCI_IER_BLKOVRE (0x1 << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */
-#define HSMCI_IER_DMADONE (0x1 << 25) /**< \brief (HSMCI_IER) DMA Transfer completed Interrupt Enable */
-#define HSMCI_IER_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */
-#define HSMCI_IER_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */
-#define HSMCI_IER_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */
-#define HSMCI_IER_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */
-#define HSMCI_IER_OVRE (0x1 << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */
-#define HSMCI_IER_UNRE (0x1 << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */
-/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */
-#define HSMCI_IDR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */
-#define HSMCI_IDR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */
-#define HSMCI_IDR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */
-#define HSMCI_IDR_BLKE (0x1 << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */
-#define HSMCI_IDR_DTIP (0x1 << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */
-#define HSMCI_IDR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */
-#define HSMCI_IDR_MCI_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IDR) */
-#define HSMCI_IDR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */
-#define HSMCI_IDR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt disable */
-#define HSMCI_IDR_RINDE (0x1 << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */
-#define HSMCI_IDR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */
-#define HSMCI_IDR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */
-#define HSMCI_IDR_RENDE (0x1 << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */
-#define HSMCI_IDR_RTOE (0x1 << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */
-#define HSMCI_IDR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */
-#define HSMCI_IDR_DTOE (0x1 << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */
-#define HSMCI_IDR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */
-#define HSMCI_IDR_BLKOVRE (0x1 << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */
-#define HSMCI_IDR_DMADONE (0x1 << 25) /**< \brief (HSMCI_IDR) DMA Transfer completed Interrupt Disable */
-#define HSMCI_IDR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */
-#define HSMCI_IDR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */
-#define HSMCI_IDR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */
-#define HSMCI_IDR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */
-#define HSMCI_IDR_OVRE (0x1 << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */
-#define HSMCI_IDR_UNRE (0x1 << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */
-/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */
-#define HSMCI_IMR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */
-#define HSMCI_IMR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */
-#define HSMCI_IMR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */
-#define HSMCI_IMR_BLKE (0x1 << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */
-#define HSMCI_IMR_DTIP (0x1 << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */
-#define HSMCI_IMR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */
-#define HSMCI_IMR_MCI_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IMR) */
-#define HSMCI_IMR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */
-#define HSMCI_IMR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */
-#define HSMCI_IMR_RINDE (0x1 << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */
-#define HSMCI_IMR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */
-#define HSMCI_IMR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */
-#define HSMCI_IMR_RENDE (0x1 << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */
-#define HSMCI_IMR_RTOE (0x1 << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */
-#define HSMCI_IMR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */
-#define HSMCI_IMR_DTOE (0x1 << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */
-#define HSMCI_IMR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */
-#define HSMCI_IMR_BLKOVRE (0x1 << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */
-#define HSMCI_IMR_DMADONE (0x1 << 25) /**< \brief (HSMCI_IMR) DMA Transfer Completed Interrupt Mask */
-#define HSMCI_IMR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */
-#define HSMCI_IMR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */
-#define HSMCI_IMR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */
-#define HSMCI_IMR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */
-#define HSMCI_IMR_OVRE (0x1 << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */
-#define HSMCI_IMR_UNRE (0x1 << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */
-/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */
-#define HSMCI_DMA_OFFSET (0x3 << 0) /**< \brief (HSMCI_DMA) DMA Write Buffer Offset */
-#define HSMCI_DMA_CHKSIZE (0x1 << 4) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */
-#define HSMCI_DMA_DMAEN (0x1 << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */
-#define HSMCI_DMA_ROPT (0x1 << 12) /**< \brief (HSMCI_DMA) Read Optimization with padding */
-/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */
-#define HSMCI_CFG_FIFOMODE (0x1 << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */
-#define HSMCI_CFG_FERRCTRL (0x1 << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */
-#define HSMCI_CFG_HSMODE (0x1 << 8) /**< \brief (HSMCI_CFG) High Speed Mode */
-#define HSMCI_CFG_LSYNC (0x1 << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */
-/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */
-#define HSMCI_WPMR_WP_EN (0x1 << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */
-#define HSMCI_WPMR_WP_KEY (0xffffff << 8) /**< \brief (HSMCI_WPMR) Write Protection Key password */
-/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */
-#define HSMCI_WPSR_WP_VS (0xf << 0) /**< \brief (HSMCI_WPSR) */
-#define HSMCI_WPSR_WP_VSRC (0xffff << 8) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3U_MATRIX AHB Bus Matrix */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Matrix hardware registers */
-typedef struct {
- RwReg MATRIX_MCFG[5]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */
- RwReg Reserved1[11];
- RwReg MATRIX_SCFG[10]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */
- RwReg Reserved2[6];
- RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */
- RwReg Reserved3[1];
- RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */
- RwReg Reserved4[1];
- RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */
- RwReg Reserved5[1];
- RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */
- RwReg Reserved6[1];
- RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */
- RwReg Reserved7[1];
- RwReg MATRIX_PRAS5; /**< \brief (Matrix Offset: 0x00A8) Priority Register A for Slave 5 */
- RwReg Reserved8[1];
- RwReg MATRIX_PRAS6; /**< \brief (Matrix Offset: 0x00B0) Priority Register A for Slave 6 */
- RwReg Reserved9[1];
- RwReg MATRIX_PRAS7; /**< \brief (Matrix Offset: 0x00B8) Priority Register A for Slave 7 */
- RwReg Reserved10[1];
- RwReg MATRIX_PRAS8; /**< \brief (Matrix Offset: 0x00C0) Priority Register A for Slave 8 */
- RwReg Reserved11[1];
- RwReg MATRIX_PRAS9; /**< \brief (Matrix Offset: 0x00C8) Priority Register A for Slave 9 */
- RwReg Reserved12[13];
- RwReg MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */
-} Matrix;
-#endif /* __ASSEMBLY__ */
-/* -------- MATRIX_MCFG[5] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */
-#define MATRIX_MCFG_ULBT (0x7 << 0) /**< \brief (MATRIX_MCFG[5]) Undefined Length Burst Type */
-/* -------- MATRIX_SCFG[10] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
-#define MATRIX_SCFG_SLOT_CYCLE (0xff << 0) /**< \brief (MATRIX_SCFG[10]) Maximum Number of Allowed Cycles for a Burst */
-#define MATRIX_SCFG_DEFMSTR_TYPE (0x3 << 16) /**< \brief (MATRIX_SCFG[10]) Default Master Type */
-#define MATRIX_SCFG_FIXED_DEFMSTR (0x7 << 18) /**< \brief (MATRIX_SCFG[10]) Fixed Default Master */
-#define MATRIX_SCFG_ARBT (0x3 << 24) /**< \brief (MATRIX_SCFG[10]) Arbitration Type */
-/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
-#define MATRIX_PRAS0_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS0) Master 0 Priority */
-#define MATRIX_PRAS0_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS0) Master 1 Priority */
-#define MATRIX_PRAS0_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS0) Master 2 Priority */
-#define MATRIX_PRAS0_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS0) Master 3 Priority */
-#define MATRIX_PRAS0_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS0) Master 4 Priority */
-/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
-#define MATRIX_PRAS1_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS1) Master 0 Priority */
-#define MATRIX_PRAS1_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS1) Master 1 Priority */
-#define MATRIX_PRAS1_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS1) Master 2 Priority */
-#define MATRIX_PRAS1_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS1) Master 3 Priority */
-#define MATRIX_PRAS1_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS1) Master 4 Priority */
-/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
-#define MATRIX_PRAS2_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS2) Master 0 Priority */
-#define MATRIX_PRAS2_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS2) Master 1 Priority */
-#define MATRIX_PRAS2_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS2) Master 2 Priority */
-#define MATRIX_PRAS2_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS2) Master 3 Priority */
-#define MATRIX_PRAS2_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS2) Master 4 Priority */
-/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
-#define MATRIX_PRAS3_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS3) Master 0 Priority */
-#define MATRIX_PRAS3_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS3) Master 1 Priority */
-#define MATRIX_PRAS3_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS3) Master 2 Priority */
-#define MATRIX_PRAS3_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS3) Master 3 Priority */
-#define MATRIX_PRAS3_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS3) Master 4 Priority */
-/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */
-#define MATRIX_PRAS4_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS4) Master 0 Priority */
-#define MATRIX_PRAS4_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS4) Master 1 Priority */
-#define MATRIX_PRAS4_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS4) Master 2 Priority */
-#define MATRIX_PRAS4_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS4) Master 3 Priority */
-#define MATRIX_PRAS4_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS4) Master 4 Priority */
-/* -------- MATRIX_PRAS5 : (MATRIX Offset: 0x00A8) Priority Register A for Slave 5 -------- */
-#define MATRIX_PRAS5_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS5) Master 0 Priority */
-#define MATRIX_PRAS5_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS5) Master 1 Priority */
-#define MATRIX_PRAS5_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS5) Master 2 Priority */
-#define MATRIX_PRAS5_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS5) Master 3 Priority */
-#define MATRIX_PRAS5_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS5) Master 4 Priority */
-/* -------- MATRIX_PRAS6 : (MATRIX Offset: 0x00B0) Priority Register A for Slave 6 -------- */
-#define MATRIX_PRAS6_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS6) Master 0 Priority */
-#define MATRIX_PRAS6_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS6) Master 1 Priority */
-#define MATRIX_PRAS6_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS6) Master 2 Priority */
-#define MATRIX_PRAS6_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS6) Master 3 Priority */
-#define MATRIX_PRAS6_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS6) Master 4 Priority */
-/* -------- MATRIX_PRAS7 : (MATRIX Offset: 0x00B8) Priority Register A for Slave 7 -------- */
-#define MATRIX_PRAS7_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS7) Master 0 Priority */
-#define MATRIX_PRAS7_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS7) Master 1 Priority */
-#define MATRIX_PRAS7_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS7) Master 2 Priority */
-#define MATRIX_PRAS7_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS7) Master 3 Priority */
-#define MATRIX_PRAS7_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS7) Master 4 Priority */
-/* -------- MATRIX_PRAS8 : (MATRIX Offset: 0x00C0) Priority Register A for Slave 8 -------- */
-#define MATRIX_PRAS8_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS8) Master 0 Priority */
-#define MATRIX_PRAS8_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS8) Master 1 Priority */
-#define MATRIX_PRAS8_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS8) Master 2 Priority */
-#define MATRIX_PRAS8_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS8) Master 3 Priority */
-#define MATRIX_PRAS8_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS8) Master 4 Priority */
-/* -------- MATRIX_PRAS9 : (MATRIX Offset: 0x00C8) Priority Register A for Slave 9 -------- */
-#define MATRIX_PRAS9_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS9) Master 0 Priority */
-#define MATRIX_PRAS9_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS9) Master 1 Priority */
-#define MATRIX_PRAS9_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS9) Master 2 Priority */
-#define MATRIX_PRAS9_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS9) Master 3 Priority */
-#define MATRIX_PRAS9_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS9) Master 4 Priority */
-/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */
-#define MATRIX_MRCR_RCB0 (0x1 << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 0 */
-#define MATRIX_MRCR_RCB1 (0x1 << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 1 */
-#define MATRIX_MRCR_RCB2 (0x1 << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 2 */
-#define MATRIX_MRCR_RCB3 (0x1 << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 3 */
-#define MATRIX_MRCR_RCB4 (0x1 << 4) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 4 */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3U_PDC Peripheral DMA Controller */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Pdc hardware registers */
-typedef struct {
- RwReg Reserved1[64];
- RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x100) Receive Pointer Register */
- RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x104) Receive Counter Register */
- RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x108) Transmit Pointer Register */
- RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0x10C) Transmit Counter Register */
- RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x110) Receive Next Pointer Register */
- RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x114) Receive Next Counter Register */
- RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x118) Transmit Next Pointer Register */
- RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x11C) Transmit Next Counter Register */
- WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x120) Transfer Control Register */
- RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x124) Transfer Status Register */
-} Pdc;
-#endif /* __ASSEMBLY__ */
-/* -------- PERIPH_RPR : (PDC Offset: 0x100) Receive Pointer Register -------- */
-#define PERIPH_RPR_RXPTR (0xffffffff << 0) /**< \brief (PERIPH_RPR) Receive Pointer Register */
-/* -------- PERIPH_RCR : (PDC Offset: 0x104) Receive Counter Register -------- */
-#define PERIPH_RCR_RXCTR (0xffff << 0) /**< \brief (PERIPH_RCR) Receive Counter Register */
-/* -------- PERIPH_TPR : (PDC Offset: 0x108) Transmit Pointer Register -------- */
-#define PERIPH_TPR_TXPTR (0xffffffff << 0) /**< \brief (PERIPH_TPR) Transmit Counter Register */
-/* -------- PERIPH_TCR : (PDC Offset: 0x10C) Transmit Counter Register -------- */
-#define PERIPH_TCR_TXCTR (0xffff << 0) /**< \brief (PERIPH_TCR) Transmit Counter Register */
-/* -------- PERIPH_RNPR : (PDC Offset: 0x110) Receive Next Pointer Register -------- */
-#define PERIPH_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PERIPH_RNPR) Receive Next Pointer */
-/* -------- PERIPH_RNCR : (PDC Offset: 0x114) Receive Next Counter Register -------- */
-#define PERIPH_RNCR_RXNCTR (0xffff << 0) /**< \brief (PERIPH_RNCR) Receive Next Counter */
-/* -------- PERIPH_TNPR : (PDC Offset: 0x118) Transmit Next Pointer Register -------- */
-#define PERIPH_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */
-/* -------- PERIPH_TNCR : (PDC Offset: 0x11C) Transmit Next Counter Register -------- */
-#define PERIPH_TNCR_TXNCTR (0xffff << 0) /**< \brief (PERIPH_TNCR) Transmit Counter Next */
-/* -------- PERIPH_PTCR : (PDC Offset: 0x120) Transfer Control Register -------- */
-#define PERIPH_PTCR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */
-#define PERIPH_PTCR_RXTDIS (0x1 << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */
-#define PERIPH_PTCR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */
-#define PERIPH_PTCR_TXTDIS (0x1 << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */
-/* -------- PERIPH_PTSR : (PDC Offset: 0x124) Transfer Status Register -------- */
-#define PERIPH_PTSR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */
-#define PERIPH_PTSR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Parallel Input/Output */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3U_PIO Parallel Input/Output */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Pio hardware registers */
-typedef struct {
- WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */
- WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */
- RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */
- RwReg Reserved1[1];
- WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */
- WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */
- RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */
- RwReg Reserved2[1];
- WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */
- WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */
- RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */
- RwReg Reserved3[1];
- WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */
- WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */
- RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */
- RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */
- WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */
- WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */
- RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */
- RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */
- WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */
- WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */
- RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */
- RwReg Reserved4[1];
- WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */
- WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */
- RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */
- RwReg Reserved5[1];
- RwReg PIO_ABSR; /**< \brief (Pio Offset: 0x0070) Peripheral AB Select Register */
- RwReg Reserved6[3];
- WoReg PIO_SCIFSR; /**< \brief (Pio Offset: 0x0080) System Clock Glitch Input Filter Select Register */
- WoReg PIO_DIFSR; /**< \brief (Pio Offset: 0x0084) Debouncing Input Filter Select Register */
- RoReg PIO_IFDGSR; /**< \brief (Pio Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register */
- RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */
- RwReg Reserved7[4];
- WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */
- WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */
- RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */
- RwReg Reserved8[1];
- WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */
- WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */
- RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */
- RwReg Reserved9[1];
- WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */
- WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */
- RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */
- RwReg Reserved10[1];
- WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */
- WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */
- RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */
- RwReg Reserved11[1];
- RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */
- RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */
- RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */
-} Pio;
-#endif /* __ASSEMBLY__ */
-/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */
-#define PIO_PER_P0 (0x1 << 0) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P1 (0x1 << 1) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P2 (0x1 << 2) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P3 (0x1 << 3) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P4 (0x1 << 4) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P5 (0x1 << 5) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P6 (0x1 << 6) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P7 (0x1 << 7) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P8 (0x1 << 8) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P9 (0x1 << 9) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P10 (0x1 << 10) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P11 (0x1 << 11) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P12 (0x1 << 12) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P13 (0x1 << 13) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P14 (0x1 << 14) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P15 (0x1 << 15) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P16 (0x1 << 16) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P17 (0x1 << 17) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P18 (0x1 << 18) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P19 (0x1 << 19) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P20 (0x1 << 20) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P21 (0x1 << 21) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P22 (0x1 << 22) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P23 (0x1 << 23) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P24 (0x1 << 24) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P25 (0x1 << 25) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P26 (0x1 << 26) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P27 (0x1 << 27) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P28 (0x1 << 28) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P29 (0x1 << 29) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P30 (0x1 << 30) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P31 (0x1 << 31) /**< \brief (PIO_PER) PIO Enable */
-/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */
-#define PIO_PDR_P0 (0x1 << 0) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P1 (0x1 << 1) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P2 (0x1 << 2) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P3 (0x1 << 3) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P4 (0x1 << 4) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P5 (0x1 << 5) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P6 (0x1 << 6) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P7 (0x1 << 7) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P8 (0x1 << 8) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P9 (0x1 << 9) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P10 (0x1 << 10) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P11 (0x1 << 11) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P12 (0x1 << 12) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P13 (0x1 << 13) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P14 (0x1 << 14) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P15 (0x1 << 15) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P16 (0x1 << 16) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P17 (0x1 << 17) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P18 (0x1 << 18) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P19 (0x1 << 19) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P20 (0x1 << 20) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P21 (0x1 << 21) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P22 (0x1 << 22) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P23 (0x1 << 23) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P24 (0x1 << 24) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P25 (0x1 << 25) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P26 (0x1 << 26) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P27 (0x1 << 27) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P28 (0x1 << 28) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P29 (0x1 << 29) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P30 (0x1 << 30) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P31 (0x1 << 31) /**< \brief (PIO_PDR) PIO Disable */
-/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */
-#define PIO_PSR_P0 (0x1 << 0) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P1 (0x1 << 1) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P2 (0x1 << 2) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P3 (0x1 << 3) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P4 (0x1 << 4) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P5 (0x1 << 5) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P6 (0x1 << 6) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P7 (0x1 << 7) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P8 (0x1 << 8) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P9 (0x1 << 9) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P10 (0x1 << 10) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P11 (0x1 << 11) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P12 (0x1 << 12) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P13 (0x1 << 13) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P14 (0x1 << 14) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P15 (0x1 << 15) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P16 (0x1 << 16) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P17 (0x1 << 17) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P18 (0x1 << 18) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P19 (0x1 << 19) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P20 (0x1 << 20) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P21 (0x1 << 21) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P22 (0x1 << 22) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P23 (0x1 << 23) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P24 (0x1 << 24) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P25 (0x1 << 25) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P26 (0x1 << 26) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P27 (0x1 << 27) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P28 (0x1 << 28) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P29 (0x1 << 29) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P30 (0x1 << 30) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P31 (0x1 << 31) /**< \brief (PIO_PSR) PIO Status */
-/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */
-#define PIO_OER_P0 (0x1 << 0) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P1 (0x1 << 1) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P2 (0x1 << 2) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P3 (0x1 << 3) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P4 (0x1 << 4) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P5 (0x1 << 5) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P6 (0x1 << 6) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P7 (0x1 << 7) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P8 (0x1 << 8) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P9 (0x1 << 9) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P10 (0x1 << 10) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P11 (0x1 << 11) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P12 (0x1 << 12) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P13 (0x1 << 13) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P14 (0x1 << 14) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P15 (0x1 << 15) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P16 (0x1 << 16) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P17 (0x1 << 17) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P18 (0x1 << 18) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P19 (0x1 << 19) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P20 (0x1 << 20) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P21 (0x1 << 21) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P22 (0x1 << 22) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P23 (0x1 << 23) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P24 (0x1 << 24) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P25 (0x1 << 25) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P26 (0x1 << 26) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P27 (0x1 << 27) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P28 (0x1 << 28) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P29 (0x1 << 29) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P30 (0x1 << 30) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P31 (0x1 << 31) /**< \brief (PIO_OER) Output Enable */
-/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */
-#define PIO_ODR_P0 (0x1 << 0) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P1 (0x1 << 1) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P2 (0x1 << 2) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P3 (0x1 << 3) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P4 (0x1 << 4) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P5 (0x1 << 5) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P6 (0x1 << 6) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P7 (0x1 << 7) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P8 (0x1 << 8) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P9 (0x1 << 9) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P10 (0x1 << 10) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P11 (0x1 << 11) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P12 (0x1 << 12) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P13 (0x1 << 13) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P14 (0x1 << 14) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P15 (0x1 << 15) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P16 (0x1 << 16) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P17 (0x1 << 17) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P18 (0x1 << 18) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P19 (0x1 << 19) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P20 (0x1 << 20) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P21 (0x1 << 21) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P22 (0x1 << 22) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P23 (0x1 << 23) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P24 (0x1 << 24) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P25 (0x1 << 25) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P26 (0x1 << 26) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P27 (0x1 << 27) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P28 (0x1 << 28) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P29 (0x1 << 29) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P30 (0x1 << 30) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P31 (0x1 << 31) /**< \brief (PIO_ODR) Output Disable */
-/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */
-#define PIO_OSR_P0 (0x1 << 0) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P1 (0x1 << 1) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P2 (0x1 << 2) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P3 (0x1 << 3) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P4 (0x1 << 4) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P5 (0x1 << 5) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P6 (0x1 << 6) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P7 (0x1 << 7) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P8 (0x1 << 8) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P9 (0x1 << 9) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P10 (0x1 << 10) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P11 (0x1 << 11) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P12 (0x1 << 12) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P13 (0x1 << 13) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P14 (0x1 << 14) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P15 (0x1 << 15) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P16 (0x1 << 16) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P17 (0x1 << 17) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P18 (0x1 << 18) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P19 (0x1 << 19) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P20 (0x1 << 20) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P21 (0x1 << 21) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P22 (0x1 << 22) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P23 (0x1 << 23) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P24 (0x1 << 24) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P25 (0x1 << 25) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P26 (0x1 << 26) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P27 (0x1 << 27) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P28 (0x1 << 28) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P29 (0x1 << 29) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P30 (0x1 << 30) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P31 (0x1 << 31) /**< \brief (PIO_OSR) Output Status */
-/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */
-#define PIO_IFER_P0 (0x1 << 0) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P1 (0x1 << 1) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P2 (0x1 << 2) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P3 (0x1 << 3) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P4 (0x1 << 4) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P5 (0x1 << 5) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P6 (0x1 << 6) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P7 (0x1 << 7) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P8 (0x1 << 8) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P9 (0x1 << 9) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P10 (0x1 << 10) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P11 (0x1 << 11) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P12 (0x1 << 12) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P13 (0x1 << 13) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P14 (0x1 << 14) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P15 (0x1 << 15) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P16 (0x1 << 16) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P17 (0x1 << 17) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P18 (0x1 << 18) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P19 (0x1 << 19) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P20 (0x1 << 20) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P21 (0x1 << 21) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P22 (0x1 << 22) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P23 (0x1 << 23) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P24 (0x1 << 24) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P25 (0x1 << 25) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P26 (0x1 << 26) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P27 (0x1 << 27) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P28 (0x1 << 28) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P29 (0x1 << 29) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P30 (0x1 << 30) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P31 (0x1 << 31) /**< \brief (PIO_IFER) Input Filter Enable */
-/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */
-#define PIO_IFDR_P0 (0x1 << 0) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P1 (0x1 << 1) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P2 (0x1 << 2) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P3 (0x1 << 3) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P4 (0x1 << 4) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P5 (0x1 << 5) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P6 (0x1 << 6) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P7 (0x1 << 7) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P8 (0x1 << 8) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P9 (0x1 << 9) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P10 (0x1 << 10) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P11 (0x1 << 11) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P12 (0x1 << 12) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P13 (0x1 << 13) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P14 (0x1 << 14) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P15 (0x1 << 15) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P16 (0x1 << 16) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P17 (0x1 << 17) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P18 (0x1 << 18) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P19 (0x1 << 19) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P20 (0x1 << 20) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P21 (0x1 << 21) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P22 (0x1 << 22) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P23 (0x1 << 23) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P24 (0x1 << 24) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P25 (0x1 << 25) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P26 (0x1 << 26) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P27 (0x1 << 27) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P28 (0x1 << 28) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P29 (0x1 << 29) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P30 (0x1 << 30) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P31 (0x1 << 31) /**< \brief (PIO_IFDR) Input Filter Disable */
-/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */
-#define PIO_IFSR_P0 (0x1 << 0) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P1 (0x1 << 1) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P2 (0x1 << 2) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P3 (0x1 << 3) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P4 (0x1 << 4) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P5 (0x1 << 5) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P6 (0x1 << 6) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P7 (0x1 << 7) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P8 (0x1 << 8) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P9 (0x1 << 9) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P10 (0x1 << 10) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P11 (0x1 << 11) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P12 (0x1 << 12) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P13 (0x1 << 13) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P14 (0x1 << 14) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P15 (0x1 << 15) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P16 (0x1 << 16) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P17 (0x1 << 17) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P18 (0x1 << 18) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P19 (0x1 << 19) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P20 (0x1 << 20) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P21 (0x1 << 21) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P22 (0x1 << 22) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P23 (0x1 << 23) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P24 (0x1 << 24) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P25 (0x1 << 25) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P26 (0x1 << 26) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P27 (0x1 << 27) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P28 (0x1 << 28) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P29 (0x1 << 29) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P30 (0x1 << 30) /**< \brief (PIO_IFSR) Input Filer Status */
-#define PIO_IFSR_P31 (0x1 << 31) /**< \brief (PIO_IFSR) Input Filer Status */
-/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */
-#define PIO_SODR_P0 (0x1 << 0) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P1 (0x1 << 1) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P2 (0x1 << 2) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P3 (0x1 << 3) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P4 (0x1 << 4) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P5 (0x1 << 5) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P6 (0x1 << 6) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P7 (0x1 << 7) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P8 (0x1 << 8) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P9 (0x1 << 9) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P10 (0x1 << 10) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P11 (0x1 << 11) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P12 (0x1 << 12) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P13 (0x1 << 13) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P14 (0x1 << 14) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P15 (0x1 << 15) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P16 (0x1 << 16) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P17 (0x1 << 17) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P18 (0x1 << 18) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P19 (0x1 << 19) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P20 (0x1 << 20) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P21 (0x1 << 21) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P22 (0x1 << 22) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P23 (0x1 << 23) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P24 (0x1 << 24) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P25 (0x1 << 25) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P26 (0x1 << 26) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P27 (0x1 << 27) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P28 (0x1 << 28) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P29 (0x1 << 29) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P30 (0x1 << 30) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P31 (0x1 << 31) /**< \brief (PIO_SODR) Set Output Data */
-/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */
-#define PIO_CODR_P0 (0x1 << 0) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P1 (0x1 << 1) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P2 (0x1 << 2) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P3 (0x1 << 3) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P4 (0x1 << 4) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P5 (0x1 << 5) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P6 (0x1 << 6) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P7 (0x1 << 7) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P8 (0x1 << 8) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P9 (0x1 << 9) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P10 (0x1 << 10) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P11 (0x1 << 11) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P12 (0x1 << 12) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P13 (0x1 << 13) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P14 (0x1 << 14) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P15 (0x1 << 15) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P16 (0x1 << 16) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P17 (0x1 << 17) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P18 (0x1 << 18) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P19 (0x1 << 19) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P20 (0x1 << 20) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P21 (0x1 << 21) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P22 (0x1 << 22) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P23 (0x1 << 23) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P24 (0x1 << 24) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P25 (0x1 << 25) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P26 (0x1 << 26) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P27 (0x1 << 27) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P28 (0x1 << 28) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P29 (0x1 << 29) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P30 (0x1 << 30) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P31 (0x1 << 31) /**< \brief (PIO_CODR) Clear Output Data */
-/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */
-#define PIO_ODSR_P0 (0x1 << 0) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P1 (0x1 << 1) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P2 (0x1 << 2) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P3 (0x1 << 3) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P4 (0x1 << 4) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P5 (0x1 << 5) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P6 (0x1 << 6) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P7 (0x1 << 7) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P8 (0x1 << 8) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P9 (0x1 << 9) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P10 (0x1 << 10) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P11 (0x1 << 11) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P12 (0x1 << 12) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P13 (0x1 << 13) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P14 (0x1 << 14) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P15 (0x1 << 15) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P16 (0x1 << 16) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P17 (0x1 << 17) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P18 (0x1 << 18) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P19 (0x1 << 19) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P20 (0x1 << 20) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P21 (0x1 << 21) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P22 (0x1 << 22) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P23 (0x1 << 23) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P24 (0x1 << 24) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P25 (0x1 << 25) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P26 (0x1 << 26) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P27 (0x1 << 27) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P28 (0x1 << 28) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P29 (0x1 << 29) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P30 (0x1 << 30) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P31 (0x1 << 31) /**< \brief (PIO_ODSR) Output Data Status */
-/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */
-#define PIO_PDSR_P0 (0x1 << 0) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P1 (0x1 << 1) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P2 (0x1 << 2) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P3 (0x1 << 3) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P4 (0x1 << 4) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P5 (0x1 << 5) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P6 (0x1 << 6) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P7 (0x1 << 7) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P8 (0x1 << 8) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P9 (0x1 << 9) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P10 (0x1 << 10) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P11 (0x1 << 11) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P12 (0x1 << 12) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P13 (0x1 << 13) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P14 (0x1 << 14) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P15 (0x1 << 15) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P16 (0x1 << 16) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P17 (0x1 << 17) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P18 (0x1 << 18) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P19 (0x1 << 19) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P20 (0x1 << 20) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P21 (0x1 << 21) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P22 (0x1 << 22) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P23 (0x1 << 23) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P24 (0x1 << 24) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P25 (0x1 << 25) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P26 (0x1 << 26) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P27 (0x1 << 27) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P28 (0x1 << 28) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P29 (0x1 << 29) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P30 (0x1 << 30) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P31 (0x1 << 31) /**< \brief (PIO_PDSR) Output Data Status */
-/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */
-#define PIO_IER_P0 (0x1 << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P1 (0x1 << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P2 (0x1 << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P3 (0x1 << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P4 (0x1 << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P5 (0x1 << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P6 (0x1 << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P7 (0x1 << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P8 (0x1 << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P9 (0x1 << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P10 (0x1 << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P11 (0x1 << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P12 (0x1 << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P13 (0x1 << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P14 (0x1 << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P15 (0x1 << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P16 (0x1 << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P17 (0x1 << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P18 (0x1 << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P19 (0x1 << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P20 (0x1 << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P21 (0x1 << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P22 (0x1 << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P23 (0x1 << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P24 (0x1 << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P25 (0x1 << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P26 (0x1 << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P27 (0x1 << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P28 (0x1 << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P29 (0x1 << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P30 (0x1 << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P31 (0x1 << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */
-#define PIO_IDR_P0 (0x1 << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P1 (0x1 << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P2 (0x1 << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P3 (0x1 << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P4 (0x1 << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P5 (0x1 << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P6 (0x1 << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P7 (0x1 << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P8 (0x1 << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P9 (0x1 << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P10 (0x1 << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P11 (0x1 << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P12 (0x1 << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P13 (0x1 << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P14 (0x1 << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P15 (0x1 << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P16 (0x1 << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P17 (0x1 << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P18 (0x1 << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P19 (0x1 << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P20 (0x1 << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P21 (0x1 << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P22 (0x1 << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P23 (0x1 << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P24 (0x1 << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P25 (0x1 << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P26 (0x1 << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P27 (0x1 << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P28 (0x1 << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P29 (0x1 << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P30 (0x1 << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P31 (0x1 << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */
-#define PIO_IMR_P0 (0x1 << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P1 (0x1 << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P2 (0x1 << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P3 (0x1 << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P4 (0x1 << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P5 (0x1 << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P6 (0x1 << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P7 (0x1 << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P8 (0x1 << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P9 (0x1 << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P10 (0x1 << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P11 (0x1 << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P12 (0x1 << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P13 (0x1 << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P14 (0x1 << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P15 (0x1 << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P16 (0x1 << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P17 (0x1 << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P18 (0x1 << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P19 (0x1 << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P20 (0x1 << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P21 (0x1 << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P22 (0x1 << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P23 (0x1 << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P24 (0x1 << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P25 (0x1 << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P26 (0x1 << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P27 (0x1 << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P28 (0x1 << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P29 (0x1 << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P30 (0x1 << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P31 (0x1 << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */
-#define PIO_ISR_P0 (0x1 << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P1 (0x1 << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P2 (0x1 << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P3 (0x1 << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P4 (0x1 << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P5 (0x1 << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P6 (0x1 << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P7 (0x1 << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P8 (0x1 << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P9 (0x1 << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P10 (0x1 << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P11 (0x1 << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P12 (0x1 << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P13 (0x1 << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P14 (0x1 << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P15 (0x1 << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P16 (0x1 << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P17 (0x1 << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P18 (0x1 << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P19 (0x1 << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P20 (0x1 << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P21 (0x1 << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P22 (0x1 << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P23 (0x1 << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P24 (0x1 << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P25 (0x1 << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P26 (0x1 << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P27 (0x1 << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P28 (0x1 << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P29 (0x1 << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P30 (0x1 << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P31 (0x1 << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */
-#define PIO_MDER_P0 (0x1 << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P1 (0x1 << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P2 (0x1 << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P3 (0x1 << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P4 (0x1 << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P5 (0x1 << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P6 (0x1 << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P7 (0x1 << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P8 (0x1 << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P9 (0x1 << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P10 (0x1 << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P11 (0x1 << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P12 (0x1 << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P13 (0x1 << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P14 (0x1 << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P15 (0x1 << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P16 (0x1 << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P17 (0x1 << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P18 (0x1 << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P19 (0x1 << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P20 (0x1 << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P21 (0x1 << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P22 (0x1 << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P23 (0x1 << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P24 (0x1 << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P25 (0x1 << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P26 (0x1 << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P27 (0x1 << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P28 (0x1 << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P29 (0x1 << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P30 (0x1 << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */
-#define PIO_MDER_P31 (0x1 << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */
-/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */
-#define PIO_MDDR_P0 (0x1 << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P1 (0x1 << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P2 (0x1 << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P3 (0x1 << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P4 (0x1 << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P5 (0x1 << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P6 (0x1 << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P7 (0x1 << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P8 (0x1 << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P9 (0x1 << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P10 (0x1 << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P11 (0x1 << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P12 (0x1 << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P13 (0x1 << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P14 (0x1 << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P15 (0x1 << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P16 (0x1 << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P17 (0x1 << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P18 (0x1 << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P19 (0x1 << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P20 (0x1 << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P21 (0x1 << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P22 (0x1 << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P23 (0x1 << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P24 (0x1 << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P25 (0x1 << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P26 (0x1 << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P27 (0x1 << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P28 (0x1 << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P29 (0x1 << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P30 (0x1 << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-#define PIO_MDDR_P31 (0x1 << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */
-/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */
-#define PIO_MDSR_P0 (0x1 << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P1 (0x1 << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P2 (0x1 << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P3 (0x1 << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P4 (0x1 << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P5 (0x1 << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P6 (0x1 << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P7 (0x1 << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P8 (0x1 << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P9 (0x1 << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P10 (0x1 << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P11 (0x1 << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P12 (0x1 << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P13 (0x1 << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P14 (0x1 << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P15 (0x1 << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P16 (0x1 << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P17 (0x1 << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P18 (0x1 << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P19 (0x1 << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P20 (0x1 << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P21 (0x1 << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P22 (0x1 << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P23 (0x1 << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P24 (0x1 << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P25 (0x1 << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P26 (0x1 << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P27 (0x1 << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P28 (0x1 << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P29 (0x1 << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P30 (0x1 << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */
-#define PIO_MDSR_P31 (0x1 << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */
-/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */
-#define PIO_PUDR_P0 (0x1 << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P1 (0x1 << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P2 (0x1 << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P3 (0x1 << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P4 (0x1 << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P5 (0x1 << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P6 (0x1 << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P7 (0x1 << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P8 (0x1 << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P9 (0x1 << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P10 (0x1 << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P11 (0x1 << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P12 (0x1 << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P13 (0x1 << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P14 (0x1 << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P15 (0x1 << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P16 (0x1 << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P17 (0x1 << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P18 (0x1 << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P19 (0x1 << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P20 (0x1 << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P21 (0x1 << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P22 (0x1 << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P23 (0x1 << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P24 (0x1 << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P25 (0x1 << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P26 (0x1 << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P27 (0x1 << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P28 (0x1 << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P29 (0x1 << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P30 (0x1 << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */
-#define PIO_PUDR_P31 (0x1 << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */
-/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */
-#define PIO_PUER_P0 (0x1 << 0) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P1 (0x1 << 1) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P2 (0x1 << 2) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P3 (0x1 << 3) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P4 (0x1 << 4) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P5 (0x1 << 5) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P6 (0x1 << 6) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P7 (0x1 << 7) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P8 (0x1 << 8) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P9 (0x1 << 9) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P10 (0x1 << 10) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P11 (0x1 << 11) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P12 (0x1 << 12) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P13 (0x1 << 13) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P14 (0x1 << 14) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P15 (0x1 << 15) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P16 (0x1 << 16) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P17 (0x1 << 17) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P18 (0x1 << 18) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P19 (0x1 << 19) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P20 (0x1 << 20) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P21 (0x1 << 21) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P22 (0x1 << 22) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P23 (0x1 << 23) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P24 (0x1 << 24) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P25 (0x1 << 25) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P26 (0x1 << 26) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P27 (0x1 << 27) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P28 (0x1 << 28) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P29 (0x1 << 29) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P30 (0x1 << 30) /**< \brief (PIO_PUER) Pull Up Enable. */
-#define PIO_PUER_P31 (0x1 << 31) /**< \brief (PIO_PUER) Pull Up Enable. */
-/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */
-#define PIO_PUSR_P0 (0x1 << 0) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P1 (0x1 << 1) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P2 (0x1 << 2) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P3 (0x1 << 3) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P4 (0x1 << 4) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P5 (0x1 << 5) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P6 (0x1 << 6) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P7 (0x1 << 7) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P8 (0x1 << 8) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P9 (0x1 << 9) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P10 (0x1 << 10) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P11 (0x1 << 11) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P12 (0x1 << 12) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P13 (0x1 << 13) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P14 (0x1 << 14) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P15 (0x1 << 15) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P16 (0x1 << 16) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P17 (0x1 << 17) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P18 (0x1 << 18) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P19 (0x1 << 19) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P20 (0x1 << 20) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P21 (0x1 << 21) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P22 (0x1 << 22) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P23 (0x1 << 23) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P24 (0x1 << 24) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P25 (0x1 << 25) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P26 (0x1 << 26) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P27 (0x1 << 27) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P28 (0x1 << 28) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P29 (0x1 << 29) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P30 (0x1 << 30) /**< \brief (PIO_PUSR) Pull Up Status. */
-#define PIO_PUSR_P31 (0x1 << 31) /**< \brief (PIO_PUSR) Pull Up Status. */
-/* -------- PIO_ABSR : (PIO Offset: 0x0070) Peripheral AB Select Register -------- */
-#define PIO_ABSR_P0 (0x1 << 0) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P1 (0x1 << 1) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P2 (0x1 << 2) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P3 (0x1 << 3) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P4 (0x1 << 4) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P5 (0x1 << 5) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P6 (0x1 << 6) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P7 (0x1 << 7) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P8 (0x1 << 8) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P9 (0x1 << 9) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P10 (0x1 << 10) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P11 (0x1 << 11) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P12 (0x1 << 12) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P13 (0x1 << 13) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P14 (0x1 << 14) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P15 (0x1 << 15) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P16 (0x1 << 16) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P17 (0x1 << 17) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P18 (0x1 << 18) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P19 (0x1 << 19) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P20 (0x1 << 20) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P21 (0x1 << 21) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P22 (0x1 << 22) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P23 (0x1 << 23) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P24 (0x1 << 24) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P25 (0x1 << 25) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P26 (0x1 << 26) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P27 (0x1 << 27) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P28 (0x1 << 28) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P29 (0x1 << 29) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P30 (0x1 << 30) /**< \brief (PIO_ABSR) Peripheral A Select. */
-#define PIO_ABSR_P31 (0x1 << 31) /**< \brief (PIO_ABSR) Peripheral A Select. */
-/* -------- PIO_SCIFSR : (PIO Offset: 0x0080) System Clock Glitch Input Filter Select Register -------- */
-#define PIO_SCIFSR_P0 (0x1 << 0) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P1 (0x1 << 1) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P2 (0x1 << 2) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P3 (0x1 << 3) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P4 (0x1 << 4) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P5 (0x1 << 5) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P6 (0x1 << 6) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P7 (0x1 << 7) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P8 (0x1 << 8) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P9 (0x1 << 9) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P10 (0x1 << 10) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P11 (0x1 << 11) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P12 (0x1 << 12) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P13 (0x1 << 13) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P14 (0x1 << 14) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P15 (0x1 << 15) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P16 (0x1 << 16) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P17 (0x1 << 17) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P18 (0x1 << 18) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P19 (0x1 << 19) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P20 (0x1 << 20) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P21 (0x1 << 21) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P22 (0x1 << 22) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P23 (0x1 << 23) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P24 (0x1 << 24) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P25 (0x1 << 25) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P26 (0x1 << 26) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P27 (0x1 << 27) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P28 (0x1 << 28) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P29 (0x1 << 29) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P30 (0x1 << 30) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-#define PIO_SCIFSR_P31 (0x1 << 31) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
-/* -------- PIO_DIFSR : (PIO Offset: 0x0084) Debouncing Input Filter Select Register -------- */
-#define PIO_DIFSR_P0 (0x1 << 0) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P1 (0x1 << 1) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P2 (0x1 << 2) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P3 (0x1 << 3) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P4 (0x1 << 4) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P5 (0x1 << 5) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P6 (0x1 << 6) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P7 (0x1 << 7) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P8 (0x1 << 8) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P9 (0x1 << 9) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P10 (0x1 << 10) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P11 (0x1 << 11) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P12 (0x1 << 12) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P13 (0x1 << 13) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P14 (0x1 << 14) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P15 (0x1 << 15) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P16 (0x1 << 16) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P17 (0x1 << 17) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P18 (0x1 << 18) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P19 (0x1 << 19) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P20 (0x1 << 20) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P21 (0x1 << 21) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P22 (0x1 << 22) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P23 (0x1 << 23) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P24 (0x1 << 24) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P25 (0x1 << 25) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P26 (0x1 << 26) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P27 (0x1 << 27) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P28 (0x1 << 28) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P29 (0x1 << 29) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P30 (0x1 << 30) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-#define PIO_DIFSR_P31 (0x1 << 31) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
-/* -------- PIO_IFDGSR : (PIO Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register -------- */
-#define PIO_IFDGSR_P0 (0x1 << 0) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P1 (0x1 << 1) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P2 (0x1 << 2) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P3 (0x1 << 3) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P4 (0x1 << 4) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P5 (0x1 << 5) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P6 (0x1 << 6) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P7 (0x1 << 7) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P8 (0x1 << 8) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P9 (0x1 << 9) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P10 (0x1 << 10) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P11 (0x1 << 11) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P12 (0x1 << 12) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P13 (0x1 << 13) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P14 (0x1 << 14) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P15 (0x1 << 15) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P16 (0x1 << 16) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P17 (0x1 << 17) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P18 (0x1 << 18) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P19 (0x1 << 19) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P20 (0x1 << 20) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P21 (0x1 << 21) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P22 (0x1 << 22) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P23 (0x1 << 23) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P24 (0x1 << 24) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P25 (0x1 << 25) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P26 (0x1 << 26) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P27 (0x1 << 27) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P28 (0x1 << 28) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P29 (0x1 << 29) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P30 (0x1 << 30) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFDGSR_P31 (0x1 << 31) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
-/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */
-#define PIO_SCDR_DIV0 (0x1 << 0) /**< \brief (PIO_SCDR) */
-#define PIO_SCDR_DIV1 (0x1 << 1) /**< \brief (PIO_SCDR) */
-#define PIO_SCDR_DIV2 (0x1 << 2) /**< \brief (PIO_SCDR) */
-#define PIO_SCDR_DIV3 (0x1 << 3) /**< \brief (PIO_SCDR) */
-#define PIO_SCDR_DIV4 (0x1 << 4) /**< \brief (PIO_SCDR) */
-#define PIO_SCDR_DIV5 (0x1 << 5) /**< \brief (PIO_SCDR) */
-#define PIO_SCDR_DIV6 (0x1 << 6) /**< \brief (PIO_SCDR) */
-#define PIO_SCDR_DIV7 (0x1 << 7) /**< \brief (PIO_SCDR) */
-#define PIO_SCDR_DIV8 (0x1 << 8) /**< \brief (PIO_SCDR) */
-#define PIO_SCDR_DIV9 (0x1 << 9) /**< \brief (PIO_SCDR) */
-#define PIO_SCDR_DIV10 (0x1 << 10) /**< \brief (PIO_SCDR) */
-#define PIO_SCDR_DIV11 (0x1 << 11) /**< \brief (PIO_SCDR) */
-#define PIO_SCDR_DIV12 (0x1 << 12) /**< \brief (PIO_SCDR) */
-#define PIO_SCDR_DIV13 (0x1 << 13) /**< \brief (PIO_SCDR) */
-/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */
-#define PIO_OWER_P0 (0x1 << 0) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P1 (0x1 << 1) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P2 (0x1 << 2) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P3 (0x1 << 3) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P4 (0x1 << 4) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P5 (0x1 << 5) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P6 (0x1 << 6) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P7 (0x1 << 7) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P8 (0x1 << 8) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P9 (0x1 << 9) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P10 (0x1 << 10) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P11 (0x1 << 11) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P12 (0x1 << 12) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P13 (0x1 << 13) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P14 (0x1 << 14) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P15 (0x1 << 15) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P16 (0x1 << 16) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P17 (0x1 << 17) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P18 (0x1 << 18) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P19 (0x1 << 19) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P20 (0x1 << 20) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P21 (0x1 << 21) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P22 (0x1 << 22) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P23 (0x1 << 23) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P24 (0x1 << 24) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P25 (0x1 << 25) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P26 (0x1 << 26) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P27 (0x1 << 27) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P28 (0x1 << 28) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P29 (0x1 << 29) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P30 (0x1 << 30) /**< \brief (PIO_OWER) Output Write Enable. */
-#define PIO_OWER_P31 (0x1 << 31) /**< \brief (PIO_OWER) Output Write Enable. */
-/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */
-#define PIO_OWDR_P0 (0x1 << 0) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P1 (0x1 << 1) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P2 (0x1 << 2) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P3 (0x1 << 3) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P4 (0x1 << 4) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P5 (0x1 << 5) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P6 (0x1 << 6) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P7 (0x1 << 7) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P8 (0x1 << 8) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P9 (0x1 << 9) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P10 (0x1 << 10) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P11 (0x1 << 11) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P12 (0x1 << 12) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P13 (0x1 << 13) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P14 (0x1 << 14) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P15 (0x1 << 15) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P16 (0x1 << 16) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P17 (0x1 << 17) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P18 (0x1 << 18) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P19 (0x1 << 19) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P20 (0x1 << 20) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P21 (0x1 << 21) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P22 (0x1 << 22) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P23 (0x1 << 23) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P24 (0x1 << 24) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P25 (0x1 << 25) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P26 (0x1 << 26) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P27 (0x1 << 27) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P28 (0x1 << 28) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P29 (0x1 << 29) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P30 (0x1 << 30) /**< \brief (PIO_OWDR) Output Write Disable. */
-#define PIO_OWDR_P31 (0x1 << 31) /**< \brief (PIO_OWDR) Output Write Disable. */
-/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */
-#define PIO_OWSR_P0 (0x1 << 0) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P1 (0x1 << 1) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P2 (0x1 << 2) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P3 (0x1 << 3) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P4 (0x1 << 4) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P5 (0x1 << 5) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P6 (0x1 << 6) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P7 (0x1 << 7) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P8 (0x1 << 8) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P9 (0x1 << 9) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P10 (0x1 << 10) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P11 (0x1 << 11) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P12 (0x1 << 12) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P13 (0x1 << 13) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P14 (0x1 << 14) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P15 (0x1 << 15) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P16 (0x1 << 16) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P17 (0x1 << 17) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P18 (0x1 << 18) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P19 (0x1 << 19) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P20 (0x1 << 20) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P21 (0x1 << 21) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P22 (0x1 << 22) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P23 (0x1 << 23) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P24 (0x1 << 24) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P25 (0x1 << 25) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P26 (0x1 << 26) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P27 (0x1 << 27) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P28 (0x1 << 28) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P29 (0x1 << 29) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P30 (0x1 << 30) /**< \brief (PIO_OWSR) Output Write Status. */
-#define PIO_OWSR_P31 (0x1 << 31) /**< \brief (PIO_OWSR) Output Write Status. */
-/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */
-#define PIO_AIMER_P0 (0x1 << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P1 (0x1 << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P2 (0x1 << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P3 (0x1 << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P4 (0x1 << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P5 (0x1 << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P6 (0x1 << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P7 (0x1 << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P8 (0x1 << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P9 (0x1 << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P10 (0x1 << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P11 (0x1 << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P12 (0x1 << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P13 (0x1 << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P14 (0x1 << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P15 (0x1 << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P16 (0x1 << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P17 (0x1 << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P18 (0x1 << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P19 (0x1 << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P20 (0x1 << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P21 (0x1 << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P22 (0x1 << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P23 (0x1 << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P24 (0x1 << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P25 (0x1 << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P26 (0x1 << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P27 (0x1 << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P28 (0x1 << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P29 (0x1 << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P30 (0x1 << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-#define PIO_AIMER_P31 (0x1 << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
-/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */
-#define PIO_AIMDR_P0 (0x1 << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P1 (0x1 << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P2 (0x1 << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P3 (0x1 << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P4 (0x1 << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P5 (0x1 << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P6 (0x1 << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P7 (0x1 << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P8 (0x1 << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P9 (0x1 << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P10 (0x1 << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P11 (0x1 << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P12 (0x1 << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P13 (0x1 << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P14 (0x1 << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P15 (0x1 << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P16 (0x1 << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P17 (0x1 << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P18 (0x1 << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P19 (0x1 << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P20 (0x1 << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P21 (0x1 << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P22 (0x1 << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P23 (0x1 << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P24 (0x1 << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P25 (0x1 << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P26 (0x1 << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P27 (0x1 << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P28 (0x1 << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P29 (0x1 << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P30 (0x1 << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-#define PIO_AIMDR_P31 (0x1 << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
-/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */
-#define PIO_AIMMR_P0 (0x1 << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P1 (0x1 << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P2 (0x1 << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P3 (0x1 << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P4 (0x1 << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P5 (0x1 << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P6 (0x1 << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P7 (0x1 << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P8 (0x1 << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P9 (0x1 << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P10 (0x1 << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P11 (0x1 << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P12 (0x1 << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P13 (0x1 << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P14 (0x1 << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P15 (0x1 << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P16 (0x1 << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P17 (0x1 << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P18 (0x1 << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P19 (0x1 << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P20 (0x1 << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P21 (0x1 << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P22 (0x1 << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P23 (0x1 << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P24 (0x1 << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P25 (0x1 << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P26 (0x1 << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P27 (0x1 << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P28 (0x1 << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P29 (0x1 << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P30 (0x1 << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-#define PIO_AIMMR_P31 (0x1 << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
-/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */
-#define PIO_ESR_P0 (0x1 << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P1 (0x1 << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P2 (0x1 << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P3 (0x1 << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P4 (0x1 << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P5 (0x1 << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P6 (0x1 << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P7 (0x1 << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P8 (0x1 << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P9 (0x1 << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P10 (0x1 << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P11 (0x1 << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P12 (0x1 << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P13 (0x1 << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P14 (0x1 << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P15 (0x1 << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P16 (0x1 << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P17 (0x1 << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P18 (0x1 << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P19 (0x1 << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P20 (0x1 << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P21 (0x1 << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P22 (0x1 << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P23 (0x1 << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P24 (0x1 << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P25 (0x1 << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P26 (0x1 << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P27 (0x1 << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P28 (0x1 << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P29 (0x1 << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P30 (0x1 << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-#define PIO_ESR_P31 (0x1 << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
-/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */
-#define PIO_LSR_P0 (0x1 << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P1 (0x1 << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P2 (0x1 << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P3 (0x1 << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P4 (0x1 << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P5 (0x1 << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P6 (0x1 << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P7 (0x1 << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P8 (0x1 << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P9 (0x1 << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P10 (0x1 << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P11 (0x1 << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P12 (0x1 << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P13 (0x1 << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P14 (0x1 << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P15 (0x1 << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P16 (0x1 << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P17 (0x1 << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P18 (0x1 << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P19 (0x1 << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P20 (0x1 << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P21 (0x1 << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P22 (0x1 << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P23 (0x1 << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P24 (0x1 << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P25 (0x1 << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P26 (0x1 << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P27 (0x1 << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P28 (0x1 << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P29 (0x1 << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P30 (0x1 << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-#define PIO_LSR_P31 (0x1 << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */
-/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */
-#define PIO_ELSR_P0 (0x1 << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P1 (0x1 << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P2 (0x1 << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P3 (0x1 << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P4 (0x1 << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P5 (0x1 << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P6 (0x1 << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P7 (0x1 << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P8 (0x1 << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P9 (0x1 << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P10 (0x1 << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P11 (0x1 << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P12 (0x1 << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P13 (0x1 << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P14 (0x1 << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P15 (0x1 << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P16 (0x1 << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P17 (0x1 << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P18 (0x1 << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P19 (0x1 << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P20 (0x1 << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P21 (0x1 << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P22 (0x1 << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P23 (0x1 << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P24 (0x1 << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P25 (0x1 << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P26 (0x1 << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P27 (0x1 << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P28 (0x1 << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P29 (0x1 << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P30 (0x1 << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-#define PIO_ELSR_P31 (0x1 << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
-/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */
-#define PIO_FELLSR_P0 (0x1 << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P1 (0x1 << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P2 (0x1 << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P3 (0x1 << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P4 (0x1 << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P5 (0x1 << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P6 (0x1 << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P7 (0x1 << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P8 (0x1 << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P9 (0x1 << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P10 (0x1 << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P11 (0x1 << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P12 (0x1 << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P13 (0x1 << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P14 (0x1 << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P15 (0x1 << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P16 (0x1 << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P17 (0x1 << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P18 (0x1 << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P19 (0x1 << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P20 (0x1 << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P21 (0x1 << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P22 (0x1 << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P23 (0x1 << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P24 (0x1 << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P25 (0x1 << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P26 (0x1 << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P27 (0x1 << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P28 (0x1 << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P29 (0x1 << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P30 (0x1 << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-#define PIO_FELLSR_P31 (0x1 << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
-/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */
-#define PIO_REHLSR_P0 (0x1 << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P1 (0x1 << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P2 (0x1 << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P3 (0x1 << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P4 (0x1 << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P5 (0x1 << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P6 (0x1 << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P7 (0x1 << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P8 (0x1 << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P9 (0x1 << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P10 (0x1 << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P11 (0x1 << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P12 (0x1 << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P13 (0x1 << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P14 (0x1 << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P15 (0x1 << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P16 (0x1 << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P17 (0x1 << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P18 (0x1 << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P19 (0x1 << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P20 (0x1 << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P21 (0x1 << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P22 (0x1 << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P23 (0x1 << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P24 (0x1 << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P25 (0x1 << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P26 (0x1 << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P27 (0x1 << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P28 (0x1 << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P29 (0x1 << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P30 (0x1 << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-#define PIO_REHLSR_P31 (0x1 << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
-/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */
-#define PIO_FRLHSR_P0 (0x1 << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P1 (0x1 << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P2 (0x1 << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P3 (0x1 << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P4 (0x1 << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P5 (0x1 << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P6 (0x1 << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P7 (0x1 << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P8 (0x1 << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P9 (0x1 << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P10 (0x1 << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P11 (0x1 << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P12 (0x1 << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P13 (0x1 << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P14 (0x1 << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P15 (0x1 << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P16 (0x1 << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P17 (0x1 << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P18 (0x1 << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P19 (0x1 << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P20 (0x1 << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P21 (0x1 << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P22 (0x1 << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P23 (0x1 << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P24 (0x1 << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P25 (0x1 << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P26 (0x1 << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P27 (0x1 << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P28 (0x1 << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P29 (0x1 << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P30 (0x1 << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-#define PIO_FRLHSR_P31 (0x1 << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
-/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */
-#define PIO_LOCKSR_P0 (0x1 << 0) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P1 (0x1 << 1) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P2 (0x1 << 2) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P3 (0x1 << 3) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P4 (0x1 << 4) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P5 (0x1 << 5) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P6 (0x1 << 6) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P7 (0x1 << 7) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P8 (0x1 << 8) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P9 (0x1 << 9) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P10 (0x1 << 10) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P11 (0x1 << 11) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P12 (0x1 << 12) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P13 (0x1 << 13) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P14 (0x1 << 14) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P15 (0x1 << 15) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P16 (0x1 << 16) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P17 (0x1 << 17) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P18 (0x1 << 18) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P19 (0x1 << 19) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P20 (0x1 << 20) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P21 (0x1 << 21) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P22 (0x1 << 22) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P23 (0x1 << 23) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P24 (0x1 << 24) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P25 (0x1 << 25) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P26 (0x1 << 26) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P27 (0x1 << 27) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P28 (0x1 << 28) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P29 (0x1 << 29) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P30 (0x1 << 30) /**< \brief (PIO_LOCKSR) Lock Status. */
-#define PIO_LOCKSR_P31 (0x1 << 31) /**< \brief (PIO_LOCKSR) Lock Status. */
-/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */
-#define PIO_WPMR_WPEN (0x1 << 0) /**< \brief (PIO_WPMR) Write Protect Enable */
-#define PIO_WPMR_WPKEY (0xffffff << 8) /**< \brief (PIO_WPMR) Write Protect KEY */
-/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */
-#define PIO_WPSR_WPVS (0x1 << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */
-#define PIO_WPSR_WPVSRC (0xffff << 8) /**< \brief (PIO_WPSR) Write Protect Violation Source */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Power Management Controller */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3U_PMC Power Management Controller */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Pmc hardware registers */
-typedef struct {
- WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */
- WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */
- RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */
- RwReg Reserved1[1];
- WoReg PMC_PCER; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register */
- WoReg PMC_PCDR; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register */
- RoReg PMC_PCSR; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register */
- RwReg CKGR_UCKR; /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */
- RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */
- RoReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */
- RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */
- RwReg Reserved2[1];
- RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */
- RwReg Reserved3[3];
- RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */
- RwReg Reserved4[5];
- WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */
- WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */
- RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */
- RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */
- RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */
- RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */
- WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */
-} Pmc;
-#endif /* __ASSEMBLY__ */
-/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
-#define PMC_SCER_PCK0 (0x1 << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */
-#define PMC_SCER_PCK1 (0x1 << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */
-#define PMC_SCER_PCK2 (0x1 << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */
-/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
-#define PMC_SCDR_PCK0 (0x1 << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */
-#define PMC_SCDR_PCK1 (0x1 << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */
-#define PMC_SCDR_PCK2 (0x1 << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */
-/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
-#define PMC_SCSR_PCK0 (0x1 << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */
-#define PMC_SCSR_PCK1 (0x1 << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */
-#define PMC_SCSR_PCK2 (0x1 << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */
-/* -------- PMC_PCER : (PMC Offset: 0x0010) Peripheral Clock Enable Register -------- */
-#define PMC_PCER_PID2 (0x1 << 2) /**< \brief (PMC_PCER) Peripheral Clock 2 Enable */
-#define PMC_PCER_PID3 (0x1 << 3) /**< \brief (PMC_PCER) Peripheral Clock 3 Enable */
-#define PMC_PCER_PID4 (0x1 << 4) /**< \brief (PMC_PCER) Peripheral Clock 4 Enable */
-#define PMC_PCER_PID5 (0x1 << 5) /**< \brief (PMC_PCER) Peripheral Clock 5 Enable */
-#define PMC_PCER_PID6 (0x1 << 6) /**< \brief (PMC_PCER) Peripheral Clock 6 Enable */
-#define PMC_PCER_PID7 (0x1 << 7) /**< \brief (PMC_PCER) Peripheral Clock 7 Enable */
-#define PMC_PCER_PID8 (0x1 << 8) /**< \brief (PMC_PCER) Peripheral Clock 8 Enable */
-#define PMC_PCER_PID9 (0x1 << 9) /**< \brief (PMC_PCER) Peripheral Clock 9 Enable */
-#define PMC_PCER_PID10 (0x1 << 10) /**< \brief (PMC_PCER) Peripheral Clock 10 Enable */
-#define PMC_PCER_PID11 (0x1 << 11) /**< \brief (PMC_PCER) Peripheral Clock 11 Enable */
-#define PMC_PCER_PID12 (0x1 << 12) /**< \brief (PMC_PCER) Peripheral Clock 12 Enable */
-#define PMC_PCER_PID13 (0x1 << 13) /**< \brief (PMC_PCER) Peripheral Clock 13 Enable */
-#define PMC_PCER_PID14 (0x1 << 14) /**< \brief (PMC_PCER) Peripheral Clock 14 Enable */
-#define PMC_PCER_PID15 (0x1 << 15) /**< \brief (PMC_PCER) Peripheral Clock 15 Enable */
-#define PMC_PCER_PID16 (0x1 << 16) /**< \brief (PMC_PCER) Peripheral Clock 16 Enable */
-#define PMC_PCER_PID17 (0x1 << 17) /**< \brief (PMC_PCER) Peripheral Clock 17 Enable */
-#define PMC_PCER_PID18 (0x1 << 18) /**< \brief (PMC_PCER) Peripheral Clock 18 Enable */
-#define PMC_PCER_PID19 (0x1 << 19) /**< \brief (PMC_PCER) Peripheral Clock 19 Enable */
-#define PMC_PCER_PID20 (0x1 << 20) /**< \brief (PMC_PCER) Peripheral Clock 20 Enable */
-#define PMC_PCER_PID21 (0x1 << 21) /**< \brief (PMC_PCER) Peripheral Clock 21 Enable */
-#define PMC_PCER_PID22 (0x1 << 22) /**< \brief (PMC_PCER) Peripheral Clock 22 Enable */
-#define PMC_PCER_PID23 (0x1 << 23) /**< \brief (PMC_PCER) Peripheral Clock 23 Enable */
-#define PMC_PCER_PID24 (0x1 << 24) /**< \brief (PMC_PCER) Peripheral Clock 24 Enable */
-#define PMC_PCER_PID25 (0x1 << 25) /**< \brief (PMC_PCER) Peripheral Clock 25 Enable */
-#define PMC_PCER_PID26 (0x1 << 26) /**< \brief (PMC_PCER) Peripheral Clock 26 Enable */
-#define PMC_PCER_PID27 (0x1 << 27) /**< \brief (PMC_PCER) Peripheral Clock 27 Enable */
-#define PMC_PCER_PID28 (0x1 << 28) /**< \brief (PMC_PCER) Peripheral Clock 28 Enable */
-#define PMC_PCER_PID29 (0x1 << 29) /**< \brief (PMC_PCER) Peripheral Clock 29 Enable */
-#define PMC_PCER_PID30 (0x1 << 30) /**< \brief (PMC_PCER) Peripheral Clock 30 Enable */
-#define PMC_PCER_PID31 (0x1 << 31) /**< \brief (PMC_PCER) Peripheral Clock 31 Enable */
-/* -------- PMC_PCDR : (PMC Offset: 0x0014) Peripheral Clock Disable Register -------- */
-#define PMC_PCDR_PID2 (0x1 << 2) /**< \brief (PMC_PCDR) Peripheral Clock 2 Disable */
-#define PMC_PCDR_PID3 (0x1 << 3) /**< \brief (PMC_PCDR) Peripheral Clock 3 Disable */
-#define PMC_PCDR_PID4 (0x1 << 4) /**< \brief (PMC_PCDR) Peripheral Clock 4 Disable */
-#define PMC_PCDR_PID5 (0x1 << 5) /**< \brief (PMC_PCDR) Peripheral Clock 5 Disable */
-#define PMC_PCDR_PID6 (0x1 << 6) /**< \brief (PMC_PCDR) Peripheral Clock 6 Disable */
-#define PMC_PCDR_PID7 (0x1 << 7) /**< \brief (PMC_PCDR) Peripheral Clock 7 Disable */
-#define PMC_PCDR_PID8 (0x1 << 8) /**< \brief (PMC_PCDR) Peripheral Clock 8 Disable */
-#define PMC_PCDR_PID9 (0x1 << 9) /**< \brief (PMC_PCDR) Peripheral Clock 9 Disable */
-#define PMC_PCDR_PID10 (0x1 << 10) /**< \brief (PMC_PCDR) Peripheral Clock 10 Disable */
-#define PMC_PCDR_PID11 (0x1 << 11) /**< \brief (PMC_PCDR) Peripheral Clock 11 Disable */
-#define PMC_PCDR_PID12 (0x1 << 12) /**< \brief (PMC_PCDR) Peripheral Clock 12 Disable */
-#define PMC_PCDR_PID13 (0x1 << 13) /**< \brief (PMC_PCDR) Peripheral Clock 13 Disable */
-#define PMC_PCDR_PID14 (0x1 << 14) /**< \brief (PMC_PCDR) Peripheral Clock 14 Disable */
-#define PMC_PCDR_PID15 (0x1 << 15) /**< \brief (PMC_PCDR) Peripheral Clock 15 Disable */
-#define PMC_PCDR_PID16 (0x1 << 16) /**< \brief (PMC_PCDR) Peripheral Clock 16 Disable */
-#define PMC_PCDR_PID17 (0x1 << 17) /**< \brief (PMC_PCDR) Peripheral Clock 17 Disable */
-#define PMC_PCDR_PID18 (0x1 << 18) /**< \brief (PMC_PCDR) Peripheral Clock 18 Disable */
-#define PMC_PCDR_PID19 (0x1 << 19) /**< \brief (PMC_PCDR) Peripheral Clock 19 Disable */
-#define PMC_PCDR_PID20 (0x1 << 20) /**< \brief (PMC_PCDR) Peripheral Clock 20 Disable */
-#define PMC_PCDR_PID21 (0x1 << 21) /**< \brief (PMC_PCDR) Peripheral Clock 21 Disable */
-#define PMC_PCDR_PID22 (0x1 << 22) /**< \brief (PMC_PCDR) Peripheral Clock 22 Disable */
-#define PMC_PCDR_PID23 (0x1 << 23) /**< \brief (PMC_PCDR) Peripheral Clock 23 Disable */
-#define PMC_PCDR_PID24 (0x1 << 24) /**< \brief (PMC_PCDR) Peripheral Clock 24 Disable */
-#define PMC_PCDR_PID25 (0x1 << 25) /**< \brief (PMC_PCDR) Peripheral Clock 25 Disable */
-#define PMC_PCDR_PID26 (0x1 << 26) /**< \brief (PMC_PCDR) Peripheral Clock 26 Disable */
-#define PMC_PCDR_PID27 (0x1 << 27) /**< \brief (PMC_PCDR) Peripheral Clock 27 Disable */
-#define PMC_PCDR_PID28 (0x1 << 28) /**< \brief (PMC_PCDR) Peripheral Clock 28 Disable */
-#define PMC_PCDR_PID29 (0x1 << 29) /**< \brief (PMC_PCDR) Peripheral Clock 29 Disable */
-#define PMC_PCDR_PID30 (0x1 << 30) /**< \brief (PMC_PCDR) Peripheral Clock 30 Disable */
-#define PMC_PCDR_PID31 (0x1 << 31) /**< \brief (PMC_PCDR) Peripheral Clock 31 Disable */
-/* -------- PMC_PCSR : (PMC Offset: 0x0018) Peripheral Clock Status Register -------- */
-#define PMC_PCSR_PID2 (0x1 << 2) /**< \brief (PMC_PCSR) Peripheral Clock 2 Status */
-#define PMC_PCSR_PID3 (0x1 << 3) /**< \brief (PMC_PCSR) Peripheral Clock 3 Status */
-#define PMC_PCSR_PID4 (0x1 << 4) /**< \brief (PMC_PCSR) Peripheral Clock 4 Status */
-#define PMC_PCSR_PID5 (0x1 << 5) /**< \brief (PMC_PCSR) Peripheral Clock 5 Status */
-#define PMC_PCSR_PID6 (0x1 << 6) /**< \brief (PMC_PCSR) Peripheral Clock 6 Status */
-#define PMC_PCSR_PID7 (0x1 << 7) /**< \brief (PMC_PCSR) Peripheral Clock 7 Status */
-#define PMC_PCSR_PID8 (0x1 << 8) /**< \brief (PMC_PCSR) Peripheral Clock 8 Status */
-#define PMC_PCSR_PID9 (0x1 << 9) /**< \brief (PMC_PCSR) Peripheral Clock 9 Status */
-#define PMC_PCSR_PID10 (0x1 << 10) /**< \brief (PMC_PCSR) Peripheral Clock 10 Status */
-#define PMC_PCSR_PID11 (0x1 << 11) /**< \brief (PMC_PCSR) Peripheral Clock 11 Status */
-#define PMC_PCSR_PID12 (0x1 << 12) /**< \brief (PMC_PCSR) Peripheral Clock 12 Status */
-#define PMC_PCSR_PID13 (0x1 << 13) /**< \brief (PMC_PCSR) Peripheral Clock 13 Status */
-#define PMC_PCSR_PID14 (0x1 << 14) /**< \brief (PMC_PCSR) Peripheral Clock 14 Status */
-#define PMC_PCSR_PID15 (0x1 << 15) /**< \brief (PMC_PCSR) Peripheral Clock 15 Status */
-#define PMC_PCSR_PID16 (0x1 << 16) /**< \brief (PMC_PCSR) Peripheral Clock 16 Status */
-#define PMC_PCSR_PID17 (0x1 << 17) /**< \brief (PMC_PCSR) Peripheral Clock 17 Status */
-#define PMC_PCSR_PID18 (0x1 << 18) /**< \brief (PMC_PCSR) Peripheral Clock 18 Status */
-#define PMC_PCSR_PID19 (0x1 << 19) /**< \brief (PMC_PCSR) Peripheral Clock 19 Status */
-#define PMC_PCSR_PID20 (0x1 << 20) /**< \brief (PMC_PCSR) Peripheral Clock 20 Status */
-#define PMC_PCSR_PID21 (0x1 << 21) /**< \brief (PMC_PCSR) Peripheral Clock 21 Status */
-#define PMC_PCSR_PID22 (0x1 << 22) /**< \brief (PMC_PCSR) Peripheral Clock 22 Status */
-#define PMC_PCSR_PID23 (0x1 << 23) /**< \brief (PMC_PCSR) Peripheral Clock 23 Status */
-#define PMC_PCSR_PID24 (0x1 << 24) /**< \brief (PMC_PCSR) Peripheral Clock 24 Status */
-#define PMC_PCSR_PID25 (0x1 << 25) /**< \brief (PMC_PCSR) Peripheral Clock 25 Status */
-#define PMC_PCSR_PID26 (0x1 << 26) /**< \brief (PMC_PCSR) Peripheral Clock 26 Status */
-#define PMC_PCSR_PID27 (0x1 << 27) /**< \brief (PMC_PCSR) Peripheral Clock 27 Status */
-#define PMC_PCSR_PID28 (0x1 << 28) /**< \brief (PMC_PCSR) Peripheral Clock 28 Status */
-#define PMC_PCSR_PID29 (0x1 << 29) /**< \brief (PMC_PCSR) Peripheral Clock 29 Status */
-#define PMC_PCSR_PID30 (0x1 << 30) /**< \brief (PMC_PCSR) Peripheral Clock 30 Status */
-#define PMC_PCSR_PID31 (0x1 << 31) /**< \brief (PMC_PCSR) Peripheral Clock 31 Status */
-/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */
-#define CKGR_UCKR_UPLLEN (0x1 << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */
-#define CKGR_UCKR_UPLLCOUNT (0xf << 20) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */
-/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
-#define CKGR_MOR_MOSCXTEN (0x1 << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */
-#define CKGR_MOR_MOSCXTBY (0x1 << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */
-#define CKGR_MOR_WAITMODE (0x1 << 2) /**< \brief (CKGR_MOR) Wait Mode Command */
-#define CKGR_MOR_MOSCRCEN (0x1 << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */
-#define CKGR_MOR_MOSCRCF (0x7 << 4) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */
-#define CKGR_MOR_MOSCXTST (0xff << 8) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */
-#define CKGR_MOR_KEY (0xff << 16) /**< \brief (CKGR_MOR) Password */
-#define CKGR_MOR_MOSCSEL (0x1 << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */
-#define CKGR_MOR_CFDEN (0x1 << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */
-/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
-#define CKGR_MCFR_MAINF (0xffff << 0) /**< \brief (CKGR_MCFR) Main Clock Frequency */
-#define CKGR_MCFR_MAINFRDY (0x1 << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */
-/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
-#define CKGR_PLLAR_DIVA (0xff << 0) /**< \brief (CKGR_PLLAR) Divider */
-#define CKGR_PLLAR_PLLACOUNT (0x3f << 8) /**< \brief (CKGR_PLLAR) PLLA Counter */
-#define CKGR_PLLAR_STMODE (0x3 << 14) /**< \brief (CKGR_PLLAR) Start Mode */
-#define CKGR_PLLAR_MULA (0x7ff << 16) /**< \brief (CKGR_PLLAR) PLLA Multiplier */
-#define CKGR_PLLAR_STUCKTO1 (0x1 << 29) /**< \brief (CKGR_PLLAR) */
-/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
-#define PMC_MCKR_CSS (0x3 << 0) /**< \brief (PMC_MCKR) Master Clock Source Selection */
-#define PMC_MCKR_CSS_SLOW_CLK (0x0 << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */
-#define PMC_MCKR_CSS_MAIN_CLK (0x1 << 0) /**< \brief (PMC_MCKR) Main Clock is selected */
-#define PMC_MCKR_CSS_PLLA_CLK (0x2 << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */
-#define PMC_MCKR_CSS_PLLB_CLK (0x3 << 0) /**< \brief (PMC_MCKR) UPLL Clock is selected */
-#define PMC_MCKR_PRES (0x7 << 4) /**< \brief (PMC_MCKR) Processor Clock Prescaler */
-#define PMC_MCKR_PRES_CLK (0x0 << 4) /**< \brief (PMC_MCKR) Selected clock */
-#define PMC_MCKR_PRES_CLK_2 (0x1 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */
-#define PMC_MCKR_PRES_CLK_4 (0x2 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */
-#define PMC_MCKR_PRES_CLK_8 (0x3 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */
-#define PMC_MCKR_PRES_CLK_16 (0x4 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */
-#define PMC_MCKR_PRES_CLK_32 (0x5 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */
-#define PMC_MCKR_PRES_CLK_64 (0x6 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */
-/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
-#define PMC_PCK_CSS (0x7 << 0) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */
-#define PMC_PCK_PRES (0x7 << 4) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */
-/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
-#define PMC_IER_MOSCXTS (0x1 << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */
-#define PMC_IER_LOCKA (0x1 << 1) /**< \brief (PMC_IER) PLL A Lock Interrupt Enable */
-#define PMC_IER_MCKRDY (0x1 << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */
-#define PMC_IER_LOCKU (0x1 << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */
-#define PMC_IER_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */
-#define PMC_IER_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */
-#define PMC_IER_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */
-#define PMC_IER_MOSCSELS (0x1 << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */
-#define PMC_IER_MOSCRCS (0x1 << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */
-#define PMC_IER_CFDEV (0x1 << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */
-/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
-#define PMC_IDR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */
-#define PMC_IDR_LOCKA (0x1 << 1) /**< \brief (PMC_IDR) PLL A Lock Interrupt Disable */
-#define PMC_IDR_MCKRDY (0x1 << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */
-#define PMC_IDR_LOCKU (0x1 << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */
-#define PMC_IDR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */
-#define PMC_IDR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */
-#define PMC_IDR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */
-#define PMC_IDR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */
-#define PMC_IDR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */
-#define PMC_IDR_CFDEV (0x1 << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */
-/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
-#define PMC_SR_MOSCXTS (0x1 << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */
-#define PMC_SR_LOCKA (0x1 << 1) /**< \brief (PMC_SR) PLL A Lock Status */
-#define PMC_SR_MCKRDY (0x1 << 3) /**< \brief (PMC_SR) Master Clock Status */
-#define PMC_SR_LOCKU (0x1 << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */
-#define PMC_SR_OSCSELS (0x1 << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */
-#define PMC_SR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */
-#define PMC_SR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */
-#define PMC_SR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */
-#define PMC_SR_MOSCSELS (0x1 << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */
-#define PMC_SR_MOSCRCS (0x1 << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */
-#define PMC_SR_CFDEV (0x1 << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */
-#define PMC_SR_CFDS (0x1 << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */
-#define PMC_SR_FOS (0x1 << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */
-/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
-#define PMC_IMR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */
-#define PMC_IMR_LOCKA (0x1 << 1) /**< \brief (PMC_IMR) PLL A Lock Interrupt Mask */
-#define PMC_IMR_MCKRDY (0x1 << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */
-#define PMC_IMR_LOCKU (0x1 << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */
-#define PMC_IMR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */
-#define PMC_IMR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */
-#define PMC_IMR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */
-#define PMC_IMR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */
-#define PMC_IMR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */
-#define PMC_IMR_CFDEV (0x1 << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */
-/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
-#define PMC_FSMR_FSTT0 (0x1 << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */
-#define PMC_FSMR_FSTT1 (0x1 << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */
-#define PMC_FSMR_FSTT2 (0x1 << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */
-#define PMC_FSMR_FSTT3 (0x1 << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */
-#define PMC_FSMR_FSTT4 (0x1 << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */
-#define PMC_FSMR_FSTT5 (0x1 << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */
-#define PMC_FSMR_FSTT6 (0x1 << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */
-#define PMC_FSMR_FSTT7 (0x1 << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */
-#define PMC_FSMR_FSTT8 (0x1 << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */
-#define PMC_FSMR_FSTT9 (0x1 << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */
-#define PMC_FSMR_FSTT10 (0x1 << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */
-#define PMC_FSMR_FSTT11 (0x1 << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */
-#define PMC_FSMR_FSTT12 (0x1 << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */
-#define PMC_FSMR_FSTT13 (0x1 << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */
-#define PMC_FSMR_FSTT14 (0x1 << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */
-#define PMC_FSMR_FSTT15 (0x1 << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */
-#define PMC_FSMR_RTTAL (0x1 << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */
-#define PMC_FSMR_RTCAL (0x1 << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */
-#define PMC_FSMR_USBAL (0x1 << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */
-#define PMC_FSMR_LPM (0x1 << 20) /**< \brief (PMC_FSMR) Low Power Mode */
-/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
-#define PMC_FSPR_FSTP0 (0x1 << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 0 */
-#define PMC_FSPR_FSTP1 (0x1 << 1) /**< \brief (PMC_FSPR) */
-#define PMC_FSPR_FSTP2 (0x1 << 2) /**< \brief (PMC_FSPR) */
-#define PMC_FSPR_FSTP3 (0x1 << 3) /**< \brief (PMC_FSPR) */
-#define PMC_FSPR_FSTP4 (0x1 << 4) /**< \brief (PMC_FSPR) */
-#define PMC_FSPR_FSTP5 (0x1 << 5) /**< \brief (PMC_FSPR) */
-#define PMC_FSPR_FSTP6 (0x1 << 6) /**< \brief (PMC_FSPR) */
-#define PMC_FSPR_FSTP7 (0x1 << 7) /**< \brief (PMC_FSPR) */
-#define PMC_FSPR_FSTP8 (0x1 << 8) /**< \brief (PMC_FSPR) */
-#define PMC_FSPR_FSTP9 (0x1 << 9) /**< \brief (PMC_FSPR) */
-#define PMC_FSPR_FSTP10 (0x1 << 10) /**< \brief (PMC_FSPR) */
-#define PMC_FSPR_FSTP11 (0x1 << 11) /**< \brief (PMC_FSPR) */
-#define PMC_FSPR_FSTP12 (0x1 << 12) /**< \brief (PMC_FSPR) */
-#define PMC_FSPR_FSTP13 (0x1 << 13) /**< \brief (PMC_FSPR) */
-#define PMC_FSPR_FSTP14 (0x1 << 14) /**< \brief (PMC_FSPR) */
-#define PMC_FSPR_FSTP15 (0x1 << 15) /**< \brief (PMC_FSPR) */
-/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
-#define PMC_FOCR_FOCLR (0x1 << 0) /**< \brief (PMC_FOCR) Fault Output Clear */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3U_PWM Pulse Width Modulation Controller */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief PwmCh_num hardware registers */
-typedef struct {
- RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */
- RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */
- RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */
- RwReg PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */
- RwReg PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */
- RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */
- RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */
- RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */
-} PwmCh_num;
-/** \brief Pwm hardware registers */
-typedef struct {
- RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */
- WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */
- WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */
- RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */
- WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */
- WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */
- RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */
- RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */
- RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */
- RwReg Reserved1[1];
- RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */
- RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */
- WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */
- WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */
- WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */
- RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */
- RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */
- RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */
- RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */
- WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */
- WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */
- WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */
- WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */
- RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */
- RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */
- WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */
- RwReg PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */
- RwReg PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */
- RwReg Reserved2[3];
- RwReg PWM_ELxMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */
- RwReg Reserved3[24];
- WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */
- RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */
- RwReg Reserved4[5];
- RwReg PWM_RPR; /**< \brief (Pwm Offset: 0x100) Receive Pointer Register */
- RwReg PWM_RCR; /**< \brief (Pwm Offset: 0x104) Receive Counter Register */
- RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */
- RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */
- RwReg PWM_RNPR; /**< \brief (Pwm Offset: 0x110) Receive Next Pointer Register */
- RwReg PWM_RNCR; /**< \brief (Pwm Offset: 0x114) Receive Next Counter Register */
- RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */
- RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */
- WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */
- RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */
- RwReg Reserved5[2];
- RwReg PWM_CMP0V; /**< \brief (Pwm Offset: 0x130) PWM Comparison 0 Value Register */
- WoReg PWM_CMP0VUPD; /**< \brief (Pwm Offset: 0x134) PWM Comparison 0 Value Update Register */
- RwReg PWM_CMP0M; /**< \brief (Pwm Offset: 0x138) PWM Comparison 0 Mode Register */
- WoReg PWM_CMP0MUPD; /**< \brief (Pwm Offset: 0x13C) PWM Comparison 0 Mode Update Register */
- RwReg PWM_CMP1V; /**< \brief (Pwm Offset: 0x140) PWM Comparison 1 Value Register */
- WoReg PWM_CMP1VUPD; /**< \brief (Pwm Offset: 0x144) PWM Comparison 1 Value Update Register */
- RwReg PWM_CMP1M; /**< \brief (Pwm Offset: 0x148) PWM Comparison 1 Mode Register */
- WoReg PWM_CMP1MUPD; /**< \brief (Pwm Offset: 0x14C) PWM Comparison 1 Mode Update Register */
- RwReg PWM_CMP2V; /**< \brief (Pwm Offset: 0x150) PWM Comparison 2 Value Register */
- WoReg PWM_CMP2VUPD; /**< \brief (Pwm Offset: 0x154) PWM Comparison 2 Value Update Register */
- RwReg PWM_CMP2M; /**< \brief (Pwm Offset: 0x158) PWM Comparison 2 Mode Register */
- WoReg PWM_CMP2MUPD; /**< \brief (Pwm Offset: 0x15C) PWM Comparison 2 Mode Update Register */
- RwReg PWM_CMP3V; /**< \brief (Pwm Offset: 0x160) PWM Comparison 3 Value Register */
- WoReg PWM_CMP3VUPD; /**< \brief (Pwm Offset: 0x164) PWM Comparison 3 Value Update Register */
- RwReg PWM_CMP3M; /**< \brief (Pwm Offset: 0x168) PWM Comparison 3 Mode Register */
- WoReg PWM_CMP3MUPD; /**< \brief (Pwm Offset: 0x16C) PWM Comparison 3 Mode Update Register */
- RwReg PWM_CMP4V; /**< \brief (Pwm Offset: 0x170) PWM Comparison 4 Value Register */
- WoReg PWM_CMP4VUPD; /**< \brief (Pwm Offset: 0x174) PWM Comparison 4 Value Update Register */
- RwReg PWM_CMP4M; /**< \brief (Pwm Offset: 0x178) PWM Comparison 4 Mode Register */
- WoReg PWM_CMP4MUPD; /**< \brief (Pwm Offset: 0x17C) PWM Comparison 4 Mode Update Register */
- RwReg PWM_CMP5V; /**< \brief (Pwm Offset: 0x180) PWM Comparison 5 Value Register */
- WoReg PWM_CMP5VUPD; /**< \brief (Pwm Offset: 0x184) PWM Comparison 5 Value Update Register */
- RwReg PWM_CMP5M; /**< \brief (Pwm Offset: 0x188) PWM Comparison 5 Mode Register */
- WoReg PWM_CMP5MUPD; /**< \brief (Pwm Offset: 0x18C) PWM Comparison 5 Mode Update Register */
- RwReg PWM_CMP6V; /**< \brief (Pwm Offset: 0x190) PWM Comparison 6 Value Register */
- WoReg PWM_CMP6VUPD; /**< \brief (Pwm Offset: 0x194) PWM Comparison 6 Value Update Register */
- RwReg PWM_CMP6M; /**< \brief (Pwm Offset: 0x198) PWM Comparison 6 Mode Register */
- WoReg PWM_CMP6MUPD; /**< \brief (Pwm Offset: 0x19C) PWM Comparison 6 Mode Update Register */
- RwReg PWM_CMP7V; /**< \brief (Pwm Offset: 0x1A0) PWM Comparison 7 Value Register */
- WoReg PWM_CMP7VUPD; /**< \brief (Pwm Offset: 0x1A4) PWM Comparison 7 Value Update Register */
- RwReg PWM_CMP7M; /**< \brief (Pwm Offset: 0x1A8) PWM Comparison 7 Mode Register */
- WoReg PWM_CMP7MUPD; /**< \brief (Pwm Offset: 0x1AC) PWM Comparison 7 Mode Update Register */
- RwReg Reserved6[20];
- PwmCh_num PWM_CH_NUM[4]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */
-} Pwm;
-#endif /* __ASSEMBLY__ */
-/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */
-#define PWM_CLK_DIVA (0xff << 0) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
-#define PWM_CLK_PREA (0xf << 8) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
-#define PWM_CLK_DIVB (0xff << 16) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
-#define PWM_CLK_PREB (0xf << 24) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
-/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
-#define PWM_ENA_CHID0 (0x1 << 0) /**< \brief (PWM_ENA) Channel ID */
-#define PWM_ENA_CHID1 (0x1 << 1) /**< \brief (PWM_ENA) Channel ID */
-#define PWM_ENA_CHID2 (0x1 << 2) /**< \brief (PWM_ENA) Channel ID */
-#define PWM_ENA_CHID3 (0x1 << 3) /**< \brief (PWM_ENA) Channel ID */
-/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
-#define PWM_DIS_CHID0 (0x1 << 0) /**< \brief (PWM_DIS) Channel ID */
-#define PWM_DIS_CHID1 (0x1 << 1) /**< \brief (PWM_DIS) Channel ID */
-#define PWM_DIS_CHID2 (0x1 << 2) /**< \brief (PWM_DIS) Channel ID */
-#define PWM_DIS_CHID3 (0x1 << 3) /**< \brief (PWM_DIS) Channel ID */
-/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
-#define PWM_SR_CHID0 (0x1 << 0) /**< \brief (PWM_SR) Channel ID */
-#define PWM_SR_CHID1 (0x1 << 1) /**< \brief (PWM_SR) Channel ID */
-#define PWM_SR_CHID2 (0x1 << 2) /**< \brief (PWM_SR) Channel ID */
-#define PWM_SR_CHID3 (0x1 << 3) /**< \brief (PWM_SR) Channel ID */
-/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */
-#define PWM_IER1_CHID0 (0x1 << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */
-#define PWM_IER1_CHID1 (0x1 << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */
-#define PWM_IER1_CHID2 (0x1 << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */
-#define PWM_IER1_CHID3 (0x1 << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */
-#define PWM_IER1_FCHID0 (0x1 << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */
-#define PWM_IER1_FCHID1 (0x1 << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */
-#define PWM_IER1_FCHID2 (0x1 << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */
-#define PWM_IER1_FCHID3 (0x1 << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */
-/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */
-#define PWM_IDR1_CHID0 (0x1 << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */
-#define PWM_IDR1_CHID1 (0x1 << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */
-#define PWM_IDR1_CHID2 (0x1 << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */
-#define PWM_IDR1_CHID3 (0x1 << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */
-#define PWM_IDR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */
-#define PWM_IDR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */
-#define PWM_IDR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */
-#define PWM_IDR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */
-/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */
-#define PWM_IMR1_CHID0 (0x1 << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */
-#define PWM_IMR1_CHID1 (0x1 << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */
-#define PWM_IMR1_CHID2 (0x1 << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */
-#define PWM_IMR1_CHID3 (0x1 << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */
-#define PWM_IMR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */
-#define PWM_IMR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */
-#define PWM_IMR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */
-#define PWM_IMR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */
-/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */
-#define PWM_ISR1_CHID0 (0x1 << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */
-#define PWM_ISR1_CHID1 (0x1 << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */
-#define PWM_ISR1_CHID2 (0x1 << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */
-#define PWM_ISR1_CHID3 (0x1 << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */
-#define PWM_ISR1_FCHID0 (0x1 << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */
-#define PWM_ISR1_FCHID1 (0x1 << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */
-#define PWM_ISR1_FCHID2 (0x1 << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */
-#define PWM_ISR1_FCHID3 (0x1 << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */
-/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */
-#define PWM_SCM_SYNC0 (0x1 << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */
-#define PWM_SCM_SYNC1 (0x1 << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */
-#define PWM_SCM_SYNC2 (0x1 << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */
-#define PWM_SCM_SYNC3 (0x1 << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */
-#define PWM_SCM_UPDM (0x3 << 16) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */
-#define PWM_SCM_UPDM_MODE0 (0x0 << 16) // (PWMC) Manual write of data and manual trigger of the update
-#define PWM_SCM_UPDM_MODE1 (0x1 << 16) // (PWMC) Manual write of data and automatic trigger of the update
-#define PWM_SCM_UPDM_MODE2 (0x2 << 16) // (PWMC) Automatic write of data and automatic trigger of the update
-#define PWM_SCM_PTRM (0x1 << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */
-#define PWM_SCM_PTRCS (0x7 << 21) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */
-/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */
-#define PWM_SCUC_UPDULOCK (0x1 << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */
-/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */
-#define PWM_SCUP_UPR (0xf << 0) /**< \brief (PWM_SCUP) Update Period */
-#define PWM_SCUP_UPRCNT (0xf << 4) /**< \brief (PWM_SCUP) Update Period Counter */
-/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */
-#define PWM_SCUPUPD_UPRUPD (0xf << 0) /**< \brief (PWM_SCUPUPD) Update Period Update */
-/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */
-#define PWM_IER2_WRDY (0x1 << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */
-#define PWM_IER2_ENDTX (0x1 << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */
-#define PWM_IER2_TXBUFE (0x1 << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */
-#define PWM_IER2_UNRE (0x1 << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */
-#define PWM_IER2_CMPM0 (0x1 << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */
-#define PWM_IER2_CMPM1 (0x1 << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */
-#define PWM_IER2_CMPM2 (0x1 << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */
-#define PWM_IER2_CMPM3 (0x1 << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */
-#define PWM_IER2_CMPM4 (0x1 << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */
-#define PWM_IER2_CMPM5 (0x1 << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */
-#define PWM_IER2_CMPM6 (0x1 << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */
-#define PWM_IER2_CMPM7 (0x1 << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */
-#define PWM_IER2_CMPU0 (0x1 << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */
-#define PWM_IER2_CMPU1 (0x1 << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */
-#define PWM_IER2_CMPU2 (0x1 << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */
-#define PWM_IER2_CMPU3 (0x1 << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */
-#define PWM_IER2_CMPU4 (0x1 << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */
-#define PWM_IER2_CMPU5 (0x1 << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */
-#define PWM_IER2_CMPU6 (0x1 << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */
-#define PWM_IER2_CMPU7 (0x1 << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */
-/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */
-#define PWM_IDR2_WRDY (0x1 << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */
-#define PWM_IDR2_ENDTX (0x1 << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */
-#define PWM_IDR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */
-#define PWM_IDR2_UNRE (0x1 << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */
-#define PWM_IDR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */
-#define PWM_IDR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */
-#define PWM_IDR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */
-#define PWM_IDR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */
-#define PWM_IDR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */
-#define PWM_IDR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */
-#define PWM_IDR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */
-#define PWM_IDR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */
-#define PWM_IDR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */
-#define PWM_IDR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */
-#define PWM_IDR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */
-#define PWM_IDR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */
-#define PWM_IDR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */
-#define PWM_IDR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */
-#define PWM_IDR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */
-#define PWM_IDR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */
-/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */
-#define PWM_IMR2_WRDY (0x1 << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */
-#define PWM_IMR2_ENDTX (0x1 << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */
-#define PWM_IMR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */
-#define PWM_IMR2_UNRE (0x1 << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */
-#define PWM_IMR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */
-#define PWM_IMR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */
-#define PWM_IMR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */
-#define PWM_IMR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */
-#define PWM_IMR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */
-#define PWM_IMR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */
-#define PWM_IMR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */
-#define PWM_IMR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */
-#define PWM_IMR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */
-#define PWM_IMR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */
-#define PWM_IMR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */
-#define PWM_IMR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */
-#define PWM_IMR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */
-#define PWM_IMR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */
-#define PWM_IMR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */
-#define PWM_IMR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */
-/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */
-#define PWM_ISR2_WRDY (0x1 << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */
-#define PWM_ISR2_ENDTX (0x1 << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */
-#define PWM_ISR2_TXBUFE (0x1 << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */
-#define PWM_ISR2_UNRE (0x1 << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */
-#define PWM_ISR2_CMPM0 (0x1 << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */
-#define PWM_ISR2_CMPM1 (0x1 << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */
-#define PWM_ISR2_CMPM2 (0x1 << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */
-#define PWM_ISR2_CMPM3 (0x1 << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */
-#define PWM_ISR2_CMPM4 (0x1 << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */
-#define PWM_ISR2_CMPM5 (0x1 << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */
-#define PWM_ISR2_CMPM6 (0x1 << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */
-#define PWM_ISR2_CMPM7 (0x1 << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */
-#define PWM_ISR2_CMPU0 (0x1 << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */
-#define PWM_ISR2_CMPU1 (0x1 << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */
-#define PWM_ISR2_CMPU2 (0x1 << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */
-#define PWM_ISR2_CMPU3 (0x1 << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */
-#define PWM_ISR2_CMPU4 (0x1 << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */
-#define PWM_ISR2_CMPU5 (0x1 << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */
-#define PWM_ISR2_CMPU6 (0x1 << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */
-#define PWM_ISR2_CMPU7 (0x1 << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */
-/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */
-#define PWM_OOV_OOVH0 (0x1 << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */
-#define PWM_OOV_OOVH1 (0x1 << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */
-#define PWM_OOV_OOVH2 (0x1 << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */
-#define PWM_OOV_OOVH3 (0x1 << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */
-#define PWM_OOV_OOVL0 (0x1 << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */
-#define PWM_OOV_OOVL1 (0x1 << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */
-#define PWM_OOV_OOVL2 (0x1 << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */
-#define PWM_OOV_OOVL3 (0x1 << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */
-/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */
-#define PWM_OS_OSH0 (0x1 << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */
-#define PWM_OS_OSH1 (0x1 << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */
-#define PWM_OS_OSH2 (0x1 << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */
-#define PWM_OS_OSH3 (0x1 << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */
-#define PWM_OS_OSL0 (0x1 << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */
-#define PWM_OS_OSL1 (0x1 << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */
-#define PWM_OS_OSL2 (0x1 << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */
-#define PWM_OS_OSL3 (0x1 << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */
-/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */
-#define PWM_OSS_OSSH0 (0x1 << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */
-#define PWM_OSS_OSSH1 (0x1 << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */
-#define PWM_OSS_OSSH2 (0x1 << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */
-#define PWM_OSS_OSSH3 (0x1 << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */
-#define PWM_OSS_OSSL0 (0x1 << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */
-#define PWM_OSS_OSSL1 (0x1 << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */
-#define PWM_OSS_OSSL2 (0x1 << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */
-#define PWM_OSS_OSSL3 (0x1 << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */
-/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */
-#define PWM_OSC_OSCH0 (0x1 << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */
-#define PWM_OSC_OSCH1 (0x1 << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */
-#define PWM_OSC_OSCH2 (0x1 << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */
-#define PWM_OSC_OSCH3 (0x1 << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */
-#define PWM_OSC_OSCL0 (0x1 << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */
-#define PWM_OSC_OSCL1 (0x1 << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */
-#define PWM_OSC_OSCL2 (0x1 << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */
-#define PWM_OSC_OSCL3 (0x1 << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */
-/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */
-#define PWM_OSSUPD_OSSUPH0 (0x1 << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */
-#define PWM_OSSUPD_OSSUPH1 (0x1 << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */
-#define PWM_OSSUPD_OSSUPH2 (0x1 << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */
-#define PWM_OSSUPD_OSSUPH3 (0x1 << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */
-#define PWM_OSSUPD_OSSUPL0 (0x1 << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */
-#define PWM_OSSUPD_OSSUPL1 (0x1 << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */
-#define PWM_OSSUPD_OSSUPL2 (0x1 << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */
-#define PWM_OSSUPD_OSSUPL3 (0x1 << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */
-/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */
-#define PWM_OSCUPD_OSCUPH0 (0x1 << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */
-#define PWM_OSCUPD_OSCUPH1 (0x1 << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */
-#define PWM_OSCUPD_OSCUPH2 (0x1 << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */
-#define PWM_OSCUPD_OSCUPH3 (0x1 << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */
-#define PWM_OSCUPD_OSCUPL0 (0x1 << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */
-#define PWM_OSCUPD_OSCUPL1 (0x1 << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */
-#define PWM_OSCUPD_OSCUPL2 (0x1 << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */
-#define PWM_OSCUPD_OSCUPL3 (0x1 << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */
-/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */
-#define PWM_FMR_FPOL0 (0x1 << 0) /**< \brief (PWM_FMR) Fault 0 Polarity */
-#define PWM_FMR_FPOL1 (0x1 << 1) /**< \brief (PWM_FMR) Fault 1 Polarity */
-#define PWM_FMR_FPOL2 (0x1 << 2) /**< \brief (PWM_FMR) Fault 2 Polarity */
-#define PWM_FMR_FPOL3 (0x1 << 3) /**< \brief (PWM_FMR) Fault 3 Polarity */
-#define PWM_FMR_FMOD0 (0x1 << 8) /**< \brief (PWM_FMR) Fault 0 Activation Mode */
-#define PWM_FMR_FMOD1 (0x1 << 9) /**< \brief (PWM_FMR) Fault 1 Activation Mode */
-#define PWM_FMR_FMOD2 (0x1 << 10) /**< \brief (PWM_FMR) Fault 2 Activation Mode */
-#define PWM_FMR_FMOD3 (0x1 << 11) /**< \brief (PWM_FMR) Fault 3 Activation Mode */
-#define PWM_FMR_FFIL0 (0x1 << 16) /**< \brief (PWM_FMR) Fault 0 Filtering */
-#define PWM_FMR_FFIL1 (0x1 << 17) /**< \brief (PWM_FMR) Fault 1 Filtering */
-#define PWM_FMR_FFIL2 (0x1 << 18) /**< \brief (PWM_FMR) Fault 2 Filtering */
-#define PWM_FMR_FFIL3 (0x1 << 19) /**< \brief (PWM_FMR) Fault 3 Filtering */
-/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */
-#define PWM_FSR_FIV0 (0x1 << 0) /**< \brief (PWM_FSR) Fault Input 0 Value */
-#define PWM_FSR_FIV1 (0x1 << 1) /**< \brief (PWM_FSR) Fault Input 1 Value */
-#define PWM_FSR_FIV2 (0x1 << 2) /**< \brief (PWM_FSR) Fault Input 2 Value */
-#define PWM_FSR_FIV3 (0x1 << 3) /**< \brief (PWM_FSR) Fault Input 3 Value */
-#define PWM_FSR_FS0 (0x1 << 8) /**< \brief (PWM_FSR) Fault 0 Status */
-#define PWM_FSR_FS1 (0x1 << 9) /**< \brief (PWM_FSR) Fault 1 Status */
-#define PWM_FSR_FS2 (0x1 << 10) /**< \brief (PWM_FSR) Fault 2 Status */
-#define PWM_FSR_FS3 (0x1 << 11) /**< \brief (PWM_FSR) Fault 3 Status */
-/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */
-#define PWM_FCR_FCLR0 (0x1 << 0) /**< \brief (PWM_FCR) Fault 0 Clear */
-#define PWM_FCR_FCLR1 (0x1 << 1) /**< \brief (PWM_FCR) Fault 1 Clear */
-#define PWM_FCR_FCLR2 (0x1 << 2) /**< \brief (PWM_FCR) Fault 2 Clear */
-#define PWM_FCR_FCLR3 (0x1 << 3) /**< \brief (PWM_FCR) Fault 3 Clear */
-/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */
-#define PWM_FPV_FPVH0 (0x1 << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */
-#define PWM_FPV_FPVH1 (0x1 << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */
-#define PWM_FPV_FPVH2 (0x1 << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */
-#define PWM_FPV_FPVH3 (0x1 << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */
-#define PWM_FPV_FPVL0 (0x1 << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */
-#define PWM_FPV_FPVL1 (0x1 << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */
-#define PWM_FPV_FPVL2 (0x1 << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */
-#define PWM_FPV_FPVL3 (0x1 << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */
-/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */
-#define PWM_FPE_FPE0 (0xff << 0) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 0 for channel x */
-#define PWM_FPE_FPE1 (0xff << 8) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 1 for channel x */
-#define PWM_FPE_FPE2 (0xff << 16) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 2 for channel x */
-#define PWM_FPE_FPE3 (0xff << 24) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 3 for channel x */
-/* -------- PWM_ELxMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */
-#define PWM_ELxMR_CSEL0 (0x1 << 0) /**< \brief (PWM_ELxMR[2]) Comparison 0 Selection */
-#define PWM_ELxMR_CSEL1 (0x1 << 1) /**< \brief (PWM_ELxMR[2]) Comparison 1 Selection */
-#define PWM_ELxMR_CSEL2 (0x1 << 2) /**< \brief (PWM_ELxMR[2]) Comparison 2 Selection */
-#define PWM_ELxMR_CSEL3 (0x1 << 3) /**< \brief (PWM_ELxMR[2]) Comparison 3 Selection */
-#define PWM_ELxMR_CSEL4 (0x1 << 4) /**< \brief (PWM_ELxMR[2]) Comparison 4 Selection */
-#define PWM_ELxMR_CSEL5 (0x1 << 5) /**< \brief (PWM_ELxMR[2]) Comparison 5 Selection */
-#define PWM_ELxMR_CSEL6 (0x1 << 6) /**< \brief (PWM_ELxMR[2]) Comparison 6 Selection */
-#define PWM_ELxMR_CSEL7 (0x1 << 7) /**< \brief (PWM_ELxMR[2]) Comparison 7 Selection */
-/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */
-#define PWM_WPCR_WPCMD (0x3 << 0) /**< \brief (PWM_WPCR) Write Protect Command */
-#define PWM_WPCR_WPRG0 (0x1 << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */
-#define PWM_WPCR_WPRG1 (0x1 << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */
-#define PWM_WPCR_WPRG2 (0x1 << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */
-#define PWM_WPCR_WPRG3 (0x1 << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */
-#define PWM_WPCR_WPRG4 (0x1 << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */
-#define PWM_WPCR_WPRG5 (0x1 << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */
-#define PWM_WPCR_WPKEY (0xffffff << 8) /**< \brief (PWM_WPCR) Write Protect Key */
-/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */
-#define PWM_WPSR_WPSWS0 (0x1 << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */
-#define PWM_WPSR_WPSWS1 (0x1 << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */
-#define PWM_WPSR_WPSWS2 (0x1 << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */
-#define PWM_WPSR_WPSWS3 (0x1 << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */
-#define PWM_WPSR_WPSWS4 (0x1 << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */
-#define PWM_WPSR_WPSWS5 (0x1 << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */
-#define PWM_WPSR_WPVS (0x1 << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */
-#define PWM_WPSR_WPHWS0 (0x1 << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */
-#define PWM_WPSR_WPHWS1 (0x1 << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */
-#define PWM_WPSR_WPHWS2 (0x1 << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */
-#define PWM_WPSR_WPHWS3 (0x1 << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */
-#define PWM_WPSR_WPHWS4 (0x1 << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */
-#define PWM_WPSR_WPHWS5 (0x1 << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */
-#define PWM_WPSR_WPVSRC (0xffff << 16) /**< \brief (PWM_WPSR) Write Protect Violation Source */
-/* -------- PWM_RPR : (PWM Offset: 0x100) Receive Pointer Register -------- */
-#define PWM_RPR_RXPTR (0xffffffff << 0) /**< \brief (PWM_RPR) Receive Pointer Register */
-/* -------- PWM_RCR : (PWM Offset: 0x104) Receive Counter Register -------- */
-#define PWM_RCR_RXCTR (0xffff << 0) /**< \brief (PWM_RCR) Receive Counter Register */
-/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */
-#define PWM_TPR_TXPTR (0xffffffff << 0) /**< \brief (PWM_TPR) Transmit Counter Register */
-/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */
-#define PWM_TCR_TXCTR (0xffff << 0) /**< \brief (PWM_TCR) Transmit Counter Register */
-/* -------- PWM_RNPR : (PWM Offset: 0x110) Receive Next Pointer Register -------- */
-#define PWM_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PWM_RNPR) Receive Next Pointer */
-/* -------- PWM_RNCR : (PWM Offset: 0x114) Receive Next Counter Register -------- */
-#define PWM_RNCR_RXNCTR (0xffff << 0) /**< \brief (PWM_RNCR) Receive Next Counter */
-/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */
-#define PWM_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PWM_TNPR) Transmit Next Pointer */
-/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */
-#define PWM_TNCR_TXNCTR (0xffff << 0) /**< \brief (PWM_TNCR) Transmit Counter Next */
-/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */
-#define PWM_PTCR_RXTEN (0x1 << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */
-#define PWM_PTCR_RXTDIS (0x1 << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */
-#define PWM_PTCR_TXTEN (0x1 << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */
-#define PWM_PTCR_TXTDIS (0x1 << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */
-/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */
-#define PWM_PTSR_RXTEN (0x1 << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */
-#define PWM_PTSR_TXTEN (0x1 << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */
-/* -------- PWM_CMP0V : (PWM Offset: 0x130) PWM Comparison 0 Value Register -------- */
-#define PWM_CMP0V_CV (0xffffff << 0) /**< \brief (PWM_CMP0V) Comparison x Value */
-#define PWM_CMP0V_CVM (0x1 << 24) /**< \brief (PWM_CMP0V) Comparison x Value Mode */
-/* -------- PWM_CMP0VUPD : (PWM Offset: 0x134) PWM Comparison 0 Value Update Register -------- */
-#define PWM_CMP0VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP0VUPD) Comparison x Value Update */
-#define PWM_CMP0VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP0VUPD) Comparison x Value Mode Update */
-/* -------- PWM_CMP0M : (PWM Offset: 0x138) PWM Comparison 0 Mode Register -------- */
-#define PWM_CMP0M_CEN (0x1 << 0) /**< \brief (PWM_CMP0M) Comparison x Enable */
-#define PWM_CMP0M_CTR (0xf << 4) /**< \brief (PWM_CMP0M) Comparison x Trigger */
-#define PWM_CMP0M_CPR (0xf << 8) /**< \brief (PWM_CMP0M) Comparison x Period */
-#define PWM_CMP0M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP0M) Comparison x Period Counter */
-#define PWM_CMP0M_CUPR (0xf << 16) /**< \brief (PWM_CMP0M) Comparison x Update Period */
-#define PWM_CMP0M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP0M) Comparison x Update Period Counter */
-/* -------- PWM_CMP0MUPD : (PWM Offset: 0x13C) PWM Comparison 0 Mode Update Register -------- */
-#define PWM_CMP0MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP0MUPD) Comparison x Enable Update */
-#define PWM_CMP0MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP0MUPD) Comparison x Trigger Update */
-#define PWM_CMP0MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP0MUPD) Comparison x Period Update */
-#define PWM_CMP0MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP0MUPD) Comparison x Update Period Update */
-/* -------- PWM_CMP1V : (PWM Offset: 0x140) PWM Comparison 1 Value Register -------- */
-#define PWM_CMP1V_CV (0xffffff << 0) /**< \brief (PWM_CMP1V) Comparison x Value */
-#define PWM_CMP1V_CVM (0x1 << 24) /**< \brief (PWM_CMP1V) Comparison x Value Mode */
-/* -------- PWM_CMP1VUPD : (PWM Offset: 0x144) PWM Comparison 1 Value Update Register -------- */
-#define PWM_CMP1VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP1VUPD) Comparison x Value Update */
-#define PWM_CMP1VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP1VUPD) Comparison x Value Mode Update */
-/* -------- PWM_CMP1M : (PWM Offset: 0x148) PWM Comparison 1 Mode Register -------- */
-#define PWM_CMP1M_CEN (0x1 << 0) /**< \brief (PWM_CMP1M) Comparison x Enable */
-#define PWM_CMP1M_CTR (0xf << 4) /**< \brief (PWM_CMP1M) Comparison x Trigger */
-#define PWM_CMP1M_CPR (0xf << 8) /**< \brief (PWM_CMP1M) Comparison x Period */
-#define PWM_CMP1M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP1M) Comparison x Period Counter */
-#define PWM_CMP1M_CUPR (0xf << 16) /**< \brief (PWM_CMP1M) Comparison x Update Period */
-#define PWM_CMP1M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP1M) Comparison x Update Period Counter */
-/* -------- PWM_CMP1MUPD : (PWM Offset: 0x14C) PWM Comparison 1 Mode Update Register -------- */
-#define PWM_CMP1MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP1MUPD) Comparison x Enable Update */
-#define PWM_CMP1MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP1MUPD) Comparison x Trigger Update */
-#define PWM_CMP1MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP1MUPD) Comparison x Period Update */
-#define PWM_CMP1MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP1MUPD) Comparison x Update Period Update */
-/* -------- PWM_CMP2V : (PWM Offset: 0x150) PWM Comparison 2 Value Register -------- */
-#define PWM_CMP2V_CV (0xffffff << 0) /**< \brief (PWM_CMP2V) Comparison x Value */
-#define PWM_CMP2V_CVM (0x1 << 24) /**< \brief (PWM_CMP2V) Comparison x Value Mode */
-/* -------- PWM_CMP2VUPD : (PWM Offset: 0x154) PWM Comparison 2 Value Update Register -------- */
-#define PWM_CMP2VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP2VUPD) Comparison x Value Update */
-#define PWM_CMP2VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP2VUPD) Comparison x Value Mode Update */
-/* -------- PWM_CMP2M : (PWM Offset: 0x158) PWM Comparison 2 Mode Register -------- */
-#define PWM_CMP2M_CEN (0x1 << 0) /**< \brief (PWM_CMP2M) Comparison x Enable */
-#define PWM_CMP2M_CTR (0xf << 4) /**< \brief (PWM_CMP2M) Comparison x Trigger */
-#define PWM_CMP2M_CPR (0xf << 8) /**< \brief (PWM_CMP2M) Comparison x Period */
-#define PWM_CMP2M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP2M) Comparison x Period Counter */
-#define PWM_CMP2M_CUPR (0xf << 16) /**< \brief (PWM_CMP2M) Comparison x Update Period */
-#define PWM_CMP2M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP2M) Comparison x Update Period Counter */
-/* -------- PWM_CMP2MUPD : (PWM Offset: 0x15C) PWM Comparison 2 Mode Update Register -------- */
-#define PWM_CMP2MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP2MUPD) Comparison x Enable Update */
-#define PWM_CMP2MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP2MUPD) Comparison x Trigger Update */
-#define PWM_CMP2MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP2MUPD) Comparison x Period Update */
-#define PWM_CMP2MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP2MUPD) Comparison x Update Period Update */
-/* -------- PWM_CMP3V : (PWM Offset: 0x160) PWM Comparison 3 Value Register -------- */
-#define PWM_CMP3V_CV (0xffffff << 0) /**< \brief (PWM_CMP3V) Comparison x Value */
-#define PWM_CMP3V_CVM (0x1 << 24) /**< \brief (PWM_CMP3V) Comparison x Value Mode */
-/* -------- PWM_CMP3VUPD : (PWM Offset: 0x164) PWM Comparison 3 Value Update Register -------- */
-#define PWM_CMP3VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP3VUPD) Comparison x Value Update */
-#define PWM_CMP3VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP3VUPD) Comparison x Value Mode Update */
-/* -------- PWM_CMP3M : (PWM Offset: 0x168) PWM Comparison 3 Mode Register -------- */
-#define PWM_CMP3M_CEN (0x1 << 0) /**< \brief (PWM_CMP3M) Comparison x Enable */
-#define PWM_CMP3M_CTR (0xf << 4) /**< \brief (PWM_CMP3M) Comparison x Trigger */
-#define PWM_CMP3M_CPR (0xf << 8) /**< \brief (PWM_CMP3M) Comparison x Period */
-#define PWM_CMP3M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP3M) Comparison x Period Counter */
-#define PWM_CMP3M_CUPR (0xf << 16) /**< \brief (PWM_CMP3M) Comparison x Update Period */
-#define PWM_CMP3M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP3M) Comparison x Update Period Counter */
-/* -------- PWM_CMP3MUPD : (PWM Offset: 0x16C) PWM Comparison 3 Mode Update Register -------- */
-#define PWM_CMP3MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP3MUPD) Comparison x Enable Update */
-#define PWM_CMP3MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP3MUPD) Comparison x Trigger Update */
-#define PWM_CMP3MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP3MUPD) Comparison x Period Update */
-#define PWM_CMP3MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP3MUPD) Comparison x Update Period Update */
-/* -------- PWM_CMP4V : (PWM Offset: 0x170) PWM Comparison 4 Value Register -------- */
-#define PWM_CMP4V_CV (0xffffff << 0) /**< \brief (PWM_CMP4V) Comparison x Value */
-#define PWM_CMP4V_CVM (0x1 << 24) /**< \brief (PWM_CMP4V) Comparison x Value Mode */
-/* -------- PWM_CMP4VUPD : (PWM Offset: 0x174) PWM Comparison 4 Value Update Register -------- */
-#define PWM_CMP4VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP4VUPD) Comparison x Value Update */
-#define PWM_CMP4VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP4VUPD) Comparison x Value Mode Update */
-/* -------- PWM_CMP4M : (PWM Offset: 0x178) PWM Comparison 4 Mode Register -------- */
-#define PWM_CMP4M_CEN (0x1 << 0) /**< \brief (PWM_CMP4M) Comparison x Enable */
-#define PWM_CMP4M_CTR (0xf << 4) /**< \brief (PWM_CMP4M) Comparison x Trigger */
-#define PWM_CMP4M_CPR (0xf << 8) /**< \brief (PWM_CMP4M) Comparison x Period */
-#define PWM_CMP4M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP4M) Comparison x Period Counter */
-#define PWM_CMP4M_CUPR (0xf << 16) /**< \brief (PWM_CMP4M) Comparison x Update Period */
-#define PWM_CMP4M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP4M) Comparison x Update Period Counter */
-/* -------- PWM_CMP4MUPD : (PWM Offset: 0x17C) PWM Comparison 4 Mode Update Register -------- */
-#define PWM_CMP4MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP4MUPD) Comparison x Enable Update */
-#define PWM_CMP4MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP4MUPD) Comparison x Trigger Update */
-#define PWM_CMP4MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP4MUPD) Comparison x Period Update */
-#define PWM_CMP4MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP4MUPD) Comparison x Update Period Update */
-/* -------- PWM_CMP5V : (PWM Offset: 0x180) PWM Comparison 5 Value Register -------- */
-#define PWM_CMP5V_CV (0xffffff << 0) /**< \brief (PWM_CMP5V) Comparison x Value */
-#define PWM_CMP5V_CVM (0x1 << 24) /**< \brief (PWM_CMP5V) Comparison x Value Mode */
-/* -------- PWM_CMP5VUPD : (PWM Offset: 0x184) PWM Comparison 5 Value Update Register -------- */
-#define PWM_CMP5VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP5VUPD) Comparison x Value Update */
-#define PWM_CMP5VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP5VUPD) Comparison x Value Mode Update */
-/* -------- PWM_CMP5M : (PWM Offset: 0x188) PWM Comparison 5 Mode Register -------- */
-#define PWM_CMP5M_CEN (0x1 << 0) /**< \brief (PWM_CMP5M) Comparison x Enable */
-#define PWM_CMP5M_CTR (0xf << 4) /**< \brief (PWM_CMP5M) Comparison x Trigger */
-#define PWM_CMP5M_CPR (0xf << 8) /**< \brief (PWM_CMP5M) Comparison x Period */
-#define PWM_CMP5M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP5M) Comparison x Period Counter */
-#define PWM_CMP5M_CUPR (0xf << 16) /**< \brief (PWM_CMP5M) Comparison x Update Period */
-#define PWM_CMP5M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP5M) Comparison x Update Period Counter */
-/* -------- PWM_CMP5MUPD : (PWM Offset: 0x18C) PWM Comparison 5 Mode Update Register -------- */
-#define PWM_CMP5MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP5MUPD) Comparison x Enable Update */
-#define PWM_CMP5MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP5MUPD) Comparison x Trigger Update */
-#define PWM_CMP5MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP5MUPD) Comparison x Period Update */
-#define PWM_CMP5MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP5MUPD) Comparison x Update Period Update */
-/* -------- PWM_CMP6V : (PWM Offset: 0x190) PWM Comparison 6 Value Register -------- */
-#define PWM_CMP6V_CV (0xffffff << 0) /**< \brief (PWM_CMP6V) Comparison x Value */
-#define PWM_CMP6V_CVM (0x1 << 24) /**< \brief (PWM_CMP6V) Comparison x Value Mode */
-/* -------- PWM_CMP6VUPD : (PWM Offset: 0x194) PWM Comparison 6 Value Update Register -------- */
-#define PWM_CMP6VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP6VUPD) Comparison x Value Update */
-#define PWM_CMP6VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP6VUPD) Comparison x Value Mode Update */
-/* -------- PWM_CMP6M : (PWM Offset: 0x198) PWM Comparison 6 Mode Register -------- */
-#define PWM_CMP6M_CEN (0x1 << 0) /**< \brief (PWM_CMP6M) Comparison x Enable */
-#define PWM_CMP6M_CTR (0xf << 4) /**< \brief (PWM_CMP6M) Comparison x Trigger */
-#define PWM_CMP6M_CPR (0xf << 8) /**< \brief (PWM_CMP6M) Comparison x Period */
-#define PWM_CMP6M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP6M) Comparison x Period Counter */
-#define PWM_CMP6M_CUPR (0xf << 16) /**< \brief (PWM_CMP6M) Comparison x Update Period */
-#define PWM_CMP6M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP6M) Comparison x Update Period Counter */
-/* -------- PWM_CMP6MUPD : (PWM Offset: 0x19C) PWM Comparison 6 Mode Update Register -------- */
-#define PWM_CMP6MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP6MUPD) Comparison x Enable Update */
-#define PWM_CMP6MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP6MUPD) Comparison x Trigger Update */
-#define PWM_CMP6MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP6MUPD) Comparison x Period Update */
-#define PWM_CMP6MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP6MUPD) Comparison x Update Period Update */
-/* -------- PWM_CMP7V : (PWM Offset: 0x1A0) PWM Comparison 7 Value Register -------- */
-#define PWM_CMP7V_CV (0xffffff << 0) /**< \brief (PWM_CMP7V) Comparison x Value */
-#define PWM_CMP7V_CVM (0x1 << 24) /**< \brief (PWM_CMP7V) Comparison x Value Mode */
-/* -------- PWM_CMP7VUPD : (PWM Offset: 0x1A4) PWM Comparison 7 Value Update Register -------- */
-#define PWM_CMP7VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP7VUPD) Comparison x Value Update */
-#define PWM_CMP7VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP7VUPD) Comparison x Value Mode Update */
-/* -------- PWM_CMP7M : (PWM Offset: 0x1A8) PWM Comparison 7 Mode Register -------- */
-#define PWM_CMP7M_CEN (0x1 << 0) /**< \brief (PWM_CMP7M) Comparison x Enable */
-#define PWM_CMP7M_CTR (0xf << 4) /**< \brief (PWM_CMP7M) Comparison x Trigger */
-#define PWM_CMP7M_CPR (0xf << 8) /**< \brief (PWM_CMP7M) Comparison x Period */
-#define PWM_CMP7M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP7M) Comparison x Period Counter */
-#define PWM_CMP7M_CUPR (0xf << 16) /**< \brief (PWM_CMP7M) Comparison x Update Period */
-#define PWM_CMP7M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP7M) Comparison x Update Period Counter */
-/* -------- PWM_CMP7MUPD : (PWM Offset: 0x1AC) PWM Comparison 7 Mode Update Register -------- */
-#define PWM_CMP7MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP7MUPD) Comparison x Enable Update */
-#define PWM_CMP7MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP7MUPD) Comparison x Trigger Update */
-#define PWM_CMP7MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP7MUPD) Comparison x Period Update */
-#define PWM_CMP7MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP7MUPD) Comparison x Update Period Update */
-/* -------- PWM_CMR0 : (PWM Offset: 0x200) PWM Channel Mode Register (ch_num = 0) -------- */
-#define PWM_CMR0_CPRE (0xf << 0) /**< \brief (PWM_CMR0) Channel Pre-scaler */
-#define PWM_CMR0_CPRE_MCK_DIV_2 (0x1) // (PWMC_CH)
-#define PWM_CMR0_CPRE_MCK_DIV_4 (0x2) // (PWMC_CH)
-#define PWM_CMR0_CPRE_MCK_DIV_8 (0x3) // (PWMC_CH)
-#define PWM_CMR0_CPRE_MCK_DIV_16 (0x4) // (PWMC_CH)
-#define PWM_CMR0_CPRE_MCK_DIV_32 (0x5) // (PWMC_CH)
-#define PWM_CMR0_CPRE_MCK_DIV_64 (0x6) // (PWMC_CH)
-#define PWM_CMR0_CPRE_MCK_DIV_128 (0x7) // (PWMC_CH)
-#define PWM_CMR0_CPRE_MCK_DIV_256 (0x8) // (PWMC_CH)
-#define PWM_CMR0_CPRE_MCK_DIV_512 (0x9) // (PWMC_CH)
-#define PWM_CMR0_CPRE_MCK_DIV_1024 (0xA) // (PWMC_CH)
-#define PWM_CMR0_CPRE_MCKA (0xB) // (PWMC_CH)
-#define PWM_CMR0_CPRE_MCKB (0xC) // (PWMC_CH)
-#define PWM_CMR0_CALG (0x1 << 8) /**< \brief (PWM_CMR0) Channel Alignment */
-#define PWM_CMR0_CPOL (0x1 << 9) /**< \brief (PWM_CMR0) Channel Polarity */
-#define PWM_CMR0_CES (0x1 << 10) /**< \brief (PWM_CMR0) Counter Event Selection */
-#define PWM_CMR0_DTE (0x1 << 16) /**< \brief (PWM_CMR0) Dead-Time Generator Enable */
-#define PWM_CMR0_DTHI (0x1 << 17) /**< \brief (PWM_CMR0) Dead-Time PWMHx Output Inverted */
-#define PWM_CMR0_DTLI (0x1 << 18) /**< \brief (PWM_CMR0) Dead-Time PWMLx Output Inverted */
-/* -------- PWM_CDTY0 : (PWM Offset: 0x204) PWM Channel Duty Cycle Register (ch_num = 0) -------- */
-#define PWM_CDTY0_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY0) Channel Duty-Cycle */
-/* -------- PWM_CDTYUPD0 : (PWM Offset: 0x208) PWM Channel Duty Cycle Update Register (ch_num = 0) -------- */
-#define PWM_CDTYUPD0_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD0) Channel Duty-Cycle Update */
-/* -------- PWM_CPRD0 : (PWM Offset: 0x20C) PWM Channel Period Register (ch_num = 0) -------- */
-#define PWM_CPRD0_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD0) Channel Period */
-/* -------- PWM_CPRDUPD0 : (PWM Offset: 0x210) PWM Channel Period Update Register (ch_num = 0) -------- */
-#define PWM_CPRDUPD0_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD0) Channel Period Update */
-/* -------- PWM_CCNT0 : (PWM Offset: 0x214) PWM Channel Counter Register (ch_num = 0) -------- */
-#define PWM_CCNT0_CNT (0xffffff << 0) /**< \brief (PWM_CCNT0) Channel Counter Register */
-/* -------- PWM_DT0 : (PWM Offset: 0x218) PWM Channel Dead Time Register (ch_num = 0) -------- */
-#define PWM_DT0_DTH (0xffff << 0) /**< \brief (PWM_DT0) Dead-Time Value for PWMHx Output */
-#define PWM_DT0_DTL (0xffff << 16) /**< \brief (PWM_DT0) Dead-Time Value for PWMLx Output */
-/* -------- PWM_DTUPD0 : (PWM Offset: 0x21C) PWM Channel Dead Time Update Register (ch_num = 0) -------- */
-#define PWM_DTUPD0_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMHx Output */
-#define PWM_DTUPD0_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMLx Output */
-/* -------- PWM_CMR1 : (PWM Offset: 0x220) PWM Channel Mode Register (ch_num = 1) -------- */
-#define PWM_CMR1_CPRE (0xf << 0) /**< \brief (PWM_CMR1) Channel Pre-scaler */
-#define PWM_CMR1_CPRE_MCK_DIV_2 (0x1) // (PWMC_CH)
-#define PWM_CMR1_CPRE_MCK_DIV_4 (0x2) // (PWMC_CH)
-#define PWM_CMR1_CPRE_MCK_DIV_8 (0x3) // (PWMC_CH)
-#define PWM_CMR1_CPRE_MCK_DIV_16 (0x4) // (PWMC_CH)
-#define PWM_CMR1_CPRE_MCK_DIV_32 (0x5) // (PWMC_CH)
-#define PWM_CMR1_CPRE_MCK_DIV_64 (0x6) // (PWMC_CH)
-#define PWM_CMR1_CPRE_MCK_DIV_128 (0x7) // (PWMC_CH)
-#define PWM_CMR1_CPRE_MCK_DIV_256 (0x8) // (PWMC_CH)
-#define PWM_CMR1_CPRE_MCK_DIV_512 (0x9) // (PWMC_CH)
-#define PWM_CMR1_CPRE_MCK_DIV_1024 (0xA) // (PWMC_CH)
-#define PWM_CMR1_CPRE_MCKA (0xB) // (PWMC_CH)
-#define PWM_CMR1_CPRE_MCKB (0xC) // (PWMC_CH)
-#define PWM_CMR1_CALG (0x1 << 8) /**< \brief (PWM_CMR1) Channel Alignment */
-#define PWM_CMR1_CPOL (0x1 << 9) /**< \brief (PWM_CMR1) Channel Polarity */
-#define PWM_CMR1_CES (0x1 << 10) /**< \brief (PWM_CMR1) Counter Event Selection */
-#define PWM_CMR1_DTE (0x1 << 16) /**< \brief (PWM_CMR1) Dead-Time Generator Enable */
-#define PWM_CMR1_DTHI (0x1 << 17) /**< \brief (PWM_CMR1) Dead-Time PWMHx Output Inverted */
-#define PWM_CMR1_DTLI (0x1 << 18) /**< \brief (PWM_CMR1) Dead-Time PWMLx Output Inverted */
-/* -------- PWM_CDTY1 : (PWM Offset: 0x224) PWM Channel Duty Cycle Register (ch_num = 1) -------- */
-#define PWM_CDTY1_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY1) Channel Duty-Cycle */
-/* -------- PWM_CDTYUPD1 : (PWM Offset: 0x228) PWM Channel Duty Cycle Update Register (ch_num = 1) -------- */
-#define PWM_CDTYUPD1_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD1) Channel Duty-Cycle Update */
-/* -------- PWM_CPRD1 : (PWM Offset: 0x22C) PWM Channel Period Register (ch_num = 1) -------- */
-#define PWM_CPRD1_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD1) Channel Period */
-/* -------- PWM_CPRDUPD1 : (PWM Offset: 0x230) PWM Channel Period Update Register (ch_num = 1) -------- */
-#define PWM_CPRDUPD1_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD1) Channel Period Update */
-/* -------- PWM_CCNT1 : (PWM Offset: 0x234) PWM Channel Counter Register (ch_num = 1) -------- */
-#define PWM_CCNT1_CNT (0xffffff << 0) /**< \brief (PWM_CCNT1) Channel Counter Register */
-/* -------- PWM_DT1 : (PWM Offset: 0x238) PWM Channel Dead Time Register (ch_num = 1) -------- */
-#define PWM_DT1_DTH (0xffff << 0) /**< \brief (PWM_DT1) Dead-Time Value for PWMHx Output */
-#define PWM_DT1_DTL (0xffff << 16) /**< \brief (PWM_DT1) Dead-Time Value for PWMLx Output */
-/* -------- PWM_DTUPD1 : (PWM Offset: 0x23C) PWM Channel Dead Time Update Register (ch_num = 1) -------- */
-#define PWM_DTUPD1_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMHx Output */
-#define PWM_DTUPD1_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMLx Output */
-/* -------- PWM_CMR2 : (PWM Offset: 0x240) PWM Channel Mode Register (ch_num = 2) -------- */
-#define PWM_CMR2_CPRE (0xf << 0) /**< \brief (PWM_CMR2) Channel Pre-scaler */
-#define PWM_CMR2_CPRE_MCK_DIV_2 (0x1) // (PWMC_CH)
-#define PWM_CMR2_CPRE_MCK_DIV_4 (0x2) // (PWMC_CH)
-#define PWM_CMR2_CPRE_MCK_DIV_8 (0x3) // (PWMC_CH)
-#define PWM_CMR2_CPRE_MCK_DIV_16 (0x4) // (PWMC_CH)
-#define PWM_CMR2_CPRE_MCK_DIV_32 (0x5) // (PWMC_CH)
-#define PWM_CMR2_CPRE_MCK_DIV_64 (0x6) // (PWMC_CH)
-#define PWM_CMR2_CPRE_MCK_DIV_128 (0x7) // (PWMC_CH)
-#define PWM_CMR2_CPRE_MCK_DIV_256 (0x8) // (PWMC_CH)
-#define PWM_CMR2_CPRE_MCK_DIV_512 (0x9) // (PWMC_CH)
-#define PWM_CMR2_CPRE_MCK_DIV_1024 (0xA) // (PWMC_CH)
-#define PWM_CMR2_CPRE_MCKA (0xB) // (PWMC_CH)
-#define PWM_CMR2_CPRE_MCKB (0xC) // (PWMC_CH)
-#define PWM_CMR2_CALG (0x1 << 8) /**< \brief (PWM_CMR2) Channel Alignment */
-#define PWM_CMR2_CPOL (0x1 << 9) /**< \brief (PWM_CMR2) Channel Polarity */
-#define PWM_CMR2_CES (0x1 << 10) /**< \brief (PWM_CMR2) Counter Event Selection */
-#define PWM_CMR2_DTE (0x1 << 16) /**< \brief (PWM_CMR2) Dead-Time Generator Enable */
-#define PWM_CMR2_DTHI (0x1 << 17) /**< \brief (PWM_CMR2) Dead-Time PWMHx Output Inverted */
-#define PWM_CMR2_DTLI (0x1 << 18) /**< \brief (PWM_CMR2) Dead-Time PWMLx Output Inverted */
-/* -------- PWM_CDTY2 : (PWM Offset: 0x244) PWM Channel Duty Cycle Register (ch_num = 2) -------- */
-#define PWM_CDTY2_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY2) Channel Duty-Cycle */
-/* -------- PWM_CDTYUPD2 : (PWM Offset: 0x248) PWM Channel Duty Cycle Update Register (ch_num = 2) -------- */
-#define PWM_CDTYUPD2_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD2) Channel Duty-Cycle Update */
-/* -------- PWM_CPRD2 : (PWM Offset: 0x24C) PWM Channel Period Register (ch_num = 2) -------- */
-#define PWM_CPRD2_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD2) Channel Period */
-/* -------- PWM_CPRDUPD2 : (PWM Offset: 0x250) PWM Channel Period Update Register (ch_num = 2) -------- */
-#define PWM_CPRDUPD2_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD2) Channel Period Update */
-/* -------- PWM_CCNT2 : (PWM Offset: 0x254) PWM Channel Counter Register (ch_num = 2) -------- */
-#define PWM_CCNT2_CNT (0xffffff << 0) /**< \brief (PWM_CCNT2) Channel Counter Register */
-/* -------- PWM_DT2 : (PWM Offset: 0x258) PWM Channel Dead Time Register (ch_num = 2) -------- */
-#define PWM_DT2_DTH (0xffff << 0) /**< \brief (PWM_DT2) Dead-Time Value for PWMHx Output */
-#define PWM_DT2_DTL (0xffff << 16) /**< \brief (PWM_DT2) Dead-Time Value for PWMLx Output */
-/* -------- PWM_DTUPD2 : (PWM Offset: 0x25C) PWM Channel Dead Time Update Register (ch_num = 2) -------- */
-#define PWM_DTUPD2_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMHx Output */
-#define PWM_DTUPD2_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMLx Output */
-/* -------- PWM_CMR3 : (PWM Offset: 0x260) PWM Channel Mode Register (ch_num = 3) -------- */
-#define PWM_CMR3_CPRE (0xf << 0) /**< \brief (PWM_CMR3) Channel Pre-scaler */
-#define PWM_CMR3_CPRE_MCK_DIV_2 (0x1) // (PWMC_CH)
-#define PWM_CMR3_CPRE_MCK_DIV_4 (0x2) // (PWMC_CH)
-#define PWM_CMR3_CPRE_MCK_DIV_8 (0x3) // (PWMC_CH)
-#define PWM_CMR3_CPRE_MCK_DIV_16 (0x4) // (PWMC_CH)
-#define PWM_CMR3_CPRE_MCK_DIV_32 (0x5) // (PWMC_CH)
-#define PWM_CMR3_CPRE_MCK_DIV_64 (0x6) // (PWMC_CH)
-#define PWM_CMR3_CPRE_MCK_DIV_128 (0x7) // (PWMC_CH)
-#define PWM_CMR3_CPRE_MCK_DIV_256 (0x8) // (PWMC_CH)
-#define PWM_CMR3_CPRE_MCK_DIV_512 (0x9) // (PWMC_CH)
-#define PWM_CMR3_CPRE_MCK_DIV_1024 (0xA) // (PWMC_CH)
-#define PWM_CMR3_CPRE_MCKA (0xB) // (PWMC_CH)
-#define PWM_CMR3_CPRE_MCKB (0xC) // (PWMC_CH)
-#define PWM_CMR3_CALG (0x1 << 8) /**< \brief (PWM_CMR3) Channel Alignment */
-#define PWM_CMR3_CPOL (0x1 << 9) /**< \brief (PWM_CMR3) Channel Polarity */
-#define PWM_CMR3_CES (0x1 << 10) /**< \brief (PWM_CMR3) Counter Event Selection */
-#define PWM_CMR3_DTE (0x1 << 16) /**< \brief (PWM_CMR3) Dead-Time Generator Enable */
-#define PWM_CMR3_DTHI (0x1 << 17) /**< \brief (PWM_CMR3) Dead-Time PWMHx Output Inverted */
-#define PWM_CMR3_DTLI (0x1 << 18) /**< \brief (PWM_CMR3) Dead-Time PWMLx Output Inverted */
-/* -------- PWM_CDTY3 : (PWM Offset: 0x264) PWM Channel Duty Cycle Register (ch_num = 3) -------- */
-#define PWM_CDTY3_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY3) Channel Duty-Cycle */
-/* -------- PWM_CDTYUPD3 : (PWM Offset: 0x268) PWM Channel Duty Cycle Update Register (ch_num = 3) -------- */
-#define PWM_CDTYUPD3_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD3) Channel Duty-Cycle Update */
-/* -------- PWM_CPRD3 : (PWM Offset: 0x26C) PWM Channel Period Register (ch_num = 3) -------- */
-#define PWM_CPRD3_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD3) Channel Period */
-/* -------- PWM_CPRDUPD3 : (PWM Offset: 0x270) PWM Channel Period Update Register (ch_num = 3) -------- */
-#define PWM_CPRDUPD3_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD3) Channel Period Update */
-/* -------- PWM_CCNT3 : (PWM Offset: 0x274) PWM Channel Counter Register (ch_num = 3) -------- */
-#define PWM_CCNT3_CNT (0xffffff << 0) /**< \brief (PWM_CCNT3) Channel Counter Register */
-/* -------- PWM_DT3 : (PWM Offset: 0x278) PWM Channel Dead Time Register (ch_num = 3) -------- */
-#define PWM_DT3_DTH (0xffff << 0) /**< \brief (PWM_DT3) Dead-Time Value for PWMHx Output */
-#define PWM_DT3_DTL (0xffff << 16) /**< \brief (PWM_DT3) Dead-Time Value for PWMLx Output */
-/* -------- PWM_DTUPD3 : (PWM Offset: 0x27C) PWM Channel Dead Time Update Register (ch_num = 3) -------- */
-#define PWM_DTUPD3_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMHx Output */
-#define PWM_DTUPD3_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMLx Output */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Reset Controller */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3U_RSTC Reset Controller */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Rstc hardware registers */
-typedef struct {
- WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
- RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
- RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
-} Rstc;
-#endif /* __ASSEMBLY__ */
-/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
-#define RSTC_CR_PROCRST (0x1 << 0) /**< \brief (RSTC_CR) Processor Reset */
-#define RSTC_CR_PERRST (0x1 << 2) /**< \brief (RSTC_CR) Peripheral Reset */
-#define RSTC_CR_EXTRST (0x1 << 3) /**< \brief (RSTC_CR) External Reset */
-#define RSTC_CR_KEY (0xff << 24) /**< \brief (RSTC_CR) Password */
-/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
-#define RSTC_SR_URSTS (0x1 << 0) /**< \brief (RSTC_SR) User Reset Status */
-#define RSTC_SR_RSTTYP (0x7 << 8) /**< \brief (RSTC_SR) Reset Type */
-#define RSTC_SR_NRSTL (0x1 << 16) /**< \brief (RSTC_SR) NRST Pin Level */
-#define RSTC_SR_SRCMP (0x1 << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
-/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
-#define RSTC_MR_URSTEN (0x1 << 0) /**< \brief (RSTC_MR) User Reset Enable */
-#define RSTC_MR_URSTIEN (0x1 << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
-#define RSTC_MR_ERSTL (0xf << 8) /**< \brief (RSTC_MR) External Reset Length */
-#define RSTC_MR_KEY (0xff << 24) /**< \brief (RSTC_MR) Password */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Real-time Clock */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3U_RTC Real-time Clock */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Rtc hardware registers */
-typedef struct {
- RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */
- RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */
- RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */
- RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */
- RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
- RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
- RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */
- WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
- WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
- WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
- RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
- RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
-} Rtc;
-#endif /* __ASSEMBLY__ */
-/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
-#define RTC_CR_UPDTIM (0x1 << 0) /**< \brief (RTC_CR) Update Request Time Register */
-#define RTC_CR_UPDCAL (0x1 << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
-#define RTC_CR_TIMEVSEL (0x3 << 8) /**< \brief (RTC_CR) Time Event Selection */
-#define RTC_CR_TIMEVSEL_MINUTE (0x0 << 8) /**< \brief (RTC_CR) Minute change. */
-#define RTC_CR_TIMEVSEL_HOUR (0x1 << 8) /**< \brief (RTC_CR) Hour change. */
-#define RTC_CR_TIMEVSEL_DAY24 (0x2 << 8) /**< \brief (RTC_CR) Every day at midnight. */
-#define RTC_CR_TIMEVSEL_DAY12 (0x3 << 8) /**< \brief (RTC_CR) Every day at noon. */
-#define RTC_CR_CALEVSEL (0x3 << 16) /**< \brief (RTC_CR) Calendar Event Selection */
-#define RTC_CR_CALEVSEL_WEEK (0x0 << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00). */
-#define RTC_CR_CALEVSEL_MONTH (0x1 << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00). */
-/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
-#define RTC_MR_HRMOD (0x1 << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
-/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
-#define RTC_TIMR_SEC (0x7f << 0) /**< \brief (RTC_TIMR) Current Second */
-#define RTC_TIMR_MIN (0x7f << 8) /**< \brief (RTC_TIMR) Current Minute */
-#define RTC_TIMR_HOUR (0x3f << 16) /**< \brief (RTC_TIMR) Current Hour */
-#define RTC_TIMR_AMPM (0x1 << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
-/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
-#define RTC_CALR_CENT (0x7f << 0) /**< \brief (RTC_CALR) Current Century */
-#define RTC_CALR_YEAR (0xff << 8) /**< \brief (RTC_CALR) Current Year */
-#define RTC_CALR_MONTH (0x1f << 16) /**< \brief (RTC_CALR) Current Month */
-#define RTC_CALR_DAY (0x7 << 21) /**< \brief (RTC_CALR) Current Day in Current Week */
-#define RTC_CALR_DATE (0x3f << 24) /**< \brief (RTC_CALR) Current Day in Current Month */
-/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
-#define RTC_TIMALR_SEC (0x7f << 0) /**< \brief (RTC_TIMALR) Second Alarm */
-#define RTC_TIMALR_SECEN (0x1 << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
-#define RTC_TIMALR_MIN (0x7f << 8) /**< \brief (RTC_TIMALR) Minute Alarm */
-#define RTC_TIMALR_MINEN (0x1 << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
-#define RTC_TIMALR_HOUR (0x3f << 16) /**< \brief (RTC_TIMALR) Hour Alarm */
-#define RTC_TIMALR_AMPM (0x1 << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
-#define RTC_TIMALR_HOUREN (0x1 << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
-/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
-#define RTC_CALALR_MONTH (0x1f << 16) /**< \brief (RTC_CALALR) Month Alarm */
-#define RTC_CALALR_MTHEN (0x1 << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
-#define RTC_CALALR_DATE (0x3f << 24) /**< \brief (RTC_CALALR) Date Alarm */
-#define RTC_CALALR_DATEEN (0x1 << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
-/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
-#define RTC_SR_ACKUPD (0x1 << 0) /**< \brief (RTC_SR) Acknowledge for Update */
-#define RTC_SR_ALARM (0x1 << 1) /**< \brief (RTC_SR) Alarm Flag */
-#define RTC_SR_SEC (0x1 << 2) /**< \brief (RTC_SR) Second Event */
-#define RTC_SR_TIMEV (0x1 << 3) /**< \brief (RTC_SR) Time Event */
-#define RTC_SR_CALEV (0x1 << 4) /**< \brief (RTC_SR) Calendar Event */
-/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
-#define RTC_SCCR_ACKCLR (0x1 << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
-#define RTC_SCCR_ALRCLR (0x1 << 1) /**< \brief (RTC_SCCR) Alarm Clear */
-#define RTC_SCCR_SECCLR (0x1 << 2) /**< \brief (RTC_SCCR) Second Clear */
-#define RTC_SCCR_TIMCLR (0x1 << 3) /**< \brief (RTC_SCCR) Time Clear */
-#define RTC_SCCR_CALCLR (0x1 << 4) /**< \brief (RTC_SCCR) Calendar Clear */
-/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
-#define RTC_IER_ACKEN (0x1 << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
-#define RTC_IER_ALREN (0x1 << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
-#define RTC_IER_SECEN (0x1 << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
-#define RTC_IER_TIMEN (0x1 << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
-#define RTC_IER_CALEN (0x1 << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
-/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
-#define RTC_IDR_ACKDIS (0x1 << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
-#define RTC_IDR_ALRDIS (0x1 << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
-#define RTC_IDR_SECDIS (0x1 << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
-#define RTC_IDR_TIMDIS (0x1 << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
-#define RTC_IDR_CALDIS (0x1 << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
-/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
-#define RTC_IMR_ACK (0x1 << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
-#define RTC_IMR_ALR (0x1 << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
-#define RTC_IMR_SEC (0x1 << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
-#define RTC_IMR_TIM (0x1 << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
-#define RTC_IMR_CAL (0x1 << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
-/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
-#define RTC_VER_NVTIM (0x1 << 0) /**< \brief (RTC_VER) Non-valid Time */
-#define RTC_VER_NVCAL (0x1 << 1) /**< \brief (RTC_VER) Non-valid Calendar */
-#define RTC_VER_NVTIMALR (0x1 << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
-#define RTC_VER_NVCALALR (0x1 << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Real-time Timer */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3U_RTT Real-time Timer */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Rtt hardware registers */
-typedef struct {
- RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */
- RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */
- RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */
- RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */
-} Rtt;
-#endif /* __ASSEMBLY__ */
-/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */
-#define RTT_MR_RTPRES (0xffff << 0) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */
-#define RTT_MR_ALMIEN (0x1 << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */
-#define RTT_MR_RTTINCIEN (0x1 << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */
-#define RTT_MR_RTTRST (0x1 << 18) /**< \brief (RTT_MR) Real-time Timer Restart */
-/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */
-#define RTT_AR_ALMV (0xffffffff << 0) /**< \brief (RTT_AR) Alarm Value */
-/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */
-#define RTT_VR_CRTV (0xffffffff << 0) /**< \brief (RTT_VR) Current Real-time Value */
-/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */
-#define RTT_SR_ALMS (0x1 << 0) /**< \brief (RTT_SR) Real-time Alarm Status */
-#define RTT_SR_RTTINC (0x1 << 1) /**< \brief (RTT_SR) Real-time Timer Increment */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Static Memory Controller */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3U_SMC Static Memory Controller */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief SmcCs_number hardware registers */
-typedef struct {
- RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC SETUP Register */
- RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC PULSE Register */
- RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC CYCLE Register */
- RwReg SMC_TIMINGS; /**< \brief (SmcCs_number Offset: 0xC) SMC TIMINGS Register */
- RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0x10) SMC MODE Register */
-} SmcCs_number;
-/** \brief Smc hardware registers */
-typedef struct {
- RwReg SMC_CFG; /**< \brief (Smc Offset: 0x000) SMC NFC Configuration Register */
- WoReg SMC_CTRL; /**< \brief (Smc Offset: 0x004) SMC NFC Control Register */
- RoReg SMC_SR; /**< \brief (Smc Offset: 0x008) SMC NFC Status Register */
- WoReg SMC_IER; /**< \brief (Smc Offset: 0x00C) SMC NFC Interrupt Enable Register */
- WoReg SMC_IDR; /**< \brief (Smc Offset: 0x010) SMC NFC Interrupt Disable Register */
- RoReg SMC_IMR; /**< \brief (Smc Offset: 0x014) SMC NFC Interrupt Mask Register */
- RwReg SMC_ADDR; /**< \brief (Smc Offset: 0x018) SMC NFC Address Cycle Zero Register */
- RwReg SMC_BANK; /**< \brief (Smc Offset: 0x01C) SMC Bank Address Register */
- WoReg SMC_ECC_CTRL; /**< \brief (Smc Offset: 0x020) SMC ECC Control Register */
- RwReg SMC_ECC_MD; /**< \brief (Smc Offset: 0x024) SMC ECC Mode Register */
- RoReg SMC_ECC_SR1; /**< \brief (Smc Offset: 0x028) SMC ECC Status 1 Register */
- RoReg SMC_ECC_PR0; /**< \brief (Smc Offset: 0x02C) SMC ECC Parity 0 Register */
- RoReg SMC_ECC_PR1; /**< \brief (Smc Offset: 0x030) SMC ECC parity 1 Register */
- RoReg SMC_ECC_SR2; /**< \brief (Smc Offset: 0x034) SMC ECC status 2 Register */
- RoReg SMC_ECC_PR2; /**< \brief (Smc Offset: 0x038) SMC ECC parity 2 Register */
- RoReg SMC_ECC_PR3; /**< \brief (Smc Offset: 0x03C) SMC ECC parity 3 Register */
- RoReg SMC_ECC_PR4; /**< \brief (Smc Offset: 0x040) SMC ECC parity 4 Register */
- RoReg SMC_ECC_PR5; /**< \brief (Smc Offset: 0x044) SMC ECC parity 5 Register */
- RoReg SMC_ECC_PR6; /**< \brief (Smc Offset: 0x048) SMC ECC parity 6 Register */
- RoReg SMC_ECC_PR7; /**< \brief (Smc Offset: 0x04C) SMC ECC parity 7 Register */
- RoReg SMC_ECC_PR8; /**< \brief (Smc Offset: 0x050) SMC ECC parity 8 Register */
- RoReg SMC_ECC_PR9; /**< \brief (Smc Offset: 0x054) SMC ECC parity 9 Register */
- RoReg SMC_ECC_PR10; /**< \brief (Smc Offset: 0x058) SMC ECC parity 10 Register */
- RoReg SMC_ECC_PR11; /**< \brief (Smc Offset: 0x05C) SMC ECC parity 11 Register */
- RoReg SMC_ECC_PR12; /**< \brief (Smc Offset: 0x060) SMC ECC parity 12 Register */
- RoReg SMC_ECC_PR13; /**< \brief (Smc Offset: 0x064) SMC ECC parity 13 Register */
- RoReg SMC_ECC_PR14; /**< \brief (Smc Offset: 0x068) SMC ECC parity 14 Register */
- RoReg SMC_ECC_PR15; /**< \brief (Smc Offset: 0x06C) SMC ECC parity 15 Register */
- SmcCs_number SMC_CS_NUMBER[4]; /**< \brief (Smc Offset: 0x70) CS_number = 0 .. 3 */
- RwReg Reserved1[20];
- RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x110) SMC OCMS MODE Register */
- WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x114) SMC KEY1 Register */
- WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x118) SMC KEY2 Register */
- RwReg Reserved2[50];
- WoReg SMC_WPCR; /**< \brief (Smc Offset: 0x1E4) Write Protection Control Register */
- RoReg SMC_WPSR; /**< \brief (Smc Offset: 0x1E8) Write Protection Status Register */
-} Smc;
-#endif /* __ASSEMBLY__ */
-/* -------- SMC_CFG : (SMC Offset: 0x000) SMC NFC Configuration Register -------- */
-#define SMC_CFG_PAGESIZE (0x3 << 0) /**< \brief (SMC_CFG) */
-#define SMC_CFG_WSPARE (0x1 << 8) /**< \brief (SMC_CFG) Write Spare Area */
-#define SMC_CFG_RSPARE (0x1 << 9) /**< \brief (SMC_CFG) Read Spare Area */
-#define SMC_CFG_EDGECTRL (0x1 << 12) /**< \brief (SMC_CFG) Rising/Falling Edge Detection Control */
-#define SMC_CFG_RBEDGE (0x1 << 13) /**< \brief (SMC_CFG) Ready/Busy Signal Edge Detection */
-#define SMC_CFG_DTOCYC (0xf << 16) /**< \brief (SMC_CFG) Data Timeout Cycle Number */
-#define SMC_CFG_DTOMUL (0x7 << 20) /**< \brief (SMC_CFG) Data Timeout Multiplier */
-/* -------- SMC_CTRL : (SMC Offset: 0x004) SMC NFC Control Register -------- */
-#define SMC_CTRL_NFCEN (0x1 << 0) /**< \brief (SMC_CTRL) NAND Flash Controller Enable */
-#define SMC_CTRL_NFCDIS (0x1 << 1) /**< \brief (SMC_CTRL) NAND Flash Controller Disable */
-/* -------- SMC_SR : (SMC Offset: 0x008) SMC NFC Status Register -------- */
-#define SMC_SR_SMCSTS (0x1 << 0) /**< \brief (SMC_SR) NAND Flash Controller status (this field cannot be reset) */
-#define SMC_SR_RB_RISE (0x1 << 4) /**< \brief (SMC_SR) Selected Ready Busy Rising Edge Detected */
-#define SMC_SR_RB_FALL (0x1 << 5) /**< \brief (SMC_SR) Selected Ready Busy Falling Edge Detected */
-#define SMC_SR_NFCBUSY (0x1 << 8) /**< \brief (SMC_SR) NFC Busy (this field cannot be reset) */
-#define SMC_SR_NFCWR (0x1 << 11) /**< \brief (SMC_SR) NFC Write/Read Operation (this field cannot be reset) */
-#define SMC_SR_NFCSID (0x7 << 12) /**< \brief (SMC_SR) NFC Chip Select ID (this field cannot be reset) */
-#define SMC_SR_XFRDONE (0x1 << 16) /**< \brief (SMC_SR) NFC Data Transfer Terminated */
-#define SMC_SR_CMDDONE (0x1 << 17) /**< \brief (SMC_SR) Command Done */
-#define SMC_SR_DTOE (0x1 << 20) /**< \brief (SMC_SR) Data Timeout Error */
-#define SMC_SR_UNDEF (0x1 << 21) /**< \brief (SMC_SR) Undefined Area Error */
-#define SMC_SR_AWB (0x1 << 22) /**< \brief (SMC_SR) Accessing While Busy */
-#define SMC_SR_NFCASE (0x1 << 23) /**< \brief (SMC_SR) NFC Access Size Error */
-#define SMC_SR_RB_EDGE0 (0x1 << 24) /**< \brief (SMC_SR) Ready/Busy Line 0 Edge Detected */
-/* -------- SMC_IER : (SMC Offset: 0x00C) SMC NFC Interrupt Enable Register -------- */
-#define SMC_IER_RB_RISE (0x1 << 4) /**< \brief (SMC_IER) Ready Busy Rising Edge Detection Interrupt Enable */
-#define SMC_IER_RB_FALL (0x1 << 5) /**< \brief (SMC_IER) Ready Busy Falling Edge Detection Interrupt Enable */
-#define SMC_IER_XFRDONE (0x1 << 16) /**< \brief (SMC_IER) Transfer Done Interrupt Enable */
-#define SMC_IER_CMDDONE (0x1 << 17) /**< \brief (SMC_IER) Command Done Interrupt Enable */
-#define SMC_IER_DTOE (0x1 << 20) /**< \brief (SMC_IER) Data Timeout Error Interrupt Enable */
-#define SMC_IER_UNDEF (0x1 << 21) /**< \brief (SMC_IER) Undefined Area Access Interrupt Enable */
-#define SMC_IER_AWB (0x1 << 22) /**< \brief (SMC_IER) Accessing While Busy Interrupt Enable */
-#define SMC_IER_NFCASE (0x1 << 23) /**< \brief (SMC_IER) NFC Access Size Error Interrupt Enable */
-#define SMC_IER_RB_EDGE0 (0x1 << 24) /**< \brief (SMC_IER) Ready/Busy Line 0 Interrupt Enable */
-/* -------- SMC_IDR : (SMC Offset: 0x010) SMC NFC Interrupt Disable Register -------- */
-#define SMC_IDR_RB_RISE (0x1 << 4) /**< \brief (SMC_IDR) Ready Busy Rising Edge Detection Interrupt Disable */
-#define SMC_IDR_RB_FALL (0x1 << 5) /**< \brief (SMC_IDR) Ready Busy Falling Edge Detection Interrupt Disable */
-#define SMC_IDR_XFRDONE (0x1 << 16) /**< \brief (SMC_IDR) Transfer Done Interrupt Disable */
-#define SMC_IDR_CMDDONE (0x1 << 17) /**< \brief (SMC_IDR) Command Done Interrupt Disable */
-#define SMC_IDR_DTOE (0x1 << 20) /**< \brief (SMC_IDR) Data Timeout Error Interrupt Disable */
-#define SMC_IDR_UNDEF (0x1 << 21) /**< \brief (SMC_IDR) Undefined Area Access Interrupt Disable */
-#define SMC_IDR_AWB (0x1 << 22) /**< \brief (SMC_IDR) Accessing While Busy Interrupt Disable */
-#define SMC_IDR_NFCASE (0x1 << 23) /**< \brief (SMC_IDR) NFC Access Size Error Interrupt Disable */
-#define SMC_IDR_RB_EDGE0 (0x1 << 24) /**< \brief (SMC_IDR) Ready/Busy Line 0 Interrupt Disable */
-/* -------- SMC_IMR : (SMC Offset: 0x014) SMC NFC Interrupt Mask Register -------- */
-#define SMC_IMR_RB_RISE (0x1 << 4) /**< \brief (SMC_IMR) Ready Busy Rising Edge Detection Interrupt Mask */
-#define SMC_IMR_RB_FALL (0x1 << 5) /**< \brief (SMC_IMR) Ready Busy Falling Edge Detection Interrupt Mask */
-#define SMC_IMR_XFRDONE (0x1 << 16) /**< \brief (SMC_IMR) Transfer Done Interrupt Mask */
-#define SMC_IMR_CMDDONE (0x1 << 17) /**< \brief (SMC_IMR) Command Done Interrupt Mask */
-#define SMC_IMR_DTOE (0x1 << 20) /**< \brief (SMC_IMR) Data Timeout Error Interrupt Mask */
-#define SMC_IMR_UNDEF (0x1 << 21) /**< \brief (SMC_IMR) Undefined Area Access Interrupt Mask5 */
-#define SMC_IMR_AWB (0x1 << 22) /**< \brief (SMC_IMR) Accessing While Busy Interrupt Mask */
-#define SMC_IMR_NFCASE (0x1 << 23) /**< \brief (SMC_IMR) NFC Access Size Error Interrupt Mask */
-#define SMC_IMR_RB_EDGE0 (0x1 << 24) /**< \brief (SMC_IMR) Ready/Busy Line 0 Interrupt Mask */
-/* -------- SMC_ADDR : (SMC Offset: 0x018) SMC NFC Address Cycle Zero Register -------- */
-#define SMC_ADDR_ADDR_CYCLE0 (0xff << 0) /**< \brief (SMC_ADDR) NAND Flash Array Address cycle 0 */
-/* -------- SMC_BANK : (SMC Offset: 0x01C) SMC Bank Address Register -------- */
-#define SMC_BANK_BANK (0x7 << 0) /**< \brief (SMC_BANK) Bank Identifier */
-/* -------- SMC_ECC_CTRL : (SMC Offset: 0x020) SMC ECC Control Register -------- */
-#define SMC_ECC_CTRL_RST (0x1 << 0) /**< \brief (SMC_ECC_CTRL) Reset ECC */
-#define SMC_ECC_CTRL_SWRST (0x1 << 1) /**< \brief (SMC_ECC_CTRL) Software Reset */
-/* -------- SMC_ECC_MD : (SMC Offset: 0x024) SMC ECC Mode Register -------- */
-#define SMC_ECC_MD_ECC_PAGESIZE (0x3 << 0) /**< \brief (SMC_ECC_MD) */
-#define SMC_ECC_MD_TYPCORREC (0x3 << 4) /**< \brief (SMC_ECC_MD) type of correction */
-/* -------- SMC_ECC_SR1 : (SMC Offset: 0x028) SMC ECC Status 1 Register -------- */
-#define SMC_ECC_SR1_RECERR0 (0x1 << 0) /**< \brief (SMC_ECC_SR1) Recoverable Error */
-#define SMC_ECC_SR1_ECCERR0 (0x3 << 1) /**< \brief (SMC_ECC_SR1) ECC Error */
-#define SMC_ECC_SR1_RECERR1 (0x1 << 4) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 256th and the 511th bytes or the 512nd and the 1023rd bytes */
-#define SMC_ECC_SR1_ECCERR1 (0x1 << 5) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */
-#define SMC_ECC_SR1_MULERR1 (0x1 << 6) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */
-#define SMC_ECC_SR1_RECERR2 (0x1 << 8) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
-#define SMC_ECC_SR1_ECCERR2 (0x1 << 9) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
-#define SMC_ECC_SR1_MULERR2 (0x1 << 10) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
-#define SMC_ECC_SR1_RECERR3 (0x1 << 12) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
-#define SMC_ECC_SR1_ECCERR3 (0x1 << 13) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
-#define SMC_ECC_SR1_MULERR3 (0x1 << 14) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
-#define SMC_ECC_SR1_RECERR4 (0x1 << 16) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */
-#define SMC_ECC_SR1_ECCERR4 (0x3 << 17) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */
-#define SMC_ECC_SR1_RECERR5 (0x1 << 20) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */
-#define SMC_ECC_SR1_ECCERR5 (0x3 << 21) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */
-#define SMC_ECC_SR1_RECERR6 (0x1 << 24) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */
-#define SMC_ECC_SR1_ECCERR6 (0x3 << 25) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */
-#define SMC_ECC_SR1_RECERR7 (0x1 << 28) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */
-#define SMC_ECC_SR1_ECCERR7 (0x3 << 29) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */
-/* -------- SMC_ECC_PR0 : (SMC Offset: 0x02C) SMC ECC Parity 0 Register -------- */
-#define SMC_ECC_PR0_BITADDR (0xf << 0) /**< \brief (SMC_ECC_PR0) Bit Address */
-#define SMC_ECC_PR0_WORDADDR (0xfff << 4) /**< \brief (SMC_ECC_PR0) Word Address */
-/* -------- SMC_ECC_PR1 : (SMC Offset: 0x030) SMC ECC parity 1 Register -------- */
-#define SMC_ECC_PR1_NPARITY (0xffff << 0) /**< \brief (SMC_ECC_PR1) */
-/* -------- SMC_ECC_SR2 : (SMC Offset: 0x034) SMC ECC status 2 Register -------- */
-#define SMC_ECC_SR2_RECERR8 (0x1 << 0) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2048th and the 2303rd bytes */
-#define SMC_ECC_SR2_ECCERR8 (0x3 << 1) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2048th and the 2303rd bytes */
-#define SMC_ECC_SR2_RECERR9 (0x1 << 4) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2304th and the 2559th bytes */
-#define SMC_ECC_SR2_ECCERR9 (0x1 << 5) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2304th and the 2559th bytes */
-#define SMC_ECC_SR2_MULERR9 (0x1 << 6) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2304th and the 2559th bytes */
-#define SMC_ECC_SR2_RECERR10 (0x1 << 8) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2560th and the 2815th bytes */
-#define SMC_ECC_SR2_ECCERR10 (0x1 << 9) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2560th and the 2815th bytes */
-#define SMC_ECC_SR2_MULERR10 (0x1 << 10) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2560th and the 2815th bytes */
-#define SMC_ECC_SR2_RECERR11 (0x1 << 12) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2816th and the 3071st bytes */
-#define SMC_ECC_SR2_ECCERR11 (0x1 << 13) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2816th and the 3071st bytes */
-#define SMC_ECC_SR2_MULERR11 (0x1 << 14) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2816th and the 3071st bytes */
-#define SMC_ECC_SR2_RECERR12 (0x1 << 16) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3072nd and the 3327th bytes */
-#define SMC_ECC_SR2_ECCERR12 (0x3 << 17) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3072nd and the 3327th bytes */
-#define SMC_ECC_SR2_RECERR13 (0x1 << 20) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3328th and the 3583rd bytes */
-#define SMC_ECC_SR2_ECCERR13 (0x3 << 21) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3328th and the 3583rd bytes */
-#define SMC_ECC_SR2_RECERR14 (0x1 << 24) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3584th and the 3839th bytes */
-#define SMC_ECC_SR2_ECCERR14 (0x3 << 25) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3584th and the 3839th bytes */
-#define SMC_ECC_SR2_RECERR15 (0x1 << 28) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3840th and the 4095th bytes */
-#define SMC_ECC_SR2_ECCERR15 (0x3 << 29) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3840th and the 4095th bytes */
-/* -------- SMC_ECC_PR2 : (SMC Offset: 0x038) SMC ECC parity 2 Register -------- */
-/* -------- SMC_ECC_PR3 : (SMC Offset: 0x03C) SMC ECC parity 3 Register -------- */
-/* -------- SMC_ECC_PR4 : (SMC Offset: 0x040) SMC ECC parity 4 Register -------- */
-/* -------- SMC_ECC_PR5 : (SMC Offset: 0x044) SMC ECC parity 5 Register -------- */
-/* -------- SMC_ECC_PR6 : (SMC Offset: 0x048) SMC ECC parity 6 Register -------- */
-/* -------- SMC_ECC_PR7 : (SMC Offset: 0x04C) SMC ECC parity 7 Register -------- */
-/* -------- SMC_ECC_PR8 : (SMC Offset: 0x050) SMC ECC parity 8 Register -------- */
-/* -------- SMC_ECC_PR9 : (SMC Offset: 0x054) SMC ECC parity 9 Register -------- */
-/* -------- SMC_ECC_PR10 : (SMC Offset: 0x058) SMC ECC parity 10 Register -------- */
-/* -------- SMC_ECC_PR11 : (SMC Offset: 0x05C) SMC ECC parity 11 Register -------- */
-/* -------- SMC_ECC_PR12 : (SMC Offset: 0x060) SMC ECC parity 12 Register -------- */
-/* -------- SMC_ECC_PR13 : (SMC Offset: 0x064) SMC ECC parity 13 Register -------- */
-/* -------- SMC_ECC_PR14 : (SMC Offset: 0x068) SMC ECC parity 14 Register -------- */
-/* -------- SMC_ECC_PR15 : (SMC Offset: 0x06C) SMC ECC parity 15 Register -------- */
-/* -------- SMC_SETUP0 : (SMC Offset: 0x70) SMC SETUP Register (CS_number = 0) -------- */
-#define SMC_SETUP0_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP0) NWE Setup length */
-#define SMC_SETUP0_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP0) NCS Setup length in Write access */
-#define SMC_SETUP0_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP0) NRD Setup length */
-#define SMC_SETUP0_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP0) NCS Setup length in Read access */
-/* -------- SMC_PULSE0 : (SMC Offset: 0x74) SMC PULSE Register (CS_number = 0) -------- */
-#define SMC_PULSE0_NWE_PULSE (0x3f << 0) /**< \brief (SMC_PULSE0) NWE Pulse Length */
-#define SMC_PULSE0_NCS_WR_PULSE (0x3f << 8) /**< \brief (SMC_PULSE0) NCS Pulse Length in WRITE Access */
-#define SMC_PULSE0_NRD_PULSE (0x3f << 16) /**< \brief (SMC_PULSE0) NRD Pulse Length */
-#define SMC_PULSE0_NCS_RD_PULSE (0x3f << 24) /**< \brief (SMC_PULSE0) NCS Pulse Length in READ Access */
-/* -------- SMC_CYCLE0 : (SMC Offset: 0x78) SMC CYCLE Register (CS_number = 0) -------- */
-#define SMC_CYCLE0_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE0) Total Write Cycle Length */
-#define SMC_CYCLE0_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE0) Total Read Cycle Length */
-/* -------- SMC_TIMINGS0 : (SMC Offset: 0x7C) SMC TIMINGS Register (CS_number = 0) -------- */
-#define SMC_TIMINGS0_TCLR (0xf << 0) /**< \brief (SMC_TIMINGS0) CLE to REN Low Delay */
-#define SMC_TIMINGS0_TADL (0xf << 4) /**< \brief (SMC_TIMINGS0) ALE to Data Start */
-#define SMC_TIMINGS0_TAR (0xf << 8) /**< \brief (SMC_TIMINGS0) ALE to REN Low Delay */
-#define SMC_TIMINGS0_OCMS (0x1 << 12) /**< \brief (SMC_TIMINGS0) Off Chip Memory Scrambling Enable */
-#define SMC_TIMINGS0_TRR (0xf << 16) /**< \brief (SMC_TIMINGS0) Ready to REN Low Delay */
-#define SMC_TIMINGS0_TWB (0xf << 24) /**< \brief (SMC_TIMINGS0) WEN High to REN to Busy */
-#define SMC_TIMINGS0_RBNSEL (0x7 << 28) /**< \brief (SMC_TIMINGS0) Ready/Busy Line Selection */
-#define SMC_TIMINGS0_NFSEL (0x1 << 31) /**< \brief (SMC_TIMINGS0) NAND Flash Selection */
-/* -------- SMC_MODE0 : (SMC Offset: 0x80) SMC MODE Register (CS_number = 0) -------- */
-#define SMC_MODE0_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE0) */
-#define SMC_MODE0_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE0) */
-#define SMC_MODE0_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE0) NWAIT Mode */
-#define SMC_MODE0_BAT (0x1 << 8) /**< \brief (SMC_MODE0) Byte Access Type */
-#define SMC_MODE0_DBW (0x1 << 12) /**< \brief (SMC_MODE0) Data Bus Width */
-#define SMC_MODE0_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE0) Data Float Time */
-#define SMC_MODE0_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE0) TDF Optimization */
-/* -------- SMC_SETUP1 : (SMC Offset: 0x84) SMC SETUP Register (CS_number = 1) -------- */
-#define SMC_SETUP1_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP1) NWE Setup length */
-#define SMC_SETUP1_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP1) NCS Setup length in Write access */
-#define SMC_SETUP1_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP1) NRD Setup length */
-#define SMC_SETUP1_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP1) NCS Setup length in Read access */
-/* -------- SMC_PULSE1 : (SMC Offset: 0x88) SMC PULSE Register (CS_number = 1) -------- */
-#define SMC_PULSE1_NWE_PULSE (0x3f << 0) /**< \brief (SMC_PULSE1) NWE Pulse Length */
-#define SMC_PULSE1_NCS_WR_PULSE (0x3f << 8) /**< \brief (SMC_PULSE1) NCS Pulse Length in WRITE Access */
-#define SMC_PULSE1_NRD_PULSE (0x3f << 16) /**< \brief (SMC_PULSE1) NRD Pulse Length */
-#define SMC_PULSE1_NCS_RD_PULSE (0x3f << 24) /**< \brief (SMC_PULSE1) NCS Pulse Length in READ Access */
-/* -------- SMC_CYCLE1 : (SMC Offset: 0x8C) SMC CYCLE Register (CS_number = 1) -------- */
-#define SMC_CYCLE1_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE1) Total Write Cycle Length */
-#define SMC_CYCLE1_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE1) Total Read Cycle Length */
-/* -------- SMC_TIMINGS1 : (SMC Offset: 0x90) SMC TIMINGS Register (CS_number = 1) -------- */
-#define SMC_TIMINGS1_TCLR (0xf << 0) /**< \brief (SMC_TIMINGS1) CLE to REN Low Delay */
-#define SMC_TIMINGS1_TADL (0xf << 4) /**< \brief (SMC_TIMINGS1) ALE to Data Start */
-#define SMC_TIMINGS1_TAR (0xf << 8) /**< \brief (SMC_TIMINGS1) ALE to REN Low Delay */
-#define SMC_TIMINGS1_OCMS (0x1 << 12) /**< \brief (SMC_TIMINGS1) Off Chip Memory Scrambling Enable */
-#define SMC_TIMINGS1_TRR (0xf << 16) /**< \brief (SMC_TIMINGS1) Ready to REN Low Delay */
-#define SMC_TIMINGS1_TWB (0xf << 24) /**< \brief (SMC_TIMINGS1) WEN High to REN to Busy */
-#define SMC_TIMINGS1_RBNSEL (0x7 << 28) /**< \brief (SMC_TIMINGS1) Ready/Busy Line Selection */
-#define SMC_TIMINGS1_NFSEL (0x1 << 31) /**< \brief (SMC_TIMINGS1) NAND Flash Selection */
-/* -------- SMC_MODE1 : (SMC Offset: 0x94) SMC MODE Register (CS_number = 1) -------- */
-#define SMC_MODE1_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE1) */
-#define SMC_MODE1_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE1) */
-#define SMC_MODE1_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE1) NWAIT Mode */
-#define SMC_MODE1_BAT (0x1 << 8) /**< \brief (SMC_MODE1) Byte Access Type */
-#define SMC_MODE1_DBW (0x1 << 12) /**< \brief (SMC_MODE1) Data Bus Width */
-#define SMC_MODE1_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE1) Data Float Time */
-#define SMC_MODE1_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE1) TDF Optimization */
-/* -------- SMC_SETUP2 : (SMC Offset: 0x98) SMC SETUP Register (CS_number = 2) -------- */
-#define SMC_SETUP2_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP2) NWE Setup length */
-#define SMC_SETUP2_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP2) NCS Setup length in Write access */
-#define SMC_SETUP2_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP2) NRD Setup length */
-#define SMC_SETUP2_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP2) NCS Setup length in Read access */
-/* -------- SMC_PULSE2 : (SMC Offset: 0x9C) SMC PULSE Register (CS_number = 2) -------- */
-#define SMC_PULSE2_NWE_PULSE (0x3f << 0) /**< \brief (SMC_PULSE2) NWE Pulse Length */
-#define SMC_PULSE2_NCS_WR_PULSE (0x3f << 8) /**< \brief (SMC_PULSE2) NCS Pulse Length in WRITE Access */
-#define SMC_PULSE2_NRD_PULSE (0x3f << 16) /**< \brief (SMC_PULSE2) NRD Pulse Length */
-#define SMC_PULSE2_NCS_RD_PULSE (0x3f << 24) /**< \brief (SMC_PULSE2) NCS Pulse Length in READ Access */
-/* -------- SMC_CYCLE2 : (SMC Offset: 0xA0) SMC CYCLE Register (CS_number = 2) -------- */
-#define SMC_CYCLE2_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE2) Total Write Cycle Length */
-#define SMC_CYCLE2_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE2) Total Read Cycle Length */
-/* -------- SMC_TIMINGS2 : (SMC Offset: 0xA4) SMC TIMINGS Register (CS_number = 2) -------- */
-#define SMC_TIMINGS2_TCLR (0xf << 0) /**< \brief (SMC_TIMINGS2) CLE to REN Low Delay */
-#define SMC_TIMINGS2_TADL (0xf << 4) /**< \brief (SMC_TIMINGS2) ALE to Data Start */
-#define SMC_TIMINGS2_TAR (0xf << 8) /**< \brief (SMC_TIMINGS2) ALE to REN Low Delay */
-#define SMC_TIMINGS2_OCMS (0x1 << 12) /**< \brief (SMC_TIMINGS2) Off Chip Memory Scrambling Enable */
-#define SMC_TIMINGS2_TRR (0xf << 16) /**< \brief (SMC_TIMINGS2) Ready to REN Low Delay */
-#define SMC_TIMINGS2_TWB (0xf << 24) /**< \brief (SMC_TIMINGS2) WEN High to REN to Busy */
-#define SMC_TIMINGS2_RBNSEL (0x7 << 28) /**< \brief (SMC_TIMINGS2) Ready/Busy Line Selection */
-#define SMC_TIMINGS2_NFSEL (0x1 << 31) /**< \brief (SMC_TIMINGS2) NAND Flash Selection */
-/* -------- SMC_MODE2 : (SMC Offset: 0xA8) SMC MODE Register (CS_number = 2) -------- */
-#define SMC_MODE2_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE2) */
-#define SMC_MODE2_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE2) */
-#define SMC_MODE2_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE2) NWAIT Mode */
-#define SMC_MODE2_BAT (0x1 << 8) /**< \brief (SMC_MODE2) Byte Access Type */
-#define SMC_MODE2_DBW (0x1 << 12) /**< \brief (SMC_MODE2) Data Bus Width */
-#define SMC_MODE2_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE2) Data Float Time */
-#define SMC_MODE2_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE2) TDF Optimization */
-/* -------- SMC_SETUP3 : (SMC Offset: 0xAC) SMC SETUP Register (CS_number = 3) -------- */
-#define SMC_SETUP3_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP3) NWE Setup length */
-#define SMC_SETUP3_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP3) NCS Setup length in Write access */
-#define SMC_SETUP3_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP3) NRD Setup length */
-#define SMC_SETUP3_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP3) NCS Setup length in Read access */
-/* -------- SMC_PULSE3 : (SMC Offset: 0xB0) SMC PULSE Register (CS_number = 3) -------- */
-#define SMC_PULSE3_NWE_PULSE (0x3f << 0) /**< \brief (SMC_PULSE3) NWE Pulse Length */
-#define SMC_PULSE3_NCS_WR_PULSE (0x3f << 8) /**< \brief (SMC_PULSE3) NCS Pulse Length in WRITE Access */
-#define SMC_PULSE3_NRD_PULSE (0x3f << 16) /**< \brief (SMC_PULSE3) NRD Pulse Length */
-#define SMC_PULSE3_NCS_RD_PULSE (0x3f << 24) /**< \brief (SMC_PULSE3) NCS Pulse Length in READ Access */
-/* -------- SMC_CYCLE3 : (SMC Offset: 0xB4) SMC CYCLE Register (CS_number = 3) -------- */
-#define SMC_CYCLE3_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE3) Total Write Cycle Length */
-#define SMC_CYCLE3_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE3) Total Read Cycle Length */
-/* -------- SMC_TIMINGS3 : (SMC Offset: 0xB8) SMC TIMINGS Register (CS_number = 3) -------- */
-#define SMC_TIMINGS3_TCLR (0xf << 0) /**< \brief (SMC_TIMINGS3) CLE to REN Low Delay */
-#define SMC_TIMINGS3_TADL (0xf << 4) /**< \brief (SMC_TIMINGS3) ALE to Data Start */
-#define SMC_TIMINGS3_TAR (0xf << 8) /**< \brief (SMC_TIMINGS3) ALE to REN Low Delay */
-#define SMC_TIMINGS3_OCMS (0x1 << 12) /**< \brief (SMC_TIMINGS3) Off Chip Memory Scrambling Enable */
-#define SMC_TIMINGS3_TRR (0xf << 16) /**< \brief (SMC_TIMINGS3) Ready to REN Low Delay */
-#define SMC_TIMINGS3_TWB (0xf << 24) /**< \brief (SMC_TIMINGS3) WEN High to REN to Busy */
-#define SMC_TIMINGS3_RBNSEL (0x7 << 28) /**< \brief (SMC_TIMINGS3) Ready/Busy Line Selection */
-#define SMC_TIMINGS3_NFSEL (0x1 << 31) /**< \brief (SMC_TIMINGS3) NAND Flash Selection */
-/* -------- SMC_MODE3 : (SMC Offset: 0xBC) SMC MODE Register (CS_number = 3) -------- */
-#define SMC_MODE3_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE3) */
-#define SMC_MODE3_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE3) */
-#define SMC_MODE3_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE3) NWAIT Mode */
-#define SMC_MODE3_BAT (0x1 << 8) /**< \brief (SMC_MODE3) Byte Access Type */
-#define SMC_MODE3_DBW (0x1 << 12) /**< \brief (SMC_MODE3) Data Bus Width */
-#define SMC_MODE3_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE3) Data Float Time */
-#define SMC_MODE3_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE3) TDF Optimization */
-/* -------- SMC_OCMS : (SMC Offset: 0x110) SMC OCMS MODE Register -------- */
-#define SMC_OCMS_SMSE (0x1 << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */
-#define SMC_OCMS_SRSE (0x1 << 1) /**< \brief (SMC_OCMS) SRAM Scrambling Enable */
-/* -------- SMC_KEY1 : (SMC Offset: 0x114) SMC KEY1 Register -------- */
-#define SMC_KEY1_KEY1 (0xffffffff << 0) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */
-/* -------- SMC_KEY2 : (SMC Offset: 0x118) SMC KEY2 Register -------- */
-#define SMC_KEY2_KEY2 (0xffffffff << 0) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */
-/* -------- SMC_WPCR : (SMC Offset: 0x1E4) Write Protection Control Register -------- */
-#define SMC_WPCR_WP_EN (0x1 << 0) /**< \brief (SMC_WPCR) */
-#define SMC_WPCR_WP_KEY (0xffffff << 8) /**< \brief (SMC_WPCR) Write Protection KEY password */
-/* -------- SMC_WPSR : (SMC Offset: 0x1E8) Write Protection Status Register -------- */
-#define SMC_WPSR_WP_VS (0xf << 0) /**< \brief (SMC_WPSR) Write Protection Violation Status */
-#define SMC_WPSR_WP_VSRC (0xffff << 8) /**< \brief (SMC_WPSR) Write Protection Violation SouRCe */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3U_SPI Serial Peripheral Interface */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Spi hardware registers */
-typedef struct {
- WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */
- RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */
- RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */
- WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */
- RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */
- WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */
- WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */
- RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */
- RwReg Reserved1[4];
- RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */
- RwReg Reserved2[41];
- RwReg SPI_WPCR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */
- RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */
-} Spi;
-#endif /* __ASSEMBLY__ */
-/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
-#define SPI_CR_SPIEN (0x1 << 0) /**< \brief (SPI_CR) SPI Enable */
-#define SPI_CR_SPIDIS (0x1 << 1) /**< \brief (SPI_CR) SPI Disable */
-#define SPI_CR_SWRST (0x1 << 7) /**< \brief (SPI_CR) SPI Software Reset */
-#define SPI_CR_LASTXFER (0x1 << 24) /**< \brief (SPI_CR) Last Transfer */
-/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
-#define SPI_MR_MSTR (0x1 << 0) /**< \brief (SPI_MR) Master/Slave Mode */
-#define SPI_MR_PS (0x1 << 1) /**< \brief (SPI_MR) Peripheral Select */
-#define SPI_MR_PS_FIXED (0x0 << 1) /**< \brief (SPI_MR) Fixed Peripheral Select. */
-#define SPI_MR_PS_VARIABLE (0x1 << 1) /**< \brief (SPI_MR) Variable Peripheral Select. */
-#define SPI_MR_PCSDEC (0x1 << 2) /**< \brief (SPI_MR) Chip Select Decode */
-#define SPI_MR_MODFDIS (0x1 << 4) /**< \brief (SPI_MR) Mode Fault Detection */
-#define SPI_MR_WDRBT (0x1 << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
-#define SPI_MR_LLB (0x1 << 7) /**< \brief (SPI_MR) Local Loopback Enable */
-#define SPI_MR_PCS (0xf << 16) /**< \brief (SPI_MR) Peripheral Chip Select */
-#define SPI_MR_DLYBCS (0xff << 24) /**< \brief (SPI_MR) Delay Between Chip Selects */
-/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
-#define SPI_RDR_RD (0xffff << 0) /**< \brief (SPI_RDR) Receive Data */
-#define SPI_RDR_PCS (0xf << 16) /**< \brief (SPI_RDR) Peripheral Chip Select */
-/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
-#define SPI_TDR_TD (0xffff << 0) /**< \brief (SPI_TDR) Transmit Data */
-#define SPI_TDR_PCS (0xf << 16) /**< \brief (SPI_TDR) Peripheral Chip Select */
-#define SPI_TDR_LASTXFER (0x1 << 24) /**< \brief (SPI_TDR) Last Transfer */
-/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
-#define SPI_SR_RDRF (0x1 << 0) /**< \brief (SPI_SR) Receive Data Register Full */
-#define SPI_SR_TDRE (0x1 << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */
-#define SPI_SR_MODF (0x1 << 2) /**< \brief (SPI_SR) Mode Fault Error */
-#define SPI_SR_OVRES (0x1 << 3) /**< \brief (SPI_SR) Overrun Error Status */
-#define SPI_SR_RXBUFF (0x1 << 6) /**< \brief (SPI_SR) */
-#define SPI_SR_NSSR (0x1 << 8) /**< \brief (SPI_SR) NSS Rising */
-#define SPI_SR_TXEMPTY (0x1 << 9) /**< \brief (SPI_SR) Transmission Registers Empty */
-#define SPI_SR_UNDES (0x1 << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */
-#define SPI_SR_SPIENS (0x1 << 16) /**< \brief (SPI_SR) SPI Enable Status */
-/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
-#define SPI_IER_RDRF (0x1 << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
-#define SPI_IER_TDRE (0x1 << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
-#define SPI_IER_MODF (0x1 << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
-#define SPI_IER_OVRES (0x1 << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
-#define SPI_IER_RXBUFF (0x1 << 6) /**< \brief (SPI_IER) */
-#define SPI_IER_NSSR (0x1 << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
-#define SPI_IER_TXEMPTY (0x1 << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
-#define SPI_IER_UNDES (0x1 << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
-/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
-#define SPI_IDR_RDRF (0x1 << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
-#define SPI_IDR_TDRE (0x1 << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
-#define SPI_IDR_MODF (0x1 << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
-#define SPI_IDR_OVRES (0x1 << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
-#define SPI_IDR_RXBUFF (0x1 << 6) /**< \brief (SPI_IDR) */
-#define SPI_IDR_NSSR (0x1 << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
-#define SPI_IDR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
-#define SPI_IDR_UNDES (0x1 << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
-/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
-#define SPI_IMR_RDRF (0x1 << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
-#define SPI_IMR_TDRE (0x1 << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
-#define SPI_IMR_MODF (0x1 << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
-#define SPI_IMR_OVRES (0x1 << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
-#define SPI_IMR_RXBUFF (0x1 << 6) /**< \brief (SPI_IMR) */
-#define SPI_IMR_NSSR (0x1 << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
-#define SPI_IMR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
-#define SPI_IMR_UNDES (0x1 << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
-/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
-#define SPI_CSR_CPOL (0x1 << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */
-#define SPI_CSR_NCPHA (0x1 << 1) /**< \brief (SPI_CSR[4]) Clock Phase */
-#define SPI_CSR_CSNAAT (0x1 << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
-#define SPI_CSR_CSAAT (0x1 << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
-#define SPI_CSR_BITS (0xf << 4) /**< \brief (SPI_CSR[4]) Bits Per Transfer (See the (Note:) below the register table; Section 9.9 "SPI Chip Select Register" on page 37.) */
-#define SPI_CSR_BITS_8 (0x0 << 4) /**< \brief (SPI_CSR[4]) 8 */
-#define SPI_CSR_BITS_9 (0x1 << 4) /**< \brief (SPI_CSR[4]) 9 */
-#define SPI_CSR_BITS_10 (0x2 << 4) /**< \brief (SPI_CSR[4]) 10 */
-#define SPI_CSR_BITS_11 (0x3 << 4) /**< \brief (SPI_CSR[4]) 11 */
-#define SPI_CSR_BITS_12 (0x4 << 4) /**< \brief (SPI_CSR[4]) 12 */
-#define SPI_CSR_BITS_13 (0x5 << 4) /**< \brief (SPI_CSR[4]) 13 */
-#define SPI_CSR_BITS_14 (0x6 << 4) /**< \brief (SPI_CSR[4]) 14 */
-#define SPI_CSR_BITS_15 (0x7 << 4) /**< \brief (SPI_CSR[4]) 15 */
-#define SPI_CSR_BITS_16 (0x8 << 4) /**< \brief (SPI_CSR[4]) 16 */
-#define SPI_CSR_SCBR (0xff << 8) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */
-#define SPI_CSR_DLYBS (0xff << 16) /**< \brief (SPI_CSR[4]) Delay Before SPCK */
-#define SPI_CSR_DLYBCT (0xff << 24) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */
-/* -------- SPI_WPCR : (SPI Offset: 0xE4) Write Protection Control Register -------- */
-#define SPI_WPCR_SPIWPEN (0x1 << 0) /**< \brief (SPI_WPCR) SPI Write Protection Enable */
-#define SPI_WPCR_SPIWPKEY (0xffffff << 8) /**< \brief (SPI_WPCR) SPI Write Protection Key Password */
-/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
-#define SPI_WPSR_SPIWPVS (0x7 << 0) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */
-#define SPI_WPSR_SPIWPVSRC (0xff << 8) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3U_SSC Synchronous Serial Controller */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Ssc hardware registers */
-typedef struct {
- WoReg SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */
- RwReg SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */
- RwReg Reserved1[2];
- RwReg SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */
- RwReg SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */
- RwReg SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */
- RwReg SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */
- RoReg SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */
- WoReg SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */
- RwReg Reserved2[2];
- RoReg SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */
- RwReg SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */
- RwReg SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */
- RwReg SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */
- RoReg SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */
- WoReg SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */
- WoReg SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */
- RoReg SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */
- RwReg Reserved3[37];
- RwReg SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */
- RoReg SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */
-} Ssc;
-#endif /* __ASSEMBLY__ */
-/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */
-#define SSC_CR_RXEN (0x1 << 0) /**< \brief (SSC_CR) Receive Enable */
-#define SSC_CR_RXDIS (0x1 << 1) /**< \brief (SSC_CR) Receive Disable */
-#define SSC_CR_TXEN (0x1 << 8) /**< \brief (SSC_CR) Transmit Enable */
-#define SSC_CR_TXDIS (0x1 << 9) /**< \brief (SSC_CR) Transmit Disable */
-#define SSC_CR_SWRST (0x1 << 15) /**< \brief (SSC_CR) Software Reset */
-/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */
-#define SSC_CMR_DIV (0xfff << 0) /**< \brief (SSC_CMR) Clock Divider */
-/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */
-#define SSC_RCMR_CKS (0x3 << 0) /**< \brief (SSC_RCMR) Receive Clock Selection */
-#define SSC_RCMR_CKS_DIV (0x0 << 0) /**< \brief (SSC_RCMR) Divided Clock */
-#define SSC_RCMR_CKS_TK (0x1 << 0) /**< \brief (SSC_RCMR) TK Clock signal */
-#define SSC_RCMR_CKS_RK (0x2 << 0) /**< \brief (SSC_RCMR) RK pin */
-#define SSC_RCMR_CKO (0x7 << 2) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */
-#define SSC_RCMR_CKI (0x1 << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */
-#define SSC_RCMR_CKG (0x3 << 6) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */
-#define SSC_RCMR_CKG_NONE (0x0 << 6) /**< \brief (SSC_RCMR) None, continuous clock */
-#define SSC_RCMR_CKG_LOW (0x1 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */
-#define SSC_RCMR_CKG_HIGH (0x2 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */
-#define SSC_RCMR_START (0xf << 8) /**< \brief (SSC_RCMR) Receive Start Selection */
-#define SSC_RCMR_STOP (0x1 << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */
-#define SSC_RCMR_STTDLY (0xff << 16) /**< \brief (SSC_RCMR) Receive Start Delay */
-#define SSC_RCMR_PERIOD (0xff << 24) /**< \brief (SSC_RCMR) Receive Period Divider Selection */
-/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */
-#define SSC_RFMR_DATLEN (0x1f << 0) /**< \brief (SSC_RFMR) Data Length */
-#define SSC_RFMR_LOOP (0x1 << 5) /**< \brief (SSC_RFMR) Loop Mode */
-#define SSC_RFMR_MSBF (0x1 << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */
-#define SSC_RFMR_DATNB (0xf << 8) /**< \brief (SSC_RFMR) Data Number per Frame */
-#define SSC_RFMR_FSLEN (0xf << 16) /**< \brief (SSC_RFMR) Receive Frame Sync Length */
-#define SSC_RFMR_FSOS (0x7 << 20) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */
-#define SSC_RFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */
-#define SSC_RFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_RFMR) FSLEN Field Extension */
-/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */
-#define SSC_TCMR_CKS (0x3 << 0) /**< \brief (SSC_TCMR) Transmit Clock Selection */
-#define SSC_TCMR_CKO (0x7 << 2) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */
-#define SSC_TCMR_CKI (0x1 << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */
-#define SSC_TCMR_CKG (0x3 << 6) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */
-#define SSC_TCMR_START (0xf << 8) /**< \brief (SSC_TCMR) Transmit Start Selection */
-#define SSC_TCMR_STTDLY (0xff << 16) /**< \brief (SSC_TCMR) Transmit Start Delay */
-#define SSC_TCMR_PERIOD (0xff << 24) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */
-/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */
-#define SSC_TFMR_DATLEN (0x1f << 0) /**< \brief (SSC_TFMR) Data Length */
-#define SSC_TFMR_DATDEF (0x1 << 5) /**< \brief (SSC_TFMR) Data Default Value */
-#define SSC_TFMR_MSBF (0x1 << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */
-#define SSC_TFMR_DATNB (0xf << 8) /**< \brief (SSC_TFMR) Data Number per frame */
-#define SSC_TFMR_FSLEN (0xf << 16) /**< \brief (SSC_TFMR) Transmit Frame Syn Length */
-#define SSC_TFMR_FSOS (0x7 << 20) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */
-#define SSC_TFMR_FSDEN (0x1 << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */
-#define SSC_TFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */
-#define SSC_TFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_TFMR) FSLEN Field Extension */
-/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */
-#define SSC_RHR_RDAT (0xffffffff << 0) /**< \brief (SSC_RHR) Receive Data */
-/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */
-#define SSC_THR_TDAT (0xffffffff << 0) /**< \brief (SSC_THR) Transmit Data */
-/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */
-#define SSC_RSHR_RSDAT (0xffff << 0) /**< \brief (SSC_RSHR) Receive Synchronization Data */
-/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */
-#define SSC_TSHR_TSDAT (0xffff << 0) /**< \brief (SSC_TSHR) Transmit Synchronization Data */
-/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */
-#define SSC_RC0R_CP0 (0xffff << 0) /**< \brief (SSC_RC0R) Receive Compare Data 0 */
-/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */
-#define SSC_RC1R_CP1 (0xffff << 0) /**< \brief (SSC_RC1R) Receive Compare Data 1 */
-/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */
-#define SSC_SR_TXRDY (0x1 << 0) /**< \brief (SSC_SR) Transmit Ready */
-#define SSC_SR_TXEMPTY (0x1 << 1) /**< \brief (SSC_SR) Transmit Empty */
-#define SSC_SR_ENDTX (0x1 << 2) /**< \brief (SSC_SR) End of Transmission */
-#define SSC_SR_TXBUFE (0x1 << 3) /**< \brief (SSC_SR) Transmit Buffer Empty */
-#define SSC_SR_RXRDY (0x1 << 4) /**< \brief (SSC_SR) Receive Ready */
-#define SSC_SR_OVRUN (0x1 << 5) /**< \brief (SSC_SR) Receive Overrun */
-#define SSC_SR_ENDRX (0x1 << 6) /**< \brief (SSC_SR) End of Reception */
-#define SSC_SR_RXBUFF (0x1 << 7) /**< \brief (SSC_SR) Receive Buffer Full */
-#define SSC_SR_CP0 (0x1 << 8) /**< \brief (SSC_SR) Compare 0 */
-#define SSC_SR_CP1 (0x1 << 9) /**< \brief (SSC_SR) Compare 1 */
-#define SSC_SR_TXSYN (0x1 << 10) /**< \brief (SSC_SR) Transmit Sync */
-#define SSC_SR_RXSYN (0x1 << 11) /**< \brief (SSC_SR) Receive Sync */
-#define SSC_SR_TXEN (0x1 << 16) /**< \brief (SSC_SR) Transmit Enable */
-#define SSC_SR_RXEN (0x1 << 17) /**< \brief (SSC_SR) Receive Enable */
-/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */
-#define SSC_IER_TXRDY (0x1 << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */
-#define SSC_IER_TXEMPTY (0x1 << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */
-#define SSC_IER_ENDTX (0x1 << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */
-#define SSC_IER_TXBUFE (0x1 << 3) /**< \brief (SSC_IER) Transmit Buffer Empty Interrupt Enable */
-#define SSC_IER_RXRDY (0x1 << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */
-#define SSC_IER_OVRUN (0x1 << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */
-#define SSC_IER_ENDRX (0x1 << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */
-#define SSC_IER_RXBUFF (0x1 << 7) /**< \brief (SSC_IER) Receive Buffer Full Interrupt Enable */
-#define SSC_IER_CP0 (0x1 << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */
-#define SSC_IER_CP1 (0x1 << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */
-#define SSC_IER_TXSYN (0x1 << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */
-#define SSC_IER_RXSYN (0x1 << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */
-/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */
-#define SSC_IDR_TXRDY (0x1 << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */
-#define SSC_IDR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */
-#define SSC_IDR_ENDTX (0x1 << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */
-#define SSC_IDR_TXBUFE (0x1 << 3) /**< \brief (SSC_IDR) Transmit Buffer Empty Interrupt Disable */
-#define SSC_IDR_RXRDY (0x1 << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */
-#define SSC_IDR_OVRUN (0x1 << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */
-#define SSC_IDR_ENDRX (0x1 << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */
-#define SSC_IDR_RXBUFF (0x1 << 7) /**< \brief (SSC_IDR) Receive Buffer Full Interrupt Disable */
-#define SSC_IDR_CP0 (0x1 << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */
-#define SSC_IDR_CP1 (0x1 << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */
-#define SSC_IDR_TXSYN (0x1 << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */
-#define SSC_IDR_RXSYN (0x1 << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */
-/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */
-#define SSC_IMR_TXRDY (0x1 << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */
-#define SSC_IMR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */
-#define SSC_IMR_ENDTX (0x1 << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */
-#define SSC_IMR_TXBUFE (0x1 << 3) /**< \brief (SSC_IMR) Transmit Buffer Empty Interrupt Mask */
-#define SSC_IMR_RXRDY (0x1 << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */
-#define SSC_IMR_OVRUN (0x1 << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */
-#define SSC_IMR_ENDRX (0x1 << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */
-#define SSC_IMR_RXBUFF (0x1 << 7) /**< \brief (SSC_IMR) Receive Buffer Full Interrupt Mask */
-#define SSC_IMR_CP0 (0x1 << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */
-#define SSC_IMR_CP1 (0x1 << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */
-#define SSC_IMR_TXSYN (0x1 << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */
-#define SSC_IMR_RXSYN (0x1 << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */
-/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */
-#define SSC_WPMR_WPEN (0x1 << 0) /**< \brief (SSC_WPMR) Write Protect Enable */
-#define SSC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SSC_WPMR) Write Protect KEY */
-/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */
-#define SSC_WPSR_WPVS (0x1 << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */
-#define SSC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SSC_WPSR) Write Protect Violation Source */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Supply Controller */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3U_SUPC Supply Controller */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Supc hardware registers */
-typedef struct {
- WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */
- RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */
- RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */
- RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */
- RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */
- RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */
-} Supc;
-#endif /* __ASSEMBLY__ */
-/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
-#define SUPC_CR_VROFF (0x1 << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */
-#define SUPC_CR_VROFF_NO_EFFECT (0x0 << 2) /**< \brief (SUPC_CR) no effect. */
-#define SUPC_CR_VROFF_STOP_VREG (0x1 << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */
-#define SUPC_CR_XTALSEL (0x1 << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */
-#define SUPC_CR_XTALSEL_NO_EFFECT (0x0 << 3) /**< \brief (SUPC_CR) no effect. */
-#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1 << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */
-#define SUPC_CR_KEY (0xff << 24) /**< \brief (SUPC_CR) Password */
-/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
-#define SUPC_SMMR_SMTH (0xf << 0) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */
-#define SUPC_SMMR_SMTH_1_9V (0x0 << 0) /**< \brief (SUPC_SMMR) 1.9 V */
-#define SUPC_SMMR_SMTH_2_0V (0x1 << 0) /**< \brief (SUPC_SMMR) 2.0 V */
-#define SUPC_SMMR_SMTH_2_1V (0x2 << 0) /**< \brief (SUPC_SMMR) 2.1 V */
-#define SUPC_SMMR_SMTH_2_2V (0x3 << 0) /**< \brief (SUPC_SMMR) 2.2 V */
-#define SUPC_SMMR_SMTH_2_3V (0x4 << 0) /**< \brief (SUPC_SMMR) 2.3 V */
-#define SUPC_SMMR_SMTH_2_4V (0x5 << 0) /**< \brief (SUPC_SMMR) 2.4 V */
-#define SUPC_SMMR_SMTH_2_5V (0x6 << 0) /**< \brief (SUPC_SMMR) 2.5 V */
-#define SUPC_SMMR_SMTH_2_6V (0x7 << 0) /**< \brief (SUPC_SMMR) 2.6 V */
-#define SUPC_SMMR_SMTH_2_7V (0x8 << 0) /**< \brief (SUPC_SMMR) 2.7 V */
-#define SUPC_SMMR_SMTH_2_8V (0x9 << 0) /**< \brief (SUPC_SMMR) 2.8 V */
-#define SUPC_SMMR_SMTH_2_9V (0xA << 0) /**< \brief (SUPC_SMMR) 2.9 V */
-#define SUPC_SMMR_SMTH_3_0V (0xB << 0) /**< \brief (SUPC_SMMR) 3.0 V */
-#define SUPC_SMMR_SMTH_3_1V (0xC << 0) /**< \brief (SUPC_SMMR) 3.1 V */
-#define SUPC_SMMR_SMTH_3_2V (0xD << 0) /**< \brief (SUPC_SMMR) 3.2 V */
-#define SUPC_SMMR_SMTH_3_3V (0xE << 0) /**< \brief (SUPC_SMMR) 3.3 V */
-#define SUPC_SMMR_SMTH_3_4V (0xF << 0) /**< \brief (SUPC_SMMR) 3.4 V */
-#define SUPC_SMMR_SMSMPL (0x7 << 8) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */
-#define SUPC_SMMR_SMSMPL_SMD (0x0 << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */
-#define SUPC_SMMR_SMSMPL_CSM (0x1 << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */
-#define SUPC_SMMR_SMSMPL_32SLCK (0x2 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */
-#define SUPC_SMMR_SMSMPL_256SLCK (0x3 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */
-#define SUPC_SMMR_SMSMPL_2048SLCK (0x4 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */
-#define SUPC_SMMR_SMRSTEN (0x1 << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */
-#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */
-#define SUPC_SMMR_SMRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */
-#define SUPC_SMMR_SMIEN (0x1 << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */
-#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */
-#define SUPC_SMMR_SMIEN_ENABLE (0x1 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */
-/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
-#define SUPC_MR_BODRSTEN (0x1 << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */
-#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */
-#define SUPC_MR_BODRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */
-#define SUPC_MR_BODDIS (0x1 << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */
-#define SUPC_MR_BODDIS_ENABLE (0x0 << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */
-#define SUPC_MR_BODDIS_DISABLE (0x1 << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */
-#define SUPC_MR_VDDIORDY (0x1 << 14) /**< \brief (SUPC_MR) VDDIO Ready */
-#define SUPC_MR_VDDIORDY_VDDIO_REMOVED (0x0 << 14) /**< \brief (SUPC_MR) VDDIO is removed (used before going to backup mode when backup batteries are used) */
-#define SUPC_MR_VDDIORDY_VDDIO_PRESENT (0x1 << 14) /**< \brief (SUPC_MR) VDDIO is present (used before going to backup mode when backup batteries are used) */
-#define SUPC_MR_OSCBYPASS (0x1 << 20) /**< \brief (SUPC_MR) Oscillator Bypass */
-#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0 << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */
-#define SUPC_MR_OSCBYPASS_BYPASS (0x1 << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */
-#define SUPC_MR_KEY (0xff << 24) /**< \brief (SUPC_MR) Password Key */
-/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */
-#define SUPC_WUMR_FWUPEN (0x1 << 0) /**< \brief (SUPC_WUMR) Force Wake Up Enable */
-#define SUPC_WUMR_FWUPEN_NOT_ENABLE (0x0 << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin has no wake up effect. */
-#define SUPC_WUMR_FWUPEN_ENABLE (0x1 << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin low forces the wake up of the core power supply. */
-#define SUPC_WUMR_SMEN (0x1 << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */
-#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */
-#define SUPC_WUMR_SMEN_ENABLE (0x1 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */
-#define SUPC_WUMR_RTTEN (0x1 << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */
-#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */
-#define SUPC_WUMR_RTTEN_ENABLE (0x1 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */
-#define SUPC_WUMR_RTCEN (0x1 << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */
-#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */
-#define SUPC_WUMR_RTCEN_ENABLE (0x1 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */
-#define SUPC_WUMR_FWUPDBC (0x7 << 8) /**< \brief (SUPC_WUMR) Force Wake Up Debouncer */
-#define SUPC_WUMR_FWUPDBC_1SCLK (0x0 << 8) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
-#define SUPC_WUMR_FWUPDBC_3SCLK (0x1 << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 3 SLCK periods */
-#define SUPC_WUMR_FWUPDBC_32SCLK (0x2 << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32 SLCK periods */
-#define SUPC_WUMR_FWUPDBC_512SCLK (0x3 << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 512 SLCK periods */
-#define SUPC_WUMR_FWUPDBC_4096SCLK (0x4 << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 4,096 SLCK periods */
-#define SUPC_WUMR_FWUPDBC_32768SCLK (0x5 << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32,768 SLCK periods */
-#define SUPC_WUMR_WKUPDBC (0x7 << 12) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer */
-#define SUPC_WUMR_WKUPDBC_1SCLK (0x0 << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
-#define SUPC_WUMR_WKUPDBC_3SCLK (0x1 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 3 SLCK periods */
-#define SUPC_WUMR_WKUPDBC_32SCLK (0x2 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32 SLCK periods */
-#define SUPC_WUMR_WKUPDBC_512SCLK (0x3 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 512 SLCK periods */
-#define SUPC_WUMR_WKUPDBC_4096SCLK (0x4 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 4,096 SLCK periods */
-#define SUPC_WUMR_WKUPDBC_32768SCLK (0x5 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32,768 SLCK periods */
-/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */
-#define SUPC_WUIR_WKUPEN0 (0x1 << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */
-#define SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN0_ENABLE (0x1 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN1 (0x1 << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */
-#define SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN1_ENABLE (0x1 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN2 (0x1 << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */
-#define SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN2_ENABLE (0x1 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN3 (0x1 << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */
-#define SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN3_ENABLE (0x1 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN4 (0x1 << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */
-#define SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN4_ENABLE (0x1 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN5 (0x1 << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */
-#define SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN5_ENABLE (0x1 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN6 (0x1 << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */
-#define SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN6_ENABLE (0x1 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN7 (0x1 << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */
-#define SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN7_ENABLE (0x1 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN8 (0x1 << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */
-#define SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN8_ENABLE (0x1 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN9 (0x1 << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */
-#define SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN9_ENABLE (0x1 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN10 (0x1 << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */
-#define SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN10_ENABLE (0x1 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN11 (0x1 << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */
-#define SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN11_ENABLE (0x1 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN12 (0x1 << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */
-#define SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN12_ENABLE (0x1 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN13 (0x1 << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */
-#define SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN13_ENABLE (0x1 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN14 (0x1 << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */
-#define SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN14_ENABLE (0x1 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPEN15 (0x1 << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */
-#define SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
-#define SUPC_WUIR_WKUPEN15_ENABLE (0x1 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT0 (0x1 << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */
-#define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0 << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1 << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT1 (0x1 << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */
-#define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0 << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1 << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT2 (0x1 << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */
-#define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0 << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1 << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT3 (0x1 << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */
-#define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0 << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1 << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT4 (0x1 << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */
-#define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0 << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1 << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT5 (0x1 << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */
-#define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0 << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1 << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT6 (0x1 << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */
-#define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0 << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1 << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT7 (0x1 << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */
-#define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0 << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1 << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT8 (0x1 << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */
-#define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0 << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1 << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT9 (0x1 << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */
-#define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0 << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1 << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT10 (0x1 << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */
-#define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0 << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1 << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT11 (0x1 << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */
-#define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0 << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1 << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT12 (0x1 << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */
-#define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0 << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1 << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT13 (0x1 << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */
-#define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0 << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1 << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT14 (0x1 << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */
-#define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0 << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1 << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT15 (0x1 << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */
-#define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0 << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-#define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1 << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
-/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
-#define SUPC_SR_FWUPS (0x1 << 0) /**< \brief (SUPC_SR) FWUP Wake Up Status */
-#define SUPC_SR_FWUPS_NO (0x0 << 0) /**< \brief (SUPC_SR) no wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_FWUPS_PRESENT (0x1 << 0) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPS (0x1 << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */
-#define SUPC_SR_WKUPS_NO (0x0 << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPS_PRESENT (0x1 << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_SMWS (0x1 << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */
-#define SUPC_SR_SMWS_NO (0x0 << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_SMWS_PRESENT (0x1 << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_BODRSTS (0x1 << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */
-#define SUPC_SR_BODRSTS_NO (0x0 << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */
-#define SUPC_SR_BODRSTS_PRESENT (0x1 << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */
-#define SUPC_SR_SMRSTS (0x1 << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */
-#define SUPC_SR_SMRSTS_NO (0x0 << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
-#define SUPC_SR_SMRSTS_PRESENT (0x1 << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
-#define SUPC_SR_SMS (0x1 << 5) /**< \brief (SUPC_SR) Supply Monitor Status */
-#define SUPC_SR_SMS_NO (0x0 << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */
-#define SUPC_SR_SMS_PRESENT (0x1 << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */
-#define SUPC_SR_SMOS (0x1 << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */
-#define SUPC_SR_SMOS_HIGH (0x0 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI higher than its threshold at its last measurement. */
-#define SUPC_SR_SMOS_LOW (0x1 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI lower than its threshold at its last measurement. */
-#define SUPC_SR_OSCSEL (0x1 << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */
-#define SUPC_SR_OSCSEL_RC (0x0 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */
-#define SUPC_SR_OSCSEL_CRYST (0x1 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */
-#define SUPC_SR_FWUPIS (0x1 << 12) /**< \brief (SUPC_SR) FWUP Input Status */
-#define SUPC_SR_FWUPIS_LOW (0x0 << 12) /**< \brief (SUPC_SR) FWUP input is tied low. */
-#define SUPC_SR_FWUPIS_HIGH (0x1 << 12) /**< \brief (SUPC_SR) FWUP input is tied high. */
-#define SUPC_SR_WKUPIS0 (0x1 << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */
-#define SUPC_SR_WKUPIS0_DIS (0x0 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS0_EN (0x1 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS1 (0x1 << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */
-#define SUPC_SR_WKUPIS1_DIS (0x0 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS1_EN (0x1 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS2 (0x1 << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */
-#define SUPC_SR_WKUPIS2_DIS (0x0 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS2_EN (0x1 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS3 (0x1 << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */
-#define SUPC_SR_WKUPIS3_DIS (0x0 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS3_EN (0x1 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS4 (0x1 << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */
-#define SUPC_SR_WKUPIS4_DIS (0x0 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS4_EN (0x1 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS5 (0x1 << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */
-#define SUPC_SR_WKUPIS5_DIS (0x0 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS5_EN (0x1 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS6 (0x1 << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */
-#define SUPC_SR_WKUPIS6_DIS (0x0 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS6_EN (0x1 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS7 (0x1 << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */
-#define SUPC_SR_WKUPIS7_DIS (0x0 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS7_EN (0x1 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS8 (0x1 << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */
-#define SUPC_SR_WKUPIS8_DIS (0x0 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS8_EN (0x1 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS9 (0x1 << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */
-#define SUPC_SR_WKUPIS9_DIS (0x0 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS9_EN (0x1 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS10 (0x1 << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */
-#define SUPC_SR_WKUPIS10_DIS (0x0 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS10_EN (0x1 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS11 (0x1 << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */
-#define SUPC_SR_WKUPIS11_DIS (0x0 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS11_EN (0x1 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS12 (0x1 << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */
-#define SUPC_SR_WKUPIS12_DIS (0x0 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS12_EN (0x1 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS13 (0x1 << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */
-#define SUPC_SR_WKUPIS13_DIS (0x0 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS13_EN (0x1 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS14 (0x1 << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */
-#define SUPC_SR_WKUPIS14_DIS (0x0 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS14_EN (0x1 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS15 (0x1 << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */
-#define SUPC_SR_WKUPIS15_DIS (0x0 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
-#define SUPC_SR_WKUPIS15_EN (0x1 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Timer Counter */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3U_TC Timer Counter */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief TcChannel hardware registers */
-typedef struct {
- RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
- RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
- RwReg Reserved1[2];
- RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */
- RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */
- RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */
- RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */
- RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */
- RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
- RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
- RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
- RwReg Reserved2[4];
-} TcChannel;
-/** \brief Tc hardware registers */
-typedef struct {
- TcChannel TC_CHANNEL[3]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
- WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */
- RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */
- WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */
- WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */
- RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */
- RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */
- RwReg Reserved1[9];
- RoReg TC_VER; /**< \brief (Tc Offset: 0xFC) Version Register */
-} Tc;
-#endif /* __ASSEMBLY__ */
-/* -------- TC_CCR0 : (TC Offset: 0x0) Channel Control Register (channel = 0) -------- */
-#define TC_CCR0_CLKEN (0x1 << 0) /**< \brief (TC_CCR0) Counter Clock Enable Command */
-#define TC_CCR0_CLKDIS (0x1 << 1) /**< \brief (TC_CCR0) Counter Clock Disable Command */
-#define TC_CCR0_SWTRG (0x1 << 2) /**< \brief (TC_CCR0) Software Trigger Command */
-/* -------- TC_CMR0 : (TC Offset: 0x4) Channel Mode Register (channel = 0) -------- */
-#define TC_CMR0_TCCLKS (0x7 << 0) /**< \brief (TC_CMR0) Clock Selection */
-#define TC_CMR0_CLKI (0x1 << 3) /**< \brief (TC_CMR0) Clock Invert */
-#define TC_CMR0_BURST (0x3 << 4) /**< \brief (TC_CMR0) Burst Signal Selection */
-#define TC_CMR0_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR0) The clock is not gated by an external signal. */
-#define TC_CMR0_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR0) XC0 is ANDed with the selected clock. */
-#define TC_CMR0_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR0) XC1 is ANDed with the selected clock. */
-#define TC_CMR0_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR0) XC2 is ANDed with the selected clock. */
-#define TC_CMR0_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR0) Counter Clock Stopped with RB Loading */
-#define TC_CMR0_LDBDIS (0x1 << 7) /**< \brief (TC_CMR0) Counter Clock Disable with RB Loading */
-#define TC_CMR0_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR0) External Trigger Edge Selection */
-#define TC_CMR0_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR0) none */
-#define TC_CMR0_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR0) rising edge */
-#define TC_CMR0_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR0) falling edge */
-#define TC_CMR0_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR0) each edge */
-#define TC_CMR0_ABETRG (0x1 << 10) /**< \brief (TC_CMR0) TIOA or TIOB External Trigger Selection */
-#define TC_CMR0_CPCTRG (0x1 << 14) /**< \brief (TC_CMR0) RC Compare Trigger Enable */
-#define TC_CMR0_WAVE (0x1 << 15) /**< \brief (TC_CMR0) */
-#define TC_CMR0_LDRA (0x3 << 16) /**< \brief (TC_CMR0) RA Loading Selection */
-#define TC_CMR0_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR0) none */
-#define TC_CMR0_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR0) rising edge of TIOA */
-#define TC_CMR0_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR0) falling edge of TIOA */
-#define TC_CMR0_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR0) each edge of TIOA */
-#define TC_CMR0_LDRB (0x3 << 18) /**< \brief (TC_CMR0) RB Loading Selection */
-#define TC_CMR0_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR0) none */
-#define TC_CMR0_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR0) rising edge of TIOA */
-#define TC_CMR0_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR0) falling edge of TIOA */
-#define TC_CMR0_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR0) each edge of TIOA */
-/* -------- TC_CV0 : (TC Offset: 0x10) Counter Value (channel = 0) -------- */
-#define TC_CV0_CV (0xffff << 0) /**< \brief (TC_CV0) Counter Value */
-/* -------- TC_RA0 : (TC Offset: 0x14) Register A (channel = 0) -------- */
-#define TC_RA0_RA (0xffff << 0) /**< \brief (TC_RA0) Register A */
-/* -------- TC_RB0 : (TC Offset: 0x18) Register B (channel = 0) -------- */
-#define TC_RB0_RB (0xffff << 0) /**< \brief (TC_RB0) Register B */
-/* -------- TC_RC0 : (TC Offset: 0x1C) Register C (channel = 0) -------- */
-#define TC_RC0_RC (0xffff << 0) /**< \brief (TC_RC0) Register C */
-/* -------- TC_SR0 : (TC Offset: 0x20) Status Register (channel = 0) -------- */
-#define TC_SR0_COVFS (0x1 << 0) /**< \brief (TC_SR0) Counter Overflow Status */
-#define TC_SR0_LOVRS (0x1 << 1) /**< \brief (TC_SR0) Load Overrun Status */
-#define TC_SR0_CPAS (0x1 << 2) /**< \brief (TC_SR0) RA Compare Status */
-#define TC_SR0_CPBS (0x1 << 3) /**< \brief (TC_SR0) RB Compare Status */
-#define TC_SR0_CPCS (0x1 << 4) /**< \brief (TC_SR0) RC Compare Status */
-#define TC_SR0_LDRAS (0x1 << 5) /**< \brief (TC_SR0) RA Loading Status */
-#define TC_SR0_LDRBS (0x1 << 6) /**< \brief (TC_SR0) RB Loading Status */
-#define TC_SR0_ETRGS (0x1 << 7) /**< \brief (TC_SR0) External Trigger Status */
-#define TC_SR0_CLKSTA (0x1 << 16) /**< \brief (TC_SR0) Clock Enabling Status */
-#define TC_SR0_MTIOA (0x1 << 17) /**< \brief (TC_SR0) TIOA Mirror */
-#define TC_SR0_MTIOB (0x1 << 18) /**< \brief (TC_SR0) TIOB Mirror */
-/* -------- TC_IER0 : (TC Offset: 0x24) Interrupt Enable Register (channel = 0) -------- */
-#define TC_IER0_COVFS (0x1 << 0) /**< \brief (TC_IER0) Counter Overflow */
-#define TC_IER0_LOVRS (0x1 << 1) /**< \brief (TC_IER0) Load Overrun */
-#define TC_IER0_CPAS (0x1 << 2) /**< \brief (TC_IER0) RA Compare */
-#define TC_IER0_CPBS (0x1 << 3) /**< \brief (TC_IER0) RB Compare */
-#define TC_IER0_CPCS (0x1 << 4) /**< \brief (TC_IER0) RC Compare */
-#define TC_IER0_LDRAS (0x1 << 5) /**< \brief (TC_IER0) RA Loading */
-#define TC_IER0_LDRBS (0x1 << 6) /**< \brief (TC_IER0) RB Loading */
-#define TC_IER0_ETRGS (0x1 << 7) /**< \brief (TC_IER0) External Trigger */
-/* -------- TC_IDR0 : (TC Offset: 0x28) Interrupt Disable Register (channel = 0) -------- */
-#define TC_IDR0_COVFS (0x1 << 0) /**< \brief (TC_IDR0) Counter Overflow */
-#define TC_IDR0_LOVRS (0x1 << 1) /**< \brief (TC_IDR0) Load Overrun */
-#define TC_IDR0_CPAS (0x1 << 2) /**< \brief (TC_IDR0) RA Compare */
-#define TC_IDR0_CPBS (0x1 << 3) /**< \brief (TC_IDR0) RB Compare */
-#define TC_IDR0_CPCS (0x1 << 4) /**< \brief (TC_IDR0) RC Compare */
-#define TC_IDR0_LDRAS (0x1 << 5) /**< \brief (TC_IDR0) RA Loading */
-#define TC_IDR0_LDRBS (0x1 << 6) /**< \brief (TC_IDR0) RB Loading */
-#define TC_IDR0_ETRGS (0x1 << 7) /**< \brief (TC_IDR0) External Trigger */
-/* -------- TC_IMR0 : (TC Offset: 0x2C) Interrupt Mask Register (channel = 0) -------- */
-#define TC_IMR0_COVFS (0x1 << 0) /**< \brief (TC_IMR0) Counter Overflow */
-#define TC_IMR0_LOVRS (0x1 << 1) /**< \brief (TC_IMR0) Load Overrun */
-#define TC_IMR0_CPAS (0x1 << 2) /**< \brief (TC_IMR0) RA Compare */
-#define TC_IMR0_CPBS (0x1 << 3) /**< \brief (TC_IMR0) RB Compare */
-#define TC_IMR0_CPCS (0x1 << 4) /**< \brief (TC_IMR0) RC Compare */
-#define TC_IMR0_LDRAS (0x1 << 5) /**< \brief (TC_IMR0) RA Loading */
-#define TC_IMR0_LDRBS (0x1 << 6) /**< \brief (TC_IMR0) RB Loading */
-#define TC_IMR0_ETRGS (0x1 << 7) /**< \brief (TC_IMR0) External Trigger */
-/* -------- TC_CCR1 : (TC Offset: 0x40) Channel Control Register (channel = 1) -------- */
-#define TC_CCR1_CLKEN (0x1 << 0) /**< \brief (TC_CCR1) Counter Clock Enable Command */
-#define TC_CCR1_CLKDIS (0x1 << 1) /**< \brief (TC_CCR1) Counter Clock Disable Command */
-#define TC_CCR1_SWTRG (0x1 << 2) /**< \brief (TC_CCR1) Software Trigger Command */
-/* -------- TC_CMR1 : (TC Offset: 0x44) Channel Mode Register (channel = 1) -------- */
-#define TC_CMR1_TCCLKS (0x7 << 0) /**< \brief (TC_CMR1) Clock Selection */
-#define TC_CMR1_CLKI (0x1 << 3) /**< \brief (TC_CMR1) Clock Invert */
-#define TC_CMR1_BURST (0x3 << 4) /**< \brief (TC_CMR1) Burst Signal Selection */
-#define TC_CMR1_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR1) The clock is not gated by an external signal. */
-#define TC_CMR1_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR1) XC0 is ANDed with the selected clock. */
-#define TC_CMR1_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR1) XC1 is ANDed with the selected clock. */
-#define TC_CMR1_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR1) XC2 is ANDed with the selected clock. */
-#define TC_CMR1_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR1) Counter Clock Stopped with RB Loading */
-#define TC_CMR1_LDBDIS (0x1 << 7) /**< \brief (TC_CMR1) Counter Clock Disable with RB Loading */
-#define TC_CMR1_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR1) External Trigger Edge Selection */
-#define TC_CMR1_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR1) none */
-#define TC_CMR1_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR1) rising edge */
-#define TC_CMR1_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR1) falling edge */
-#define TC_CMR1_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR1) each edge */
-#define TC_CMR1_ABETRG (0x1 << 10) /**< \brief (TC_CMR1) TIOA or TIOB External Trigger Selection */
-#define TC_CMR1_CPCTRG (0x1 << 14) /**< \brief (TC_CMR1) RC Compare Trigger Enable */
-#define TC_CMR1_WAVE (0x1 << 15) /**< \brief (TC_CMR1) */
-#define TC_CMR1_LDRA (0x3 << 16) /**< \brief (TC_CMR1) RA Loading Selection */
-#define TC_CMR1_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR1) none */
-#define TC_CMR1_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR1) rising edge of TIOA */
-#define TC_CMR1_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR1) falling edge of TIOA */
-#define TC_CMR1_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR1) each edge of TIOA */
-#define TC_CMR1_LDRB (0x3 << 18) /**< \brief (TC_CMR1) RB Loading Selection */
-#define TC_CMR1_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR1) none */
-#define TC_CMR1_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR1) rising edge of TIOA */
-#define TC_CMR1_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR1) falling edge of TIOA */
-#define TC_CMR1_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR1) each edge of TIOA */
-/* -------- TC_CV1 : (TC Offset: 0x50) Counter Value (channel = 1) -------- */
-#define TC_CV1_CV (0xffff << 0) /**< \brief (TC_CV1) Counter Value */
-/* -------- TC_RA1 : (TC Offset: 0x54) Register A (channel = 1) -------- */
-#define TC_RA1_RA (0xffff << 0) /**< \brief (TC_RA1) Register A */
-/* -------- TC_RB1 : (TC Offset: 0x58) Register B (channel = 1) -------- */
-#define TC_RB1_RB (0xffff << 0) /**< \brief (TC_RB1) Register B */
-/* -------- TC_RC1 : (TC Offset: 0x5C) Register C (channel = 1) -------- */
-#define TC_RC1_RC (0xffff << 0) /**< \brief (TC_RC1) Register C */
-/* -------- TC_SR1 : (TC Offset: 0x60) Status Register (channel = 1) -------- */
-#define TC_SR1_COVFS (0x1 << 0) /**< \brief (TC_SR1) Counter Overflow Status */
-#define TC_SR1_LOVRS (0x1 << 1) /**< \brief (TC_SR1) Load Overrun Status */
-#define TC_SR1_CPAS (0x1 << 2) /**< \brief (TC_SR1) RA Compare Status */
-#define TC_SR1_CPBS (0x1 << 3) /**< \brief (TC_SR1) RB Compare Status */
-#define TC_SR1_CPCS (0x1 << 4) /**< \brief (TC_SR1) RC Compare Status */
-#define TC_SR1_LDRAS (0x1 << 5) /**< \brief (TC_SR1) RA Loading Status */
-#define TC_SR1_LDRBS (0x1 << 6) /**< \brief (TC_SR1) RB Loading Status */
-#define TC_SR1_ETRGS (0x1 << 7) /**< \brief (TC_SR1) External Trigger Status */
-#define TC_SR1_CLKSTA (0x1 << 16) /**< \brief (TC_SR1) Clock Enabling Status */
-#define TC_SR1_MTIOA (0x1 << 17) /**< \brief (TC_SR1) TIOA Mirror */
-#define TC_SR1_MTIOB (0x1 << 18) /**< \brief (TC_SR1) TIOB Mirror */
-/* -------- TC_IER1 : (TC Offset: 0x64) Interrupt Enable Register (channel = 1) -------- */
-#define TC_IER1_COVFS (0x1 << 0) /**< \brief (TC_IER1) Counter Overflow */
-#define TC_IER1_LOVRS (0x1 << 1) /**< \brief (TC_IER1) Load Overrun */
-#define TC_IER1_CPAS (0x1 << 2) /**< \brief (TC_IER1) RA Compare */
-#define TC_IER1_CPBS (0x1 << 3) /**< \brief (TC_IER1) RB Compare */
-#define TC_IER1_CPCS (0x1 << 4) /**< \brief (TC_IER1) RC Compare */
-#define TC_IER1_LDRAS (0x1 << 5) /**< \brief (TC_IER1) RA Loading */
-#define TC_IER1_LDRBS (0x1 << 6) /**< \brief (TC_IER1) RB Loading */
-#define TC_IER1_ETRGS (0x1 << 7) /**< \brief (TC_IER1) External Trigger */
-/* -------- TC_IDR1 : (TC Offset: 0x68) Interrupt Disable Register (channel = 1) -------- */
-#define TC_IDR1_COVFS (0x1 << 0) /**< \brief (TC_IDR1) Counter Overflow */
-#define TC_IDR1_LOVRS (0x1 << 1) /**< \brief (TC_IDR1) Load Overrun */
-#define TC_IDR1_CPAS (0x1 << 2) /**< \brief (TC_IDR1) RA Compare */
-#define TC_IDR1_CPBS (0x1 << 3) /**< \brief (TC_IDR1) RB Compare */
-#define TC_IDR1_CPCS (0x1 << 4) /**< \brief (TC_IDR1) RC Compare */
-#define TC_IDR1_LDRAS (0x1 << 5) /**< \brief (TC_IDR1) RA Loading */
-#define TC_IDR1_LDRBS (0x1 << 6) /**< \brief (TC_IDR1) RB Loading */
-#define TC_IDR1_ETRGS (0x1 << 7) /**< \brief (TC_IDR1) External Trigger */
-/* -------- TC_IMR1 : (TC Offset: 0x6C) Interrupt Mask Register (channel = 1) -------- */
-#define TC_IMR1_COVFS (0x1 << 0) /**< \brief (TC_IMR1) Counter Overflow */
-#define TC_IMR1_LOVRS (0x1 << 1) /**< \brief (TC_IMR1) Load Overrun */
-#define TC_IMR1_CPAS (0x1 << 2) /**< \brief (TC_IMR1) RA Compare */
-#define TC_IMR1_CPBS (0x1 << 3) /**< \brief (TC_IMR1) RB Compare */
-#define TC_IMR1_CPCS (0x1 << 4) /**< \brief (TC_IMR1) RC Compare */
-#define TC_IMR1_LDRAS (0x1 << 5) /**< \brief (TC_IMR1) RA Loading */
-#define TC_IMR1_LDRBS (0x1 << 6) /**< \brief (TC_IMR1) RB Loading */
-#define TC_IMR1_ETRGS (0x1 << 7) /**< \brief (TC_IMR1) External Trigger */
-/* -------- TC_CCR2 : (TC Offset: 0x80) Channel Control Register (channel = 2) -------- */
-#define TC_CCR2_CLKEN (0x1 << 0) /**< \brief (TC_CCR2) Counter Clock Enable Command */
-#define TC_CCR2_CLKDIS (0x1 << 1) /**< \brief (TC_CCR2) Counter Clock Disable Command */
-#define TC_CCR2_SWTRG (0x1 << 2) /**< \brief (TC_CCR2) Software Trigger Command */
-/* -------- TC_CMR2 : (TC Offset: 0x84) Channel Mode Register (channel = 2) -------- */
-#define TC_CMR2_TCCLKS (0x7 << 0) /**< \brief (TC_CMR2) Clock Selection */
-#define TC_CMR2_CLKI (0x1 << 3) /**< \brief (TC_CMR2) Clock Invert */
-#define TC_CMR2_BURST (0x3 << 4) /**< \brief (TC_CMR2) Burst Signal Selection */
-#define TC_CMR2_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR2) The clock is not gated by an external signal. */
-#define TC_CMR2_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR2) XC0 is ANDed with the selected clock. */
-#define TC_CMR2_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR2) XC1 is ANDed with the selected clock. */
-#define TC_CMR2_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR2) XC2 is ANDed with the selected clock. */
-#define TC_CMR2_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR2) Counter Clock Stopped with RB Loading */
-#define TC_CMR2_LDBDIS (0x1 << 7) /**< \brief (TC_CMR2) Counter Clock Disable with RB Loading */
-#define TC_CMR2_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR2) External Trigger Edge Selection */
-#define TC_CMR2_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR2) none */
-#define TC_CMR2_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR2) rising edge */
-#define TC_CMR2_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR2) falling edge */
-#define TC_CMR2_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR2) each edge */
-#define TC_CMR2_ABETRG (0x1 << 10) /**< \brief (TC_CMR2) TIOA or TIOB External Trigger Selection */
-#define TC_CMR2_CPCTRG (0x1 << 14) /**< \brief (TC_CMR2) RC Compare Trigger Enable */
-#define TC_CMR2_WAVE (0x1 << 15) /**< \brief (TC_CMR2) */
-#define TC_CMR2_LDRA (0x3 << 16) /**< \brief (TC_CMR2) RA Loading Selection */
-#define TC_CMR2_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR2) none */
-#define TC_CMR2_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR2) rising edge of TIOA */
-#define TC_CMR2_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR2) falling edge of TIOA */
-#define TC_CMR2_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR2) each edge of TIOA */
-#define TC_CMR2_LDRB (0x3 << 18) /**< \brief (TC_CMR2) RB Loading Selection */
-#define TC_CMR2_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR2) none */
-#define TC_CMR2_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR2) rising edge of TIOA */
-#define TC_CMR2_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR2) falling edge of TIOA */
-#define TC_CMR2_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR2) each edge of TIOA */
-/* -------- TC_CV2 : (TC Offset: 0x90) Counter Value (channel = 2) -------- */
-#define TC_CV2_CV (0xffff << 0) /**< \brief (TC_CV2) Counter Value */
-/* -------- TC_RA2 : (TC Offset: 0x94) Register A (channel = 2) -------- */
-#define TC_RA2_RA (0xffff << 0) /**< \brief (TC_RA2) Register A */
-/* -------- TC_RB2 : (TC Offset: 0x98) Register B (channel = 2) -------- */
-#define TC_RB2_RB (0xffff << 0) /**< \brief (TC_RB2) Register B */
-/* -------- TC_RC2 : (TC Offset: 0x9C) Register C (channel = 2) -------- */
-#define TC_RC2_RC (0xffff << 0) /**< \brief (TC_RC2) Register C */
-/* -------- TC_SR2 : (TC Offset: 0xA0) Status Register (channel = 2) -------- */
-#define TC_SR2_COVFS (0x1 << 0) /**< \brief (TC_SR2) Counter Overflow Status */
-#define TC_SR2_LOVRS (0x1 << 1) /**< \brief (TC_SR2) Load Overrun Status */
-#define TC_SR2_CPAS (0x1 << 2) /**< \brief (TC_SR2) RA Compare Status */
-#define TC_SR2_CPBS (0x1 << 3) /**< \brief (TC_SR2) RB Compare Status */
-#define TC_SR2_CPCS (0x1 << 4) /**< \brief (TC_SR2) RC Compare Status */
-#define TC_SR2_LDRAS (0x1 << 5) /**< \brief (TC_SR2) RA Loading Status */
-#define TC_SR2_LDRBS (0x1 << 6) /**< \brief (TC_SR2) RB Loading Status */
-#define TC_SR2_ETRGS (0x1 << 7) /**< \brief (TC_SR2) External Trigger Status */
-#define TC_SR2_CLKSTA (0x1 << 16) /**< \brief (TC_SR2) Clock Enabling Status */
-#define TC_SR2_MTIOA (0x1 << 17) /**< \brief (TC_SR2) TIOA Mirror */
-#define TC_SR2_MTIOB (0x1 << 18) /**< \brief (TC_SR2) TIOB Mirror */
-/* -------- TC_IER2 : (TC Offset: 0xA4) Interrupt Enable Register (channel = 2) -------- */
-#define TC_IER2_COVFS (0x1 << 0) /**< \brief (TC_IER2) Counter Overflow */
-#define TC_IER2_LOVRS (0x1 << 1) /**< \brief (TC_IER2) Load Overrun */
-#define TC_IER2_CPAS (0x1 << 2) /**< \brief (TC_IER2) RA Compare */
-#define TC_IER2_CPBS (0x1 << 3) /**< \brief (TC_IER2) RB Compare */
-#define TC_IER2_CPCS (0x1 << 4) /**< \brief (TC_IER2) RC Compare */
-#define TC_IER2_LDRAS (0x1 << 5) /**< \brief (TC_IER2) RA Loading */
-#define TC_IER2_LDRBS (0x1 << 6) /**< \brief (TC_IER2) RB Loading */
-#define TC_IER2_ETRGS (0x1 << 7) /**< \brief (TC_IER2) External Trigger */
-/* -------- TC_IDR2 : (TC Offset: 0xA8) Interrupt Disable Register (channel = 2) -------- */
-#define TC_IDR2_COVFS (0x1 << 0) /**< \brief (TC_IDR2) Counter Overflow */
-#define TC_IDR2_LOVRS (0x1 << 1) /**< \brief (TC_IDR2) Load Overrun */
-#define TC_IDR2_CPAS (0x1 << 2) /**< \brief (TC_IDR2) RA Compare */
-#define TC_IDR2_CPBS (0x1 << 3) /**< \brief (TC_IDR2) RB Compare */
-#define TC_IDR2_CPCS (0x1 << 4) /**< \brief (TC_IDR2) RC Compare */
-#define TC_IDR2_LDRAS (0x1 << 5) /**< \brief (TC_IDR2) RA Loading */
-#define TC_IDR2_LDRBS (0x1 << 6) /**< \brief (TC_IDR2) RB Loading */
-#define TC_IDR2_ETRGS (0x1 << 7) /**< \brief (TC_IDR2) External Trigger */
-/* -------- TC_IMR2 : (TC Offset: 0xAC) Interrupt Mask Register (channel = 2) -------- */
-#define TC_IMR2_COVFS (0x1 << 0) /**< \brief (TC_IMR2) Counter Overflow */
-#define TC_IMR2_LOVRS (0x1 << 1) /**< \brief (TC_IMR2) Load Overrun */
-#define TC_IMR2_CPAS (0x1 << 2) /**< \brief (TC_IMR2) RA Compare */
-#define TC_IMR2_CPBS (0x1 << 3) /**< \brief (TC_IMR2) RB Compare */
-#define TC_IMR2_CPCS (0x1 << 4) /**< \brief (TC_IMR2) RC Compare */
-#define TC_IMR2_LDRAS (0x1 << 5) /**< \brief (TC_IMR2) RA Loading */
-#define TC_IMR2_LDRBS (0x1 << 6) /**< \brief (TC_IMR2) RB Loading */
-#define TC_IMR2_ETRGS (0x1 << 7) /**< \brief (TC_IMR2) External Trigger */
-/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
-#define TC_BCR_SYNC (0x1 << 0) /**< \brief (TC_BCR) Synchro Command */
-/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
-#define TC_BMR_TC0XC0S (0x3 << 0) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
-#define TC_BMR_TC0XC0S_TCLK0 (0x0 << 0) /**< \brief (TC_BMR) TCLK0 */
-#define TC_BMR_TC0XC0S_NONE (0x1 << 0) /**< \brief (TC_BMR) none */
-#define TC_BMR_TC0XC0S_TIOA1 (0x2 << 0) /**< \brief (TC_BMR) TIOA1 */
-#define TC_BMR_TC0XC0S_TIOA2 (0x3 << 0) /**< \brief (TC_BMR) TIOA2 */
-#define TC_BMR_TC1XC1S (0x3 << 2) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
-#define TC_BMR_TC1XC1S_TCLK1 (0x0 << 2) /**< \brief (TC_BMR) TCLK1 */
-#define TC_BMR_TC1XC1S_NONE (0x1 << 2) /**< \brief (TC_BMR) none */
-#define TC_BMR_TC1XC1S_TIOA0 (0x2 << 2) /**< \brief (TC_BMR) TIOA0 */
-#define TC_BMR_TC1XC1S_TIOA2 (0x3 << 2) /**< \brief (TC_BMR) TIOA2 */
-#define TC_BMR_TC2XC2S (0x3 << 4) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
-#define TC_BMR_TC2XC2S_TCLK2 (0x0 << 4) /**< \brief (TC_BMR) TCLK2 */
-#define TC_BMR_TC2XC2S_NONE (0x1 << 4) /**< \brief (TC_BMR) none */
-#define TC_BMR_TC2XC2S_TIOA0 (0x2 << 4) /**< \brief (TC_BMR) TIOA0 */
-#define TC_BMR_TC2XC2S_TIOA1 (0x3 << 4) /**< \brief (TC_BMR) TIOA1 */
-#define TC_BMR_QDEN (0x1 << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */
-#define TC_BMR_POSEN (0x1 << 9) /**< \brief (TC_BMR) POSition ENabled */
-#define TC_BMR_SPEEDEN (0x1 << 10) /**< \brief (TC_BMR) SPEED ENabled */
-#define TC_BMR_QDTRANS (0x1 << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */
-#define TC_BMR_EDGPHA (0x1 << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */
-#define TC_BMR_INVA (0x1 << 13) /**< \brief (TC_BMR) INVerted phA */
-#define TC_BMR_INVB (0x1 << 14) /**< \brief (TC_BMR) INVerted phB */
-#define TC_BMR_INVIDX (0x1 << 15) /**< \brief (TC_BMR) INVerted InDeX */
-#define TC_BMR_SWAP (0x1 << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */
-#define TC_BMR_IDXPHB (0x1 << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */
-#define TC_BMR_FILTER (0x1 << 19) /**< \brief (TC_BMR) */
-#define TC_BMR_MAXFILT (0x3f << 20) /**< \brief (TC_BMR) MAXimum FILTer */
-/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
-#define TC_QIER_IDX (0x1 << 0) /**< \brief (TC_QIER) InDeX */
-#define TC_QIER_DIRCHG (0x1 << 1) /**< \brief (TC_QIER) DIRection CHanGe */
-#define TC_QIER_QERR (0x1 << 2) /**< \brief (TC_QIER) Quadrature ERRor */
-/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
-#define TC_QIDR_IDX (0x1 << 0) /**< \brief (TC_QIDR) InDeX */
-#define TC_QIDR_DIRCHG (0x1 << 1) /**< \brief (TC_QIDR) DIRection CHanGe */
-#define TC_QIDR_QERR (0x1 << 2) /**< \brief (TC_QIDR) Quadrature ERRor */
-/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
-#define TC_QIMR_IDX (0x1 << 0) /**< \brief (TC_QIMR) InDeX */
-#define TC_QIMR_DIRCHG (0x1 << 1) /**< \brief (TC_QIMR) DIRection CHanGe */
-#define TC_QIMR_QERR (0x1 << 2) /**< \brief (TC_QIMR) Quadrature ERRor */
-/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
-#define TC_QISR_IDX (0x1 << 0) /**< \brief (TC_QISR) InDeX */
-#define TC_QISR_DIRCHG (0x1 << 1) /**< \brief (TC_QISR) DIRection CHanGe */
-#define TC_QISR_QERR (0x1 << 2) /**< \brief (TC_QISR) Quadrature ERRor */
-#define TC_QISR_DIR (0x1 << 8) /**< \brief (TC_QISR) Direction */
-/* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */
-#define TC_VER_VERSION (0xfff << 0) /**< \brief (TC_VER) */
-#define TC_VER_MFN (0x7 << 16) /**< \brief (TC_VER) */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Two-wire Interface */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3U_TWI Two-wire Interface */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Twi hardware registers */
-typedef struct {
- WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */
- RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */
- RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */
- RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */
- RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */
- RwReg Reserved1[3];
- RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */
- WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */
- WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */
- RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */
- RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */
- WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */
- RwReg Reserved2[50];
- RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */
- RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */
- RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */
- RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */
- RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */
- RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */
- RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */
- RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */
- WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */
- RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */
-} Twi;
-#endif /* __ASSEMBLY__ */
-/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
-#define TWI_CR_START (0x1 << 0) /**< \brief (TWI_CR) Send a START Condition */
-#define TWI_CR_STOP (0x1 << 1) /**< \brief (TWI_CR) Send a STOP Condition */
-#define TWI_CR_MSEN (0x1 << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */
-#define TWI_CR_MSDIS (0x1 << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */
-#define TWI_CR_SVEN (0x1 << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */
-#define TWI_CR_SVDIS (0x1 << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */
-#define TWI_CR_QUICK (0x1 << 6) /**< \brief (TWI_CR) SMBUS Quick Command */
-#define TWI_CR_SWRST (0x1 << 7) /**< \brief (TWI_CR) Software Reset */
-/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
-#define TWI_MMR_IADRSZ (0x3 << 8) /**< \brief (TWI_MMR) Internal Device Address Size */
-#define TWI_MMR_IADRSZ_NO (0x0 << 8) /**< \brief (TWI_MMR) No internal device address */
-#define TWI_MMR_IADRSZ_1_BYTE (0x1 << 8) /**< \brief (TWI_MMR) One-byte internal device address */
-#define TWI_MMR_IADRSZ_2_BYTE (0x2 << 8) /**< \brief (TWI_MMR) Two-byte internal device address */
-#define TWI_MMR_IADRSZ_3_BYTE (0x3 << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
-#define TWI_MMR_MREAD (0x1 << 12) /**< \brief (TWI_MMR) Master Read Direction */
-#define TWI_MMR_DADR (0x7f << 16) /**< \brief (TWI_MMR) Device Address */
-/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
-#define TWI_SMR_SADR (0x7f << 16) /**< \brief (TWI_SMR) Slave Address */
-/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
-#define TWI_IADR_IADR (0xffffff << 0) /**< \brief (TWI_IADR) Internal Address */
-/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
-#define TWI_CWGR_CLDIV (0xff << 0) /**< \brief (TWI_CWGR) Clock Low Divider */
-#define TWI_CWGR_CHDIV (0xff << 8) /**< \brief (TWI_CWGR) Clock High Divider */
-#define TWI_CWGR_CKDIV (0x7 << 16) /**< \brief (TWI_CWGR) Clock Divider */
-/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
-#define TWI_SR_TXCOMP (0x1 << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */
-#define TWI_SR_RXRDY (0x1 << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */
-#define TWI_SR_TXRDY (0x1 << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */
-#define TWI_SR_SVREAD (0x1 << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */
-#define TWI_SR_SVACC (0x1 << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */
-#define TWI_SR_GACC (0x1 << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */
-#define TWI_SR_OVRE (0x1 << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */
-#define TWI_SR_NACK (0x1 << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */
-#define TWI_SR_ARBLST (0x1 << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */
-#define TWI_SR_SCLWS (0x1 << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */
-#define TWI_SR_EOSACC (0x1 << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */
-#define TWI_SR_ENDRX (0x1 << 12) /**< \brief (TWI_SR) End of RX buffer */
-#define TWI_SR_ENDTX (0x1 << 13) /**< \brief (TWI_SR) End of TX buffer */
-#define TWI_SR_RXBUFF (0x1 << 14) /**< \brief (TWI_SR) RX Buffer Full */
-#define TWI_SR_TXBUFE (0x1 << 15) /**< \brief (TWI_SR) TX Buffer Empty */
-/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
-#define TWI_IER_TXCOMP (0x1 << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */
-#define TWI_IER_RXRDY (0x1 << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */
-#define TWI_IER_TXRDY (0x1 << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */
-#define TWI_IER_SVACC (0x1 << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */
-#define TWI_IER_GACC (0x1 << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */
-#define TWI_IER_OVRE (0x1 << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */
-#define TWI_IER_NACK (0x1 << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */
-#define TWI_IER_ARBLST (0x1 << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */
-#define TWI_IER_SCL_WS (0x1 << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */
-#define TWI_IER_EOSACC (0x1 << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */
-#define TWI_IER_ENDRX (0x1 << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */
-#define TWI_IER_ENDTX (0x1 << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */
-#define TWI_IER_RXBUFF (0x1 << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */
-#define TWI_IER_TXBUFE (0x1 << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */
-/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
-#define TWI_IDR_TXCOMP (0x1 << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */
-#define TWI_IDR_RXRDY (0x1 << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */
-#define TWI_IDR_TXRDY (0x1 << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */
-#define TWI_IDR_SVACC (0x1 << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */
-#define TWI_IDR_GACC (0x1 << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */
-#define TWI_IDR_OVRE (0x1 << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */
-#define TWI_IDR_NACK (0x1 << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */
-#define TWI_IDR_ARBLST (0x1 << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */
-#define TWI_IDR_SCL_WS (0x1 << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */
-#define TWI_IDR_EOSACC (0x1 << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */
-#define TWI_IDR_ENDRX (0x1 << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */
-#define TWI_IDR_ENDTX (0x1 << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */
-#define TWI_IDR_RXBUFF (0x1 << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */
-#define TWI_IDR_TXBUFE (0x1 << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */
-/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
-#define TWI_IMR_TXCOMP (0x1 << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */
-#define TWI_IMR_RXRDY (0x1 << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */
-#define TWI_IMR_TXRDY (0x1 << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */
-#define TWI_IMR_SVACC (0x1 << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */
-#define TWI_IMR_GACC (0x1 << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */
-#define TWI_IMR_OVRE (0x1 << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */
-#define TWI_IMR_NACK (0x1 << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */
-#define TWI_IMR_ARBLST (0x1 << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */
-#define TWI_IMR_SCL_WS (0x1 << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */
-#define TWI_IMR_EOSACC (0x1 << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */
-#define TWI_IMR_ENDRX (0x1 << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */
-#define TWI_IMR_ENDTX (0x1 << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */
-#define TWI_IMR_RXBUFF (0x1 << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */
-#define TWI_IMR_TXBUFE (0x1 << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */
-/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
-#define TWI_RHR_RXDATA (0xff << 0) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */
-/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
-#define TWI_THR_TXDATA (0xff << 0) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */
-/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */
-#define TWI_RPR_RXPTR (0xffffffff << 0) /**< \brief (TWI_RPR) Receive Pointer Register */
-/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */
-#define TWI_RCR_RXCTR (0xffff << 0) /**< \brief (TWI_RCR) Receive Counter Register */
-/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */
-#define TWI_TPR_TXPTR (0xffffffff << 0) /**< \brief (TWI_TPR) Transmit Counter Register */
-/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */
-#define TWI_TCR_TXCTR (0xffff << 0) /**< \brief (TWI_TCR) Transmit Counter Register */
-/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */
-#define TWI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (TWI_RNPR) Receive Next Pointer */
-/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */
-#define TWI_RNCR_RXNCTR (0xffff << 0) /**< \brief (TWI_RNCR) Receive Next Counter */
-/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */
-#define TWI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (TWI_TNPR) Transmit Next Pointer */
-/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */
-#define TWI_TNCR_TXNCTR (0xffff << 0) /**< \brief (TWI_TNCR) Transmit Counter Next */
-/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */
-#define TWI_PTCR_RXTEN (0x1 << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */
-#define TWI_PTCR_RXTDIS (0x1 << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */
-#define TWI_PTCR_TXTEN (0x1 << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */
-#define TWI_PTCR_TXTDIS (0x1 << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */
-/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */
-#define TWI_PTSR_RXTEN (0x1 << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */
-#define TWI_PTSR_TXTEN (0x1 << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3U_UART Universal Asynchronous Receiver Transmitter */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Uart hardware registers */
-typedef struct {
- WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */
- RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */
- WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
- WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
- RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
- RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */
- RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
- WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
- RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
- RwReg Reserved1[55];
- RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */
- RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */
- RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */
- RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */
- RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */
- RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */
- RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */
- RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */
- WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */
- RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */
-} Uart;
-#endif /* __ASSEMBLY__ */
-/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
-#define UART_CR_RSTRX (0x1 << 2) /**< \brief (UART_CR) Reset Receiver */
-#define UART_CR_RSTTX (0x1 << 3) /**< \brief (UART_CR) Reset Transmitter */
-#define UART_CR_RXEN (0x1 << 4) /**< \brief (UART_CR) Receiver Enable */
-#define UART_CR_RXDIS (0x1 << 5) /**< \brief (UART_CR) Receiver Disable */
-#define UART_CR_TXEN (0x1 << 6) /**< \brief (UART_CR) Transmitter Enable */
-#define UART_CR_TXDIS (0x1 << 7) /**< \brief (UART_CR) Transmitter Disable */
-#define UART_CR_RSTSTA (0x1 << 8) /**< \brief (UART_CR) Reset Status Bits */
-/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
-#define UART_MR_PAR (0x7 << 9) /**< \brief (UART_MR) Parity Type */
-#define UART_MR_CHMODE (0x3 << 14) /**< \brief (UART_MR) Channel Mode */
-/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
-#define UART_IER_RXRDY (0x1 << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
-#define UART_IER_TXRDY (0x1 << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
-#define UART_IER_ENDRX (0x1 << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */
-#define UART_IER_ENDTX (0x1 << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */
-#define UART_IER_OVRE (0x1 << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
-#define UART_IER_FRAME (0x1 << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
-#define UART_IER_PARE (0x1 << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
-#define UART_IER_TXEMPTY (0x1 << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
-#define UART_IER_TXBUFE (0x1 << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */
-#define UART_IER_RXBUFF (0x1 << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */
-/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
-#define UART_IDR_RXRDY (0x1 << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
-#define UART_IDR_TXRDY (0x1 << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
-#define UART_IDR_ENDRX (0x1 << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */
-#define UART_IDR_ENDTX (0x1 << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */
-#define UART_IDR_OVRE (0x1 << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
-#define UART_IDR_FRAME (0x1 << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
-#define UART_IDR_PARE (0x1 << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
-#define UART_IDR_TXEMPTY (0x1 << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
-#define UART_IDR_TXBUFE (0x1 << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */
-#define UART_IDR_RXBUFF (0x1 << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */
-/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
-#define UART_IMR_RXRDY (0x1 << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
-#define UART_IMR_TXRDY (0x1 << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
-#define UART_IMR_ENDRX (0x1 << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */
-#define UART_IMR_ENDTX (0x1 << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */
-#define UART_IMR_OVRE (0x1 << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
-#define UART_IMR_FRAME (0x1 << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
-#define UART_IMR_PARE (0x1 << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
-#define UART_IMR_TXEMPTY (0x1 << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
-#define UART_IMR_TXBUFE (0x1 << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */
-#define UART_IMR_RXBUFF (0x1 << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */
-/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
-#define UART_SR_RXRDY (0x1 << 0) /**< \brief (UART_SR) Receiver Ready */
-#define UART_SR_TXRDY (0x1 << 1) /**< \brief (UART_SR) Transmitter Ready */
-#define UART_SR_ENDRX (0x1 << 3) /**< \brief (UART_SR) End of Receiver Transfer */
-#define UART_SR_ENDTX (0x1 << 4) /**< \brief (UART_SR) End of Transmitter Transfer */
-#define UART_SR_OVRE (0x1 << 5) /**< \brief (UART_SR) Overrun Error */
-#define UART_SR_FRAME (0x1 << 6) /**< \brief (UART_SR) Framing Error */
-#define UART_SR_PARE (0x1 << 7) /**< \brief (UART_SR) Parity Error */
-#define UART_SR_TXEMPTY (0x1 << 9) /**< \brief (UART_SR) Transmitter Empty */
-#define UART_SR_TXBUFE (0x1 << 11) /**< \brief (UART_SR) Transmission Buffer Empty */
-#define UART_SR_RXBUFF (0x1 << 12) /**< \brief (UART_SR) Receive Buffer Full */
-/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
-#define UART_RHR_RXCHR (0xff << 0) /**< \brief (UART_RHR) Received Character */
-/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
-#define UART_THR_TXCHR (0xff << 0) /**< \brief (UART_THR) Character to be Transmitted */
-/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
-#define UART_BRGR_CD (0xffff << 0) /**< \brief (UART_BRGR) Clock Divisor */
-/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */
-#define UART_RPR_RXPTR (0xffffffff << 0) /**< \brief (UART_RPR) Receive Pointer Register */
-/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */
-#define UART_RCR_RXCTR (0xffff << 0) /**< \brief (UART_RCR) Receive Counter Register */
-/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */
-#define UART_TPR_TXPTR (0xffffffff << 0) /**< \brief (UART_TPR) Transmit Counter Register */
-/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */
-#define UART_TCR_TXCTR (0xffff << 0) /**< \brief (UART_TCR) Transmit Counter Register */
-/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */
-#define UART_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (UART_RNPR) Receive Next Pointer */
-/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */
-#define UART_RNCR_RXNCTR (0xffff << 0) /**< \brief (UART_RNCR) Receive Next Counter */
-/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */
-#define UART_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (UART_TNPR) Transmit Next Pointer */
-/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */
-#define UART_TNCR_TXNCTR (0xffff << 0) /**< \brief (UART_TNCR) Transmit Counter Next */
-/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */
-#define UART_PTCR_RXTEN (0x1 << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */
-#define UART_PTCR_RXTDIS (0x1 << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */
-#define UART_PTCR_TXTEN (0x1 << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */
-#define UART_PTCR_TXTDIS (0x1 << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */
-/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */
-#define UART_PTSR_RXTEN (0x1 << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */
-#define UART_PTSR_TXTEN (0x1 << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR USB High Speed Device Port */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3U_UDPHS USB High Speed Device Port */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief UdphsDma hardware registers */
-typedef struct {
- RwReg UDPHS_DMANXTDSC; /**< \brief (UdphsDma Offset: 0x0) UDPHS DMA Next Descriptor Address Register */
- RwReg UDPHS_DMAADDRESS; /**< \brief (UdphsDma Offset: 0x4) UDPHS DMA Channel Address Register */
- RwReg UDPHS_DMACONTROL; /**< \brief (UdphsDma Offset: 0x8) UDPHS DMA Channel Control Register */
- RwReg UDPHS_DMASTATUS; /**< \brief (UdphsDma Offset: 0xC) UDPHS DMA Channel Status Register */
-} UdphsDma;
-/** \brief UdphsEpt hardware registers */
-typedef struct {
- RwReg UDPHS_EPTCFG; /**< \brief (UdphsEpt Offset: 0x0) UDPHS Endpoint Configuration Register */
- RwReg UDPHS_EPTCTLENB; /**< \brief (UdphsEpt Offset: 0x4) UDPHS Endpoint Control Enable Register */
- RwReg UDPHS_EPTCTLDIS; /**< \brief (UdphsEpt Offset: 0x8) UDPHS Endpoint Control Disable Register */
- RwReg UDPHS_EPTCTL; /**< \brief (UdphsEpt Offset: 0xC) UDPHS Endpoint Control Register */
- RwReg Reserved1[1];
- RwReg UDPHS_EPTSETSTA; /**< \brief (UdphsEpt Offset: 0x14) UDPHS Endpoint Set Status Register */
- RwReg UDPHS_EPTCLRSTA; /**< \brief (UdphsEpt Offset: 0x18) UDPHS Endpoint Clear Status Register */
- RwReg UDPHS_EPTSTA; /**< \brief (UdphsEpt Offset: 0x1C) UDPHS Endpoint Status Register */
-} UdphsEpt;
-/** \brief Udphs hardware registers */
-typedef struct {
- RwReg UDPHS_CTRL; /**< \brief (Udphs Offset: 0x00) UDPHS Control Register */
- RoReg UDPHS_FNUM; /**< \brief (Udphs Offset: 0x04) UDPHS Frame Number Register */
- RwReg Reserved1[2];
- RwReg UDPHS_IEN; /**< \brief (Udphs Offset: 0x10) UDPHS Interrupt Enable Register */
- RoReg UDPHS_INTSTA; /**< \brief (Udphs Offset: 0x14) UDPHS Interrupt Status Register */
- WoReg UDPHS_CLRINT; /**< \brief (Udphs Offset: 0x18) UDPHS Clear Interrupt Register */
- WoReg UDPHS_EPTRST; /**< \brief (Udphs Offset: 0x1C) UDPHS Endpoints Reset Register */
- RwReg Reserved2[48];
- RwReg UDPHS_TST; /**< \brief (Udphs Offset: 0xE0) UDPHS Test Register */
- RwReg Reserved3[3];
- RoReg UDPHS_IPNAME1; /**< \brief (Udphs Offset: 0xF0) UDPHS Name1 Register */
- RoReg UDPHS_IPNAME2; /**< \brief (Udphs Offset: 0xF4) UDPHS Name2 Register */
- RoReg UDPHS_IPFEATURES; /**< \brief (Udphs Offset: 0xF8) UDPHS Features Register */
- RwReg Reserved4[1];
- UdphsEpt UDPHS_EPT[7]; /**< \brief (Udphs Offset: 0x100) endpoint = 0 .. 6 */
- RwReg Reserved5[80];
- UdphsDma UDPHS_DMA[5]; /**< \brief (Udphs Offset: 0x320) channel = 1 .. 5 */
-} Udphs;
-#endif /* __ASSEMBLY__ */
-/* -------- UDPHS_CTRL : (UDPHS Offset: 0x00) UDPHS Control Register -------- */
-#define UDPHS_CTRL_DEV_ADDR (0x7f << 0) /**< \brief (UDPHS_CTRL) UDPHS Address */
-#define UDPHS_CTRL_FADDR_EN (0x1 << 7) /**< \brief (UDPHS_CTRL) Function Address Enable */
-#define UDPHS_CTRL_EN_UDPHS (0x1 << 8) /**< \brief (UDPHS_CTRL) UDPHS Enable */
-#define UDPHS_CTRL_DETACH (0x1 << 9) /**< \brief (UDPHS_CTRL) Detach Command */
-#define UDPHS_CTRL_REWAKEUP (0x1 << 10) /**< \brief (UDPHS_CTRL) Send Remote Wake Up */
-#define UDPHS_CTRL_PULLD_DIS (0x1 << 11) /**< \brief (UDPHS_CTRL) Pull-Down Disable */
-/* -------- UDPHS_FNUM : (UDPHS Offset: 0x04) UDPHS Frame Number Register -------- */
-#define UDPHS_FNUM_MICRO_FRAME_NUM (0x7 << 0) /**< \brief (UDPHS_FNUM) Microframe Number */
-#define UDPHS_FNUM_FRAME_NUMBER (0x7ff << 3) /**< \brief (UDPHS_FNUM) Frame Number as defined in the Packet Field Formats */
-#define UDPHS_FNUM_FNUM_ERR (0x1 << 31) /**< \brief (UDPHS_FNUM) Frame Number CRC Error */
-/* -------- UDPHS_IEN : (UDPHS Offset: 0x10) UDPHS Interrupt Enable Register -------- */
-#define UDPHS_IEN_DET_SUSPD (0x1 << 1) /**< \brief (UDPHS_IEN) Suspend Interrupt Enable */
-#define UDPHS_IEN_MICRO_SOF (0x1 << 2) /**< \brief (UDPHS_IEN) Micro-SOF Interrupt Enable */
-#define UDPHS_IEN_INT_SOF (0x1 << 3) /**< \brief (UDPHS_IEN) SOF Interrupt Enable */
-#define UDPHS_IEN_ENDRESET (0x1 << 4) /**< \brief (UDPHS_IEN) End Of Reset Interrupt Enable */
-#define UDPHS_IEN_WAKE_UP (0x1 << 5) /**< \brief (UDPHS_IEN) Wake Up CPU Interrupt Enable */
-#define UDPHS_IEN_ENDOFRSM (0x1 << 6) /**< \brief (UDPHS_IEN) End Of Resume Interrupt Enable */
-#define UDPHS_IEN_UPSTR_RES (0x1 << 7) /**< \brief (UDPHS_IEN) Upstream Resume Interrupt Enable */
-#define UDPHS_IEN_EPT_0 (0x1 << 8) /**< \brief (UDPHS_IEN) Endpoint 0 Interrupt Enable */
-#define UDPHS_IEN_EPT_1 (0x1 << 9) /**< \brief (UDPHS_IEN) Endpoint 1 Interrupt Enable */
-#define UDPHS_IEN_EPT_2 (0x1 << 10) /**< \brief (UDPHS_IEN) Endpoint 2 Interrupt Enable */
-#define UDPHS_IEN_EPT_3 (0x1 << 11) /**< \brief (UDPHS_IEN) Endpoint 3 Interrupt Enable */
-#define UDPHS_IEN_EPT_4 (0x1 << 12) /**< \brief (UDPHS_IEN) Endpoint 4 Interrupt Enable */
-#define UDPHS_IEN_EPT_5 (0x1 << 13) /**< \brief (UDPHS_IEN) Endpoint 5 Interrupt Enable */
-#define UDPHS_IEN_EPT_6 (0x1 << 14) /**< \brief (UDPHS_IEN) Endpoint 6 Interrupt Enable */
-#define UDPHS_IEN_DMA_1 (0x1 << 25) /**< \brief (UDPHS_IEN) DMA Channel 1 Interrupt Enable */
-#define UDPHS_IEN_DMA_2 (0x1 << 26) /**< \brief (UDPHS_IEN) DMA Channel 2 Interrupt Enable */
-#define UDPHS_IEN_DMA_3 (0x1 << 27) /**< \brief (UDPHS_IEN) DMA Channel 3 Interrupt Enable */
-#define UDPHS_IEN_DMA_4 (0x1 << 28) /**< \brief (UDPHS_IEN) DMA Channel 4 Interrupt Enable */
-#define UDPHS_IEN_DMA_5 (0x1 << 29) /**< \brief (UDPHS_IEN) DMA Channel 5 Interrupt Enable */
-#define UDPHS_IEN_DMA_6 (0x1 << 30) /**< \brief (UDPHS_IEN) DMA Channel 6 Interrupt Enable */
-/* -------- UDPHS_INTSTA : (UDPHS Offset: 0x14) UDPHS Interrupt Status Register -------- */
-#define UDPHS_INTSTA_SPEED (0x1 << 0) /**< \brief (UDPHS_INTSTA) Speed Status */
-#define UDPHS_INTSTA_DET_SUSPD (0x1 << 1) /**< \brief (UDPHS_INTSTA) Suspend Interrupt */
-#define UDPHS_INTSTA_MICRO_SOF (0x1 << 2) /**< \brief (UDPHS_INTSTA) Micro Start Of Frame Interrupt */
-#define UDPHS_INTSTA_INT_SOF (0x1 << 3) /**< \brief (UDPHS_INTSTA) Start Of Frame Interrupt */
-#define UDPHS_INTSTA_ENDRESET (0x1 << 4) /**< \brief (UDPHS_INTSTA) End Of Reset Interrupt */
-#define UDPHS_INTSTA_WAKE_UP (0x1 << 5) /**< \brief (UDPHS_INTSTA) Wake Up CPU Interrupt */
-#define UDPHS_INTSTA_ENDOFRSM (0x1 << 6) /**< \brief (UDPHS_INTSTA) End Of Resume Interrupt */
-#define UDPHS_INTSTA_UPSTR_RES (0x1 << 7) /**< \brief (UDPHS_INTSTA) Upstream Resume Interrupt */
-#define UDPHS_INTSTA_EPT_0 (0x1 << 8) /**< \brief (UDPHS_INTSTA) Endpoint 0 Interrupt */
-#define UDPHS_INTSTA_EPT_1 (0x1 << 9) /**< \brief (UDPHS_INTSTA) Endpoint 1 Interrupt */
-#define UDPHS_INTSTA_EPT_2 (0x1 << 10) /**< \brief (UDPHS_INTSTA) Endpoint 2 Interrupt */
-#define UDPHS_INTSTA_EPT_3 (0x1 << 11) /**< \brief (UDPHS_INTSTA) Endpoint 3 Interrupt */
-#define UDPHS_INTSTA_EPT_4 (0x1 << 12) /**< \brief (UDPHS_INTSTA) Endpoint 4 Interrupt */
-#define UDPHS_INTSTA_EPT_5 (0x1 << 13) /**< \brief (UDPHS_INTSTA) Endpoint 5 Interrupt */
-#define UDPHS_INTSTA_EPT_6 (0x1 << 14) /**< \brief (UDPHS_INTSTA) Endpoint 6 Interrupt */
-#define UDPHS_INTSTA_DMA_1 (0x1 << 25) /**< \brief (UDPHS_INTSTA) DMA Channel 1 Interrupt */
-#define UDPHS_INTSTA_DMA_2 (0x1 << 26) /**< \brief (UDPHS_INTSTA) DMA Channel 2 Interrupt */
-#define UDPHS_INTSTA_DMA_3 (0x1 << 27) /**< \brief (UDPHS_INTSTA) DMA Channel 3 Interrupt */
-#define UDPHS_INTSTA_DMA_4 (0x1 << 28) /**< \brief (UDPHS_INTSTA) DMA Channel 4 Interrupt */
-#define UDPHS_INTSTA_DMA_5 (0x1 << 29) /**< \brief (UDPHS_INTSTA) DMA Channel 5 Interrupt */
-#define UDPHS_INTSTA_DMA_6 (0x1 << 30) /**< \brief (UDPHS_INTSTA) DMA Channel 6 Interrupt */
-/* -------- UDPHS_CLRINT : (UDPHS Offset: 0x18) UDPHS Clear Interrupt Register -------- */
-#define UDPHS_CLRINT_DET_SUSPD (0x1 << 1) /**< \brief (UDPHS_CLRINT) Suspend Interrupt Clear */
-#define UDPHS_CLRINT_MICRO_SOF (0x1 << 2) /**< \brief (UDPHS_CLRINT) Micro Start Of Frame Interrupt Clear */
-#define UDPHS_CLRINT_INT_SOF (0x1 << 3) /**< \brief (UDPHS_CLRINT) Start Of Frame Interrupt Clear */
-#define UDPHS_CLRINT_ENDRESET (0x1 << 4) /**< \brief (UDPHS_CLRINT) End Of Reset Interrupt Clear */
-#define UDPHS_CLRINT_WAKE_UP (0x1 << 5) /**< \brief (UDPHS_CLRINT) Wake Up CPU Interrupt Clear */
-#define UDPHS_CLRINT_ENDOFRSM (0x1 << 6) /**< \brief (UDPHS_CLRINT) End Of Resume Interrupt Clear */
-#define UDPHS_CLRINT_UPSTR_RES (0x1 << 7) /**< \brief (UDPHS_CLRINT) Upstream Resume Interrupt Clear */
-/* -------- UDPHS_EPTRST : (UDPHS Offset: 0x1C) UDPHS Endpoints Reset Register -------- */
-#define UDPHS_EPTRST_EPT_0 (0x1 << 0) /**< \brief (UDPHS_EPTRST) Endpoint 0 Reset */
-#define UDPHS_EPTRST_EPT_1 (0x1 << 1) /**< \brief (UDPHS_EPTRST) Endpoint 1 Reset */
-#define UDPHS_EPTRST_EPT_2 (0x1 << 2) /**< \brief (UDPHS_EPTRST) Endpoint 2 Reset */
-#define UDPHS_EPTRST_EPT_3 (0x1 << 3) /**< \brief (UDPHS_EPTRST) Endpoint 3 Reset */
-#define UDPHS_EPTRST_EPT_4 (0x1 << 4) /**< \brief (UDPHS_EPTRST) Endpoint 4 Reset */
-#define UDPHS_EPTRST_EPT_5 (0x1 << 5) /**< \brief (UDPHS_EPTRST) Endpoint 5 Reset */
-#define UDPHS_EPTRST_EPT_6 (0x1 << 6) /**< \brief (UDPHS_EPTRST) Endpoint 6 Reset */
-/* -------- UDPHS_TST : (UDPHS Offset: 0xE0) UDPHS Test Register -------- */
-#define UDPHS_TST_SPEED_CFG (0x3 << 0) /**< \brief (UDPHS_TST) Speed Configuration */
-#define UDPHS_TST_TST_J (0x1 << 2) /**< \brief (UDPHS_TST) Test J Mode */
-#define UDPHS_TST_TST_K (0x1 << 3) /**< \brief (UDPHS_TST) Test K Mode */
-#define UDPHS_TST_TST_PKT (0x1 << 4) /**< \brief (UDPHS_TST) Test Packet Mode */
-#define UDPHS_TST_OPMODE2 (0x1 << 5) /**< \brief (UDPHS_TST) OpMode2 */
-/* -------- UDPHS_IPNAME1 : (UDPHS Offset: 0xF0) UDPHS Name1 Register -------- */
-#define UDPHS_IPNAME1_IP_NAME1 (0xffffffff << 0) /**< \brief (UDPHS_IPNAME1) */
-/* -------- UDPHS_IPNAME2 : (UDPHS Offset: 0xF4) UDPHS Name2 Register -------- */
-#define UDPHS_IPNAME2_IP_NAME2 (0xffffffff << 0) /**< \brief (UDPHS_IPNAME2) */
-/* -------- UDPHS_IPFEATURES : (UDPHS Offset: 0xF8) UDPHS Features Register -------- */
-#define UDPHS_IPFEATURES_EPT_NBR_MAX (0xf << 0) /**< \brief (UDPHS_IPFEATURES) Max Number of Endpoints */
-#define UDPHS_IPFEATURES_DMA_CHANNEL_NBR (0x7 << 4) /**< \brief (UDPHS_IPFEATURES) Number of DMA Channels */
-#define UDPHS_IPFEATURES_DMA_B_SIZ (0x1 << 7) /**< \brief (UDPHS_IPFEATURES) DMA Buffer Size */
-#define UDPHS_IPFEATURES_DMA_FIFO_WORD_DEPTH (0xf << 8) /**< \brief (UDPHS_IPFEATURES) DMA FIFO Depth in Words */
-#define UDPHS_IPFEATURES_FIFO_MAX_SIZE (0x7 << 12) /**< \brief (UDPHS_IPFEATURES) DPRAM Size */
-#define UDPHS_IPFEATURES_BW_DPRAM (0x1 << 15) /**< \brief (UDPHS_IPFEATURES) DPRAM Byte Write Capability */
-#define UDPHS_IPFEATURES_DATAB16_8 (0x1 << 16) /**< \brief (UDPHS_IPFEATURES) UTMI DataBus16_8 */
-#define UDPHS_IPFEATURES_ISO_EPT_1 (0x1 << 17) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
-#define UDPHS_IPFEATURES_ISO_EPT_2 (0x1 << 18) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
-#define UDPHS_IPFEATURES_ISO_EPT_3 (0x1 << 19) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
-#define UDPHS_IPFEATURES_ISO_EPT_4 (0x1 << 20) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
-#define UDPHS_IPFEATURES_ISO_EPT_5 (0x1 << 21) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
-#define UDPHS_IPFEATURES_ISO_EPT_6 (0x1 << 22) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
-#define UDPHS_IPFEATURES_ISO_EPT_7 (0x1 << 23) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
-#define UDPHS_IPFEATURES_ISO_EPT_8 (0x1 << 24) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
-#define UDPHS_IPFEATURES_ISO_EPT_9 (0x1 << 25) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
-#define UDPHS_IPFEATURES_ISO_EPT_10 (0x1 << 26) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
-#define UDPHS_IPFEATURES_ISO_EPT_11 (0x1 << 27) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
-#define UDPHS_IPFEATURES_ISO_EPT_12 (0x1 << 28) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
-#define UDPHS_IPFEATURES_ISO_EPT_13 (0x1 << 29) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
-#define UDPHS_IPFEATURES_ISO_EPT_14 (0x1 << 30) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
-#define UDPHS_IPFEATURES_ISO_EPT_15 (0x1 << 31) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
-/* -------- UDPHS_EPTCFG0 : (UDPHS Offset: 0x100) UDPHS Endpoint Configuration Register (endpoint = 0) -------- */
-#define UDPHS_EPTCFG0_EPT_SIZE (0x7 << 0) /**< \brief (UDPHS_EPTCFG0) Endpoint Size */
-#define UDPHS_EPTCFG0_EPT_SIZE_8 (0x0 << 0) /**< \brief (UDPHS_EPTCFG0) 8 bytes */
-#define UDPHS_EPTCFG0_EPT_SIZE_16 (0x1 << 0) /**< \brief (UDPHS_EPTCFG0) 16 bytes */
-#define UDPHS_EPTCFG0_EPT_SIZE_32 (0x2 << 0) /**< \brief (UDPHS_EPTCFG0) 32 bytes */
-#define UDPHS_EPTCFG0_EPT_SIZE_64 (0x3 << 0) /**< \brief (UDPHS_EPTCFG0) 64 bytes */
-#define UDPHS_EPTCFG0_EPT_SIZE_128 (0x4 << 0) /**< \brief (UDPHS_EPTCFG0) 128 bytes */
-#define UDPHS_EPTCFG0_EPT_SIZE_256 (0x5 << 0) /**< \brief (UDPHS_EPTCFG0) 256 bytes */
-#define UDPHS_EPTCFG0_EPT_SIZE_512 (0x6 << 0) /**< \brief (UDPHS_EPTCFG0) 512 bytes */
-#define UDPHS_EPTCFG0_EPT_SIZE_1024 (0x7 << 0) /**< \brief (UDPHS_EPTCFG0) 1024 bytes */
-#define UDPHS_EPTCFG0_EPT_DIR (0x1 << 3) /**< \brief (UDPHS_EPTCFG0) Endpoint Direction */
-#define UDPHS_EPTCFG0_EPT_DIR_OUT (0x0 << 3) /**< \brief (UDPHS_EPTCFG0) Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. */
-#define UDPHS_EPTCFG0_EPT_DIR_IN (0x1 << 3) /**< \brief (UDPHS_EPTCFG0) set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. */
-#define UDPHS_EPTCFG0_EPT_TYPE (0x3 << 4) /**< \brief (UDPHS_EPTCFG0) Endpoint Type */
-#define UDPHS_EPTCFG0_EPT_TYPE_CTL_EPT (0x0 << 4) /**< \brief (UDPHS_EPTCFG0) Control endpoint */
-#define UDPHS_EPTCFG0_EPT_TYPE_ISO_EPT (0x1 << 4) /**< \brief (UDPHS_EPTCFG0) Isochronous endpoint */
-#define UDPHS_EPTCFG0_EPT_TYPE_BUL_EPT (0x2 << 4) /**< \brief (UDPHS_EPTCFG0) Bulk endpoint */
-#define UDPHS_EPTCFG0_EPT_TYPE_INT_EPT (0x3 << 4) /**< \brief (UDPHS_EPTCFG0) Interrupt endpoint */
-#define UDPHS_EPTCFG0_BK_NUMBER (0x3 << 6) /**< \brief (UDPHS_EPTCFG0) Number of Banks */
-#define UDPHS_EPTCFG0_BK_NUMBER_0 (0x0 << 6) /**< \brief (UDPHS_EPTCFG0) Zero bank, the endpoint is not mapped in memory */
-#define UDPHS_EPTCFG0_BK_NUMBER_1 (0x1 << 6) /**< \brief (UDPHS_EPTCFG0) One bank (bank 0) */
-#define UDPHS_EPTCFG0_BK_NUMBER_2 (0x2 << 6) /**< \brief (UDPHS_EPTCFG0) Double bank (Ping-Pong: bank 0/bank 1) */
-#define UDPHS_EPTCFG0_BK_NUMBER_3 (0x3 << 6) /**< \brief (UDPHS_EPTCFG0) Triple bank (bank 0/bank 1/bank 2) */
-#define UDPHS_EPTCFG0_NB_TRANS (0x3 << 8) /**< \brief (UDPHS_EPTCFG0) Number Of Transaction per Microframe */
-#define UDPHS_EPTCFG0_EPT_MAPD (0x1 << 31) /**< \brief (UDPHS_EPTCFG0) Endpoint Mapped */
-/* -------- UDPHS_EPTCTLENB0 : (UDPHS Offset: 0x104) UDPHS Endpoint Control Enable Register (endpoint = 0) -------- */
-#define UDPHS_EPTCTLENB0_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLENB0) Endpoint Enable */
-#define UDPHS_EPTCTLENB0_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLENB0) Packet Auto-Valid Enable */
-#define UDPHS_EPTCTLENB0_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLENB0) Interrupts Disable DMA */
-#define UDPHS_EPTCTLENB0_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLENB0) NYET Disable (Only for High Speed Bulk OUT endpoints) */
-#define UDPHS_EPTCTLENB0_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLENB0) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLENB0_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLENB0) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLENB0_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLENB0) Overflow Error Interrupt Enable */
-#define UDPHS_EPTCTLENB0_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLENB0) Received OUT Data Interrupt Enable */
-#define UDPHS_EPTCTLENB0_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLENB0) Transmitted IN Data Complete Interrupt Enable */
-#define UDPHS_EPTCTLENB0_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLENB0) TX Packet Ready/Transaction Error Interrupt Enable */
-#define UDPHS_EPTCTLENB0_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLENB0) Received SETUP/Error Flow Interrupt Enable */
-#define UDPHS_EPTCTLENB0_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLENB0) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */
-#define UDPHS_EPTCTLENB0_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLENB0) NAKIN/Bank Flush Error Interrupt Enable */
-#define UDPHS_EPTCTLENB0_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLENB0) NAKOUT Interrupt Enable */
-#define UDPHS_EPTCTLENB0_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLENB0) Busy Bank Interrupt Enable */
-#define UDPHS_EPTCTLENB0_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLENB0) Short Packet Send/Short Packet Interrupt Enable */
-/* -------- UDPHS_EPTCTLDIS0 : (UDPHS Offset: 0x108) UDPHS Endpoint Control Disable Register (endpoint = 0) -------- */
-#define UDPHS_EPTCTLDIS0_EPT_DISABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLDIS0) Endpoint Disable */
-#define UDPHS_EPTCTLDIS0_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLDIS0) Packet Auto-Valid Disable */
-#define UDPHS_EPTCTLDIS0_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLDIS0) Interrupts Disable DMA */
-#define UDPHS_EPTCTLDIS0_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLDIS0) NYET Enable (Only for High Speed Bulk OUT endpoints) */
-#define UDPHS_EPTCTLDIS0_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLDIS0) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLDIS0_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLDIS0) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLDIS0_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLDIS0) Overflow Error Interrupt Disable */
-#define UDPHS_EPTCTLDIS0_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLDIS0) Received OUT Data Interrupt Disable */
-#define UDPHS_EPTCTLDIS0_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLDIS0) Transmitted IN Data Complete Interrupt Disable */
-#define UDPHS_EPTCTLDIS0_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLDIS0) TX Packet Ready/Transaction Error Interrupt Disable */
-#define UDPHS_EPTCTLDIS0_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLDIS0) Received SETUP/Error Flow Interrupt Disable */
-#define UDPHS_EPTCTLDIS0_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLDIS0) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */
-#define UDPHS_EPTCTLDIS0_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLDIS0) NAKIN/bank flush error Interrupt Disable */
-#define UDPHS_EPTCTLDIS0_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLDIS0) NAKOUT Interrupt Disable */
-#define UDPHS_EPTCTLDIS0_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLDIS0) Busy Bank Interrupt Disable */
-#define UDPHS_EPTCTLDIS0_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLDIS0) Short Packet Interrupt Disable */
-/* -------- UDPHS_EPTCTL0 : (UDPHS Offset: 0x10C) UDPHS Endpoint Control Register (endpoint = 0) -------- */
-#define UDPHS_EPTCTL0_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTL0) Endpoint Enable */
-#define UDPHS_EPTCTL0_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTL0) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */
-#define UDPHS_EPTCTL0_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTL0) Interrupt Disables DMA */
-#define UDPHS_EPTCTL0_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTL0) NYET Disable (Only for High Speed Bulk OUT endpoints) */
-#define UDPHS_EPTCTL0_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTL0) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTL0_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTL0) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTL0_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTL0) Overflow Error Interrupt Enabled */
-#define UDPHS_EPTCTL0_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTL0) Received OUT Data Interrupt Enabled */
-#define UDPHS_EPTCTL0_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTL0) Transmitted IN Data Complete Interrupt Enabled */
-#define UDPHS_EPTCTL0_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTL0) TX Packet Ready/Transaction Error Interrupt Enabled */
-#define UDPHS_EPTCTL0_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTL0) Received SETUP/Error Flow Interrupt Enabled */
-#define UDPHS_EPTCTL0_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTL0) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */
-#define UDPHS_EPTCTL0_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTL0) NAKIN/Bank Flush Error Interrupt Enabled */
-#define UDPHS_EPTCTL0_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTL0) NAKOUT Interrupt Enabled */
-#define UDPHS_EPTCTL0_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTL0) Busy Bank Interrupt Enabled */
-#define UDPHS_EPTCTL0_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTL0) Short Packet Interrupt Enabled */
-/* -------- UDPHS_EPTSETSTA0 : (UDPHS Offset: 0x114) UDPHS Endpoint Set Status Register (endpoint = 0) -------- */
-#define UDPHS_EPTSETSTA0_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSETSTA0) Stall Handshake Request Set */
-#define UDPHS_EPTSETSTA0_KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSETSTA0) KILL Bank Set (for IN Endpoint) */
-#define UDPHS_EPTSETSTA0_TX_PK_RDY (0x1 << 11) /**< \brief (UDPHS_EPTSETSTA0) TX Packet Ready Set */
-/* -------- UDPHS_EPTCLRSTA0 : (UDPHS Offset: 0x118) UDPHS Endpoint Clear Status Register (endpoint = 0) -------- */
-#define UDPHS_EPTCLRSTA0_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTCLRSTA0) Stall Handshake Request Clear */
-#define UDPHS_EPTCLRSTA0_TOGGLESQ (0x1 << 6) /**< \brief (UDPHS_EPTCLRSTA0) Data Toggle Clear */
-#define UDPHS_EPTCLRSTA0_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCLRSTA0) Received OUT Data Clear */
-#define UDPHS_EPTCLRSTA0_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCLRSTA0) Transmitted IN Data Complete Clear */
-#define UDPHS_EPTCLRSTA0_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCLRSTA0) Received SETUP/Error Flow Clear */
-#define UDPHS_EPTCLRSTA0_STALL_SNT__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCLRSTA0) Stall Sent/Number of Transaction Error Clear */
-#define UDPHS_EPTCLRSTA0_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCLRSTA0) NAKIN/Bank Flush Error Clear */
-#define UDPHS_EPTCLRSTA0_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCLRSTA0) NAKOUT Clear */
-/* -------- UDPHS_EPTSTA0 : (UDPHS Offset: 0x11C) UDPHS Endpoint Status Register (endpoint = 0) -------- */
-#define UDPHS_EPTSTA0_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSTA0) Stall Handshake Request */
-#define UDPHS_EPTSTA0_TOGGLESQ_STA (0x3 << 6) /**< \brief (UDPHS_EPTSTA0) Toggle Sequencing */
-#define UDPHS_EPTSTA0_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTSTA0) Overflow Error */
-#define UDPHS_EPTSTA0_RX_BK_RDY__KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSTA0) Received OUT Data/KILL Bank */
-#define UDPHS_EPTSTA0_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTSTA0) Transmitted IN Data Complete */
-#define UDPHS_EPTSTA0_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTSTA0) TX Packet Ready/Transaction Error */
-#define UDPHS_EPTSTA0_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTSTA0) Received SETUP/Error Flow */
-#define UDPHS_EPTSTA0_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTSTA0) Stall Sent/CRC ISO Error/Number of Transaction Error */
-#define UDPHS_EPTSTA0_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTSTA0) NAK IN/Bank Flush Error */
-#define UDPHS_EPTSTA0_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTSTA0) NAK OUT */
-#define UDPHS_EPTSTA0_CURRENT_BANK__CONTROL_DIR (0x3 << 16) /**< \brief (UDPHS_EPTSTA0) Current Bank/Control Direction */
-#define UDPHS_EPTSTA0_BUSY_BANK_STA (0x3 << 18) /**< \brief (UDPHS_EPTSTA0) Busy Bank Number */
-#define UDPHS_EPTSTA0_BYTE_COUNT (0x7ff << 20) /**< \brief (UDPHS_EPTSTA0) UDPHS Byte Count */
-#define UDPHS_EPTSTA0_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTSTA0) Short Packet */
-/* -------- UDPHS_EPTCFG1 : (UDPHS Offset: 0x120) UDPHS Endpoint Configuration Register (endpoint = 1) -------- */
-#define UDPHS_EPTCFG1_EPT_SIZE (0x7 << 0) /**< \brief (UDPHS_EPTCFG1) Endpoint Size */
-#define UDPHS_EPTCFG1_EPT_SIZE_8 (0x0 << 0) /**< \brief (UDPHS_EPTCFG1) 8 bytes */
-#define UDPHS_EPTCFG1_EPT_SIZE_16 (0x1 << 0) /**< \brief (UDPHS_EPTCFG1) 16 bytes */
-#define UDPHS_EPTCFG1_EPT_SIZE_32 (0x2 << 0) /**< \brief (UDPHS_EPTCFG1) 32 bytes */
-#define UDPHS_EPTCFG1_EPT_SIZE_64 (0x3 << 0) /**< \brief (UDPHS_EPTCFG1) 64 bytes */
-#define UDPHS_EPTCFG1_EPT_SIZE_128 (0x4 << 0) /**< \brief (UDPHS_EPTCFG1) 128 bytes */
-#define UDPHS_EPTCFG1_EPT_SIZE_256 (0x5 << 0) /**< \brief (UDPHS_EPTCFG1) 256 bytes */
-#define UDPHS_EPTCFG1_EPT_SIZE_512 (0x6 << 0) /**< \brief (UDPHS_EPTCFG1) 512 bytes */
-#define UDPHS_EPTCFG1_EPT_SIZE_1024 (0x7 << 0) /**< \brief (UDPHS_EPTCFG1) 1024 bytes */
-#define UDPHS_EPTCFG1_EPT_DIR (0x1 << 3) /**< \brief (UDPHS_EPTCFG1) Endpoint Direction */
-#define UDPHS_EPTCFG1_EPT_DIR_OUT (0x0 << 3) /**< \brief (UDPHS_EPTCFG1) Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. */
-#define UDPHS_EPTCFG1_EPT_DIR_IN (0x1 << 3) /**< \brief (UDPHS_EPTCFG1) set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. */
-#define UDPHS_EPTCFG1_EPT_TYPE (0x3 << 4) /**< \brief (UDPHS_EPTCFG1) Endpoint Type */
-#define UDPHS_EPTCFG1_EPT_TYPE_CTL_EPT (0x0 << 4) /**< \brief (UDPHS_EPTCFG1) Control endpoint */
-#define UDPHS_EPTCFG1_EPT_TYPE_ISO_EPT (0x1 << 4) /**< \brief (UDPHS_EPTCFG1) Isochronous endpoint */
-#define UDPHS_EPTCFG1_EPT_TYPE_BUL_EPT (0x2 << 4) /**< \brief (UDPHS_EPTCFG1) Bulk endpoint */
-#define UDPHS_EPTCFG1_EPT_TYPE_INT_EPT (0x3 << 4) /**< \brief (UDPHS_EPTCFG1) Interrupt endpoint */
-#define UDPHS_EPTCFG1_BK_NUMBER (0x3 << 6) /**< \brief (UDPHS_EPTCFG1) Number of Banks */
-#define UDPHS_EPTCFG1_BK_NUMBER_0 (0x0 << 6) /**< \brief (UDPHS_EPTCFG1) Zero bank, the endpoint is not mapped in memory */
-#define UDPHS_EPTCFG1_BK_NUMBER_1 (0x1 << 6) /**< \brief (UDPHS_EPTCFG1) One bank (bank 0) */
-#define UDPHS_EPTCFG1_BK_NUMBER_2 (0x2 << 6) /**< \brief (UDPHS_EPTCFG1) Double bank (Ping-Pong: bank 0/bank 1) */
-#define UDPHS_EPTCFG1_BK_NUMBER_3 (0x3 << 6) /**< \brief (UDPHS_EPTCFG1) Triple bank (bank 0/bank 1/bank 2) */
-#define UDPHS_EPTCFG1_NB_TRANS (0x3 << 8) /**< \brief (UDPHS_EPTCFG1) Number Of Transaction per Microframe */
-#define UDPHS_EPTCFG1_EPT_MAPD (0x1 << 31) /**< \brief (UDPHS_EPTCFG1) Endpoint Mapped */
-/* -------- UDPHS_EPTCTLENB1 : (UDPHS Offset: 0x124) UDPHS Endpoint Control Enable Register (endpoint = 1) -------- */
-#define UDPHS_EPTCTLENB1_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLENB1) Endpoint Enable */
-#define UDPHS_EPTCTLENB1_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLENB1) Packet Auto-Valid Enable */
-#define UDPHS_EPTCTLENB1_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLENB1) Interrupts Disable DMA */
-#define UDPHS_EPTCTLENB1_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLENB1) NYET Disable (Only for High Speed Bulk OUT endpoints) */
-#define UDPHS_EPTCTLENB1_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLENB1) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLENB1_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLENB1) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLENB1_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLENB1) Overflow Error Interrupt Enable */
-#define UDPHS_EPTCTLENB1_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLENB1) Received OUT Data Interrupt Enable */
-#define UDPHS_EPTCTLENB1_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLENB1) Transmitted IN Data Complete Interrupt Enable */
-#define UDPHS_EPTCTLENB1_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLENB1) TX Packet Ready/Transaction Error Interrupt Enable */
-#define UDPHS_EPTCTLENB1_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLENB1) Received SETUP/Error Flow Interrupt Enable */
-#define UDPHS_EPTCTLENB1_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLENB1) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */
-#define UDPHS_EPTCTLENB1_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLENB1) NAKIN/Bank Flush Error Interrupt Enable */
-#define UDPHS_EPTCTLENB1_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLENB1) NAKOUT Interrupt Enable */
-#define UDPHS_EPTCTLENB1_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLENB1) Busy Bank Interrupt Enable */
-#define UDPHS_EPTCTLENB1_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLENB1) Short Packet Send/Short Packet Interrupt Enable */
-/* -------- UDPHS_EPTCTLDIS1 : (UDPHS Offset: 0x128) UDPHS Endpoint Control Disable Register (endpoint = 1) -------- */
-#define UDPHS_EPTCTLDIS1_EPT_DISABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLDIS1) Endpoint Disable */
-#define UDPHS_EPTCTLDIS1_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLDIS1) Packet Auto-Valid Disable */
-#define UDPHS_EPTCTLDIS1_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLDIS1) Interrupts Disable DMA */
-#define UDPHS_EPTCTLDIS1_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLDIS1) NYET Enable (Only for High Speed Bulk OUT endpoints) */
-#define UDPHS_EPTCTLDIS1_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLDIS1) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLDIS1_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLDIS1) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLDIS1_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLDIS1) Overflow Error Interrupt Disable */
-#define UDPHS_EPTCTLDIS1_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLDIS1) Received OUT Data Interrupt Disable */
-#define UDPHS_EPTCTLDIS1_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLDIS1) Transmitted IN Data Complete Interrupt Disable */
-#define UDPHS_EPTCTLDIS1_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLDIS1) TX Packet Ready/Transaction Error Interrupt Disable */
-#define UDPHS_EPTCTLDIS1_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLDIS1) Received SETUP/Error Flow Interrupt Disable */
-#define UDPHS_EPTCTLDIS1_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLDIS1) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */
-#define UDPHS_EPTCTLDIS1_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLDIS1) NAKIN/bank flush error Interrupt Disable */
-#define UDPHS_EPTCTLDIS1_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLDIS1) NAKOUT Interrupt Disable */
-#define UDPHS_EPTCTLDIS1_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLDIS1) Busy Bank Interrupt Disable */
-#define UDPHS_EPTCTLDIS1_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLDIS1) Short Packet Interrupt Disable */
-/* -------- UDPHS_EPTCTL1 : (UDPHS Offset: 0x12C) UDPHS Endpoint Control Register (endpoint = 1) -------- */
-#define UDPHS_EPTCTL1_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTL1) Endpoint Enable */
-#define UDPHS_EPTCTL1_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTL1) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */
-#define UDPHS_EPTCTL1_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTL1) Interrupt Disables DMA */
-#define UDPHS_EPTCTL1_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTL1) NYET Disable (Only for High Speed Bulk OUT endpoints) */
-#define UDPHS_EPTCTL1_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTL1) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTL1_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTL1) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTL1_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTL1) Overflow Error Interrupt Enabled */
-#define UDPHS_EPTCTL1_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTL1) Received OUT Data Interrupt Enabled */
-#define UDPHS_EPTCTL1_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTL1) Transmitted IN Data Complete Interrupt Enabled */
-#define UDPHS_EPTCTL1_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTL1) TX Packet Ready/Transaction Error Interrupt Enabled */
-#define UDPHS_EPTCTL1_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTL1) Received SETUP/Error Flow Interrupt Enabled */
-#define UDPHS_EPTCTL1_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTL1) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */
-#define UDPHS_EPTCTL1_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTL1) NAKIN/Bank Flush Error Interrupt Enabled */
-#define UDPHS_EPTCTL1_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTL1) NAKOUT Interrupt Enabled */
-#define UDPHS_EPTCTL1_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTL1) Busy Bank Interrupt Enabled */
-#define UDPHS_EPTCTL1_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTL1) Short Packet Interrupt Enabled */
-/* -------- UDPHS_EPTSETSTA1 : (UDPHS Offset: 0x134) UDPHS Endpoint Set Status Register (endpoint = 1) -------- */
-#define UDPHS_EPTSETSTA1_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSETSTA1) Stall Handshake Request Set */
-#define UDPHS_EPTSETSTA1_KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSETSTA1) KILL Bank Set (for IN Endpoint) */
-#define UDPHS_EPTSETSTA1_TX_PK_RDY (0x1 << 11) /**< \brief (UDPHS_EPTSETSTA1) TX Packet Ready Set */
-/* -------- UDPHS_EPTCLRSTA1 : (UDPHS Offset: 0x138) UDPHS Endpoint Clear Status Register (endpoint = 1) -------- */
-#define UDPHS_EPTCLRSTA1_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTCLRSTA1) Stall Handshake Request Clear */
-#define UDPHS_EPTCLRSTA1_TOGGLESQ (0x1 << 6) /**< \brief (UDPHS_EPTCLRSTA1) Data Toggle Clear */
-#define UDPHS_EPTCLRSTA1_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCLRSTA1) Received OUT Data Clear */
-#define UDPHS_EPTCLRSTA1_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCLRSTA1) Transmitted IN Data Complete Clear */
-#define UDPHS_EPTCLRSTA1_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCLRSTA1) Received SETUP/Error Flow Clear */
-#define UDPHS_EPTCLRSTA1_STALL_SNT__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCLRSTA1) Stall Sent/Number of Transaction Error Clear */
-#define UDPHS_EPTCLRSTA1_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCLRSTA1) NAKIN/Bank Flush Error Clear */
-#define UDPHS_EPTCLRSTA1_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCLRSTA1) NAKOUT Clear */
-/* -------- UDPHS_EPTSTA1 : (UDPHS Offset: 0x13C) UDPHS Endpoint Status Register (endpoint = 1) -------- */
-#define UDPHS_EPTSTA1_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSTA1) Stall Handshake Request */
-#define UDPHS_EPTSTA1_TOGGLESQ_STA (0x3 << 6) /**< \brief (UDPHS_EPTSTA1) Toggle Sequencing */
-#define UDPHS_EPTSTA1_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTSTA1) Overflow Error */
-#define UDPHS_EPTSTA1_RX_BK_RDY__KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSTA1) Received OUT Data/KILL Bank */
-#define UDPHS_EPTSTA1_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTSTA1) Transmitted IN Data Complete */
-#define UDPHS_EPTSTA1_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTSTA1) TX Packet Ready/Transaction Error */
-#define UDPHS_EPTSTA1_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTSTA1) Received SETUP/Error Flow */
-#define UDPHS_EPTSTA1_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTSTA1) Stall Sent/CRC ISO Error/Number of Transaction Error */
-#define UDPHS_EPTSTA1_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTSTA1) NAK IN/Bank Flush Error */
-#define UDPHS_EPTSTA1_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTSTA1) NAK OUT */
-#define UDPHS_EPTSTA1_CURRENT_BANK__CONTROL_DIR (0x3 << 16) /**< \brief (UDPHS_EPTSTA1) Current Bank/Control Direction */
-#define UDPHS_EPTSTA1_BUSY_BANK_STA (0x3 << 18) /**< \brief (UDPHS_EPTSTA1) Busy Bank Number */
-#define UDPHS_EPTSTA1_BYTE_COUNT (0x7ff << 20) /**< \brief (UDPHS_EPTSTA1) UDPHS Byte Count */
-#define UDPHS_EPTSTA1_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTSTA1) Short Packet */
-/* -------- UDPHS_EPTCFG2 : (UDPHS Offset: 0x140) UDPHS Endpoint Configuration Register (endpoint = 2) -------- */
-#define UDPHS_EPTCFG2_EPT_SIZE (0x7 << 0) /**< \brief (UDPHS_EPTCFG2) Endpoint Size */
-#define UDPHS_EPTCFG2_EPT_SIZE_8 (0x0 << 0) /**< \brief (UDPHS_EPTCFG2) 8 bytes */
-#define UDPHS_EPTCFG2_EPT_SIZE_16 (0x1 << 0) /**< \brief (UDPHS_EPTCFG2) 16 bytes */
-#define UDPHS_EPTCFG2_EPT_SIZE_32 (0x2 << 0) /**< \brief (UDPHS_EPTCFG2) 32 bytes */
-#define UDPHS_EPTCFG2_EPT_SIZE_64 (0x3 << 0) /**< \brief (UDPHS_EPTCFG2) 64 bytes */
-#define UDPHS_EPTCFG2_EPT_SIZE_128 (0x4 << 0) /**< \brief (UDPHS_EPTCFG2) 128 bytes */
-#define UDPHS_EPTCFG2_EPT_SIZE_256 (0x5 << 0) /**< \brief (UDPHS_EPTCFG2) 256 bytes */
-#define UDPHS_EPTCFG2_EPT_SIZE_512 (0x6 << 0) /**< \brief (UDPHS_EPTCFG2) 512 bytes */
-#define UDPHS_EPTCFG2_EPT_SIZE_1024 (0x7 << 0) /**< \brief (UDPHS_EPTCFG2) 1024 bytes */
-#define UDPHS_EPTCFG2_EPT_DIR (0x1 << 3) /**< \brief (UDPHS_EPTCFG2) Endpoint Direction */
-#define UDPHS_EPTCFG2_EPT_DIR_OUT (0x0 << 3) /**< \brief (UDPHS_EPTCFG2) Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. */
-#define UDPHS_EPTCFG2_EPT_DIR_IN (0x1 << 3) /**< \brief (UDPHS_EPTCFG2) set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. */
-#define UDPHS_EPTCFG2_EPT_TYPE (0x3 << 4) /**< \brief (UDPHS_EPTCFG2) Endpoint Type */
-#define UDPHS_EPTCFG2_EPT_TYPE_CTL_EPT (0x0 << 4) /**< \brief (UDPHS_EPTCFG2) Control endpoint */
-#define UDPHS_EPTCFG2_EPT_TYPE_ISO_EPT (0x1 << 4) /**< \brief (UDPHS_EPTCFG2) Isochronous endpoint */
-#define UDPHS_EPTCFG2_EPT_TYPE_BUL_EPT (0x2 << 4) /**< \brief (UDPHS_EPTCFG2) Bulk endpoint */
-#define UDPHS_EPTCFG2_EPT_TYPE_INT_EPT (0x3 << 4) /**< \brief (UDPHS_EPTCFG2) Interrupt endpoint */
-#define UDPHS_EPTCFG2_BK_NUMBER (0x3 << 6) /**< \brief (UDPHS_EPTCFG2) Number of Banks */
-#define UDPHS_EPTCFG2_BK_NUMBER_0 (0x0 << 6) /**< \brief (UDPHS_EPTCFG2) Zero bank, the endpoint is not mapped in memory */
-#define UDPHS_EPTCFG2_BK_NUMBER_1 (0x1 << 6) /**< \brief (UDPHS_EPTCFG2) One bank (bank 0) */
-#define UDPHS_EPTCFG2_BK_NUMBER_2 (0x2 << 6) /**< \brief (UDPHS_EPTCFG2) Double bank (Ping-Pong: bank 0/bank 1) */
-#define UDPHS_EPTCFG2_BK_NUMBER_3 (0x3 << 6) /**< \brief (UDPHS_EPTCFG2) Triple bank (bank 0/bank 1/bank 2) */
-#define UDPHS_EPTCFG2_NB_TRANS (0x3 << 8) /**< \brief (UDPHS_EPTCFG2) Number Of Transaction per Microframe */
-#define UDPHS_EPTCFG2_EPT_MAPD (0x1 << 31) /**< \brief (UDPHS_EPTCFG2) Endpoint Mapped */
-/* -------- UDPHS_EPTCTLENB2 : (UDPHS Offset: 0x144) UDPHS Endpoint Control Enable Register (endpoint = 2) -------- */
-#define UDPHS_EPTCTLENB2_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLENB2) Endpoint Enable */
-#define UDPHS_EPTCTLENB2_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLENB2) Packet Auto-Valid Enable */
-#define UDPHS_EPTCTLENB2_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLENB2) Interrupts Disable DMA */
-#define UDPHS_EPTCTLENB2_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLENB2) NYET Disable (Only for High Speed Bulk OUT endpoints) */
-#define UDPHS_EPTCTLENB2_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLENB2) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLENB2_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLENB2) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLENB2_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLENB2) Overflow Error Interrupt Enable */
-#define UDPHS_EPTCTLENB2_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLENB2) Received OUT Data Interrupt Enable */
-#define UDPHS_EPTCTLENB2_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLENB2) Transmitted IN Data Complete Interrupt Enable */
-#define UDPHS_EPTCTLENB2_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLENB2) TX Packet Ready/Transaction Error Interrupt Enable */
-#define UDPHS_EPTCTLENB2_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLENB2) Received SETUP/Error Flow Interrupt Enable */
-#define UDPHS_EPTCTLENB2_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLENB2) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */
-#define UDPHS_EPTCTLENB2_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLENB2) NAKIN/Bank Flush Error Interrupt Enable */
-#define UDPHS_EPTCTLENB2_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLENB2) NAKOUT Interrupt Enable */
-#define UDPHS_EPTCTLENB2_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLENB2) Busy Bank Interrupt Enable */
-#define UDPHS_EPTCTLENB2_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLENB2) Short Packet Send/Short Packet Interrupt Enable */
-/* -------- UDPHS_EPTCTLDIS2 : (UDPHS Offset: 0x148) UDPHS Endpoint Control Disable Register (endpoint = 2) -------- */
-#define UDPHS_EPTCTLDIS2_EPT_DISABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLDIS2) Endpoint Disable */
-#define UDPHS_EPTCTLDIS2_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLDIS2) Packet Auto-Valid Disable */
-#define UDPHS_EPTCTLDIS2_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLDIS2) Interrupts Disable DMA */
-#define UDPHS_EPTCTLDIS2_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLDIS2) NYET Enable (Only for High Speed Bulk OUT endpoints) */
-#define UDPHS_EPTCTLDIS2_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLDIS2) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLDIS2_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLDIS2) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLDIS2_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLDIS2) Overflow Error Interrupt Disable */
-#define UDPHS_EPTCTLDIS2_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLDIS2) Received OUT Data Interrupt Disable */
-#define UDPHS_EPTCTLDIS2_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLDIS2) Transmitted IN Data Complete Interrupt Disable */
-#define UDPHS_EPTCTLDIS2_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLDIS2) TX Packet Ready/Transaction Error Interrupt Disable */
-#define UDPHS_EPTCTLDIS2_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLDIS2) Received SETUP/Error Flow Interrupt Disable */
-#define UDPHS_EPTCTLDIS2_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLDIS2) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */
-#define UDPHS_EPTCTLDIS2_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLDIS2) NAKIN/bank flush error Interrupt Disable */
-#define UDPHS_EPTCTLDIS2_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLDIS2) NAKOUT Interrupt Disable */
-#define UDPHS_EPTCTLDIS2_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLDIS2) Busy Bank Interrupt Disable */
-#define UDPHS_EPTCTLDIS2_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLDIS2) Short Packet Interrupt Disable */
-/* -------- UDPHS_EPTCTL2 : (UDPHS Offset: 0x14C) UDPHS Endpoint Control Register (endpoint = 2) -------- */
-#define UDPHS_EPTCTL2_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTL2) Endpoint Enable */
-#define UDPHS_EPTCTL2_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTL2) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */
-#define UDPHS_EPTCTL2_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTL2) Interrupt Disables DMA */
-#define UDPHS_EPTCTL2_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTL2) NYET Disable (Only for High Speed Bulk OUT endpoints) */
-#define UDPHS_EPTCTL2_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTL2) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTL2_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTL2) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTL2_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTL2) Overflow Error Interrupt Enabled */
-#define UDPHS_EPTCTL2_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTL2) Received OUT Data Interrupt Enabled */
-#define UDPHS_EPTCTL2_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTL2) Transmitted IN Data Complete Interrupt Enabled */
-#define UDPHS_EPTCTL2_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTL2) TX Packet Ready/Transaction Error Interrupt Enabled */
-#define UDPHS_EPTCTL2_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTL2) Received SETUP/Error Flow Interrupt Enabled */
-#define UDPHS_EPTCTL2_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTL2) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */
-#define UDPHS_EPTCTL2_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTL2) NAKIN/Bank Flush Error Interrupt Enabled */
-#define UDPHS_EPTCTL2_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTL2) NAKOUT Interrupt Enabled */
-#define UDPHS_EPTCTL2_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTL2) Busy Bank Interrupt Enabled */
-#define UDPHS_EPTCTL2_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTL2) Short Packet Interrupt Enabled */
-/* -------- UDPHS_EPTSETSTA2 : (UDPHS Offset: 0x154) UDPHS Endpoint Set Status Register (endpoint = 2) -------- */
-#define UDPHS_EPTSETSTA2_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSETSTA2) Stall Handshake Request Set */
-#define UDPHS_EPTSETSTA2_KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSETSTA2) KILL Bank Set (for IN Endpoint) */
-#define UDPHS_EPTSETSTA2_TX_PK_RDY (0x1 << 11) /**< \brief (UDPHS_EPTSETSTA2) TX Packet Ready Set */
-/* -------- UDPHS_EPTCLRSTA2 : (UDPHS Offset: 0x158) UDPHS Endpoint Clear Status Register (endpoint = 2) -------- */
-#define UDPHS_EPTCLRSTA2_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTCLRSTA2) Stall Handshake Request Clear */
-#define UDPHS_EPTCLRSTA2_TOGGLESQ (0x1 << 6) /**< \brief (UDPHS_EPTCLRSTA2) Data Toggle Clear */
-#define UDPHS_EPTCLRSTA2_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCLRSTA2) Received OUT Data Clear */
-#define UDPHS_EPTCLRSTA2_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCLRSTA2) Transmitted IN Data Complete Clear */
-#define UDPHS_EPTCLRSTA2_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCLRSTA2) Received SETUP/Error Flow Clear */
-#define UDPHS_EPTCLRSTA2_STALL_SNT__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCLRSTA2) Stall Sent/Number of Transaction Error Clear */
-#define UDPHS_EPTCLRSTA2_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCLRSTA2) NAKIN/Bank Flush Error Clear */
-#define UDPHS_EPTCLRSTA2_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCLRSTA2) NAKOUT Clear */
-/* -------- UDPHS_EPTSTA2 : (UDPHS Offset: 0x15C) UDPHS Endpoint Status Register (endpoint = 2) -------- */
-#define UDPHS_EPTSTA2_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSTA2) Stall Handshake Request */
-#define UDPHS_EPTSTA2_TOGGLESQ_STA (0x3 << 6) /**< \brief (UDPHS_EPTSTA2) Toggle Sequencing */
-#define UDPHS_EPTSTA2_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTSTA2) Overflow Error */
-#define UDPHS_EPTSTA2_RX_BK_RDY__KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSTA2) Received OUT Data/KILL Bank */
-#define UDPHS_EPTSTA2_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTSTA2) Transmitted IN Data Complete */
-#define UDPHS_EPTSTA2_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTSTA2) TX Packet Ready/Transaction Error */
-#define UDPHS_EPTSTA2_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTSTA2) Received SETUP/Error Flow */
-#define UDPHS_EPTSTA2_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTSTA2) Stall Sent/CRC ISO Error/Number of Transaction Error */
-#define UDPHS_EPTSTA2_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTSTA2) NAK IN/Bank Flush Error */
-#define UDPHS_EPTSTA2_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTSTA2) NAK OUT */
-#define UDPHS_EPTSTA2_CURRENT_BANK__CONTROL_DIR (0x3 << 16) /**< \brief (UDPHS_EPTSTA2) Current Bank/Control Direction */
-#define UDPHS_EPTSTA2_BUSY_BANK_STA (0x3 << 18) /**< \brief (UDPHS_EPTSTA2) Busy Bank Number */
-#define UDPHS_EPTSTA2_BYTE_COUNT (0x7ff << 20) /**< \brief (UDPHS_EPTSTA2) UDPHS Byte Count */
-#define UDPHS_EPTSTA2_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTSTA2) Short Packet */
-/* -------- UDPHS_EPTCFG3 : (UDPHS Offset: 0x160) UDPHS Endpoint Configuration Register (endpoint = 3) -------- */
-#define UDPHS_EPTCFG3_EPT_SIZE (0x7 << 0) /**< \brief (UDPHS_EPTCFG3) Endpoint Size */
-#define UDPHS_EPTCFG3_EPT_SIZE_8 (0x0 << 0) /**< \brief (UDPHS_EPTCFG3) 8 bytes */
-#define UDPHS_EPTCFG3_EPT_SIZE_16 (0x1 << 0) /**< \brief (UDPHS_EPTCFG3) 16 bytes */
-#define UDPHS_EPTCFG3_EPT_SIZE_32 (0x2 << 0) /**< \brief (UDPHS_EPTCFG3) 32 bytes */
-#define UDPHS_EPTCFG3_EPT_SIZE_64 (0x3 << 0) /**< \brief (UDPHS_EPTCFG3) 64 bytes */
-#define UDPHS_EPTCFG3_EPT_SIZE_128 (0x4 << 0) /**< \brief (UDPHS_EPTCFG3) 128 bytes */
-#define UDPHS_EPTCFG3_EPT_SIZE_256 (0x5 << 0) /**< \brief (UDPHS_EPTCFG3) 256 bytes */
-#define UDPHS_EPTCFG3_EPT_SIZE_512 (0x6 << 0) /**< \brief (UDPHS_EPTCFG3) 512 bytes */
-#define UDPHS_EPTCFG3_EPT_SIZE_1024 (0x7 << 0) /**< \brief (UDPHS_EPTCFG3) 1024 bytes */
-#define UDPHS_EPTCFG3_EPT_DIR (0x1 << 3) /**< \brief (UDPHS_EPTCFG3) Endpoint Direction */
-#define UDPHS_EPTCFG3_EPT_DIR_OUT (0x0 << 3) /**< \brief (UDPHS_EPTCFG3) Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. */
-#define UDPHS_EPTCFG3_EPT_DIR_IN (0x1 << 3) /**< \brief (UDPHS_EPTCFG3) set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. */
-#define UDPHS_EPTCFG3_EPT_TYPE (0x3 << 4) /**< \brief (UDPHS_EPTCFG3) Endpoint Type */
-#define UDPHS_EPTCFG3_EPT_TYPE_CTL_EPT (0x0 << 4) /**< \brief (UDPHS_EPTCFG3) Control endpoint */
-#define UDPHS_EPTCFG3_EPT_TYPE_ISO_EPT (0x1 << 4) /**< \brief (UDPHS_EPTCFG3) Isochronous endpoint */
-#define UDPHS_EPTCFG3_EPT_TYPE_BUL_EPT (0x2 << 4) /**< \brief (UDPHS_EPTCFG3) Bulk endpoint */
-#define UDPHS_EPTCFG3_EPT_TYPE_INT_EPT (0x3 << 4) /**< \brief (UDPHS_EPTCFG3) Interrupt endpoint */
-#define UDPHS_EPTCFG3_BK_NUMBER (0x3 << 6) /**< \brief (UDPHS_EPTCFG3) Number of Banks */
-#define UDPHS_EPTCFG3_BK_NUMBER_0 (0x0 << 6) /**< \brief (UDPHS_EPTCFG3) Zero bank, the endpoint is not mapped in memory */
-#define UDPHS_EPTCFG3_BK_NUMBER_1 (0x1 << 6) /**< \brief (UDPHS_EPTCFG3) One bank (bank 0) */
-#define UDPHS_EPTCFG3_BK_NUMBER_2 (0x2 << 6) /**< \brief (UDPHS_EPTCFG3) Double bank (Ping-Pong: bank 0/bank 1) */
-#define UDPHS_EPTCFG3_BK_NUMBER_3 (0x3 << 6) /**< \brief (UDPHS_EPTCFG3) Triple bank (bank 0/bank 1/bank 2) */
-#define UDPHS_EPTCFG3_NB_TRANS (0x3 << 8) /**< \brief (UDPHS_EPTCFG3) Number Of Transaction per Microframe */
-#define UDPHS_EPTCFG3_EPT_MAPD (0x1 << 31) /**< \brief (UDPHS_EPTCFG3) Endpoint Mapped */
-/* -------- UDPHS_EPTCTLENB3 : (UDPHS Offset: 0x164) UDPHS Endpoint Control Enable Register (endpoint = 3) -------- */
-#define UDPHS_EPTCTLENB3_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLENB3) Endpoint Enable */
-#define UDPHS_EPTCTLENB3_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLENB3) Packet Auto-Valid Enable */
-#define UDPHS_EPTCTLENB3_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLENB3) Interrupts Disable DMA */
-#define UDPHS_EPTCTLENB3_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLENB3) NYET Disable (Only for High Speed Bulk OUT endpoints) */
-#define UDPHS_EPTCTLENB3_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLENB3) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLENB3_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLENB3) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLENB3_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLENB3) Overflow Error Interrupt Enable */
-#define UDPHS_EPTCTLENB3_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLENB3) Received OUT Data Interrupt Enable */
-#define UDPHS_EPTCTLENB3_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLENB3) Transmitted IN Data Complete Interrupt Enable */
-#define UDPHS_EPTCTLENB3_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLENB3) TX Packet Ready/Transaction Error Interrupt Enable */
-#define UDPHS_EPTCTLENB3_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLENB3) Received SETUP/Error Flow Interrupt Enable */
-#define UDPHS_EPTCTLENB3_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLENB3) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */
-#define UDPHS_EPTCTLENB3_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLENB3) NAKIN/Bank Flush Error Interrupt Enable */
-#define UDPHS_EPTCTLENB3_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLENB3) NAKOUT Interrupt Enable */
-#define UDPHS_EPTCTLENB3_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLENB3) Busy Bank Interrupt Enable */
-#define UDPHS_EPTCTLENB3_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLENB3) Short Packet Send/Short Packet Interrupt Enable */
-/* -------- UDPHS_EPTCTLDIS3 : (UDPHS Offset: 0x168) UDPHS Endpoint Control Disable Register (endpoint = 3) -------- */
-#define UDPHS_EPTCTLDIS3_EPT_DISABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLDIS3) Endpoint Disable */
-#define UDPHS_EPTCTLDIS3_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLDIS3) Packet Auto-Valid Disable */
-#define UDPHS_EPTCTLDIS3_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLDIS3) Interrupts Disable DMA */
-#define UDPHS_EPTCTLDIS3_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLDIS3) NYET Enable (Only for High Speed Bulk OUT endpoints) */
-#define UDPHS_EPTCTLDIS3_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLDIS3) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLDIS3_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLDIS3) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLDIS3_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLDIS3) Overflow Error Interrupt Disable */
-#define UDPHS_EPTCTLDIS3_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLDIS3) Received OUT Data Interrupt Disable */
-#define UDPHS_EPTCTLDIS3_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLDIS3) Transmitted IN Data Complete Interrupt Disable */
-#define UDPHS_EPTCTLDIS3_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLDIS3) TX Packet Ready/Transaction Error Interrupt Disable */
-#define UDPHS_EPTCTLDIS3_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLDIS3) Received SETUP/Error Flow Interrupt Disable */
-#define UDPHS_EPTCTLDIS3_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLDIS3) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */
-#define UDPHS_EPTCTLDIS3_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLDIS3) NAKIN/bank flush error Interrupt Disable */
-#define UDPHS_EPTCTLDIS3_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLDIS3) NAKOUT Interrupt Disable */
-#define UDPHS_EPTCTLDIS3_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLDIS3) Busy Bank Interrupt Disable */
-#define UDPHS_EPTCTLDIS3_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLDIS3) Short Packet Interrupt Disable */
-/* -------- UDPHS_EPTCTL3 : (UDPHS Offset: 0x16C) UDPHS Endpoint Control Register (endpoint = 3) -------- */
-#define UDPHS_EPTCTL3_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTL3) Endpoint Enable */
-#define UDPHS_EPTCTL3_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTL3) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */
-#define UDPHS_EPTCTL3_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTL3) Interrupt Disables DMA */
-#define UDPHS_EPTCTL3_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTL3) NYET Disable (Only for High Speed Bulk OUT endpoints) */
-#define UDPHS_EPTCTL3_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTL3) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTL3_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTL3) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTL3_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTL3) Overflow Error Interrupt Enabled */
-#define UDPHS_EPTCTL3_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTL3) Received OUT Data Interrupt Enabled */
-#define UDPHS_EPTCTL3_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTL3) Transmitted IN Data Complete Interrupt Enabled */
-#define UDPHS_EPTCTL3_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTL3) TX Packet Ready/Transaction Error Interrupt Enabled */
-#define UDPHS_EPTCTL3_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTL3) Received SETUP/Error Flow Interrupt Enabled */
-#define UDPHS_EPTCTL3_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTL3) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */
-#define UDPHS_EPTCTL3_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTL3) NAKIN/Bank Flush Error Interrupt Enabled */
-#define UDPHS_EPTCTL3_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTL3) NAKOUT Interrupt Enabled */
-#define UDPHS_EPTCTL3_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTL3) Busy Bank Interrupt Enabled */
-#define UDPHS_EPTCTL3_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTL3) Short Packet Interrupt Enabled */
-/* -------- UDPHS_EPTSETSTA3 : (UDPHS Offset: 0x174) UDPHS Endpoint Set Status Register (endpoint = 3) -------- */
-#define UDPHS_EPTSETSTA3_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSETSTA3) Stall Handshake Request Set */
-#define UDPHS_EPTSETSTA3_KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSETSTA3) KILL Bank Set (for IN Endpoint) */
-#define UDPHS_EPTSETSTA3_TX_PK_RDY (0x1 << 11) /**< \brief (UDPHS_EPTSETSTA3) TX Packet Ready Set */
-/* -------- UDPHS_EPTCLRSTA3 : (UDPHS Offset: 0x178) UDPHS Endpoint Clear Status Register (endpoint = 3) -------- */
-#define UDPHS_EPTCLRSTA3_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTCLRSTA3) Stall Handshake Request Clear */
-#define UDPHS_EPTCLRSTA3_TOGGLESQ (0x1 << 6) /**< \brief (UDPHS_EPTCLRSTA3) Data Toggle Clear */
-#define UDPHS_EPTCLRSTA3_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCLRSTA3) Received OUT Data Clear */
-#define UDPHS_EPTCLRSTA3_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCLRSTA3) Transmitted IN Data Complete Clear */
-#define UDPHS_EPTCLRSTA3_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCLRSTA3) Received SETUP/Error Flow Clear */
-#define UDPHS_EPTCLRSTA3_STALL_SNT__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCLRSTA3) Stall Sent/Number of Transaction Error Clear */
-#define UDPHS_EPTCLRSTA3_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCLRSTA3) NAKIN/Bank Flush Error Clear */
-#define UDPHS_EPTCLRSTA3_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCLRSTA3) NAKOUT Clear */
-/* -------- UDPHS_EPTSTA3 : (UDPHS Offset: 0x17C) UDPHS Endpoint Status Register (endpoint = 3) -------- */
-#define UDPHS_EPTSTA3_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSTA3) Stall Handshake Request */
-#define UDPHS_EPTSTA3_TOGGLESQ_STA (0x3 << 6) /**< \brief (UDPHS_EPTSTA3) Toggle Sequencing */
-#define UDPHS_EPTSTA3_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTSTA3) Overflow Error */
-#define UDPHS_EPTSTA3_RX_BK_RDY__KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSTA3) Received OUT Data/KILL Bank */
-#define UDPHS_EPTSTA3_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTSTA3) Transmitted IN Data Complete */
-#define UDPHS_EPTSTA3_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTSTA3) TX Packet Ready/Transaction Error */
-#define UDPHS_EPTSTA3_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTSTA3) Received SETUP/Error Flow */
-#define UDPHS_EPTSTA3_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTSTA3) Stall Sent/CRC ISO Error/Number of Transaction Error */
-#define UDPHS_EPTSTA3_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTSTA3) NAK IN/Bank Flush Error */
-#define UDPHS_EPTSTA3_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTSTA3) NAK OUT */
-#define UDPHS_EPTSTA3_CURRENT_BANK__CONTROL_DIR (0x3 << 16) /**< \brief (UDPHS_EPTSTA3) Current Bank/Control Direction */
-#define UDPHS_EPTSTA3_BUSY_BANK_STA (0x3 << 18) /**< \brief (UDPHS_EPTSTA3) Busy Bank Number */
-#define UDPHS_EPTSTA3_BYTE_COUNT (0x7ff << 20) /**< \brief (UDPHS_EPTSTA3) UDPHS Byte Count */
-#define UDPHS_EPTSTA3_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTSTA3) Short Packet */
-/* -------- UDPHS_EPTCFG4 : (UDPHS Offset: 0x180) UDPHS Endpoint Configuration Register (endpoint = 4) -------- */
-#define UDPHS_EPTCFG4_EPT_SIZE (0x7 << 0) /**< \brief (UDPHS_EPTCFG4) Endpoint Size */
-#define UDPHS_EPTCFG4_EPT_SIZE_8 (0x0 << 0) /**< \brief (UDPHS_EPTCFG4) 8 bytes */
-#define UDPHS_EPTCFG4_EPT_SIZE_16 (0x1 << 0) /**< \brief (UDPHS_EPTCFG4) 16 bytes */
-#define UDPHS_EPTCFG4_EPT_SIZE_32 (0x2 << 0) /**< \brief (UDPHS_EPTCFG4) 32 bytes */
-#define UDPHS_EPTCFG4_EPT_SIZE_64 (0x3 << 0) /**< \brief (UDPHS_EPTCFG4) 64 bytes */
-#define UDPHS_EPTCFG4_EPT_SIZE_128 (0x4 << 0) /**< \brief (UDPHS_EPTCFG4) 128 bytes */
-#define UDPHS_EPTCFG4_EPT_SIZE_256 (0x5 << 0) /**< \brief (UDPHS_EPTCFG4) 256 bytes */
-#define UDPHS_EPTCFG4_EPT_SIZE_512 (0x6 << 0) /**< \brief (UDPHS_EPTCFG4) 512 bytes */
-#define UDPHS_EPTCFG4_EPT_SIZE_1024 (0x7 << 0) /**< \brief (UDPHS_EPTCFG4) 1024 bytes */
-#define UDPHS_EPTCFG4_EPT_DIR (0x1 << 3) /**< \brief (UDPHS_EPTCFG4) Endpoint Direction */
-#define UDPHS_EPTCFG4_EPT_DIR_OUT (0x0 << 3) /**< \brief (UDPHS_EPTCFG4) Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. */
-#define UDPHS_EPTCFG4_EPT_DIR_IN (0x1 << 3) /**< \brief (UDPHS_EPTCFG4) set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. */
-#define UDPHS_EPTCFG4_EPT_TYPE (0x3 << 4) /**< \brief (UDPHS_EPTCFG4) Endpoint Type */
-#define UDPHS_EPTCFG4_EPT_TYPE_CTL_EPT (0x0 << 4) /**< \brief (UDPHS_EPTCFG4) Control endpoint */
-#define UDPHS_EPTCFG4_EPT_TYPE_ISO_EPT (0x1 << 4) /**< \brief (UDPHS_EPTCFG4) Isochronous endpoint */
-#define UDPHS_EPTCFG4_EPT_TYPE_BUL_EPT (0x2 << 4) /**< \brief (UDPHS_EPTCFG4) Bulk endpoint */
-#define UDPHS_EPTCFG4_EPT_TYPE_INT_EPT (0x3 << 4) /**< \brief (UDPHS_EPTCFG4) Interrupt endpoint */
-#define UDPHS_EPTCFG4_BK_NUMBER (0x3 << 6) /**< \brief (UDPHS_EPTCFG4) Number of Banks */
-#define UDPHS_EPTCFG4_BK_NUMBER_0 (0x0 << 6) /**< \brief (UDPHS_EPTCFG4) Zero bank, the endpoint is not mapped in memory */
-#define UDPHS_EPTCFG4_BK_NUMBER_1 (0x1 << 6) /**< \brief (UDPHS_EPTCFG4) One bank (bank 0) */
-#define UDPHS_EPTCFG4_BK_NUMBER_2 (0x2 << 6) /**< \brief (UDPHS_EPTCFG4) Double bank (Ping-Pong: bank 0/bank 1) */
-#define UDPHS_EPTCFG4_BK_NUMBER_3 (0x3 << 6) /**< \brief (UDPHS_EPTCFG4) Triple bank (bank 0/bank 1/bank 2) */
-#define UDPHS_EPTCFG4_NB_TRANS (0x3 << 8) /**< \brief (UDPHS_EPTCFG4) Number Of Transaction per Microframe */
-#define UDPHS_EPTCFG4_EPT_MAPD (0x1 << 31) /**< \brief (UDPHS_EPTCFG4) Endpoint Mapped */
-/* -------- UDPHS_EPTCTLENB4 : (UDPHS Offset: 0x184) UDPHS Endpoint Control Enable Register (endpoint = 4) -------- */
-#define UDPHS_EPTCTLENB4_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLENB4) Endpoint Enable */
-#define UDPHS_EPTCTLENB4_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLENB4) Packet Auto-Valid Enable */
-#define UDPHS_EPTCTLENB4_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLENB4) Interrupts Disable DMA */
-#define UDPHS_EPTCTLENB4_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLENB4) NYET Disable (Only for High Speed Bulk OUT endpoints) */
-#define UDPHS_EPTCTLENB4_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLENB4) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLENB4_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLENB4) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLENB4_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLENB4) Overflow Error Interrupt Enable */
-#define UDPHS_EPTCTLENB4_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLENB4) Received OUT Data Interrupt Enable */
-#define UDPHS_EPTCTLENB4_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLENB4) Transmitted IN Data Complete Interrupt Enable */
-#define UDPHS_EPTCTLENB4_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLENB4) TX Packet Ready/Transaction Error Interrupt Enable */
-#define UDPHS_EPTCTLENB4_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLENB4) Received SETUP/Error Flow Interrupt Enable */
-#define UDPHS_EPTCTLENB4_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLENB4) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */
-#define UDPHS_EPTCTLENB4_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLENB4) NAKIN/Bank Flush Error Interrupt Enable */
-#define UDPHS_EPTCTLENB4_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLENB4) NAKOUT Interrupt Enable */
-#define UDPHS_EPTCTLENB4_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLENB4) Busy Bank Interrupt Enable */
-#define UDPHS_EPTCTLENB4_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLENB4) Short Packet Send/Short Packet Interrupt Enable */
-/* -------- UDPHS_EPTCTLDIS4 : (UDPHS Offset: 0x188) UDPHS Endpoint Control Disable Register (endpoint = 4) -------- */
-#define UDPHS_EPTCTLDIS4_EPT_DISABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLDIS4) Endpoint Disable */
-#define UDPHS_EPTCTLDIS4_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLDIS4) Packet Auto-Valid Disable */
-#define UDPHS_EPTCTLDIS4_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLDIS4) Interrupts Disable DMA */
-#define UDPHS_EPTCTLDIS4_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLDIS4) NYET Enable (Only for High Speed Bulk OUT endpoints) */
-#define UDPHS_EPTCTLDIS4_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLDIS4) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLDIS4_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLDIS4) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLDIS4_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLDIS4) Overflow Error Interrupt Disable */
-#define UDPHS_EPTCTLDIS4_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLDIS4) Received OUT Data Interrupt Disable */
-#define UDPHS_EPTCTLDIS4_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLDIS4) Transmitted IN Data Complete Interrupt Disable */
-#define UDPHS_EPTCTLDIS4_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLDIS4) TX Packet Ready/Transaction Error Interrupt Disable */
-#define UDPHS_EPTCTLDIS4_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLDIS4) Received SETUP/Error Flow Interrupt Disable */
-#define UDPHS_EPTCTLDIS4_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLDIS4) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */
-#define UDPHS_EPTCTLDIS4_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLDIS4) NAKIN/bank flush error Interrupt Disable */
-#define UDPHS_EPTCTLDIS4_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLDIS4) NAKOUT Interrupt Disable */
-#define UDPHS_EPTCTLDIS4_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLDIS4) Busy Bank Interrupt Disable */
-#define UDPHS_EPTCTLDIS4_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLDIS4) Short Packet Interrupt Disable */
-/* -------- UDPHS_EPTCTL4 : (UDPHS Offset: 0x18C) UDPHS Endpoint Control Register (endpoint = 4) -------- */
-#define UDPHS_EPTCTL4_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTL4) Endpoint Enable */
-#define UDPHS_EPTCTL4_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTL4) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */
-#define UDPHS_EPTCTL4_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTL4) Interrupt Disables DMA */
-#define UDPHS_EPTCTL4_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTL4) NYET Disable (Only for High Speed Bulk OUT endpoints) */
-#define UDPHS_EPTCTL4_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTL4) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTL4_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTL4) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTL4_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTL4) Overflow Error Interrupt Enabled */
-#define UDPHS_EPTCTL4_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTL4) Received OUT Data Interrupt Enabled */
-#define UDPHS_EPTCTL4_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTL4) Transmitted IN Data Complete Interrupt Enabled */
-#define UDPHS_EPTCTL4_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTL4) TX Packet Ready/Transaction Error Interrupt Enabled */
-#define UDPHS_EPTCTL4_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTL4) Received SETUP/Error Flow Interrupt Enabled */
-#define UDPHS_EPTCTL4_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTL4) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */
-#define UDPHS_EPTCTL4_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTL4) NAKIN/Bank Flush Error Interrupt Enabled */
-#define UDPHS_EPTCTL4_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTL4) NAKOUT Interrupt Enabled */
-#define UDPHS_EPTCTL4_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTL4) Busy Bank Interrupt Enabled */
-#define UDPHS_EPTCTL4_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTL4) Short Packet Interrupt Enabled */
-/* -------- UDPHS_EPTSETSTA4 : (UDPHS Offset: 0x194) UDPHS Endpoint Set Status Register (endpoint = 4) -------- */
-#define UDPHS_EPTSETSTA4_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSETSTA4) Stall Handshake Request Set */
-#define UDPHS_EPTSETSTA4_KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSETSTA4) KILL Bank Set (for IN Endpoint) */
-#define UDPHS_EPTSETSTA4_TX_PK_RDY (0x1 << 11) /**< \brief (UDPHS_EPTSETSTA4) TX Packet Ready Set */
-/* -------- UDPHS_EPTCLRSTA4 : (UDPHS Offset: 0x198) UDPHS Endpoint Clear Status Register (endpoint = 4) -------- */
-#define UDPHS_EPTCLRSTA4_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTCLRSTA4) Stall Handshake Request Clear */
-#define UDPHS_EPTCLRSTA4_TOGGLESQ (0x1 << 6) /**< \brief (UDPHS_EPTCLRSTA4) Data Toggle Clear */
-#define UDPHS_EPTCLRSTA4_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCLRSTA4) Received OUT Data Clear */
-#define UDPHS_EPTCLRSTA4_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCLRSTA4) Transmitted IN Data Complete Clear */
-#define UDPHS_EPTCLRSTA4_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCLRSTA4) Received SETUP/Error Flow Clear */
-#define UDPHS_EPTCLRSTA4_STALL_SNT__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCLRSTA4) Stall Sent/Number of Transaction Error Clear */
-#define UDPHS_EPTCLRSTA4_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCLRSTA4) NAKIN/Bank Flush Error Clear */
-#define UDPHS_EPTCLRSTA4_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCLRSTA4) NAKOUT Clear */
-/* -------- UDPHS_EPTSTA4 : (UDPHS Offset: 0x19C) UDPHS Endpoint Status Register (endpoint = 4) -------- */
-#define UDPHS_EPTSTA4_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSTA4) Stall Handshake Request */
-#define UDPHS_EPTSTA4_TOGGLESQ_STA (0x3 << 6) /**< \brief (UDPHS_EPTSTA4) Toggle Sequencing */
-#define UDPHS_EPTSTA4_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTSTA4) Overflow Error */
-#define UDPHS_EPTSTA4_RX_BK_RDY__KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSTA4) Received OUT Data/KILL Bank */
-#define UDPHS_EPTSTA4_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTSTA4) Transmitted IN Data Complete */
-#define UDPHS_EPTSTA4_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTSTA4) TX Packet Ready/Transaction Error */
-#define UDPHS_EPTSTA4_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTSTA4) Received SETUP/Error Flow */
-#define UDPHS_EPTSTA4_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTSTA4) Stall Sent/CRC ISO Error/Number of Transaction Error */
-#define UDPHS_EPTSTA4_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTSTA4) NAK IN/Bank Flush Error */
-#define UDPHS_EPTSTA4_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTSTA4) NAK OUT */
-#define UDPHS_EPTSTA4_CURRENT_BANK__CONTROL_DIR (0x3 << 16) /**< \brief (UDPHS_EPTSTA4) Current Bank/Control Direction */
-#define UDPHS_EPTSTA4_BUSY_BANK_STA (0x3 << 18) /**< \brief (UDPHS_EPTSTA4) Busy Bank Number */
-#define UDPHS_EPTSTA4_BYTE_COUNT (0x7ff << 20) /**< \brief (UDPHS_EPTSTA4) UDPHS Byte Count */
-#define UDPHS_EPTSTA4_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTSTA4) Short Packet */
-/* -------- UDPHS_EPTCFG5 : (UDPHS Offset: 0x1A0) UDPHS Endpoint Configuration Register (endpoint = 5) -------- */
-#define UDPHS_EPTCFG5_EPT_SIZE (0x7 << 0) /**< \brief (UDPHS_EPTCFG5) Endpoint Size */
-#define UDPHS_EPTCFG5_EPT_SIZE_8 (0x0 << 0) /**< \brief (UDPHS_EPTCFG5) 8 bytes */
-#define UDPHS_EPTCFG5_EPT_SIZE_16 (0x1 << 0) /**< \brief (UDPHS_EPTCFG5) 16 bytes */
-#define UDPHS_EPTCFG5_EPT_SIZE_32 (0x2 << 0) /**< \brief (UDPHS_EPTCFG5) 32 bytes */
-#define UDPHS_EPTCFG5_EPT_SIZE_64 (0x3 << 0) /**< \brief (UDPHS_EPTCFG5) 64 bytes */
-#define UDPHS_EPTCFG5_EPT_SIZE_128 (0x4 << 0) /**< \brief (UDPHS_EPTCFG5) 128 bytes */
-#define UDPHS_EPTCFG5_EPT_SIZE_256 (0x5 << 0) /**< \brief (UDPHS_EPTCFG5) 256 bytes */
-#define UDPHS_EPTCFG5_EPT_SIZE_512 (0x6 << 0) /**< \brief (UDPHS_EPTCFG5) 512 bytes */
-#define UDPHS_EPTCFG5_EPT_SIZE_1024 (0x7 << 0) /**< \brief (UDPHS_EPTCFG5) 1024 bytes */
-#define UDPHS_EPTCFG5_EPT_DIR (0x1 << 3) /**< \brief (UDPHS_EPTCFG5) Endpoint Direction */
-#define UDPHS_EPTCFG5_EPT_DIR_OUT (0x0 << 3) /**< \brief (UDPHS_EPTCFG5) Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. */
-#define UDPHS_EPTCFG5_EPT_DIR_IN (0x1 << 3) /**< \brief (UDPHS_EPTCFG5) set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. */
-#define UDPHS_EPTCFG5_EPT_TYPE (0x3 << 4) /**< \brief (UDPHS_EPTCFG5) Endpoint Type */
-#define UDPHS_EPTCFG5_EPT_TYPE_CTL_EPT (0x0 << 4) /**< \brief (UDPHS_EPTCFG5) Control endpoint */
-#define UDPHS_EPTCFG5_EPT_TYPE_ISO_EPT (0x1 << 4) /**< \brief (UDPHS_EPTCFG5) Isochronous endpoint */
-#define UDPHS_EPTCFG5_EPT_TYPE_BUL_EPT (0x2 << 4) /**< \brief (UDPHS_EPTCFG5) Bulk endpoint */
-#define UDPHS_EPTCFG5_EPT_TYPE_INT_EPT (0x3 << 4) /**< \brief (UDPHS_EPTCFG5) Interrupt endpoint */
-#define UDPHS_EPTCFG5_BK_NUMBER (0x3 << 6) /**< \brief (UDPHS_EPTCFG5) Number of Banks */
-#define UDPHS_EPTCFG5_BK_NUMBER_0 (0x0 << 6) /**< \brief (UDPHS_EPTCFG5) Zero bank, the endpoint is not mapped in memory */
-#define UDPHS_EPTCFG5_BK_NUMBER_1 (0x1 << 6) /**< \brief (UDPHS_EPTCFG5) One bank (bank 0) */
-#define UDPHS_EPTCFG5_BK_NUMBER_2 (0x2 << 6) /**< \brief (UDPHS_EPTCFG5) Double bank (Ping-Pong: bank 0/bank 1) */
-#define UDPHS_EPTCFG5_BK_NUMBER_3 (0x3 << 6) /**< \brief (UDPHS_EPTCFG5) Triple bank (bank 0/bank 1/bank 2) */
-#define UDPHS_EPTCFG5_NB_TRANS (0x3 << 8) /**< \brief (UDPHS_EPTCFG5) Number Of Transaction per Microframe */
-#define UDPHS_EPTCFG5_EPT_MAPD (0x1 << 31) /**< \brief (UDPHS_EPTCFG5) Endpoint Mapped */
-/* -------- UDPHS_EPTCTLENB5 : (UDPHS Offset: 0x1A4) UDPHS Endpoint Control Enable Register (endpoint = 5) -------- */
-#define UDPHS_EPTCTLENB5_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLENB5) Endpoint Enable */
-#define UDPHS_EPTCTLENB5_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLENB5) Packet Auto-Valid Enable */
-#define UDPHS_EPTCTLENB5_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLENB5) Interrupts Disable DMA */
-#define UDPHS_EPTCTLENB5_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLENB5) NYET Disable (Only for High Speed Bulk OUT endpoints) */
-#define UDPHS_EPTCTLENB5_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLENB5) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLENB5_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLENB5) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLENB5_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLENB5) Overflow Error Interrupt Enable */
-#define UDPHS_EPTCTLENB5_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLENB5) Received OUT Data Interrupt Enable */
-#define UDPHS_EPTCTLENB5_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLENB5) Transmitted IN Data Complete Interrupt Enable */
-#define UDPHS_EPTCTLENB5_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLENB5) TX Packet Ready/Transaction Error Interrupt Enable */
-#define UDPHS_EPTCTLENB5_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLENB5) Received SETUP/Error Flow Interrupt Enable */
-#define UDPHS_EPTCTLENB5_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLENB5) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */
-#define UDPHS_EPTCTLENB5_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLENB5) NAKIN/Bank Flush Error Interrupt Enable */
-#define UDPHS_EPTCTLENB5_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLENB5) NAKOUT Interrupt Enable */
-#define UDPHS_EPTCTLENB5_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLENB5) Busy Bank Interrupt Enable */
-#define UDPHS_EPTCTLENB5_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLENB5) Short Packet Send/Short Packet Interrupt Enable */
-/* -------- UDPHS_EPTCTLDIS5 : (UDPHS Offset: 0x1A8) UDPHS Endpoint Control Disable Register (endpoint = 5) -------- */
-#define UDPHS_EPTCTLDIS5_EPT_DISABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLDIS5) Endpoint Disable */
-#define UDPHS_EPTCTLDIS5_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLDIS5) Packet Auto-Valid Disable */
-#define UDPHS_EPTCTLDIS5_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLDIS5) Interrupts Disable DMA */
-#define UDPHS_EPTCTLDIS5_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLDIS5) NYET Enable (Only for High Speed Bulk OUT endpoints) */
-#define UDPHS_EPTCTLDIS5_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLDIS5) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLDIS5_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLDIS5) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLDIS5_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLDIS5) Overflow Error Interrupt Disable */
-#define UDPHS_EPTCTLDIS5_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLDIS5) Received OUT Data Interrupt Disable */
-#define UDPHS_EPTCTLDIS5_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLDIS5) Transmitted IN Data Complete Interrupt Disable */
-#define UDPHS_EPTCTLDIS5_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLDIS5) TX Packet Ready/Transaction Error Interrupt Disable */
-#define UDPHS_EPTCTLDIS5_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLDIS5) Received SETUP/Error Flow Interrupt Disable */
-#define UDPHS_EPTCTLDIS5_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLDIS5) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */
-#define UDPHS_EPTCTLDIS5_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLDIS5) NAKIN/bank flush error Interrupt Disable */
-#define UDPHS_EPTCTLDIS5_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLDIS5) NAKOUT Interrupt Disable */
-#define UDPHS_EPTCTLDIS5_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLDIS5) Busy Bank Interrupt Disable */
-#define UDPHS_EPTCTLDIS5_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLDIS5) Short Packet Interrupt Disable */
-/* -------- UDPHS_EPTCTL5 : (UDPHS Offset: 0x1AC) UDPHS Endpoint Control Register (endpoint = 5) -------- */
-#define UDPHS_EPTCTL5_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTL5) Endpoint Enable */
-#define UDPHS_EPTCTL5_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTL5) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */
-#define UDPHS_EPTCTL5_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTL5) Interrupt Disables DMA */
-#define UDPHS_EPTCTL5_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTL5) NYET Disable (Only for High Speed Bulk OUT endpoints) */
-#define UDPHS_EPTCTL5_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTL5) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTL5_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTL5) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTL5_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTL5) Overflow Error Interrupt Enabled */
-#define UDPHS_EPTCTL5_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTL5) Received OUT Data Interrupt Enabled */
-#define UDPHS_EPTCTL5_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTL5) Transmitted IN Data Complete Interrupt Enabled */
-#define UDPHS_EPTCTL5_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTL5) TX Packet Ready/Transaction Error Interrupt Enabled */
-#define UDPHS_EPTCTL5_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTL5) Received SETUP/Error Flow Interrupt Enabled */
-#define UDPHS_EPTCTL5_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTL5) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */
-#define UDPHS_EPTCTL5_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTL5) NAKIN/Bank Flush Error Interrupt Enabled */
-#define UDPHS_EPTCTL5_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTL5) NAKOUT Interrupt Enabled */
-#define UDPHS_EPTCTL5_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTL5) Busy Bank Interrupt Enabled */
-#define UDPHS_EPTCTL5_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTL5) Short Packet Interrupt Enabled */
-/* -------- UDPHS_EPTSETSTA5 : (UDPHS Offset: 0x1B4) UDPHS Endpoint Set Status Register (endpoint = 5) -------- */
-#define UDPHS_EPTSETSTA5_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSETSTA5) Stall Handshake Request Set */
-#define UDPHS_EPTSETSTA5_KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSETSTA5) KILL Bank Set (for IN Endpoint) */
-#define UDPHS_EPTSETSTA5_TX_PK_RDY (0x1 << 11) /**< \brief (UDPHS_EPTSETSTA5) TX Packet Ready Set */
-/* -------- UDPHS_EPTCLRSTA5 : (UDPHS Offset: 0x1B8) UDPHS Endpoint Clear Status Register (endpoint = 5) -------- */
-#define UDPHS_EPTCLRSTA5_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTCLRSTA5) Stall Handshake Request Clear */
-#define UDPHS_EPTCLRSTA5_TOGGLESQ (0x1 << 6) /**< \brief (UDPHS_EPTCLRSTA5) Data Toggle Clear */
-#define UDPHS_EPTCLRSTA5_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCLRSTA5) Received OUT Data Clear */
-#define UDPHS_EPTCLRSTA5_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCLRSTA5) Transmitted IN Data Complete Clear */
-#define UDPHS_EPTCLRSTA5_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCLRSTA5) Received SETUP/Error Flow Clear */
-#define UDPHS_EPTCLRSTA5_STALL_SNT__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCLRSTA5) Stall Sent/Number of Transaction Error Clear */
-#define UDPHS_EPTCLRSTA5_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCLRSTA5) NAKIN/Bank Flush Error Clear */
-#define UDPHS_EPTCLRSTA5_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCLRSTA5) NAKOUT Clear */
-/* -------- UDPHS_EPTSTA5 : (UDPHS Offset: 0x1BC) UDPHS Endpoint Status Register (endpoint = 5) -------- */
-#define UDPHS_EPTSTA5_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSTA5) Stall Handshake Request */
-#define UDPHS_EPTSTA5_TOGGLESQ_STA (0x3 << 6) /**< \brief (UDPHS_EPTSTA5) Toggle Sequencing */
-#define UDPHS_EPTSTA5_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTSTA5) Overflow Error */
-#define UDPHS_EPTSTA5_RX_BK_RDY__KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSTA5) Received OUT Data/KILL Bank */
-#define UDPHS_EPTSTA5_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTSTA5) Transmitted IN Data Complete */
-#define UDPHS_EPTSTA5_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTSTA5) TX Packet Ready/Transaction Error */
-#define UDPHS_EPTSTA5_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTSTA5) Received SETUP/Error Flow */
-#define UDPHS_EPTSTA5_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTSTA5) Stall Sent/CRC ISO Error/Number of Transaction Error */
-#define UDPHS_EPTSTA5_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTSTA5) NAK IN/Bank Flush Error */
-#define UDPHS_EPTSTA5_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTSTA5) NAK OUT */
-#define UDPHS_EPTSTA5_CURRENT_BANK__CONTROL_DIR (0x3 << 16) /**< \brief (UDPHS_EPTSTA5) Current Bank/Control Direction */
-#define UDPHS_EPTSTA5_BUSY_BANK_STA (0x3 << 18) /**< \brief (UDPHS_EPTSTA5) Busy Bank Number */
-#define UDPHS_EPTSTA5_BYTE_COUNT (0x7ff << 20) /**< \brief (UDPHS_EPTSTA5) UDPHS Byte Count */
-#define UDPHS_EPTSTA5_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTSTA5) Short Packet */
-/* -------- UDPHS_EPTCFG6 : (UDPHS Offset: 0x1C0) UDPHS Endpoint Configuration Register (endpoint = 6) -------- */
-#define UDPHS_EPTCFG6_EPT_SIZE (0x7 << 0) /**< \brief (UDPHS_EPTCFG6) Endpoint Size */
-#define UDPHS_EPTCFG6_EPT_SIZE_8 (0x0 << 0) /**< \brief (UDPHS_EPTCFG6) 8 bytes */
-#define UDPHS_EPTCFG6_EPT_SIZE_16 (0x1 << 0) /**< \brief (UDPHS_EPTCFG6) 16 bytes */
-#define UDPHS_EPTCFG6_EPT_SIZE_32 (0x2 << 0) /**< \brief (UDPHS_EPTCFG6) 32 bytes */
-#define UDPHS_EPTCFG6_EPT_SIZE_64 (0x3 << 0) /**< \brief (UDPHS_EPTCFG6) 64 bytes */
-#define UDPHS_EPTCFG6_EPT_SIZE_128 (0x4 << 0) /**< \brief (UDPHS_EPTCFG6) 128 bytes */
-#define UDPHS_EPTCFG6_EPT_SIZE_256 (0x5 << 0) /**< \brief (UDPHS_EPTCFG6) 256 bytes */
-#define UDPHS_EPTCFG6_EPT_SIZE_512 (0x6 << 0) /**< \brief (UDPHS_EPTCFG6) 512 bytes */
-#define UDPHS_EPTCFG6_EPT_SIZE_1024 (0x7 << 0) /**< \brief (UDPHS_EPTCFG6) 1024 bytes */
-#define UDPHS_EPTCFG6_EPT_DIR (0x1 << 3) /**< \brief (UDPHS_EPTCFG6) Endpoint Direction */
-#define UDPHS_EPTCFG6_EPT_DIR_OUT (0x0 << 3) /**< \brief (UDPHS_EPTCFG6) Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. */
-#define UDPHS_EPTCFG6_EPT_DIR_IN (0x1 << 3) /**< \brief (UDPHS_EPTCFG6) set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. */
-#define UDPHS_EPTCFG6_EPT_TYPE (0x3 << 4) /**< \brief (UDPHS_EPTCFG6) Endpoint Type */
-#define UDPHS_EPTCFG6_EPT_TYPE_CTL_EPT (0x0 << 4) /**< \brief (UDPHS_EPTCFG6) Control endpoint */
-#define UDPHS_EPTCFG6_EPT_TYPE_ISO_EPT (0x1 << 4) /**< \brief (UDPHS_EPTCFG6) Isochronous endpoint */
-#define UDPHS_EPTCFG6_EPT_TYPE_BUL_EPT (0x2 << 4) /**< \brief (UDPHS_EPTCFG6) Bulk endpoint */
-#define UDPHS_EPTCFG6_EPT_TYPE_INT_EPT (0x3 << 4) /**< \brief (UDPHS_EPTCFG6) Interrupt endpoint */
-#define UDPHS_EPTCFG6_BK_NUMBER (0x3 << 6) /**< \brief (UDPHS_EPTCFG6) Number of Banks */
-#define UDPHS_EPTCFG6_BK_NUMBER_0 (0x0 << 6) /**< \brief (UDPHS_EPTCFG6) Zero bank, the endpoint is not mapped in memory */
-#define UDPHS_EPTCFG6_BK_NUMBER_1 (0x1 << 6) /**< \brief (UDPHS_EPTCFG6) One bank (bank 0) */
-#define UDPHS_EPTCFG6_BK_NUMBER_2 (0x2 << 6) /**< \brief (UDPHS_EPTCFG6) Double bank (Ping-Pong: bank 0/bank 1) */
-#define UDPHS_EPTCFG6_BK_NUMBER_3 (0x3 << 6) /**< \brief (UDPHS_EPTCFG6) Triple bank (bank 0/bank 1/bank 2) */
-#define UDPHS_EPTCFG6_NB_TRANS (0x3 << 8) /**< \brief (UDPHS_EPTCFG6) Number Of Transaction per Microframe */
-#define UDPHS_EPTCFG6_EPT_MAPD (0x1 << 31) /**< \brief (UDPHS_EPTCFG6) Endpoint Mapped */
-/* -------- UDPHS_EPTCTLENB6 : (UDPHS Offset: 0x1C4) UDPHS Endpoint Control Enable Register (endpoint = 6) -------- */
-#define UDPHS_EPTCTLENB6_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLENB6) Endpoint Enable */
-#define UDPHS_EPTCTLENB6_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLENB6) Packet Auto-Valid Enable */
-#define UDPHS_EPTCTLENB6_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLENB6) Interrupts Disable DMA */
-#define UDPHS_EPTCTLENB6_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLENB6) NYET Disable (Only for High Speed Bulk OUT endpoints) */
-#define UDPHS_EPTCTLENB6_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLENB6) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLENB6_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLENB6) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLENB6_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLENB6) Overflow Error Interrupt Enable */
-#define UDPHS_EPTCTLENB6_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLENB6) Received OUT Data Interrupt Enable */
-#define UDPHS_EPTCTLENB6_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLENB6) Transmitted IN Data Complete Interrupt Enable */
-#define UDPHS_EPTCTLENB6_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLENB6) TX Packet Ready/Transaction Error Interrupt Enable */
-#define UDPHS_EPTCTLENB6_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLENB6) Received SETUP/Error Flow Interrupt Enable */
-#define UDPHS_EPTCTLENB6_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLENB6) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */
-#define UDPHS_EPTCTLENB6_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLENB6) NAKIN/Bank Flush Error Interrupt Enable */
-#define UDPHS_EPTCTLENB6_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLENB6) NAKOUT Interrupt Enable */
-#define UDPHS_EPTCTLENB6_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLENB6) Busy Bank Interrupt Enable */
-#define UDPHS_EPTCTLENB6_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLENB6) Short Packet Send/Short Packet Interrupt Enable */
-/* -------- UDPHS_EPTCTLDIS6 : (UDPHS Offset: 0x1C8) UDPHS Endpoint Control Disable Register (endpoint = 6) -------- */
-#define UDPHS_EPTCTLDIS6_EPT_DISABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLDIS6) Endpoint Disable */
-#define UDPHS_EPTCTLDIS6_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLDIS6) Packet Auto-Valid Disable */
-#define UDPHS_EPTCTLDIS6_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLDIS6) Interrupts Disable DMA */
-#define UDPHS_EPTCTLDIS6_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLDIS6) NYET Enable (Only for High Speed Bulk OUT endpoints) */
-#define UDPHS_EPTCTLDIS6_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLDIS6) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLDIS6_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLDIS6) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTLDIS6_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLDIS6) Overflow Error Interrupt Disable */
-#define UDPHS_EPTCTLDIS6_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLDIS6) Received OUT Data Interrupt Disable */
-#define UDPHS_EPTCTLDIS6_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLDIS6) Transmitted IN Data Complete Interrupt Disable */
-#define UDPHS_EPTCTLDIS6_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLDIS6) TX Packet Ready/Transaction Error Interrupt Disable */
-#define UDPHS_EPTCTLDIS6_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLDIS6) Received SETUP/Error Flow Interrupt Disable */
-#define UDPHS_EPTCTLDIS6_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLDIS6) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */
-#define UDPHS_EPTCTLDIS6_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLDIS6) NAKIN/bank flush error Interrupt Disable */
-#define UDPHS_EPTCTLDIS6_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLDIS6) NAKOUT Interrupt Disable */
-#define UDPHS_EPTCTLDIS6_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLDIS6) Busy Bank Interrupt Disable */
-#define UDPHS_EPTCTLDIS6_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLDIS6) Short Packet Interrupt Disable */
-/* -------- UDPHS_EPTCTL6 : (UDPHS Offset: 0x1CC) UDPHS Endpoint Control Register (endpoint = 6) -------- */
-#define UDPHS_EPTCTL6_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTL6) Endpoint Enable */
-#define UDPHS_EPTCTL6_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTL6) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */
-#define UDPHS_EPTCTL6_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTL6) Interrupt Disables DMA */
-#define UDPHS_EPTCTL6_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTL6) NYET Disable (Only for High Speed Bulk OUT endpoints) */
-#define UDPHS_EPTCTL6_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTL6) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTL6_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTL6) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */
-#define UDPHS_EPTCTL6_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTL6) Overflow Error Interrupt Enabled */
-#define UDPHS_EPTCTL6_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTL6) Received OUT Data Interrupt Enabled */
-#define UDPHS_EPTCTL6_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTL6) Transmitted IN Data Complete Interrupt Enabled */
-#define UDPHS_EPTCTL6_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTL6) TX Packet Ready/Transaction Error Interrupt Enabled */
-#define UDPHS_EPTCTL6_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTL6) Received SETUP/Error Flow Interrupt Enabled */
-#define UDPHS_EPTCTL6_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTL6) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */
-#define UDPHS_EPTCTL6_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTL6) NAKIN/Bank Flush Error Interrupt Enabled */
-#define UDPHS_EPTCTL6_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTL6) NAKOUT Interrupt Enabled */
-#define UDPHS_EPTCTL6_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTL6) Busy Bank Interrupt Enabled */
-#define UDPHS_EPTCTL6_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTL6) Short Packet Interrupt Enabled */
-/* -------- UDPHS_EPTSETSTA6 : (UDPHS Offset: 0x1D4) UDPHS Endpoint Set Status Register (endpoint = 6) -------- */
-#define UDPHS_EPTSETSTA6_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSETSTA6) Stall Handshake Request Set */
-#define UDPHS_EPTSETSTA6_KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSETSTA6) KILL Bank Set (for IN Endpoint) */
-#define UDPHS_EPTSETSTA6_TX_PK_RDY (0x1 << 11) /**< \brief (UDPHS_EPTSETSTA6) TX Packet Ready Set */
-/* -------- UDPHS_EPTCLRSTA6 : (UDPHS Offset: 0x1D8) UDPHS Endpoint Clear Status Register (endpoint = 6) -------- */
-#define UDPHS_EPTCLRSTA6_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTCLRSTA6) Stall Handshake Request Clear */
-#define UDPHS_EPTCLRSTA6_TOGGLESQ (0x1 << 6) /**< \brief (UDPHS_EPTCLRSTA6) Data Toggle Clear */
-#define UDPHS_EPTCLRSTA6_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCLRSTA6) Received OUT Data Clear */
-#define UDPHS_EPTCLRSTA6_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCLRSTA6) Transmitted IN Data Complete Clear */
-#define UDPHS_EPTCLRSTA6_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCLRSTA6) Received SETUP/Error Flow Clear */
-#define UDPHS_EPTCLRSTA6_STALL_SNT__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCLRSTA6) Stall Sent/Number of Transaction Error Clear */
-#define UDPHS_EPTCLRSTA6_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCLRSTA6) NAKIN/Bank Flush Error Clear */
-#define UDPHS_EPTCLRSTA6_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCLRSTA6) NAKOUT Clear */
-/* -------- UDPHS_EPTSTA6 : (UDPHS Offset: 0x1DC) UDPHS Endpoint Status Register (endpoint = 6) -------- */
-#define UDPHS_EPTSTA6_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSTA6) Stall Handshake Request */
-#define UDPHS_EPTSTA6_TOGGLESQ_STA (0x3 << 6) /**< \brief (UDPHS_EPTSTA6) Toggle Sequencing */
-#define UDPHS_EPTSTA6_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTSTA6) Overflow Error */
-#define UDPHS_EPTSTA6_RX_BK_RDY__KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSTA6) Received OUT Data/KILL Bank */
-#define UDPHS_EPTSTA6_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTSTA6) Transmitted IN Data Complete */
-#define UDPHS_EPTSTA6_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTSTA6) TX Packet Ready/Transaction Error */
-#define UDPHS_EPTSTA6_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTSTA6) Received SETUP/Error Flow */
-#define UDPHS_EPTSTA6_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTSTA6) Stall Sent/CRC ISO Error/Number of Transaction Error */
-#define UDPHS_EPTSTA6_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTSTA6) NAK IN/Bank Flush Error */
-#define UDPHS_EPTSTA6_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTSTA6) NAK OUT */
-#define UDPHS_EPTSTA6_CURRENT_BANK__CONTROL_DIR (0x3 << 16) /**< \brief (UDPHS_EPTSTA6) Current Bank/Control Direction */
-#define UDPHS_EPTSTA6_BUSY_BANK_STA (0x3 << 18) /**< \brief (UDPHS_EPTSTA6) Busy Bank Number */
-#define UDPHS_EPTSTA6_BYTE_COUNT (0x7ff << 20) /**< \brief (UDPHS_EPTSTA6) UDPHS Byte Count */
-#define UDPHS_EPTSTA6_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTSTA6) Short Packet */
-/* -------- UDPHS_DMANXTDSC1 : (UDPHS Offset: 0x320) UDPHS DMA Next Descriptor Address Register (channel = 1) -------- */
-#define UDPHS_DMANXTDSC1_NXT_DSC_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMANXTDSC1) */
-/* -------- UDPHS_DMAADDRESS1 : (UDPHS Offset: 0x324) UDPHS DMA Channel Address Register (channel = 1) -------- */
-#define UDPHS_DMAADDRESS1_BUFF_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMAADDRESS1) */
-/* -------- UDPHS_DMACONTROL1 : (UDPHS Offset: 0x328) UDPHS DMA Channel Control Register (channel = 1) -------- */
-#define UDPHS_DMACONTROL1_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMACONTROL1) */
-#define UDPHS_DMACONTROL1_LDNXT_DSC (0x1 << 1) /**< \brief (UDPHS_DMACONTROL1) Load Next Channel Transfer Descriptor Enable (Command) */
-#define UDPHS_DMACONTROL1_END_TR_EN (0x1 << 2) /**< \brief (UDPHS_DMACONTROL1) End of Transfer Enable (Control) */
-#define UDPHS_DMACONTROL1_END_B_EN (0x1 << 3) /**< \brief (UDPHS_DMACONTROL1) End of Buffer Enable (Control) */
-#define UDPHS_DMACONTROL1_END_TR_IT (0x1 << 4) /**< \brief (UDPHS_DMACONTROL1) End of Transfer Interrupt Enable */
-#define UDPHS_DMACONTROL1_END_BUFFIT (0x1 << 5) /**< \brief (UDPHS_DMACONTROL1) End of Buffer Interrupt Enable */
-#define UDPHS_DMACONTROL1_DESC_LD_IT (0x1 << 6) /**< \brief (UDPHS_DMACONTROL1) Descriptor Loaded Interrupt Enable */
-#define UDPHS_DMACONTROL1_BURST_LCK (0x1 << 7) /**< \brief (UDPHS_DMACONTROL1) Burst Lock Enable */
-#define UDPHS_DMACONTROL1_BUFF_LENGTH (0xffff << 16) /**< \brief (UDPHS_DMACONTROL1) Buffer Byte Length (Write-only) */
-/* -------- UDPHS_DMASTATUS1 : (UDPHS Offset: 0x32C) UDPHS DMA Channel Status Register (channel = 1) -------- */
-#define UDPHS_DMASTATUS1_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMASTATUS1) Channel Enable Status */
-#define UDPHS_DMASTATUS1_CHANN_ACT (0x1 << 1) /**< \brief (UDPHS_DMASTATUS1) Channel Active Status */
-#define UDPHS_DMASTATUS1_END_TR_ST (0x1 << 4) /**< \brief (UDPHS_DMASTATUS1) End of Channel Transfer Status */
-#define UDPHS_DMASTATUS1_END_BF_ST (0x1 << 5) /**< \brief (UDPHS_DMASTATUS1) End of Channel Buffer Status */
-#define UDPHS_DMASTATUS1_DESC_LDST (0x1 << 6) /**< \brief (UDPHS_DMASTATUS1) Descriptor Loaded Status */
-#define UDPHS_DMASTATUS1_BUFF_COUNT (0xffff << 16) /**< \brief (UDPHS_DMASTATUS1) Buffer Byte Count */
-/* -------- UDPHS_DMANXTDSC2 : (UDPHS Offset: 0x330) UDPHS DMA Next Descriptor Address Register (channel = 2) -------- */
-#define UDPHS_DMANXTDSC2_NXT_DSC_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMANXTDSC2) */
-/* -------- UDPHS_DMAADDRESS2 : (UDPHS Offset: 0x334) UDPHS DMA Channel Address Register (channel = 2) -------- */
-#define UDPHS_DMAADDRESS2_BUFF_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMAADDRESS2) */
-/* -------- UDPHS_DMACONTROL2 : (UDPHS Offset: 0x338) UDPHS DMA Channel Control Register (channel = 2) -------- */
-#define UDPHS_DMACONTROL2_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMACONTROL2) */
-#define UDPHS_DMACONTROL2_LDNXT_DSC (0x1 << 1) /**< \brief (UDPHS_DMACONTROL2) Load Next Channel Transfer Descriptor Enable (Command) */
-#define UDPHS_DMACONTROL2_END_TR_EN (0x1 << 2) /**< \brief (UDPHS_DMACONTROL2) End of Transfer Enable (Control) */
-#define UDPHS_DMACONTROL2_END_B_EN (0x1 << 3) /**< \brief (UDPHS_DMACONTROL2) End of Buffer Enable (Control) */
-#define UDPHS_DMACONTROL2_END_TR_IT (0x1 << 4) /**< \brief (UDPHS_DMACONTROL2) End of Transfer Interrupt Enable */
-#define UDPHS_DMACONTROL2_END_BUFFIT (0x1 << 5) /**< \brief (UDPHS_DMACONTROL2) End of Buffer Interrupt Enable */
-#define UDPHS_DMACONTROL2_DESC_LD_IT (0x1 << 6) /**< \brief (UDPHS_DMACONTROL2) Descriptor Loaded Interrupt Enable */
-#define UDPHS_DMACONTROL2_BURST_LCK (0x1 << 7) /**< \brief (UDPHS_DMACONTROL2) Burst Lock Enable */
-#define UDPHS_DMACONTROL2_BUFF_LENGTH (0xffff << 16) /**< \brief (UDPHS_DMACONTROL2) Buffer Byte Length (Write-only) */
-/* -------- UDPHS_DMASTATUS2 : (UDPHS Offset: 0x33C) UDPHS DMA Channel Status Register (channel = 2) -------- */
-#define UDPHS_DMASTATUS2_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMASTATUS2) Channel Enable Status */
-#define UDPHS_DMASTATUS2_CHANN_ACT (0x1 << 1) /**< \brief (UDPHS_DMASTATUS2) Channel Active Status */
-#define UDPHS_DMASTATUS2_END_TR_ST (0x1 << 4) /**< \brief (UDPHS_DMASTATUS2) End of Channel Transfer Status */
-#define UDPHS_DMASTATUS2_END_BF_ST (0x1 << 5) /**< \brief (UDPHS_DMASTATUS2) End of Channel Buffer Status */
-#define UDPHS_DMASTATUS2_DESC_LDST (0x1 << 6) /**< \brief (UDPHS_DMASTATUS2) Descriptor Loaded Status */
-#define UDPHS_DMASTATUS2_BUFF_COUNT (0xffff << 16) /**< \brief (UDPHS_DMASTATUS2) Buffer Byte Count */
-/* -------- UDPHS_DMANXTDSC3 : (UDPHS Offset: 0x340) UDPHS DMA Next Descriptor Address Register (channel = 3) -------- */
-#define UDPHS_DMANXTDSC3_NXT_DSC_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMANXTDSC3) */
-/* -------- UDPHS_DMAADDRESS3 : (UDPHS Offset: 0x344) UDPHS DMA Channel Address Register (channel = 3) -------- */
-#define UDPHS_DMAADDRESS3_BUFF_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMAADDRESS3) */
-/* -------- UDPHS_DMACONTROL3 : (UDPHS Offset: 0x348) UDPHS DMA Channel Control Register (channel = 3) -------- */
-#define UDPHS_DMACONTROL3_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMACONTROL3) */
-#define UDPHS_DMACONTROL3_LDNXT_DSC (0x1 << 1) /**< \brief (UDPHS_DMACONTROL3) Load Next Channel Transfer Descriptor Enable (Command) */
-#define UDPHS_DMACONTROL3_END_TR_EN (0x1 << 2) /**< \brief (UDPHS_DMACONTROL3) End of Transfer Enable (Control) */
-#define UDPHS_DMACONTROL3_END_B_EN (0x1 << 3) /**< \brief (UDPHS_DMACONTROL3) End of Buffer Enable (Control) */
-#define UDPHS_DMACONTROL3_END_TR_IT (0x1 << 4) /**< \brief (UDPHS_DMACONTROL3) End of Transfer Interrupt Enable */
-#define UDPHS_DMACONTROL3_END_BUFFIT (0x1 << 5) /**< \brief (UDPHS_DMACONTROL3) End of Buffer Interrupt Enable */
-#define UDPHS_DMACONTROL3_DESC_LD_IT (0x1 << 6) /**< \brief (UDPHS_DMACONTROL3) Descriptor Loaded Interrupt Enable */
-#define UDPHS_DMACONTROL3_BURST_LCK (0x1 << 7) /**< \brief (UDPHS_DMACONTROL3) Burst Lock Enable */
-#define UDPHS_DMACONTROL3_BUFF_LENGTH (0xffff << 16) /**< \brief (UDPHS_DMACONTROL3) Buffer Byte Length (Write-only) */
-/* -------- UDPHS_DMASTATUS3 : (UDPHS Offset: 0x34C) UDPHS DMA Channel Status Register (channel = 3) -------- */
-#define UDPHS_DMASTATUS3_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMASTATUS3) Channel Enable Status */
-#define UDPHS_DMASTATUS3_CHANN_ACT (0x1 << 1) /**< \brief (UDPHS_DMASTATUS3) Channel Active Status */
-#define UDPHS_DMASTATUS3_END_TR_ST (0x1 << 4) /**< \brief (UDPHS_DMASTATUS3) End of Channel Transfer Status */
-#define UDPHS_DMASTATUS3_END_BF_ST (0x1 << 5) /**< \brief (UDPHS_DMASTATUS3) End of Channel Buffer Status */
-#define UDPHS_DMASTATUS3_DESC_LDST (0x1 << 6) /**< \brief (UDPHS_DMASTATUS3) Descriptor Loaded Status */
-#define UDPHS_DMASTATUS3_BUFF_COUNT (0xffff << 16) /**< \brief (UDPHS_DMASTATUS3) Buffer Byte Count */
-/* -------- UDPHS_DMANXTDSC4 : (UDPHS Offset: 0x350) UDPHS DMA Next Descriptor Address Register (channel = 4) -------- */
-#define UDPHS_DMANXTDSC4_NXT_DSC_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMANXTDSC4) */
-/* -------- UDPHS_DMAADDRESS4 : (UDPHS Offset: 0x354) UDPHS DMA Channel Address Register (channel = 4) -------- */
-#define UDPHS_DMAADDRESS4_BUFF_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMAADDRESS4) */
-/* -------- UDPHS_DMACONTROL4 : (UDPHS Offset: 0x358) UDPHS DMA Channel Control Register (channel = 4) -------- */
-#define UDPHS_DMACONTROL4_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMACONTROL4) */
-#define UDPHS_DMACONTROL4_LDNXT_DSC (0x1 << 1) /**< \brief (UDPHS_DMACONTROL4) Load Next Channel Transfer Descriptor Enable (Command) */
-#define UDPHS_DMACONTROL4_END_TR_EN (0x1 << 2) /**< \brief (UDPHS_DMACONTROL4) End of Transfer Enable (Control) */
-#define UDPHS_DMACONTROL4_END_B_EN (0x1 << 3) /**< \brief (UDPHS_DMACONTROL4) End of Buffer Enable (Control) */
-#define UDPHS_DMACONTROL4_END_TR_IT (0x1 << 4) /**< \brief (UDPHS_DMACONTROL4) End of Transfer Interrupt Enable */
-#define UDPHS_DMACONTROL4_END_BUFFIT (0x1 << 5) /**< \brief (UDPHS_DMACONTROL4) End of Buffer Interrupt Enable */
-#define UDPHS_DMACONTROL4_DESC_LD_IT (0x1 << 6) /**< \brief (UDPHS_DMACONTROL4) Descriptor Loaded Interrupt Enable */
-#define UDPHS_DMACONTROL4_BURST_LCK (0x1 << 7) /**< \brief (UDPHS_DMACONTROL4) Burst Lock Enable */
-#define UDPHS_DMACONTROL4_BUFF_LENGTH (0xffff << 16) /**< \brief (UDPHS_DMACONTROL4) Buffer Byte Length (Write-only) */
-/* -------- UDPHS_DMASTATUS4 : (UDPHS Offset: 0x35C) UDPHS DMA Channel Status Register (channel = 4) -------- */
-#define UDPHS_DMASTATUS4_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMASTATUS4) Channel Enable Status */
-#define UDPHS_DMASTATUS4_CHANN_ACT (0x1 << 1) /**< \brief (UDPHS_DMASTATUS4) Channel Active Status */
-#define UDPHS_DMASTATUS4_END_TR_ST (0x1 << 4) /**< \brief (UDPHS_DMASTATUS4) End of Channel Transfer Status */
-#define UDPHS_DMASTATUS4_END_BF_ST (0x1 << 5) /**< \brief (UDPHS_DMASTATUS4) End of Channel Buffer Status */
-#define UDPHS_DMASTATUS4_DESC_LDST (0x1 << 6) /**< \brief (UDPHS_DMASTATUS4) Descriptor Loaded Status */
-#define UDPHS_DMASTATUS4_BUFF_COUNT (0xffff << 16) /**< \brief (UDPHS_DMASTATUS4) Buffer Byte Count */
-/* -------- UDPHS_DMANXTDSC5 : (UDPHS Offset: 0x360) UDPHS DMA Next Descriptor Address Register (channel = 5) -------- */
-#define UDPHS_DMANXTDSC5_NXT_DSC_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMANXTDSC5) */
-/* -------- UDPHS_DMAADDRESS5 : (UDPHS Offset: 0x364) UDPHS DMA Channel Address Register (channel = 5) -------- */
-#define UDPHS_DMAADDRESS5_BUFF_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMAADDRESS5) */
-/* -------- UDPHS_DMACONTROL5 : (UDPHS Offset: 0x368) UDPHS DMA Channel Control Register (channel = 5) -------- */
-#define UDPHS_DMACONTROL5_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMACONTROL5) */
-#define UDPHS_DMACONTROL5_LDNXT_DSC (0x1 << 1) /**< \brief (UDPHS_DMACONTROL5) Load Next Channel Transfer Descriptor Enable (Command) */
-#define UDPHS_DMACONTROL5_END_TR_EN (0x1 << 2) /**< \brief (UDPHS_DMACONTROL5) End of Transfer Enable (Control) */
-#define UDPHS_DMACONTROL5_END_B_EN (0x1 << 3) /**< \brief (UDPHS_DMACONTROL5) End of Buffer Enable (Control) */
-#define UDPHS_DMACONTROL5_END_TR_IT (0x1 << 4) /**< \brief (UDPHS_DMACONTROL5) End of Transfer Interrupt Enable */
-#define UDPHS_DMACONTROL5_END_BUFFIT (0x1 << 5) /**< \brief (UDPHS_DMACONTROL5) End of Buffer Interrupt Enable */
-#define UDPHS_DMACONTROL5_DESC_LD_IT (0x1 << 6) /**< \brief (UDPHS_DMACONTROL5) Descriptor Loaded Interrupt Enable */
-#define UDPHS_DMACONTROL5_BURST_LCK (0x1 << 7) /**< \brief (UDPHS_DMACONTROL5) Burst Lock Enable */
-#define UDPHS_DMACONTROL5_BUFF_LENGTH (0xffff << 16) /**< \brief (UDPHS_DMACONTROL5) Buffer Byte Length (Write-only) */
-/* -------- UDPHS_DMASTATUS5 : (UDPHS Offset: 0x36C) UDPHS DMA Channel Status Register (channel = 5) -------- */
-#define UDPHS_DMASTATUS5_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMASTATUS5) Channel Enable Status */
-#define UDPHS_DMASTATUS5_CHANN_ACT (0x1 << 1) /**< \brief (UDPHS_DMASTATUS5) Channel Active Status */
-#define UDPHS_DMASTATUS5_END_TR_ST (0x1 << 4) /**< \brief (UDPHS_DMASTATUS5) End of Channel Transfer Status */
-#define UDPHS_DMASTATUS5_END_BF_ST (0x1 << 5) /**< \brief (UDPHS_DMASTATUS5) End of Channel Buffer Status */
-#define UDPHS_DMASTATUS5_DESC_LDST (0x1 << 6) /**< \brief (UDPHS_DMASTATUS5) Descriptor Loaded Status */
-#define UDPHS_DMASTATUS5_BUFF_COUNT (0xffff << 16) /**< \brief (UDPHS_DMASTATUS5) Buffer Byte Count */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3U_USART Universal Synchronous Asynchronous Receiver Transmitter */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Usart hardware registers */
-typedef struct {
- WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */
- RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */
- WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
- WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
- RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
- RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */
- RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */
- WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */
- RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
- RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */
- RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
- RwReg Reserved1[5];
- RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */
- RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */
- RwReg Reserved2[1];
- RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */
- RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */
- RwReg Reserved3[36];
- RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */
- RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */
- RwReg Reserved4[4];
- RoReg US_VERSION; /**< \brief (Usart Offset: 0xFC) Version Register */
- RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */
- RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */
- RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */
- RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */
- RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */
- RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */
- RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */
- RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */
- WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */
- RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */
-} Usart;
-#endif /* __ASSEMBLY__ */
-/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
-#define US_CR_RSTRX (0x1 << 2) /**< \brief (US_CR) Reset Receiver */
-#define US_CR_RSTTX (0x1 << 3) /**< \brief (US_CR) Reset Transmitter */
-#define US_CR_RXEN (0x1 << 4) /**< \brief (US_CR) Receiver Enable */
-#define US_CR_RXDIS (0x1 << 5) /**< \brief (US_CR) Receiver Disable */
-#define US_CR_TXEN (0x1 << 6) /**< \brief (US_CR) Transmitter Enable */
-#define US_CR_TXDIS (0x1 << 7) /**< \brief (US_CR) Transmitter Disable */
-#define US_CR_RSTSTA (0x1 << 8) /**< \brief (US_CR) Reset Status Bits */
-#define US_CR_STTBRK (0x1 << 9) /**< \brief (US_CR) Start Break */
-#define US_CR_STPBRK (0x1 << 10) /**< \brief (US_CR) Stop Break */
-#define US_CR_STTTO (0x1 << 11) /**< \brief (US_CR) Start Time-out */
-#define US_CR_SENDA (0x1 << 12) /**< \brief (US_CR) Send Address */
-#define US_CR_RSTIT (0x1 << 13) /**< \brief (US_CR) Reset Iterations */
-#define US_CR_RSTNACK (0x1 << 14) /**< \brief (US_CR) Reset Non Acknowledge */
-#define US_CR_RETTO (0x1 << 15) /**< \brief (US_CR) Rearm Time-out */
-#define US_CR_RTSEN__FCS (0x1 << 18) /**< \brief (US_CR) Request to Send Enable/Force SPI Chip Select */
-#define US_CR_RTSDIS__RCS (0x1 << 19) /**< \brief (US_CR) Request to Send Disable/Release SPI Chip Select */
-/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
-#define US_MR_USART_MODE (0xf << 0) /**< \brief (US_MR) */
-#define US_MR_USCLKS (0x3 << 4) /**< \brief (US_MR) Clock Selection */
-#define US_MR_CHRL (0x3 << 6) /**< \brief (US_MR) Character Length. */
-#define US_MR_SYNC__CPHA (0x1 << 8) /**< \brief (US_MR) Synchronous Mode Select or SPI Clock Phase */
-#define US_MR_PAR (0x7 << 9) /**< \brief (US_MR) Parity Type */
-#define US_MR_NBSTOP (0x3 << 12) /**< \brief (US_MR) Number of Stop Bits */
-#define US_MR_CHMODE (0x3 << 14) /**< \brief (US_MR) Channel Mode */
-#define US_MR_MSBF__CPOL (0x1 << 16) /**< \brief (US_MR) Bit Order or SPI Clock Polarity */
-#define US_MR_MODE9 (0x1 << 17) /**< \brief (US_MR) 9-bit Character Length */
-#define US_MR_CLKO (0x1 << 18) /**< \brief (US_MR) Clock Output Select */
-#define US_MR_OVER (0x1 << 19) /**< \brief (US_MR) Oversampling Mode */
-#define US_MR_INACK (0x1 << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */
-#define US_MR_DSNACK (0x1 << 21) /**< \brief (US_MR) Disable Successive NACK */
-#define US_MR_VAR_SYNC (0x1 << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */
-#define US_MR_INVDATA (0x1 << 23) /**< \brief (US_MR) INverted Data */
-#define US_MR_MAX_ITERATION (0x7 << 24) /**< \brief (US_MR) */
-#define US_MR_FILTER (0x1 << 28) /**< \brief (US_MR) Infrared Receive Line Filter */
-#define US_MR_MAN (0x1 << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */
-#define US_MR_MODSYNC_ (0x1 << 30) /**< \brief (US_MR) */
-#define US_MR_ONEBIT (0x1 << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */
-/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
-#define US_IER_RXRDY (0x1 << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
-#define US_IER_TXRDY (0x1 << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
-#define US_IER_RXBRK (0x1 << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
-#define US_IER_ENDRX (0x1 << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */
-#define US_IER_ENDTX (0x1 << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */
-#define US_IER_OVRE (0x1 << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
-#define US_IER_FRAME (0x1 << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
-#define US_IER_PARE (0x1 << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
-#define US_IER_TIMEOUT (0x1 << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
-#define US_IER_TXEMPTY (0x1 << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
-#define US_IER_ITER__UNRE (0x1 << 10) /**< \brief (US_IER) Iteration or SPI Underrun Error Interrupt Enable */
-#define US_IER_TXBUFE (0x1 << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */
-#define US_IER_RXBUFF (0x1 << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */
-#define US_IER_NACK (0x1 << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */
-#define US_IER_CTSIC (0x1 << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
-#define US_IER_MANE (0x1 << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */
-/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
-#define US_IDR_RXRDY (0x1 << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
-#define US_IDR_TXRDY (0x1 << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
-#define US_IDR_RXBRK (0x1 << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
-#define US_IDR_ENDRX (0x1 << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */
-#define US_IDR_ENDTX (0x1 << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */
-#define US_IDR_OVRE (0x1 << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */
-#define US_IDR_FRAME (0x1 << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
-#define US_IDR_PARE (0x1 << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
-#define US_IDR_TIMEOUT (0x1 << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
-#define US_IDR_TXEMPTY (0x1 << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
-#define US_IDR_ITER__UNRE (0x1 << 10) /**< \brief (US_IDR) Iteration or SPI Underrun Error Interrupt Enable */
-#define US_IDR_TXBUFE (0x1 << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */
-#define US_IDR_RXBUFF (0x1 << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */
-#define US_IDR_NACK (0x1 << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */
-#define US_IDR_CTSIC (0x1 << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
-#define US_IDR_MANE (0x1 << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */
-/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
-#define US_IMR_RXRDY (0x1 << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
-#define US_IMR_TXRDY (0x1 << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
-#define US_IMR_RXBRK (0x1 << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
-#define US_IMR_ENDRX (0x1 << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */
-#define US_IMR_ENDTX (0x1 << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */
-#define US_IMR_OVRE (0x1 << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
-#define US_IMR_FRAME (0x1 << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
-#define US_IMR_PARE (0x1 << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
-#define US_IMR_TIMEOUT (0x1 << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
-#define US_IMR_TXEMPTY (0x1 << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
-#define US_IMR_ITER__UNRE (0x1 << 10) /**< \brief (US_IMR) Iteration or SPI Underrun Error Interrupt Enable */
-#define US_IMR_TXBUFE (0x1 << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */
-#define US_IMR_RXBUFF (0x1 << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */
-#define US_IMR_NACK (0x1 << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */
-#define US_IMR_CTSIC (0x1 << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
-#define US_IMR_MANE (0x1 << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */
-/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
-#define US_CSR_RXRDY (0x1 << 0) /**< \brief (US_CSR) Receiver Ready */
-#define US_CSR_TXRDY (0x1 << 1) /**< \brief (US_CSR) Transmitter Ready */
-#define US_CSR_RXBRK (0x1 << 2) /**< \brief (US_CSR) Break Received/End of Break */
-#define US_CSR_ENDRX (0x1 << 3) /**< \brief (US_CSR) End of Receiver Transfer */
-#define US_CSR_ENDTX (0x1 << 4) /**< \brief (US_CSR) End of Transmitter Transfer */
-#define US_CSR_OVRE (0x1 << 5) /**< \brief (US_CSR) Overrun Error */
-#define US_CSR_FRAME (0x1 << 6) /**< \brief (US_CSR) Framing Error */
-#define US_CSR_PARE (0x1 << 7) /**< \brief (US_CSR) Parity Error */
-#define US_CSR_TIMEOUT (0x1 << 8) /**< \brief (US_CSR) Receiver Time-out */
-#define US_CSR_TXEMPTY (0x1 << 9) /**< \brief (US_CSR) Transmitter Empty */
-#define US_CSR_ITER__UNRE (0x1 << 10) /**< \brief (US_CSR) Max number of Repetitions Reached or SPI Underrun Error */
-#define US_CSR_TXBUFE (0x1 << 11) /**< \brief (US_CSR) Transmission Buffer Empty */
-#define US_CSR_RXBUFF (0x1 << 12) /**< \brief (US_CSR) Reception Buffer Full */
-#define US_CSR_NACK (0x1 << 13) /**< \brief (US_CSR) */
-#define US_CSR_CTSIC (0x1 << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */
-#define US_CSR_CTS (0x1 << 23) /**< \brief (US_CSR) Image of CTS Input */
-#define US_CSR_MANERR (0x1 << 24) /**< \brief (US_CSR) Manchester Error */
-/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */
-#define US_RHR_RXCHR (0x1ff << 0) /**< \brief (US_RHR) Received Character */
-#define US_RHR_RXSYNH (0x1 << 15) /**< \brief (US_RHR) Received Sync */
-/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */
-#define US_THR_TXCHR (0x1ff << 0) /**< \brief (US_THR) Character to be Transmitted */
-#define US_THR_TXSYNH (0x1 << 15) /**< \brief (US_THR) Sync Field to be transmitted */
-/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
-#define US_BRGR_CD (0xffff << 0) /**< \brief (US_BRGR) Clock Divider */
-#define US_BRGR_FP (0x7 << 16) /**< \brief (US_BRGR) Fractional Part */
-/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
-#define US_RTOR_TO (0xffff << 0) /**< \brief (US_RTOR) Time-out Value */
-/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
-#define US_TTGR_TG (0xff << 0) /**< \brief (US_TTGR) Timeguard Value */
-/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
-#define US_FIDI_FI_DI_RATIO (0x7ff << 0) /**< \brief (US_FIDI) FI Over DI Ratio Value */
-/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
-#define US_NER_NB_ERRORS (0xff << 0) /**< \brief (US_NER) Number of Errors */
-/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
-#define US_IF_IRDA_FILTER (0xff << 0) /**< \brief (US_IF) IrDA Filter */
-/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */
-#define US_MAN_TX_PL (0xf << 0) /**< \brief (US_MAN) Transmitter Preamble Length */
-#define US_MAN_TX_PP (0x3 << 8) /**< \brief (US_MAN) Transmitter Preamble Pattern */
-#define US_MAN_TX_MPOL (0x1 << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */
-#define US_MAN_RX_PL (0xf << 16) /**< \brief (US_MAN) Receiver Preamble Length */
-#define US_MAN_RX_PP (0x3 << 24) /**< \brief (US_MAN) Receiver Preamble Pattern detected */
-#define US_MAN_RX_MPOL (0x1 << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */
-#define US_MAN_STUCKTO1 (0x1 << 29) /**< \brief (US_MAN) */
-#define US_MAN_DRIFT (0x1 << 30) /**< \brief (US_MAN) Drift compensation */
-/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */
-#define US_WPMR_WPEN (0x1 << 0) /**< \brief (US_WPMR) Write Protect Enable */
-#define US_WPMR_WPKEY (0xffffff << 8) /**< \brief (US_WPMR) Write Protect KEY */
-/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */
-#define US_WPSR_WPVS (0x1 << 0) /**< \brief (US_WPSR) Write Protect Violation Status */
-#define US_WPSR_WPVSRC (0xffff << 8) /**< \brief (US_WPSR) Write Protect Violation Source */
-/* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */
-#define US_VERSION_VERSION (0xfff << 0) /**< \brief (US_VERSION) */
-#define US_VERSION_MFN (0x7 << 16) /**< \brief (US_VERSION) */
-/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */
-#define US_RPR_RXPTR (0xffffffff << 0) /**< \brief (US_RPR) Receive Pointer Register */
-/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */
-#define US_RCR_RXCTR (0xffff << 0) /**< \brief (US_RCR) Receive Counter Register */
-/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */
-#define US_TPR_TXPTR (0xffffffff << 0) /**< \brief (US_TPR) Transmit Counter Register */
-/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */
-#define US_TCR_TXCTR (0xffff << 0) /**< \brief (US_TCR) Transmit Counter Register */
-/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */
-#define US_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (US_RNPR) Receive Next Pointer */
-/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */
-#define US_RNCR_RXNCTR (0xffff << 0) /**< \brief (US_RNCR) Receive Next Counter */
-/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */
-#define US_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (US_TNPR) Transmit Next Pointer */
-/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */
-#define US_TNCR_TXNCTR (0xffff << 0) /**< \brief (US_TNCR) Transmit Counter Next */
-/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */
-#define US_PTCR_RXTEN (0x1 << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */
-#define US_PTCR_RXTDIS (0x1 << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */
-#define US_PTCR_TXTEN (0x1 << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */
-#define US_PTCR_TXTDIS (0x1 << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */
-/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */
-#define US_PTSR_RXTEN (0x1 << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */
-#define US_PTSR_TXTEN (0x1 << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */
-
-/*@}*/
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Watchdog Timer */
-/* ============================================================================= */
-/** \addtogroup AT91SAM3U_WDT Watchdog Timer */
-/*@{*/
-
-#ifndef __ASSEMBLY__
-/** \brief Wdt hardware registers */
-typedef struct {
- WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
- RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
- RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
-} Wdt;
-#endif /* __ASSEMBLY__ */
-/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
-#define WDT_CR_WDRSTT (0x1 << 0) /**< \brief (WDT_CR) Watchdog Restart */
-#define WDT_CR_KEY (0xff << 24) /**< \brief (WDT_CR) Password */
-/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
-#define WDT_MR_WDV (0xfff << 0) /**< \brief (WDT_MR) Watchdog Counter Value */
-#define WDT_MR_WDFIEN (0x1 << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
-#define WDT_MR_WDRSTEN (0x1 << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
-#define WDT_MR_WDRPROC (0x1 << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */
-#define WDT_MR_WDDIS (0x1 << 15) /**< \brief (WDT_MR) Watchdog Disable */
-#define WDT_MR_WDD (0xfff << 16) /**< \brief (WDT_MR) Watchdog Delta Value */
-#define WDT_MR_WDDBGHLT (0x1 << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
-#define WDT_MR_WDIDLEHLT (0x1 << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
-/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
-#define WDT_SR_WDUNF (0x1 << 0) /**< \brief (WDT_SR) Watchdog Underflow */
-#define WDT_SR_WDERR (0x1 << 1) /**< \brief (WDT_SR) Watchdog Error */
-
-/*@}*/
-
-/*@}*/
-
-/* ***************************************************************************** */
-/* REGISTER ACCESS DEFINITIONS FOR AT91SAM3U */
-/* ***************************************************************************** */
-/** \addtogroup AT91SAM3U_reg Registers Access Definitions */
-/*@{*/
-
-/* ========== Register definition for HSMCI peripheral ========== */
-#define REG_HSMCI_CR REG_ACCESS(WoReg, 0x40000000U) /**< \brief (HSMCI) Control Register */
-#define REG_HSMCI_MR REG_ACCESS(RwReg, 0x40000004U) /**< \brief (HSMCI) Mode Register */
-#define REG_HSMCI_DTOR REG_ACCESS(RwReg, 0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
-#define REG_HSMCI_SDCR REG_ACCESS(RwReg, 0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
-#define REG_HSMCI_ARGR REG_ACCESS(RwReg, 0x40000010U) /**< \brief (HSMCI) Argument Register */
-#define REG_HSMCI_CMDR REG_ACCESS(WoReg, 0x40000014U) /**< \brief (HSMCI) Command Register */
-#define REG_HSMCI_BLKR REG_ACCESS(RwReg, 0x40000018U) /**< \brief (HSMCI) Block Register */
-#define REG_HSMCI_CSTOR REG_ACCESS(RwReg, 0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
-#define REG_HSMCI_RSPR REG_ACCESS(RoReg, 0x40000020U) /**< \brief (HSMCI) Response Register */
-#define REG_HSMCI_RDR REG_ACCESS(RoReg, 0x40000030U) /**< \brief (HSMCI) Receive Data Register */
-#define REG_HSMCI_TDR REG_ACCESS(WoReg, 0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
-#define REG_HSMCI_SR REG_ACCESS(RoReg, 0x40000040U) /**< \brief (HSMCI) Status Register */
-#define REG_HSMCI_IER REG_ACCESS(WoReg, 0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
-#define REG_HSMCI_IDR REG_ACCESS(WoReg, 0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
-#define REG_HSMCI_IMR REG_ACCESS(RoReg, 0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
-#define REG_HSMCI_DMA REG_ACCESS(RwReg, 0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */
-#define REG_HSMCI_CFG REG_ACCESS(RwReg, 0x40000054U) /**< \brief (HSMCI) Configuration Register */
-#define REG_HSMCI_WPMR REG_ACCESS(RwReg, 0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
-#define REG_HSMCI_WPSR REG_ACCESS(RoReg, 0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
-/* ========== Register definition for SSC peripheral ========== */
-#define REG_SSC_CR REG_ACCESS(WoReg, 0x40004000U) /**< \brief (SSC) Control Register */
-#define REG_SSC_CMR REG_ACCESS(RwReg, 0x40004004U) /**< \brief (SSC) Clock Mode Register */
-#define REG_SSC_RCMR REG_ACCESS(RwReg, 0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
-#define REG_SSC_RFMR REG_ACCESS(RwReg, 0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
-#define REG_SSC_TCMR REG_ACCESS(RwReg, 0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
-#define REG_SSC_TFMR REG_ACCESS(RwReg, 0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
-#define REG_SSC_RHR REG_ACCESS(RoReg, 0x40004020U) /**< \brief (SSC) Receive Holding Register */
-#define REG_SSC_THR REG_ACCESS(WoReg, 0x40004024U) /**< \brief (SSC) Transmit Holding Register */
-#define REG_SSC_RSHR REG_ACCESS(RoReg, 0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
-#define REG_SSC_TSHR REG_ACCESS(RwReg, 0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
-#define REG_SSC_RC0R REG_ACCESS(RwReg, 0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
-#define REG_SSC_RC1R REG_ACCESS(RwReg, 0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
-#define REG_SSC_SR REG_ACCESS(RoReg, 0x40004040U) /**< \brief (SSC) Status Register */
-#define REG_SSC_IER REG_ACCESS(WoReg, 0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
-#define REG_SSC_IDR REG_ACCESS(WoReg, 0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
-#define REG_SSC_IMR REG_ACCESS(RoReg, 0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
-#define REG_SSC_WPMR REG_ACCESS(RwReg, 0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
-#define REG_SSC_WPSR REG_ACCESS(RoReg, 0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
-/* ========== Register definition for SPI peripheral ========== */
-#define REG_SPI_CR REG_ACCESS(WoReg, 0x40008000U) /**< \brief (SPI) Control Register */
-#define REG_SPI_MR REG_ACCESS(RwReg, 0x40008004U) /**< \brief (SPI) Mode Register */
-#define REG_SPI_RDR REG_ACCESS(RoReg, 0x40008008U) /**< \brief (SPI) Receive Data Register */
-#define REG_SPI_TDR REG_ACCESS(WoReg, 0x4000800CU) /**< \brief (SPI) Transmit Data Register */
-#define REG_SPI_SR REG_ACCESS(RoReg, 0x40008010U) /**< \brief (SPI) Status Register */
-#define REG_SPI_IER REG_ACCESS(WoReg, 0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
-#define REG_SPI_IDR REG_ACCESS(WoReg, 0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
-#define REG_SPI_IMR REG_ACCESS(RoReg, 0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
-#define REG_SPI_CSR REG_ACCESS(RwReg, 0x40008030U) /**< \brief (SPI) Chip Select Register */
-#define REG_SPI_WPCR REG_ACCESS(RwReg, 0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
-#define REG_SPI_WPSR REG_ACCESS(RoReg, 0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
-/* ========== Register definition for TC0 peripheral ========== */
-#define REG_TC0_CCR0 REG_ACCESS(WoReg, 0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
-#define REG_TC0_CMR0 REG_ACCESS(RwReg, 0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
-#define REG_TC0_CV0 REG_ACCESS(RoReg, 0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */
-#define REG_TC0_RA0 REG_ACCESS(RwReg, 0x40080014U) /**< \brief (TC0) Register A (channel = 0) */
-#define REG_TC0_RB0 REG_ACCESS(RwReg, 0x40080018U) /**< \brief (TC0) Register B (channel = 0) */
-#define REG_TC0_RC0 REG_ACCESS(RwReg, 0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */
-#define REG_TC0_SR0 REG_ACCESS(RoReg, 0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */
-#define REG_TC0_IER0 REG_ACCESS(WoReg, 0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
-#define REG_TC0_IDR0 REG_ACCESS(WoReg, 0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
-#define REG_TC0_IMR0 REG_ACCESS(RoReg, 0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
-#define REG_TC0_CCR1 REG_ACCESS(WoReg, 0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
-#define REG_TC0_CMR1 REG_ACCESS(RwReg, 0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
-#define REG_TC0_CV1 REG_ACCESS(RoReg, 0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */
-#define REG_TC0_RA1 REG_ACCESS(RwReg, 0x40080054U) /**< \brief (TC0) Register A (channel = 1) */
-#define REG_TC0_RB1 REG_ACCESS(RwReg, 0x40080058U) /**< \brief (TC0) Register B (channel = 1) */
-#define REG_TC0_RC1 REG_ACCESS(RwReg, 0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */
-#define REG_TC0_SR1 REG_ACCESS(RoReg, 0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */
-#define REG_TC0_IER1 REG_ACCESS(WoReg, 0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
-#define REG_TC0_IDR1 REG_ACCESS(WoReg, 0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
-#define REG_TC0_IMR1 REG_ACCESS(RoReg, 0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
-#define REG_TC0_CCR2 REG_ACCESS(WoReg, 0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
-#define REG_TC0_CMR2 REG_ACCESS(RwReg, 0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
-#define REG_TC0_CV2 REG_ACCESS(RoReg, 0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */
-#define REG_TC0_RA2 REG_ACCESS(RwReg, 0x40080094U) /**< \brief (TC0) Register A (channel = 2) */
-#define REG_TC0_RB2 REG_ACCESS(RwReg, 0x40080098U) /**< \brief (TC0) Register B (channel = 2) */
-#define REG_TC0_RC2 REG_ACCESS(RwReg, 0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */
-#define REG_TC0_SR2 REG_ACCESS(RoReg, 0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */
-#define REG_TC0_IER2 REG_ACCESS(WoReg, 0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
-#define REG_TC0_IDR2 REG_ACCESS(WoReg, 0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
-#define REG_TC0_IMR2 REG_ACCESS(RoReg, 0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
-#define REG_TC0_BCR REG_ACCESS(WoReg, 0x400800C0U) /**< \brief (TC0) Block Control Register */
-#define REG_TC0_BMR REG_ACCESS(RwReg, 0x400800C4U) /**< \brief (TC0) Block Mode Register */
-#define REG_TC0_QIER REG_ACCESS(WoReg, 0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
-#define REG_TC0_QIDR REG_ACCESS(WoReg, 0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
-#define REG_TC0_QIMR REG_ACCESS(RoReg, 0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
-#define REG_TC0_QISR REG_ACCESS(RoReg, 0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
-#define REG_TC0_VER REG_ACCESS(RoReg, 0x400800FCU) /**< \brief (TC0) Version Register */
-/* ========== Register definition for TWI0 peripheral ========== */
-#define REG_TWI0_CR REG_ACCESS(WoReg, 0x40084000U) /**< \brief (TWI0) Control Register */
-#define REG_TWI0_MMR REG_ACCESS(RwReg, 0x40084004U) /**< \brief (TWI0) Master Mode Register */
-#define REG_TWI0_SMR REG_ACCESS(RwReg, 0x40084008U) /**< \brief (TWI0) Slave Mode Register */
-#define REG_TWI0_IADR REG_ACCESS(RwReg, 0x4008400CU) /**< \brief (TWI0) Internal Address Register */
-#define REG_TWI0_CWGR REG_ACCESS(RwReg, 0x40084010U) /**< \brief (TWI0) Clock Waveform Generator Register */
-#define REG_TWI0_SR REG_ACCESS(RoReg, 0x40084020U) /**< \brief (TWI0) Status Register */
-#define REG_TWI0_IER REG_ACCESS(WoReg, 0x40084024U) /**< \brief (TWI0) Interrupt Enable Register */
-#define REG_TWI0_IDR REG_ACCESS(WoReg, 0x40084028U) /**< \brief (TWI0) Interrupt Disable Register */
-#define REG_TWI0_IMR REG_ACCESS(RoReg, 0x4008402CU) /**< \brief (TWI0) Interrupt Mask Register */
-#define REG_TWI0_RHR REG_ACCESS(RoReg, 0x40084030U) /**< \brief (TWI0) Receive Holding Register */
-#define REG_TWI0_THR REG_ACCESS(WoReg, 0x40084034U) /**< \brief (TWI0) Transmit Holding Register */
-#define REG_TWI0_RPR REG_ACCESS(RwReg, 0x40084100U) /**< \brief (TWI0) Receive Pointer Register */
-#define REG_TWI0_RCR REG_ACCESS(RwReg, 0x40084104U) /**< \brief (TWI0) Receive Counter Register */
-#define REG_TWI0_TPR REG_ACCESS(RwReg, 0x40084108U) /**< \brief (TWI0) Transmit Pointer Register */
-#define REG_TWI0_TCR REG_ACCESS(RwReg, 0x4008410CU) /**< \brief (TWI0) Transmit Counter Register */
-#define REG_TWI0_RNPR REG_ACCESS(RwReg, 0x40084110U) /**< \brief (TWI0) Receive Next Pointer Register */
-#define REG_TWI0_RNCR REG_ACCESS(RwReg, 0x40084114U) /**< \brief (TWI0) Receive Next Counter Register */
-#define REG_TWI0_TNPR REG_ACCESS(RwReg, 0x40084118U) /**< \brief (TWI0) Transmit Next Pointer Register */
-#define REG_TWI0_TNCR REG_ACCESS(RwReg, 0x4008411CU) /**< \brief (TWI0) Transmit Next Counter Register */
-#define REG_TWI0_PTCR REG_ACCESS(WoReg, 0x40084120U) /**< \brief (TWI0) Transfer Control Register */
-#define REG_TWI0_PTSR REG_ACCESS(RoReg, 0x40084124U) /**< \brief (TWI0) Transfer Status Register */
-/* ========== Register definition for TWI1 peripheral ========== */
-#define REG_TWI1_CR REG_ACCESS(WoReg, 0x40088000U) /**< \brief (TWI1) Control Register */
-#define REG_TWI1_MMR REG_ACCESS(RwReg, 0x40088004U) /**< \brief (TWI1) Master Mode Register */
-#define REG_TWI1_SMR REG_ACCESS(RwReg, 0x40088008U) /**< \brief (TWI1) Slave Mode Register */
-#define REG_TWI1_IADR REG_ACCESS(RwReg, 0x4008800CU) /**< \brief (TWI1) Internal Address Register */
-#define REG_TWI1_CWGR REG_ACCESS(RwReg, 0x40088010U) /**< \brief (TWI1) Clock Waveform Generator Register */
-#define REG_TWI1_SR REG_ACCESS(RoReg, 0x40088020U) /**< \brief (TWI1) Status Register */
-#define REG_TWI1_IER REG_ACCESS(WoReg, 0x40088024U) /**< \brief (TWI1) Interrupt Enable Register */
-#define REG_TWI1_IDR REG_ACCESS(WoReg, 0x40088028U) /**< \brief (TWI1) Interrupt Disable Register */
-#define REG_TWI1_IMR REG_ACCESS(RoReg, 0x4008802CU) /**< \brief (TWI1) Interrupt Mask Register */
-#define REG_TWI1_RHR REG_ACCESS(RoReg, 0x40088030U) /**< \brief (TWI1) Receive Holding Register */
-#define REG_TWI1_THR REG_ACCESS(WoReg, 0x40088034U) /**< \brief (TWI1) Transmit Holding Register */
-#define REG_TWI1_RPR REG_ACCESS(RwReg, 0x40088100U) /**< \brief (TWI1) Receive Pointer Register */
-#define REG_TWI1_RCR REG_ACCESS(RwReg, 0x40088104U) /**< \brief (TWI1) Receive Counter Register */
-#define REG_TWI1_TPR REG_ACCESS(RwReg, 0x40088108U) /**< \brief (TWI1) Transmit Pointer Register */
-#define REG_TWI1_TCR REG_ACCESS(RwReg, 0x4008810CU) /**< \brief (TWI1) Transmit Counter Register */
-#define REG_TWI1_RNPR REG_ACCESS(RwReg, 0x40088110U) /**< \brief (TWI1) Receive Next Pointer Register */
-#define REG_TWI1_RNCR REG_ACCESS(RwReg, 0x40088114U) /**< \brief (TWI1) Receive Next Counter Register */
-#define REG_TWI1_TNPR REG_ACCESS(RwReg, 0x40088118U) /**< \brief (TWI1) Transmit Next Pointer Register */
-#define REG_TWI1_TNCR REG_ACCESS(RwReg, 0x4008811CU) /**< \brief (TWI1) Transmit Next Counter Register */
-#define REG_TWI1_PTCR REG_ACCESS(WoReg, 0x40088120U) /**< \brief (TWI1) Transfer Control Register */
-#define REG_TWI1_PTSR REG_ACCESS(RoReg, 0x40088124U) /**< \brief (TWI1) Transfer Status Register */
-/* ========== Register definition for PWM peripheral ========== */
-#define REG_PWM_CLK REG_ACCESS(RwReg, 0x4008C000U) /**< \brief (PWM) PWM Clock Register */
-#define REG_PWM_ENA REG_ACCESS(WoReg, 0x4008C004U) /**< \brief (PWM) PWM Enable Register */
-#define REG_PWM_DIS REG_ACCESS(WoReg, 0x4008C008U) /**< \brief (PWM) PWM Disable Register */
-#define REG_PWM_SR REG_ACCESS(RoReg, 0x4008C00CU) /**< \brief (PWM) PWM Status Register */
-#define REG_PWM_IER1 REG_ACCESS(WoReg, 0x4008C010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
-#define REG_PWM_IDR1 REG_ACCESS(WoReg, 0x4008C014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
-#define REG_PWM_IMR1 REG_ACCESS(RoReg, 0x4008C018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
-#define REG_PWM_ISR1 REG_ACCESS(RoReg, 0x4008C01CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
-#define REG_PWM_SCM REG_ACCESS(RwReg, 0x4008C020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
-#define REG_PWM_SCUC REG_ACCESS(RwReg, 0x4008C028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
-#define REG_PWM_SCUP REG_ACCESS(RwReg, 0x4008C02CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
-#define REG_PWM_SCUPUPD REG_ACCESS(WoReg, 0x4008C030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
-#define REG_PWM_IER2 REG_ACCESS(WoReg, 0x4008C034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
-#define REG_PWM_IDR2 REG_ACCESS(WoReg, 0x4008C038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
-#define REG_PWM_IMR2 REG_ACCESS(RoReg, 0x4008C03CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
-#define REG_PWM_ISR2 REG_ACCESS(RoReg, 0x4008C040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
-#define REG_PWM_OOV REG_ACCESS(RwReg, 0x4008C044U) /**< \brief (PWM) PWM Output Override Value Register */
-#define REG_PWM_OS REG_ACCESS(RwReg, 0x4008C048U) /**< \brief (PWM) PWM Output Selection Register */
-#define REG_PWM_OSS REG_ACCESS(WoReg, 0x4008C04CU) /**< \brief (PWM) PWM Output Selection Set Register */
-#define REG_PWM_OSC REG_ACCESS(WoReg, 0x4008C050U) /**< \brief (PWM) PWM Output Selection Clear Register */
-#define REG_PWM_OSSUPD REG_ACCESS(WoReg, 0x4008C054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
-#define REG_PWM_OSCUPD REG_ACCESS(WoReg, 0x4008C058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
-#define REG_PWM_FMR REG_ACCESS(RwReg, 0x4008C05CU) /**< \brief (PWM) PWM Fault Mode Register */
-#define REG_PWM_FSR REG_ACCESS(RoReg, 0x4008C060U) /**< \brief (PWM) PWM Fault Status Register */
-#define REG_PWM_FCR REG_ACCESS(WoReg, 0x4008C064U) /**< \brief (PWM) PWM Fault Clear Register */
-#define REG_PWM_FPV REG_ACCESS(RwReg, 0x4008C068U) /**< \brief (PWM) PWM Fault Protection Value Register */
-#define REG_PWM_FPE REG_ACCESS(RwReg, 0x4008C06CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
-#define REG_PWM_ELxMR REG_ACCESS(RwReg, 0x4008C07CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
-#define REG_PWM_WPCR REG_ACCESS(WoReg, 0x4008C0E4U) /**< \brief (PWM) PWM Write Protect Control Register */
-#define REG_PWM_WPSR REG_ACCESS(RoReg, 0x4008C0E8U) /**< \brief (PWM) PWM Write Protect Status Register */
-#define REG_PWM_RPR REG_ACCESS(RwReg, 0x4008C100U) /**< \brief (PWM) Receive Pointer Register */
-#define REG_PWM_RCR REG_ACCESS(RwReg, 0x4008C104U) /**< \brief (PWM) Receive Counter Register */
-#define REG_PWM_TPR REG_ACCESS(RwReg, 0x4008C108U) /**< \brief (PWM) Transmit Pointer Register */
-#define REG_PWM_TCR REG_ACCESS(RwReg, 0x4008C10CU) /**< \brief (PWM) Transmit Counter Register */
-#define REG_PWM_RNPR REG_ACCESS(RwReg, 0x4008C110U) /**< \brief (PWM) Receive Next Pointer Register */
-#define REG_PWM_RNCR REG_ACCESS(RwReg, 0x4008C114U) /**< \brief (PWM) Receive Next Counter Register */
-#define REG_PWM_TNPR REG_ACCESS(RwReg, 0x4008C118U) /**< \brief (PWM) Transmit Next Pointer Register */
-#define REG_PWM_TNCR REG_ACCESS(RwReg, 0x4008C11CU) /**< \brief (PWM) Transmit Next Counter Register */
-#define REG_PWM_PTCR REG_ACCESS(WoReg, 0x4008C120U) /**< \brief (PWM) Transfer Control Register */
-#define REG_PWM_PTSR REG_ACCESS(RoReg, 0x4008C124U) /**< \brief (PWM) Transfer Status Register */
-#define REG_PWM_CMP0V REG_ACCESS(RwReg, 0x4008C130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
-#define REG_PWM_CMP0VUPD REG_ACCESS(WoReg, 0x4008C134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
-#define REG_PWM_CMP0M REG_ACCESS(RwReg, 0x4008C138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
-#define REG_PWM_CMP0MUPD REG_ACCESS(WoReg, 0x4008C13CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
-#define REG_PWM_CMP1V REG_ACCESS(RwReg, 0x4008C140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
-#define REG_PWM_CMP1VUPD REG_ACCESS(WoReg, 0x4008C144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
-#define REG_PWM_CMP1M REG_ACCESS(RwReg, 0x4008C148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
-#define REG_PWM_CMP1MUPD REG_ACCESS(WoReg, 0x4008C14CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
-#define REG_PWM_CMP2V REG_ACCESS(RwReg, 0x4008C150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
-#define REG_PWM_CMP2VUPD REG_ACCESS(WoReg, 0x4008C154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
-#define REG_PWM_CMP2M REG_ACCESS(RwReg, 0x4008C158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
-#define REG_PWM_CMP2MUPD REG_ACCESS(WoReg, 0x4008C15CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
-#define REG_PWM_CMP3V REG_ACCESS(RwReg, 0x4008C160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
-#define REG_PWM_CMP3VUPD REG_ACCESS(WoReg, 0x4008C164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
-#define REG_PWM_CMP3M REG_ACCESS(RwReg, 0x4008C168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
-#define REG_PWM_CMP3MUPD REG_ACCESS(WoReg, 0x4008C16CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
-#define REG_PWM_CMP4V REG_ACCESS(RwReg, 0x4008C170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
-#define REG_PWM_CMP4VUPD REG_ACCESS(WoReg, 0x4008C174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
-#define REG_PWM_CMP4M REG_ACCESS(RwReg, 0x4008C178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
-#define REG_PWM_CMP4MUPD REG_ACCESS(WoReg, 0x4008C17CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
-#define REG_PWM_CMP5V REG_ACCESS(RwReg, 0x4008C180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
-#define REG_PWM_CMP5VUPD REG_ACCESS(WoReg, 0x4008C184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
-#define REG_PWM_CMP5M REG_ACCESS(RwReg, 0x4008C188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
-#define REG_PWM_CMP5MUPD REG_ACCESS(WoReg, 0x4008C18CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
-#define REG_PWM_CMP6V REG_ACCESS(RwReg, 0x4008C190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
-#define REG_PWM_CMP6VUPD REG_ACCESS(WoReg, 0x4008C194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
-#define REG_PWM_CMP6M REG_ACCESS(RwReg, 0x4008C198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
-#define REG_PWM_CMP6MUPD REG_ACCESS(WoReg, 0x4008C19CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
-#define REG_PWM_CMP7V REG_ACCESS(RwReg, 0x4008C1A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
-#define REG_PWM_CMP7VUPD REG_ACCESS(WoReg, 0x4008C1A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
-#define REG_PWM_CMP7M REG_ACCESS(RwReg, 0x4008C1A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
-#define REG_PWM_CMP7MUPD REG_ACCESS(WoReg, 0x4008C1ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
-#define REG_PWM_CMR0 REG_ACCESS(RwReg, 0x4008C200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
-#define REG_PWM_CDTY0 REG_ACCESS(RwReg, 0x4008C204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
-#define REG_PWM_CDTYUPD0 REG_ACCESS(WoReg, 0x4008C208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
-#define REG_PWM_CPRD0 REG_ACCESS(RwReg, 0x4008C20CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
-#define REG_PWM_CPRDUPD0 REG_ACCESS(WoReg, 0x4008C210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
-#define REG_PWM_CCNT0 REG_ACCESS(RoReg, 0x4008C214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
-#define REG_PWM_DT0 REG_ACCESS(RwReg, 0x4008C218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
-#define REG_PWM_DTUPD0 REG_ACCESS(WoReg, 0x4008C21CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
-#define REG_PWM_CMR1 REG_ACCESS(RwReg, 0x4008C220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
-#define REG_PWM_CDTY1 REG_ACCESS(RwReg, 0x4008C224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
-#define REG_PWM_CDTYUPD1 REG_ACCESS(WoReg, 0x4008C228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
-#define REG_PWM_CPRD1 REG_ACCESS(RwReg, 0x4008C22CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
-#define REG_PWM_CPRDUPD1 REG_ACCESS(WoReg, 0x4008C230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
-#define REG_PWM_CCNT1 REG_ACCESS(RoReg, 0x4008C234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
-#define REG_PWM_DT1 REG_ACCESS(RwReg, 0x4008C238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
-#define REG_PWM_DTUPD1 REG_ACCESS(WoReg, 0x4008C23CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
-#define REG_PWM_CMR2 REG_ACCESS(RwReg, 0x4008C240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
-#define REG_PWM_CDTY2 REG_ACCESS(RwReg, 0x4008C244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
-#define REG_PWM_CDTYUPD2 REG_ACCESS(WoReg, 0x4008C248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
-#define REG_PWM_CPRD2 REG_ACCESS(RwReg, 0x4008C24CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
-#define REG_PWM_CPRDUPD2 REG_ACCESS(WoReg, 0x4008C250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
-#define REG_PWM_CCNT2 REG_ACCESS(RoReg, 0x4008C254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
-#define REG_PWM_DT2 REG_ACCESS(RwReg, 0x4008C258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
-#define REG_PWM_DTUPD2 REG_ACCESS(WoReg, 0x4008C25CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
-#define REG_PWM_CMR3 REG_ACCESS(RwReg, 0x4008C260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
-#define REG_PWM_CDTY3 REG_ACCESS(RwReg, 0x4008C264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
-#define REG_PWM_CDTYUPD3 REG_ACCESS(WoReg, 0x4008C268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
-#define REG_PWM_CPRD3 REG_ACCESS(RwReg, 0x4008C26CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
-#define REG_PWM_CPRDUPD3 REG_ACCESS(WoReg, 0x4008C270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
-#define REG_PWM_CCNT3 REG_ACCESS(RoReg, 0x4008C274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
-#define REG_PWM_DT3 REG_ACCESS(RwReg, 0x4008C278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
-#define REG_PWM_DTUPD3 REG_ACCESS(WoReg, 0x4008C27CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
-/* ========== Register definition for USART0 peripheral ========== */
-#define REG_USART0_CR REG_ACCESS(WoReg, 0x40090000U) /**< \brief (USART0) Control Register */
-#define REG_USART0_MR REG_ACCESS(RwReg, 0x40090004U) /**< \brief (USART0) Mode Register */
-#define REG_USART0_IER REG_ACCESS(WoReg, 0x40090008U) /**< \brief (USART0) Interrupt Enable Register */
-#define REG_USART0_IDR REG_ACCESS(WoReg, 0x4009000CU) /**< \brief (USART0) Interrupt Disable Register */
-#define REG_USART0_IMR REG_ACCESS(RoReg, 0x40090010U) /**< \brief (USART0) Interrupt Mask Register */
-#define REG_USART0_CSR REG_ACCESS(RoReg, 0x40090014U) /**< \brief (USART0) Channel Status Register */
-#define REG_USART0_RHR REG_ACCESS(RoReg, 0x40090018U) /**< \brief (USART0) Receiver Holding Register */
-#define REG_USART0_THR REG_ACCESS(WoReg, 0x4009001CU) /**< \brief (USART0) Transmitter Holding Register */
-#define REG_USART0_BRGR REG_ACCESS(RwReg, 0x40090020U) /**< \brief (USART0) Baud Rate Generator Register */
-#define REG_USART0_RTOR REG_ACCESS(RwReg, 0x40090024U) /**< \brief (USART0) Receiver Time-out Register */
-#define REG_USART0_TTGR REG_ACCESS(RwReg, 0x40090028U) /**< \brief (USART0) Transmitter Timeguard Register */
-#define REG_USART0_FIDI REG_ACCESS(RwReg, 0x40090040U) /**< \brief (USART0) FI DI Ratio Register */
-#define REG_USART0_NER REG_ACCESS(RoReg, 0x40090044U) /**< \brief (USART0) Number of Errors Register */
-#define REG_USART0_IF REG_ACCESS(RwReg, 0x4009004CU) /**< \brief (USART0) IrDA Filter Register */
-#define REG_USART0_MAN REG_ACCESS(RwReg, 0x40090050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
-#define REG_USART0_WPMR REG_ACCESS(RwReg, 0x400900E4U) /**< \brief (USART0) Write Protect Mode Register */
-#define REG_USART0_WPSR REG_ACCESS(RoReg, 0x400900E8U) /**< \brief (USART0) Write Protect Status Register */
-#define REG_USART0_VERSION REG_ACCESS(RoReg, 0x400900FCU) /**< \brief (USART0) Version Register */
-#define REG_USART0_RPR REG_ACCESS(RwReg, 0x40090100U) /**< \brief (USART0) Receive Pointer Register */
-#define REG_USART0_RCR REG_ACCESS(RwReg, 0x40090104U) /**< \brief (USART0) Receive Counter Register */
-#define REG_USART0_TPR REG_ACCESS(RwReg, 0x40090108U) /**< \brief (USART0) Transmit Pointer Register */
-#define REG_USART0_TCR REG_ACCESS(RwReg, 0x4009010CU) /**< \brief (USART0) Transmit Counter Register */
-#define REG_USART0_RNPR REG_ACCESS(RwReg, 0x40090110U) /**< \brief (USART0) Receive Next Pointer Register */
-#define REG_USART0_RNCR REG_ACCESS(RwReg, 0x40090114U) /**< \brief (USART0) Receive Next Counter Register */
-#define REG_USART0_TNPR REG_ACCESS(RwReg, 0x40090118U) /**< \brief (USART0) Transmit Next Pointer Register */
-#define REG_USART0_TNCR REG_ACCESS(RwReg, 0x4009011CU) /**< \brief (USART0) Transmit Next Counter Register */
-#define REG_USART0_PTCR REG_ACCESS(WoReg, 0x40090120U) /**< \brief (USART0) Transfer Control Register */
-#define REG_USART0_PTSR REG_ACCESS(RoReg, 0x40090124U) /**< \brief (USART0) Transfer Status Register */
-/* ========== Register definition for USART1 peripheral ========== */
-#define REG_USART1_CR REG_ACCESS(WoReg, 0x40094000U) /**< \brief (USART1) Control Register */
-#define REG_USART1_MR REG_ACCESS(RwReg, 0x40094004U) /**< \brief (USART1) Mode Register */
-#define REG_USART1_IER REG_ACCESS(WoReg, 0x40094008U) /**< \brief (USART1) Interrupt Enable Register */
-#define REG_USART1_IDR REG_ACCESS(WoReg, 0x4009400CU) /**< \brief (USART1) Interrupt Disable Register */
-#define REG_USART1_IMR REG_ACCESS(RoReg, 0x40094010U) /**< \brief (USART1) Interrupt Mask Register */
-#define REG_USART1_CSR REG_ACCESS(RoReg, 0x40094014U) /**< \brief (USART1) Channel Status Register */
-#define REG_USART1_RHR REG_ACCESS(RoReg, 0x40094018U) /**< \brief (USART1) Receiver Holding Register */
-#define REG_USART1_THR REG_ACCESS(WoReg, 0x4009401CU) /**< \brief (USART1) Transmitter Holding Register */
-#define REG_USART1_BRGR REG_ACCESS(RwReg, 0x40094020U) /**< \brief (USART1) Baud Rate Generator Register */
-#define REG_USART1_RTOR REG_ACCESS(RwReg, 0x40094024U) /**< \brief (USART1) Receiver Time-out Register */
-#define REG_USART1_TTGR REG_ACCESS(RwReg, 0x40094028U) /**< \brief (USART1) Transmitter Timeguard Register */
-#define REG_USART1_FIDI REG_ACCESS(RwReg, 0x40094040U) /**< \brief (USART1) FI DI Ratio Register */
-#define REG_USART1_NER REG_ACCESS(RoReg, 0x40094044U) /**< \brief (USART1) Number of Errors Register */
-#define REG_USART1_IF REG_ACCESS(RwReg, 0x4009404CU) /**< \brief (USART1) IrDA Filter Register */
-#define REG_USART1_MAN REG_ACCESS(RwReg, 0x40094050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
-#define REG_USART1_WPMR REG_ACCESS(RwReg, 0x400940E4U) /**< \brief (USART1) Write Protect Mode Register */
-#define REG_USART1_WPSR REG_ACCESS(RoReg, 0x400940E8U) /**< \brief (USART1) Write Protect Status Register */
-#define REG_USART1_VERSION REG_ACCESS(RoReg, 0x400940FCU) /**< \brief (USART1) Version Register */
-#define REG_USART1_RPR REG_ACCESS(RwReg, 0x40094100U) /**< \brief (USART1) Receive Pointer Register */
-#define REG_USART1_RCR REG_ACCESS(RwReg, 0x40094104U) /**< \brief (USART1) Receive Counter Register */
-#define REG_USART1_TPR REG_ACCESS(RwReg, 0x40094108U) /**< \brief (USART1) Transmit Pointer Register */
-#define REG_USART1_TCR REG_ACCESS(RwReg, 0x4009410CU) /**< \brief (USART1) Transmit Counter Register */
-#define REG_USART1_RNPR REG_ACCESS(RwReg, 0x40094110U) /**< \brief (USART1) Receive Next Pointer Register */
-#define REG_USART1_RNCR REG_ACCESS(RwReg, 0x40094114U) /**< \brief (USART1) Receive Next Counter Register */
-#define REG_USART1_TNPR REG_ACCESS(RwReg, 0x40094118U) /**< \brief (USART1) Transmit Next Pointer Register */
-#define REG_USART1_TNCR REG_ACCESS(RwReg, 0x4009411CU) /**< \brief (USART1) Transmit Next Counter Register */
-#define REG_USART1_PTCR REG_ACCESS(WoReg, 0x40094120U) /**< \brief (USART1) Transfer Control Register */
-#define REG_USART1_PTSR REG_ACCESS(RoReg, 0x40094124U) /**< \brief (USART1) Transfer Status Register */
-/* ========== Register definition for USART2 peripheral ========== */
-#define REG_USART2_CR REG_ACCESS(WoReg, 0x40098000U) /**< \brief (USART2) Control Register */
-#define REG_USART2_MR REG_ACCESS(RwReg, 0x40098004U) /**< \brief (USART2) Mode Register */
-#define REG_USART2_IER REG_ACCESS(WoReg, 0x40098008U) /**< \brief (USART2) Interrupt Enable Register */
-#define REG_USART2_IDR REG_ACCESS(WoReg, 0x4009800CU) /**< \brief (USART2) Interrupt Disable Register */
-#define REG_USART2_IMR REG_ACCESS(RoReg, 0x40098010U) /**< \brief (USART2) Interrupt Mask Register */
-#define REG_USART2_CSR REG_ACCESS(RoReg, 0x40098014U) /**< \brief (USART2) Channel Status Register */
-#define REG_USART2_RHR REG_ACCESS(RoReg, 0x40098018U) /**< \brief (USART2) Receiver Holding Register */
-#define REG_USART2_THR REG_ACCESS(WoReg, 0x4009801CU) /**< \brief (USART2) Transmitter Holding Register */
-#define REG_USART2_BRGR REG_ACCESS(RwReg, 0x40098020U) /**< \brief (USART2) Baud Rate Generator Register */
-#define REG_USART2_RTOR REG_ACCESS(RwReg, 0x40098024U) /**< \brief (USART2) Receiver Time-out Register */
-#define REG_USART2_TTGR REG_ACCESS(RwReg, 0x40098028U) /**< \brief (USART2) Transmitter Timeguard Register */
-#define REG_USART2_FIDI REG_ACCESS(RwReg, 0x40098040U) /**< \brief (USART2) FI DI Ratio Register */
-#define REG_USART2_NER REG_ACCESS(RoReg, 0x40098044U) /**< \brief (USART2) Number of Errors Register */
-#define REG_USART2_IF REG_ACCESS(RwReg, 0x4009804CU) /**< \brief (USART2) IrDA Filter Register */
-#define REG_USART2_MAN REG_ACCESS(RwReg, 0x40098050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
-#define REG_USART2_WPMR REG_ACCESS(RwReg, 0x400980E4U) /**< \brief (USART2) Write Protect Mode Register */
-#define REG_USART2_WPSR REG_ACCESS(RoReg, 0x400980E8U) /**< \brief (USART2) Write Protect Status Register */
-#define REG_USART2_VERSION REG_ACCESS(RoReg, 0x400980FCU) /**< \brief (USART2) Version Register */
-#define REG_USART2_RPR REG_ACCESS(RwReg, 0x40098100U) /**< \brief (USART2) Receive Pointer Register */
-#define REG_USART2_RCR REG_ACCESS(RwReg, 0x40098104U) /**< \brief (USART2) Receive Counter Register */
-#define REG_USART2_TPR REG_ACCESS(RwReg, 0x40098108U) /**< \brief (USART2) Transmit Pointer Register */
-#define REG_USART2_TCR REG_ACCESS(RwReg, 0x4009810CU) /**< \brief (USART2) Transmit Counter Register */
-#define REG_USART2_RNPR REG_ACCESS(RwReg, 0x40098110U) /**< \brief (USART2) Receive Next Pointer Register */
-#define REG_USART2_RNCR REG_ACCESS(RwReg, 0x40098114U) /**< \brief (USART2) Receive Next Counter Register */
-#define REG_USART2_TNPR REG_ACCESS(RwReg, 0x40098118U) /**< \brief (USART2) Transmit Next Pointer Register */
-#define REG_USART2_TNCR REG_ACCESS(RwReg, 0x4009811CU) /**< \brief (USART2) Transmit Next Counter Register */
-#define REG_USART2_PTCR REG_ACCESS(WoReg, 0x40098120U) /**< \brief (USART2) Transfer Control Register */
-#define REG_USART2_PTSR REG_ACCESS(RoReg, 0x40098124U) /**< \brief (USART2) Transfer Status Register */
-/* ========== Register definition for USART3 peripheral ========== */
-#define REG_USART3_CR REG_ACCESS(WoReg, 0x4009C000U) /**< \brief (USART3) Control Register */
-#define REG_USART3_MR REG_ACCESS(RwReg, 0x4009C004U) /**< \brief (USART3) Mode Register */
-#define REG_USART3_IER REG_ACCESS(WoReg, 0x4009C008U) /**< \brief (USART3) Interrupt Enable Register */
-#define REG_USART3_IDR REG_ACCESS(WoReg, 0x4009C00CU) /**< \brief (USART3) Interrupt Disable Register */
-#define REG_USART3_IMR REG_ACCESS(RoReg, 0x4009C010U) /**< \brief (USART3) Interrupt Mask Register */
-#define REG_USART3_CSR REG_ACCESS(RoReg, 0x4009C014U) /**< \brief (USART3) Channel Status Register */
-#define REG_USART3_RHR REG_ACCESS(RoReg, 0x4009C018U) /**< \brief (USART3) Receiver Holding Register */
-#define REG_USART3_THR REG_ACCESS(WoReg, 0x4009C01CU) /**< \brief (USART3) Transmitter Holding Register */
-#define REG_USART3_BRGR REG_ACCESS(RwReg, 0x4009C020U) /**< \brief (USART3) Baud Rate Generator Register */
-#define REG_USART3_RTOR REG_ACCESS(RwReg, 0x4009C024U) /**< \brief (USART3) Receiver Time-out Register */
-#define REG_USART3_TTGR REG_ACCESS(RwReg, 0x4009C028U) /**< \brief (USART3) Transmitter Timeguard Register */
-#define REG_USART3_FIDI REG_ACCESS(RwReg, 0x4009C040U) /**< \brief (USART3) FI DI Ratio Register */
-#define REG_USART3_NER REG_ACCESS(RoReg, 0x4009C044U) /**< \brief (USART3) Number of Errors Register */
-#define REG_USART3_IF REG_ACCESS(RwReg, 0x4009C04CU) /**< \brief (USART3) IrDA Filter Register */
-#define REG_USART3_MAN REG_ACCESS(RwReg, 0x4009C050U) /**< \brief (USART3) Manchester Encoder Decoder Register */
-#define REG_USART3_WPMR REG_ACCESS(RwReg, 0x4009C0E4U) /**< \brief (USART3) Write Protect Mode Register */
-#define REG_USART3_WPSR REG_ACCESS(RoReg, 0x4009C0E8U) /**< \brief (USART3) Write Protect Status Register */
-#define REG_USART3_VERSION REG_ACCESS(RoReg, 0x4009C0FCU) /**< \brief (USART3) Version Register */
-#define REG_USART3_RPR REG_ACCESS(RwReg, 0x4009C100U) /**< \brief (USART3) Receive Pointer Register */
-#define REG_USART3_RCR REG_ACCESS(RwReg, 0x4009C104U) /**< \brief (USART3) Receive Counter Register */
-#define REG_USART3_TPR REG_ACCESS(RwReg, 0x4009C108U) /**< \brief (USART3) Transmit Pointer Register */
-#define REG_USART3_TCR REG_ACCESS(RwReg, 0x4009C10CU) /**< \brief (USART3) Transmit Counter Register */
-#define REG_USART3_RNPR REG_ACCESS(RwReg, 0x4009C110U) /**< \brief (USART3) Receive Next Pointer Register */
-#define REG_USART3_RNCR REG_ACCESS(RwReg, 0x4009C114U) /**< \brief (USART3) Receive Next Counter Register */
-#define REG_USART3_TNPR REG_ACCESS(RwReg, 0x4009C118U) /**< \brief (USART3) Transmit Next Pointer Register */
-#define REG_USART3_TNCR REG_ACCESS(RwReg, 0x4009C11CU) /**< \brief (USART3) Transmit Next Counter Register */
-#define REG_USART3_PTCR REG_ACCESS(WoReg, 0x4009C120U) /**< \brief (USART3) Transfer Control Register */
-#define REG_USART3_PTSR REG_ACCESS(RoReg, 0x4009C124U) /**< \brief (USART3) Transfer Status Register */
-/* ========== Register definition for UDPHS peripheral ========== */
-#define REG_UDPHS_CTRL REG_ACCESS(RwReg, 0x400A4000U) /**< \brief (UDPHS) UDPHS Control Register */
-#define REG_UDPHS_FNUM REG_ACCESS(RoReg, 0x400A4004U) /**< \brief (UDPHS) UDPHS Frame Number Register */
-#define REG_UDPHS_IEN REG_ACCESS(RwReg, 0x400A4010U) /**< \brief (UDPHS) UDPHS Interrupt Enable Register */
-#define REG_UDPHS_INTSTA REG_ACCESS(RoReg, 0x400A4014U) /**< \brief (UDPHS) UDPHS Interrupt Status Register */
-#define REG_UDPHS_CLRINT REG_ACCESS(WoReg, 0x400A4018U) /**< \brief (UDPHS) UDPHS Clear Interrupt Register */
-#define REG_UDPHS_EPTRST REG_ACCESS(WoReg, 0x400A401CU) /**< \brief (UDPHS) UDPHS Endpoints Reset Register */
-#define REG_UDPHS_TST REG_ACCESS(RwReg, 0x400A40E0U) /**< \brief (UDPHS) UDPHS Test Register */
-#define REG_UDPHS_IPNAME1 REG_ACCESS(RoReg, 0x400A40F0U) /**< \brief (UDPHS) UDPHS Name1 Register */
-#define REG_UDPHS_IPNAME2 REG_ACCESS(RoReg, 0x400A40F4U) /**< \brief (UDPHS) UDPHS Name2 Register */
-#define REG_UDPHS_IPFEATURES REG_ACCESS(RoReg, 0x400A40F8U) /**< \brief (UDPHS) UDPHS Features Register */
-#define REG_UDPHS_EPTCFG0 REG_ACCESS(RwReg, 0x400A4100U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 0) */
-#define REG_UDPHS_EPTCTLENB0 REG_ACCESS(WoReg, 0x400A4104U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 0) */
-#define REG_UDPHS_EPTCTLDIS0 REG_ACCESS(WoReg, 0x400A4108U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 0) */
-#define REG_UDPHS_EPTCTL0 REG_ACCESS(RoReg, 0x400A410CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 0) */
-#define REG_UDPHS_EPTSETSTA0 REG_ACCESS(WoReg, 0x400A4114U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 0) */
-#define REG_UDPHS_EPTCLRSTA0 REG_ACCESS(WoReg, 0x400A4118U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 0) */
-#define REG_UDPHS_EPTSTA0 REG_ACCESS(RoReg, 0x400A411CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 0) */
-#define REG_UDPHS_EPTCFG1 REG_ACCESS(RwReg, 0x400A4120U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 1) */
-#define REG_UDPHS_EPTCTLENB1 REG_ACCESS(WoReg, 0x400A4124U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 1) */
-#define REG_UDPHS_EPTCTLDIS1 REG_ACCESS(WoReg, 0x400A4128U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 1) */
-#define REG_UDPHS_EPTCTL1 REG_ACCESS(RoReg, 0x400A412CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 1) */
-#define REG_UDPHS_EPTSETSTA1 REG_ACCESS(WoReg, 0x400A4134U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 1) */
-#define REG_UDPHS_EPTCLRSTA1 REG_ACCESS(WoReg, 0x400A4138U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 1) */
-#define REG_UDPHS_EPTSTA1 REG_ACCESS(RoReg, 0x400A413CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 1) */
-#define REG_UDPHS_EPTCFG2 REG_ACCESS(RwReg, 0x400A4140U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 2) */
-#define REG_UDPHS_EPTCTLENB2 REG_ACCESS(WoReg, 0x400A4144U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 2) */
-#define REG_UDPHS_EPTCTLDIS2 REG_ACCESS(WoReg, 0x400A4148U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 2) */
-#define REG_UDPHS_EPTCTL2 REG_ACCESS(RoReg, 0x400A414CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 2) */
-#define REG_UDPHS_EPTSETSTA2 REG_ACCESS(WoReg, 0x400A4154U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 2) */
-#define REG_UDPHS_EPTCLRSTA2 REG_ACCESS(WoReg, 0x400A4158U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 2) */
-#define REG_UDPHS_EPTSTA2 REG_ACCESS(RoReg, 0x400A415CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 2) */
-#define REG_UDPHS_EPTCFG3 REG_ACCESS(RwReg, 0x400A4160U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 3) */
-#define REG_UDPHS_EPTCTLENB3 REG_ACCESS(WoReg, 0x400A4164U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 3) */
-#define REG_UDPHS_EPTCTLDIS3 REG_ACCESS(WoReg, 0x400A4168U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 3) */
-#define REG_UDPHS_EPTCTL3 REG_ACCESS(RoReg, 0x400A416CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 3) */
-#define REG_UDPHS_EPTSETSTA3 REG_ACCESS(WoReg, 0x400A4174U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 3) */
-#define REG_UDPHS_EPTCLRSTA3 REG_ACCESS(WoReg, 0x400A4178U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 3) */
-#define REG_UDPHS_EPTSTA3 REG_ACCESS(RoReg, 0x400A417CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 3) */
-#define REG_UDPHS_EPTCFG4 REG_ACCESS(RwReg, 0x400A4180U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 4) */
-#define REG_UDPHS_EPTCTLENB4 REG_ACCESS(WoReg, 0x400A4184U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 4) */
-#define REG_UDPHS_EPTCTLDIS4 REG_ACCESS(WoReg, 0x400A4188U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 4) */
-#define REG_UDPHS_EPTCTL4 REG_ACCESS(RoReg, 0x400A418CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 4) */
-#define REG_UDPHS_EPTSETSTA4 REG_ACCESS(WoReg, 0x400A4194U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 4) */
-#define REG_UDPHS_EPTCLRSTA4 REG_ACCESS(WoReg, 0x400A4198U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 4) */
-#define REG_UDPHS_EPTSTA4 REG_ACCESS(RoReg, 0x400A419CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 4) */
-#define REG_UDPHS_EPTCFG5 REG_ACCESS(RwReg, 0x400A41A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 5) */
-#define REG_UDPHS_EPTCTLENB5 REG_ACCESS(WoReg, 0x400A41A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 5) */
-#define REG_UDPHS_EPTCTLDIS5 REG_ACCESS(WoReg, 0x400A41A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 5) */
-#define REG_UDPHS_EPTCTL5 REG_ACCESS(RoReg, 0x400A41ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 5) */
-#define REG_UDPHS_EPTSETSTA5 REG_ACCESS(WoReg, 0x400A41B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 5) */
-#define REG_UDPHS_EPTCLRSTA5 REG_ACCESS(WoReg, 0x400A41B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 5) */
-#define REG_UDPHS_EPTSTA5 REG_ACCESS(RoReg, 0x400A41BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 5) */
-#define REG_UDPHS_EPTCFG6 REG_ACCESS(RwReg, 0x400A41C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 6) */
-#define REG_UDPHS_EPTCTLENB6 REG_ACCESS(WoReg, 0x400A41C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 6) */
-#define REG_UDPHS_EPTCTLDIS6 REG_ACCESS(WoReg, 0x400A41C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 6) */
-#define REG_UDPHS_EPTCTL6 REG_ACCESS(RoReg, 0x400A41CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 6) */
-#define REG_UDPHS_EPTSETSTA6 REG_ACCESS(WoReg, 0x400A41D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 6) */
-#define REG_UDPHS_EPTCLRSTA6 REG_ACCESS(WoReg, 0x400A41D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 6) */
-#define REG_UDPHS_EPTSTA6 REG_ACCESS(RoReg, 0x400A41DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 6) */
-#define REG_UDPHS_DMANXTDSC1 REG_ACCESS(RwReg, 0x400A4320U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 1) */
-#define REG_UDPHS_DMAADDRESS1 REG_ACCESS(RwReg, 0x400A4324U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 1) */
-#define REG_UDPHS_DMACONTROL1 REG_ACCESS(RwReg, 0x400A4328U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 1) */
-#define REG_UDPHS_DMASTATUS1 REG_ACCESS(RwReg, 0x400A432CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 1) */
-#define REG_UDPHS_DMANXTDSC2 REG_ACCESS(RwReg, 0x400A4330U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 2) */
-#define REG_UDPHS_DMAADDRESS2 REG_ACCESS(RwReg, 0x400A4334U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 2) */
-#define REG_UDPHS_DMACONTROL2 REG_ACCESS(RwReg, 0x400A4338U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 2) */
-#define REG_UDPHS_DMASTATUS2 REG_ACCESS(RwReg, 0x400A433CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 2) */
-#define REG_UDPHS_DMANXTDSC3 REG_ACCESS(RwReg, 0x400A4340U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 3) */
-#define REG_UDPHS_DMAADDRESS3 REG_ACCESS(RwReg, 0x400A4344U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 3) */
-#define REG_UDPHS_DMACONTROL3 REG_ACCESS(RwReg, 0x400A4348U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 3) */
-#define REG_UDPHS_DMASTATUS3 REG_ACCESS(RwReg, 0x400A434CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 3) */
-#define REG_UDPHS_DMANXTDSC4 REG_ACCESS(RwReg, 0x400A4350U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 4) */
-#define REG_UDPHS_DMAADDRESS4 REG_ACCESS(RwReg, 0x400A4354U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 4) */
-#define REG_UDPHS_DMACONTROL4 REG_ACCESS(RwReg, 0x400A4358U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 4) */
-#define REG_UDPHS_DMASTATUS4 REG_ACCESS(RwReg, 0x400A435CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 4) */
-#define REG_UDPHS_DMANXTDSC5 REG_ACCESS(RwReg, 0x400A4360U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 5) */
-#define REG_UDPHS_DMAADDRESS5 REG_ACCESS(RwReg, 0x400A4364U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 5) */
-#define REG_UDPHS_DMACONTROL5 REG_ACCESS(RwReg, 0x400A4368U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 5) */
-#define REG_UDPHS_DMASTATUS5 REG_ACCESS(RwReg, 0x400A436CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 5) */
-/* ========== Register definition for ADC12B peripheral ========== */
-#define REG_ADC12B_CR REG_ACCESS(WoReg, 0x400A8000U) /**< \brief (ADC12B) Control Register */
-#define REG_ADC12B_MR REG_ACCESS(RwReg, 0x400A8004U) /**< \brief (ADC12B) Mode Register */
-#define REG_ADC12B_CHER REG_ACCESS(WoReg, 0x400A8010U) /**< \brief (ADC12B) Channel Enable Register */
-#define REG_ADC12B_CHDR REG_ACCESS(WoReg, 0x400A8014U) /**< \brief (ADC12B) Channel Disable Register */
-#define REG_ADC12B_CHSR REG_ACCESS(RoReg, 0x400A8018U) /**< \brief (ADC12B) Channel Status Register */
-#define REG_ADC12B_SR REG_ACCESS(RoReg, 0x400A801CU) /**< \brief (ADC12B) Status Register */
-#define REG_ADC12B_LCDR REG_ACCESS(RoReg, 0x400A8020U) /**< \brief (ADC12B) Last Converted Data Register */
-#define REG_ADC12B_IER REG_ACCESS(WoReg, 0x400A8024U) /**< \brief (ADC12B) Interrupt Enable Register */
-#define REG_ADC12B_IDR REG_ACCESS(WoReg, 0x400A8028U) /**< \brief (ADC12B) Interrupt Disable Register */
-#define REG_ADC12B_IMR REG_ACCESS(RoReg, 0x400A802CU) /**< \brief (ADC12B) Interrupt Mask Register */
-#define REG_ADC12B_CDR REG_ACCESS(RoReg, 0x400A8030U) /**< \brief (ADC12B) Channel Data Register */
-#define REG_ADC12B_ACR REG_ACCESS(RwReg, 0x400A8064U) /**< \brief (ADC12B) Analog Control Register */
-#define REG_ADC12B_EMR REG_ACCESS(RwReg, 0x400A8068U) /**< \brief (ADC12B) Extended Mode Register */
-#define REG_ADC12B_RPR REG_ACCESS(RwReg, 0x400A8100U) /**< \brief (ADC12B) Receive Pointer Register */
-#define REG_ADC12B_RCR REG_ACCESS(RwReg, 0x400A8104U) /**< \brief (ADC12B) Receive Counter Register */
-#define REG_ADC12B_TPR REG_ACCESS(RwReg, 0x400A8108U) /**< \brief (ADC12B) Transmit Pointer Register */
-#define REG_ADC12B_TCR REG_ACCESS(RwReg, 0x400A810CU) /**< \brief (ADC12B) Transmit Counter Register */
-#define REG_ADC12B_RNPR REG_ACCESS(RwReg, 0x400A8110U) /**< \brief (ADC12B) Receive Next Pointer Register */
-#define REG_ADC12B_RNCR REG_ACCESS(RwReg, 0x400A8114U) /**< \brief (ADC12B) Receive Next Counter Register */
-#define REG_ADC12B_TNPR REG_ACCESS(RwReg, 0x400A8118U) /**< \brief (ADC12B) Transmit Next Pointer Register */
-#define REG_ADC12B_TNCR REG_ACCESS(RwReg, 0x400A811CU) /**< \brief (ADC12B) Transmit Next Counter Register */
-#define REG_ADC12B_PTCR REG_ACCESS(WoReg, 0x400A8120U) /**< \brief (ADC12B) Transfer Control Register */
-#define REG_ADC12B_PTSR REG_ACCESS(RoReg, 0x400A8124U) /**< \brief (ADC12B) Transfer Status Register */
-/* ========== Register definition for ADC peripheral ========== */
-#define REG_ADC_CR REG_ACCESS(WoReg, 0x400AC000U) /**< \brief (ADC) Control Register */
-#define REG_ADC_MR REG_ACCESS(RwReg, 0x400AC004U) /**< \brief (ADC) Mode Register */
-#define REG_ADC_CHER REG_ACCESS(WoReg, 0x400AC010U) /**< \brief (ADC) Channel Enable Register */
-#define REG_ADC_CHDR REG_ACCESS(WoReg, 0x400AC014U) /**< \brief (ADC) Channel Disable Register */
-#define REG_ADC_CHSR REG_ACCESS(RoReg, 0x400AC018U) /**< \brief (ADC) Channel Status Register */
-#define REG_ADC_SR REG_ACCESS(RoReg, 0x400AC01CU) /**< \brief (ADC) Status Register */
-#define REG_ADC_LCDR REG_ACCESS(RoReg, 0x400AC020U) /**< \brief (ADC) Last Converted Data Register */
-#define REG_ADC_IER REG_ACCESS(WoReg, 0x400AC024U) /**< \brief (ADC) Interrupt Enable Register */
-#define REG_ADC_IDR REG_ACCESS(WoReg, 0x400AC028U) /**< \brief (ADC) Interrupt Disable Register */
-#define REG_ADC_IMR REG_ACCESS(RoReg, 0x400AC02CU) /**< \brief (ADC) Interrupt Mask Register */
-#define REG_ADC_CDR REG_ACCESS(RoReg, 0x400AC030U) /**< \brief (ADC) Channel Data Register */
-#define REG_ADC_RPR REG_ACCESS(RwReg, 0x400AC100U) /**< \brief (ADC) Receive Pointer Register */
-#define REG_ADC_RCR REG_ACCESS(RwReg, 0x400AC104U) /**< \brief (ADC) Receive Counter Register */
-#define REG_ADC_TPR REG_ACCESS(RwReg, 0x400AC108U) /**< \brief (ADC) Transmit Pointer Register */
-#define REG_ADC_TCR REG_ACCESS(RwReg, 0x400AC10CU) /**< \brief (ADC) Transmit Counter Register */
-#define REG_ADC_RNPR REG_ACCESS(RwReg, 0x400AC110U) /**< \brief (ADC) Receive Next Pointer Register */
-#define REG_ADC_RNCR REG_ACCESS(RwReg, 0x400AC114U) /**< \brief (ADC) Receive Next Counter Register */
-#define REG_ADC_TNPR REG_ACCESS(RwReg, 0x400AC118U) /**< \brief (ADC) Transmit Next Pointer Register */
-#define REG_ADC_TNCR REG_ACCESS(RwReg, 0x400AC11CU) /**< \brief (ADC) Transmit Next Counter Register */
-#define REG_ADC_PTCR REG_ACCESS(WoReg, 0x400AC120U) /**< \brief (ADC) Transfer Control Register */
-#define REG_ADC_PTSR REG_ACCESS(RoReg, 0x400AC124U) /**< \brief (ADC) Transfer Status Register */
-/* ========== Register definition for DMAC peripheral ========== */
-#define REG_DMAC_GCFG REG_ACCESS(RwReg, 0x400B0000U) /**< \brief (DMAC) DMAC Global Configuration Register */
-#define REG_DMAC_EN REG_ACCESS(RwReg, 0x400B0004U) /**< \brief (DMAC) DMAC Enable Register */
-#define REG_DMAC_SREQ REG_ACCESS(RwReg, 0x400B0008U) /**< \brief (DMAC) DMAC Software Single Request Register */
-#define REG_DMAC_CREQ REG_ACCESS(RwReg, 0x400B000CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */
-#define REG_DMAC_LAST REG_ACCESS(RwReg, 0x400B0010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */
-#define REG_DMAC_EBCIER REG_ACCESS(WoReg, 0x400B0018U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. */
-#define REG_DMAC_EBCIDR REG_ACCESS(WoReg, 0x400B001CU) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register. */
-#define REG_DMAC_EBCIMR REG_ACCESS(RoReg, 0x400B0020U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register. */
-#define REG_DMAC_EBCISR REG_ACCESS(RoReg, 0x400B0024U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Status Register. */
-#define REG_DMAC_CHER REG_ACCESS(WoReg, 0x400B0028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */
-#define REG_DMAC_CHDR REG_ACCESS(WoReg, 0x400B002CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */
-#define REG_DMAC_CHSR REG_ACCESS(RoReg, 0x400B0030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */
-#define REG_DMAC_SADDR0 REG_ACCESS(RwReg, 0x400B003CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */
-#define REG_DMAC_DADDR0 REG_ACCESS(RwReg, 0x400B0040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */
-#define REG_DMAC_DSCR0 REG_ACCESS(RwReg, 0x400B0044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */
-#define REG_DMAC_CTRLA0 REG_ACCESS(RwReg, 0x400B0048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */
-#define REG_DMAC_CTRLB0 REG_ACCESS(RwReg, 0x400B004CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */
-#define REG_DMAC_CFG0 REG_ACCESS(RwReg, 0x400B0050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */
-#define REG_DMAC_SADDR1 REG_ACCESS(RwReg, 0x400B0064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */
-#define REG_DMAC_DADDR1 REG_ACCESS(RwReg, 0x400B0068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */
-#define REG_DMAC_DSCR1 REG_ACCESS(RwReg, 0x400B006CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */
-#define REG_DMAC_CTRLA1 REG_ACCESS(RwReg, 0x400B0070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */
-#define REG_DMAC_CTRLB1 REG_ACCESS(RwReg, 0x400B0074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */
-#define REG_DMAC_CFG1 REG_ACCESS(RwReg, 0x400B0078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */
-#define REG_DMAC_SADDR2 REG_ACCESS(RwReg, 0x400B008CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */
-#define REG_DMAC_DADDR2 REG_ACCESS(RwReg, 0x400B0090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */
-#define REG_DMAC_DSCR2 REG_ACCESS(RwReg, 0x400B0094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */
-#define REG_DMAC_CTRLA2 REG_ACCESS(RwReg, 0x400B0098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */
-#define REG_DMAC_CTRLB2 REG_ACCESS(RwReg, 0x400B009CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */
-#define REG_DMAC_CFG2 REG_ACCESS(RwReg, 0x400B00A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */
-#define REG_DMAC_SADDR3 REG_ACCESS(RwReg, 0x400B00B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */
-#define REG_DMAC_DADDR3 REG_ACCESS(RwReg, 0x400B00B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */
-#define REG_DMAC_DSCR3 REG_ACCESS(RwReg, 0x400B00BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */
-#define REG_DMAC_CTRLA3 REG_ACCESS(RwReg, 0x400B00C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */
-#define REG_DMAC_CTRLB3 REG_ACCESS(RwReg, 0x400B00C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */
-#define REG_DMAC_CFG3 REG_ACCESS(RwReg, 0x400B00C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */
-/* ========== Register definition for SMC peripheral ========== */
-#define REG_SMC_CFG REG_ACCESS(RwReg, 0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */
-#define REG_SMC_CTRL REG_ACCESS(WoReg, 0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */
-#define REG_SMC_SR REG_ACCESS(RoReg, 0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */
-#define REG_SMC_IER REG_ACCESS(WoReg, 0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */
-#define REG_SMC_IDR REG_ACCESS(WoReg, 0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */
-#define REG_SMC_IMR REG_ACCESS(RoReg, 0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */
-#define REG_SMC_ADDR REG_ACCESS(RwReg, 0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */
-#define REG_SMC_BANK REG_ACCESS(RwReg, 0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */
-#define REG_SMC_ECC_CTRL REG_ACCESS(WoReg, 0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */
-#define REG_SMC_ECC_MD REG_ACCESS(RwReg, 0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */
-#define REG_SMC_ECC_SR1 REG_ACCESS(RoReg, 0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */
-#define REG_SMC_ECC_PR0 REG_ACCESS(RoReg, 0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */
-#define REG_SMC_ECC_PR1 REG_ACCESS(RoReg, 0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */
-#define REG_SMC_ECC_SR2 REG_ACCESS(RoReg, 0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */
-#define REG_SMC_ECC_PR2 REG_ACCESS(RoReg, 0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */
-#define REG_SMC_ECC_PR3 REG_ACCESS(RoReg, 0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */
-#define REG_SMC_ECC_PR4 REG_ACCESS(RoReg, 0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */
-#define REG_SMC_ECC_PR5 REG_ACCESS(RoReg, 0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */
-#define REG_SMC_ECC_PR6 REG_ACCESS(RoReg, 0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */
-#define REG_SMC_ECC_PR7 REG_ACCESS(RoReg, 0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */
-#define REG_SMC_ECC_PR8 REG_ACCESS(RoReg, 0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */
-#define REG_SMC_ECC_PR9 REG_ACCESS(RoReg, 0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */
-#define REG_SMC_ECC_PR10 REG_ACCESS(RoReg, 0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */
-#define REG_SMC_ECC_PR11 REG_ACCESS(RoReg, 0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */
-#define REG_SMC_ECC_PR12 REG_ACCESS(RoReg, 0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */
-#define REG_SMC_ECC_PR13 REG_ACCESS(RoReg, 0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */
-#define REG_SMC_ECC_PR14 REG_ACCESS(RoReg, 0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */
-#define REG_SMC_ECC_PR15 REG_ACCESS(RoReg, 0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */
-#define REG_SMC_SETUP0 REG_ACCESS(RwReg, 0x400E0070U) /**< \brief (SMC) SMC SETUP Register (CS_number = 0) */
-#define REG_SMC_PULSE0 REG_ACCESS(RwReg, 0x400E0074U) /**< \brief (SMC) SMC PULSE Register (CS_number = 0) */
-#define REG_SMC_CYCLE0 REG_ACCESS(RwReg, 0x400E0078U) /**< \brief (SMC) SMC CYCLE Register (CS_number = 0) */
-#define REG_SMC_TIMINGS0 REG_ACCESS(RwReg, 0x400E007CU) /**< \brief (SMC) SMC TIMINGS Register (CS_number = 0) */
-#define REG_SMC_MODE0 REG_ACCESS(RwReg, 0x400E0080U) /**< \brief (SMC) SMC MODE Register (CS_number = 0) */
-#define REG_SMC_SETUP1 REG_ACCESS(RwReg, 0x400E0084U) /**< \brief (SMC) SMC SETUP Register (CS_number = 1) */
-#define REG_SMC_PULSE1 REG_ACCESS(RwReg, 0x400E0088U) /**< \brief (SMC) SMC PULSE Register (CS_number = 1) */
-#define REG_SMC_CYCLE1 REG_ACCESS(RwReg, 0x400E008CU) /**< \brief (SMC) SMC CYCLE Register (CS_number = 1) */
-#define REG_SMC_TIMINGS1 REG_ACCESS(RwReg, 0x400E0090U) /**< \brief (SMC) SMC TIMINGS Register (CS_number = 1) */
-#define REG_SMC_MODE1 REG_ACCESS(RwReg, 0x400E0094U) /**< \brief (SMC) SMC MODE Register (CS_number = 1) */
-#define REG_SMC_SETUP2 REG_ACCESS(RwReg, 0x400E0098U) /**< \brief (SMC) SMC SETUP Register (CS_number = 2) */
-#define REG_SMC_PULSE2 REG_ACCESS(RwReg, 0x400E009CU) /**< \brief (SMC) SMC PULSE Register (CS_number = 2) */
-#define REG_SMC_CYCLE2 REG_ACCESS(RwReg, 0x400E00A0U) /**< \brief (SMC) SMC CYCLE Register (CS_number = 2) */
-#define REG_SMC_TIMINGS2 REG_ACCESS(RwReg, 0x400E00A4U) /**< \brief (SMC) SMC TIMINGS Register (CS_number = 2) */
-#define REG_SMC_MODE2 REG_ACCESS(RwReg, 0x400E00A8U) /**< \brief (SMC) SMC MODE Register (CS_number = 2) */
-#define REG_SMC_SETUP3 REG_ACCESS(RwReg, 0x400E00ACU) /**< \brief (SMC) SMC SETUP Register (CS_number = 3) */
-#define REG_SMC_PULSE3 REG_ACCESS(RwReg, 0x400E00B0U) /**< \brief (SMC) SMC PULSE Register (CS_number = 3) */
-#define REG_SMC_CYCLE3 REG_ACCESS(RwReg, 0x400E00B4U) /**< \brief (SMC) SMC CYCLE Register (CS_number = 3) */
-#define REG_SMC_TIMINGS3 REG_ACCESS(RwReg, 0x400E00B8U) /**< \brief (SMC) SMC TIMINGS Register (CS_number = 3) */
-#define REG_SMC_MODE3 REG_ACCESS(RwReg, 0x400E00BCU) /**< \brief (SMC) SMC MODE Register (CS_number = 3) */
-#define REG_SMC_OCMS REG_ACCESS(RwReg, 0x400E0110U) /**< \brief (SMC) SMC OCMS MODE Register */
-#define REG_SMC_KEY1 REG_ACCESS(WoReg, 0x400E0114U) /**< \brief (SMC) SMC KEY1 Register */
-#define REG_SMC_KEY2 REG_ACCESS(WoReg, 0x400E0118U) /**< \brief (SMC) SMC KEY2 Register */
-#define REG_SMC_WPCR REG_ACCESS(WoReg, 0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */
-#define REG_SMC_WPSR REG_ACCESS(RoReg, 0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */
-/* ========== Register definition for MATRIX peripheral ========== */
-#define REG_MATRIX_MCFG REG_ACCESS(RwReg, 0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
-#define REG_MATRIX_SCFG REG_ACCESS(RwReg, 0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
-#define REG_MATRIX_PRAS0 REG_ACCESS(RwReg, 0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
-#define REG_MATRIX_PRAS1 REG_ACCESS(RwReg, 0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
-#define REG_MATRIX_PRAS2 REG_ACCESS(RwReg, 0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
-#define REG_MATRIX_PRAS3 REG_ACCESS(RwReg, 0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
-#define REG_MATRIX_PRAS4 REG_ACCESS(RwReg, 0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
-#define REG_MATRIX_PRAS5 REG_ACCESS(RwReg, 0x400E02A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
-#define REG_MATRIX_PRAS6 REG_ACCESS(RwReg, 0x400E02B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
-#define REG_MATRIX_PRAS7 REG_ACCESS(RwReg, 0x400E02B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
-#define REG_MATRIX_PRAS8 REG_ACCESS(RwReg, 0x400E02C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
-#define REG_MATRIX_PRAS9 REG_ACCESS(RwReg, 0x400E02C8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */
-#define REG_MATRIX_MRCR REG_ACCESS(RwReg, 0x400E0300U) /**< \brief (MATRIX) Master Remap Control Register */
-/* ========== Register definition for PMC peripheral ========== */
-#define REG_PMC_SCER REG_ACCESS(WoReg, 0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
-#define REG_PMC_SCDR REG_ACCESS(WoReg, 0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
-#define REG_PMC_SCSR REG_ACCESS(RoReg, 0x400E0408U) /**< \brief (PMC) System Clock Status Register */
-#define REG_PMC_PCER REG_ACCESS(WoReg, 0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register */
-#define REG_PMC_PCDR REG_ACCESS(WoReg, 0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register */
-//#define REG_PMC_PCSR REG_ACCESS(RoReg, 0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register */
-#define REG_PMC_UCKR REG_ACCESS(RwReg, 0x400E041CU) /**< \brief (PMC) UTMI Clock Register */
-#define REG_PMC_MOR REG_ACCESS(RwReg, 0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
-#define REG_PMC_MCFR REG_ACCESS(RoReg, 0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
-#define REG_PMC_PLLAR REG_ACCESS(RwReg, 0x400E0428U) /**< \brief (PMC) PLLA Register */
-#define REG_PMC_MCKR REG_ACCESS(RwReg, 0x400E0430U) /**< \brief (PMC) Master Clock Register */
-#define REG_PMC_PCK REG_ACCESS(RwReg, 0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
-#define REG_PMC_IER REG_ACCESS(WoReg, 0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
-#define REG_PMC_IDR REG_ACCESS(WoReg, 0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
-#define REG_PMC_SR REG_ACCESS(RoReg, 0x400E0468U) /**< \brief (PMC) Status Register */
-#define REG_PMC_IMR REG_ACCESS(RoReg, 0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
-#define REG_PMC_FSMR REG_ACCESS(RwReg, 0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
-#define REG_PMC_FSPR REG_ACCESS(RwReg, 0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
-#define REG_PMC_FOCR REG_ACCESS(WoReg, 0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
-/* ========== Register definition for UART peripheral ========== */
-#define REG_UART_CR REG_ACCESS(WoReg, 0x400E0600U) /**< \brief (UART) Control Register */
-#define REG_UART_MR REG_ACCESS(RwReg, 0x400E0604U) /**< \brief (UART) Mode Register */
-#define REG_UART_IER REG_ACCESS(WoReg, 0x400E0608U) /**< \brief (UART) Interrupt Enable Register */
-#define REG_UART_IDR REG_ACCESS(WoReg, 0x400E060CU) /**< \brief (UART) Interrupt Disable Register */
-#define REG_UART_IMR REG_ACCESS(RoReg, 0x400E0610U) /**< \brief (UART) Interrupt Mask Register */
-#define REG_UART_SR REG_ACCESS(RoReg, 0x400E0614U) /**< \brief (UART) Status Register */
-#define REG_UART_RHR REG_ACCESS(RoReg, 0x400E0618U) /**< \brief (UART) Receive Holding Register */
-#define REG_UART_THR REG_ACCESS(WoReg, 0x400E061CU) /**< \brief (UART) Transmit Holding Register */
-#define REG_UART_BRGR REG_ACCESS(RwReg, 0x400E0620U) /**< \brief (UART) Baud Rate Generator Register */
-#define REG_UART_RPR REG_ACCESS(RwReg, 0x400E0700U) /**< \brief (UART) Receive Pointer Register */
-#define REG_UART_RCR REG_ACCESS(RwReg, 0x400E0704U) /**< \brief (UART) Receive Counter Register */
-#define REG_UART_TPR REG_ACCESS(RwReg, 0x400E0708U) /**< \brief (UART) Transmit Pointer Register */
-#define REG_UART_TCR REG_ACCESS(RwReg, 0x400E070CU) /**< \brief (UART) Transmit Counter Register */
-#define REG_UART_RNPR REG_ACCESS(RwReg, 0x400E0710U) /**< \brief (UART) Receive Next Pointer Register */
-#define REG_UART_RNCR REG_ACCESS(RwReg, 0x400E0714U) /**< \brief (UART) Receive Next Counter Register */
-#define REG_UART_TNPR REG_ACCESS(RwReg, 0x400E0718U) /**< \brief (UART) Transmit Next Pointer Register */
-#define REG_UART_TNCR REG_ACCESS(RwReg, 0x400E071CU) /**< \brief (UART) Transmit Next Counter Register */
-#define REG_UART_PTCR REG_ACCESS(WoReg, 0x400E0720U) /**< \brief (UART) Transfer Control Register */
-#define REG_UART_PTSR REG_ACCESS(RoReg, 0x400E0724U) /**< \brief (UART) Transfer Status Register */
-/* ========== Register definition for CHIPID peripheral ========== */
-#define REG_CHIPID_CIDR REG_ACCESS(RoReg, 0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
-#define REG_CHIPID_EXID REG_ACCESS(RoReg, 0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
-/* ========== Register definition for EFC0 peripheral ========== */
-#define REG_EFC0_FMR REG_ACCESS(RwReg, 0x400E0800U) /**< \brief (EFC0) EEFC Flash Mode Register */
-#define REG_EFC0_FCR REG_ACCESS(WoReg, 0x400E0804U) /**< \brief (EFC0) EEFC Flash Command Register */
-#define REG_EFC0_FSR REG_ACCESS(RoReg, 0x400E0808U) /**< \brief (EFC0) EEFC Flash Status Register */
-#define REG_EFC0_FRR REG_ACCESS(RoReg, 0x400E080CU) /**< \brief (EFC0) EEFC Flash Result Register */
-/* ========== Register definition for EFC1 peripheral ========== */
-#define REG_EFC1_FMR REG_ACCESS(RwReg, 0x400E0A00U) /**< \brief (EFC1) EEFC Flash Mode Register */
-#define REG_EFC1_FCR REG_ACCESS(WoReg, 0x400E0A04U) /**< \brief (EFC1) EEFC Flash Command Register */
-#define REG_EFC1_FSR REG_ACCESS(RoReg, 0x400E0A08U) /**< \brief (EFC1) EEFC Flash Status Register */
-#define REG_EFC1_FRR REG_ACCESS(RoReg, 0x400E0A0CU) /**< \brief (EFC1) EEFC Flash Result Register */
-/* ========== Register definition for PIOA peripheral ========== */
-#define REG_PIOA_PER REG_ACCESS(WoReg, 0x400E0C00U) /**< \brief (PIOA) PIO Enable Register */
-#define REG_PIOA_PDR REG_ACCESS(WoReg, 0x400E0C04U) /**< \brief (PIOA) PIO Disable Register */
-#define REG_PIOA_PSR REG_ACCESS(RoReg, 0x400E0C08U) /**< \brief (PIOA) PIO Status Register */
-#define REG_PIOA_OER REG_ACCESS(WoReg, 0x400E0C10U) /**< \brief (PIOA) Output Enable Register */
-#define REG_PIOA_ODR REG_ACCESS(WoReg, 0x400E0C14U) /**< \brief (PIOA) Output Disable Register */
-#define REG_PIOA_OSR REG_ACCESS(RoReg, 0x400E0C18U) /**< \brief (PIOA) Output Status Register */
-#define REG_PIOA_IFER REG_ACCESS(WoReg, 0x400E0C20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
-#define REG_PIOA_IFDR REG_ACCESS(WoReg, 0x400E0C24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
-#define REG_PIOA_IFSR REG_ACCESS(RoReg, 0x400E0C28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
-#define REG_PIOA_SODR REG_ACCESS(WoReg, 0x400E0C30U) /**< \brief (PIOA) Set Output Data Register */
-#define REG_PIOA_CODR REG_ACCESS(WoReg, 0x400E0C34U) /**< \brief (PIOA) Clear Output Data Register */
-#define REG_PIOA_ODSR REG_ACCESS(RwReg, 0x400E0C38U) /**< \brief (PIOA) Output Data Status Register */
-#define REG_PIOA_PDSR REG_ACCESS(RoReg, 0x400E0C3CU) /**< \brief (PIOA) Pin Data Status Register */
-#define REG_PIOA_IER REG_ACCESS(WoReg, 0x400E0C40U) /**< \brief (PIOA) Interrupt Enable Register */
-#define REG_PIOA_IDR REG_ACCESS(WoReg, 0x400E0C44U) /**< \brief (PIOA) Interrupt Disable Register */
-#define REG_PIOA_IMR REG_ACCESS(RoReg, 0x400E0C48U) /**< \brief (PIOA) Interrupt Mask Register */
-#define REG_PIOA_ISR REG_ACCESS(RoReg, 0x400E0C4CU) /**< \brief (PIOA) Interrupt Status Register */
-#define REG_PIOA_MDER REG_ACCESS(WoReg, 0x400E0C50U) /**< \brief (PIOA) Multi-driver Enable Register */
-#define REG_PIOA_MDDR REG_ACCESS(WoReg, 0x400E0C54U) /**< \brief (PIOA) Multi-driver Disable Register */
-#define REG_PIOA_MDSR REG_ACCESS(RoReg, 0x400E0C58U) /**< \brief (PIOA) Multi-driver Status Register */
-#define REG_PIOA_PUDR REG_ACCESS(WoReg, 0x400E0C60U) /**< \brief (PIOA) Pull-up Disable Register */
-#define REG_PIOA_PUER REG_ACCESS(WoReg, 0x400E0C64U) /**< \brief (PIOA) Pull-up Enable Register */
-#define REG_PIOA_PUSR REG_ACCESS(RoReg, 0x400E0C68U) /**< \brief (PIOA) Pad Pull-up Status Register */
-#define REG_PIOA_ABSR REG_ACCESS(RwReg, 0x400E0C70U) /**< \brief (PIOA) Peripheral AB Select Register */
-#define REG_PIOA_SCIFSR REG_ACCESS(WoReg, 0x400E0C80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */
-#define REG_PIOA_DIFSR REG_ACCESS(WoReg, 0x400E0C84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */
-#define REG_PIOA_IFDGSR REG_ACCESS(RoReg, 0x400E0C88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */
-#define REG_PIOA_SCDR REG_ACCESS(RwReg, 0x400E0C8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
-#define REG_PIOA_OWER REG_ACCESS(WoReg, 0x400E0CA0U) /**< \brief (PIOA) Output Write Enable */
-#define REG_PIOA_OWDR REG_ACCESS(WoReg, 0x400E0CA4U) /**< \brief (PIOA) Output Write Disable */
-#define REG_PIOA_OWSR REG_ACCESS(RoReg, 0x400E0CA8U) /**< \brief (PIOA) Output Write Status Register */
-#define REG_PIOA_AIMER REG_ACCESS(WoReg, 0x400E0CB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
-#define REG_PIOA_AIMDR REG_ACCESS(WoReg, 0x400E0CB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
-#define REG_PIOA_AIMMR REG_ACCESS(RoReg, 0x400E0CB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
-#define REG_PIOA_ESR REG_ACCESS(WoReg, 0x400E0CC0U) /**< \brief (PIOA) Edge Select Register */
-#define REG_PIOA_LSR REG_ACCESS(WoReg, 0x400E0CC4U) /**< \brief (PIOA) Level Select Register */
-#define REG_PIOA_ELSR REG_ACCESS(RoReg, 0x400E0CC8U) /**< \brief (PIOA) Edge/Level Status Register */
-#define REG_PIOA_FELLSR REG_ACCESS(WoReg, 0x400E0CD0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
-#define REG_PIOA_REHLSR REG_ACCESS(WoReg, 0x400E0CD4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
-#define REG_PIOA_FRLHSR REG_ACCESS(RoReg, 0x400E0CD8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
-#define REG_PIOA_LOCKSR REG_ACCESS(RoReg, 0x400E0CE0U) /**< \brief (PIOA) Lock Status */
-#define REG_PIOA_WPMR REG_ACCESS(RwReg, 0x400E0CE4U) /**< \brief (PIOA) Write Protect Mode Register */
-#define REG_PIOA_WPSR REG_ACCESS(RoReg, 0x400E0CE8U) /**< \brief (PIOA) Write Protect Status Register */
-/* ========== Register definition for PIOB peripheral ========== */
-#define REG_PIOB_PER REG_ACCESS(WoReg, 0x400E0E00U) /**< \brief (PIOB) PIO Enable Register */
-#define REG_PIOB_PDR REG_ACCESS(WoReg, 0x400E0E04U) /**< \brief (PIOB) PIO Disable Register */
-#define REG_PIOB_PSR REG_ACCESS(RoReg, 0x400E0E08U) /**< \brief (PIOB) PIO Status Register */
-#define REG_PIOB_OER REG_ACCESS(WoReg, 0x400E0E10U) /**< \brief (PIOB) Output Enable Register */
-#define REG_PIOB_ODR REG_ACCESS(WoReg, 0x400E0E14U) /**< \brief (PIOB) Output Disable Register */
-#define REG_PIOB_OSR REG_ACCESS(RoReg, 0x400E0E18U) /**< \brief (PIOB) Output Status Register */
-#define REG_PIOB_IFER REG_ACCESS(WoReg, 0x400E0E20U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
-#define REG_PIOB_IFDR REG_ACCESS(WoReg, 0x400E0E24U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
-#define REG_PIOB_IFSR REG_ACCESS(RoReg, 0x400E0E28U) /**< \brief (PIOB) Glitch Input Filter Status Register */
-#define REG_PIOB_SODR REG_ACCESS(WoReg, 0x400E0E30U) /**< \brief (PIOB) Set Output Data Register */
-#define REG_PIOB_CODR REG_ACCESS(WoReg, 0x400E0E34U) /**< \brief (PIOB) Clear Output Data Register */
-#define REG_PIOB_ODSR REG_ACCESS(RwReg, 0x400E0E38U) /**< \brief (PIOB) Output Data Status Register */
-#define REG_PIOB_PDSR REG_ACCESS(RoReg, 0x400E0E3CU) /**< \brief (PIOB) Pin Data Status Register */
-#define REG_PIOB_IER REG_ACCESS(WoReg, 0x400E0E40U) /**< \brief (PIOB) Interrupt Enable Register */
-#define REG_PIOB_IDR REG_ACCESS(WoReg, 0x400E0E44U) /**< \brief (PIOB) Interrupt Disable Register */
-#define REG_PIOB_IMR REG_ACCESS(RoReg, 0x400E0E48U) /**< \brief (PIOB) Interrupt Mask Register */
-#define REG_PIOB_ISR REG_ACCESS(RoReg, 0x400E0E4CU) /**< \brief (PIOB) Interrupt Status Register */
-#define REG_PIOB_MDER REG_ACCESS(WoReg, 0x400E0E50U) /**< \brief (PIOB) Multi-driver Enable Register */
-#define REG_PIOB_MDDR REG_ACCESS(WoReg, 0x400E0E54U) /**< \brief (PIOB) Multi-driver Disable Register */
-#define REG_PIOB_MDSR REG_ACCESS(RoReg, 0x400E0E58U) /**< \brief (PIOB) Multi-driver Status Register */
-#define REG_PIOB_PUDR REG_ACCESS(WoReg, 0x400E0E60U) /**< \brief (PIOB) Pull-up Disable Register */
-#define REG_PIOB_PUER REG_ACCESS(WoReg, 0x400E0E64U) /**< \brief (PIOB) Pull-up Enable Register */
-#define REG_PIOB_PUSR REG_ACCESS(RoReg, 0x400E0E68U) /**< \brief (PIOB) Pad Pull-up Status Register */
-#define REG_PIOB_ABSR REG_ACCESS(RwReg, 0x400E0E70U) /**< \brief (PIOB) Peripheral AB Select Register */
-#define REG_PIOB_SCIFSR REG_ACCESS(WoReg, 0x400E0E80U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */
-#define REG_PIOB_DIFSR REG_ACCESS(WoReg, 0x400E0E84U) /**< \brief (PIOB) Debouncing Input Filter Select Register */
-#define REG_PIOB_IFDGSR REG_ACCESS(RoReg, 0x400E0E88U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */
-#define REG_PIOB_SCDR REG_ACCESS(RwReg, 0x400E0E8CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
-#define REG_PIOB_OWER REG_ACCESS(WoReg, 0x400E0EA0U) /**< \brief (PIOB) Output Write Enable */
-#define REG_PIOB_OWDR REG_ACCESS(WoReg, 0x400E0EA4U) /**< \brief (PIOB) Output Write Disable */
-#define REG_PIOB_OWSR REG_ACCESS(RoReg, 0x400E0EA8U) /**< \brief (PIOB) Output Write Status Register */
-#define REG_PIOB_AIMER REG_ACCESS(WoReg, 0x400E0EB0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
-#define REG_PIOB_AIMDR REG_ACCESS(WoReg, 0x400E0EB4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
-#define REG_PIOB_AIMMR REG_ACCESS(RoReg, 0x400E0EB8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
-#define REG_PIOB_ESR REG_ACCESS(WoReg, 0x400E0EC0U) /**< \brief (PIOB) Edge Select Register */
-#define REG_PIOB_LSR REG_ACCESS(WoReg, 0x400E0EC4U) /**< \brief (PIOB) Level Select Register */
-#define REG_PIOB_ELSR REG_ACCESS(RoReg, 0x400E0EC8U) /**< \brief (PIOB) Edge/Level Status Register */
-#define REG_PIOB_FELLSR REG_ACCESS(WoReg, 0x400E0ED0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
-#define REG_PIOB_REHLSR REG_ACCESS(WoReg, 0x400E0ED4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
-#define REG_PIOB_FRLHSR REG_ACCESS(RoReg, 0x400E0ED8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
-#define REG_PIOB_LOCKSR REG_ACCESS(RoReg, 0x400E0EE0U) /**< \brief (PIOB) Lock Status */
-#define REG_PIOB_WPMR REG_ACCESS(RwReg, 0x400E0EE4U) /**< \brief (PIOB) Write Protect Mode Register */
-#define REG_PIOB_WPSR REG_ACCESS(RoReg, 0x400E0EE8U) /**< \brief (PIOB) Write Protect Status Register */
-/* ========== Register definition for PIOC peripheral ========== */
-#define REG_PIOC_PER REG_ACCESS(WoReg, 0x400E1000U) /**< \brief (PIOC) PIO Enable Register */
-#define REG_PIOC_PDR REG_ACCESS(WoReg, 0x400E1004U) /**< \brief (PIOC) PIO Disable Register */
-#define REG_PIOC_PSR REG_ACCESS(RoReg, 0x400E1008U) /**< \brief (PIOC) PIO Status Register */
-#define REG_PIOC_OER REG_ACCESS(WoReg, 0x400E1010U) /**< \brief (PIOC) Output Enable Register */
-#define REG_PIOC_ODR REG_ACCESS(WoReg, 0x400E1014U) /**< \brief (PIOC) Output Disable Register */
-#define REG_PIOC_OSR REG_ACCESS(RoReg, 0x400E1018U) /**< \brief (PIOC) Output Status Register */
-#define REG_PIOC_IFER REG_ACCESS(WoReg, 0x400E1020U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
-#define REG_PIOC_IFDR REG_ACCESS(WoReg, 0x400E1024U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
-#define REG_PIOC_IFSR REG_ACCESS(RoReg, 0x400E1028U) /**< \brief (PIOC) Glitch Input Filter Status Register */
-#define REG_PIOC_SODR REG_ACCESS(WoReg, 0x400E1030U) /**< \brief (PIOC) Set Output Data Register */
-#define REG_PIOC_CODR REG_ACCESS(WoReg, 0x400E1034U) /**< \brief (PIOC) Clear Output Data Register */
-#define REG_PIOC_ODSR REG_ACCESS(RwReg, 0x400E1038U) /**< \brief (PIOC) Output Data Status Register */
-#define REG_PIOC_PDSR REG_ACCESS(RoReg, 0x400E103CU) /**< \brief (PIOC) Pin Data Status Register */
-#define REG_PIOC_IER REG_ACCESS(WoReg, 0x400E1040U) /**< \brief (PIOC) Interrupt Enable Register */
-#define REG_PIOC_IDR REG_ACCESS(WoReg, 0x400E1044U) /**< \brief (PIOC) Interrupt Disable Register */
-#define REG_PIOC_IMR REG_ACCESS(RoReg, 0x400E1048U) /**< \brief (PIOC) Interrupt Mask Register */
-#define REG_PIOC_ISR REG_ACCESS(RoReg, 0x400E104CU) /**< \brief (PIOC) Interrupt Status Register */
-#define REG_PIOC_MDER REG_ACCESS(WoReg, 0x400E1050U) /**< \brief (PIOC) Multi-driver Enable Register */
-#define REG_PIOC_MDDR REG_ACCESS(WoReg, 0x400E1054U) /**< \brief (PIOC) Multi-driver Disable Register */
-#define REG_PIOC_MDSR REG_ACCESS(RoReg, 0x400E1058U) /**< \brief (PIOC) Multi-driver Status Register */
-#define REG_PIOC_PUDR REG_ACCESS(WoReg, 0x400E1060U) /**< \brief (PIOC) Pull-up Disable Register */
-#define REG_PIOC_PUER REG_ACCESS(WoReg, 0x400E1064U) /**< \brief (PIOC) Pull-up Enable Register */
-#define REG_PIOC_PUSR REG_ACCESS(RoReg, 0x400E1068U) /**< \brief (PIOC) Pad Pull-up Status Register */
-#define REG_PIOC_ABSR REG_ACCESS(RwReg, 0x400E1070U) /**< \brief (PIOC) Peripheral AB Select Register */
-#define REG_PIOC_SCIFSR REG_ACCESS(WoReg, 0x400E1080U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */
-#define REG_PIOC_DIFSR REG_ACCESS(WoReg, 0x400E1084U) /**< \brief (PIOC) Debouncing Input Filter Select Register */
-#define REG_PIOC_IFDGSR REG_ACCESS(RoReg, 0x400E1088U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */
-#define REG_PIOC_SCDR REG_ACCESS(RwReg, 0x400E108CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
-#define REG_PIOC_OWER REG_ACCESS(WoReg, 0x400E10A0U) /**< \brief (PIOC) Output Write Enable */
-#define REG_PIOC_OWDR REG_ACCESS(WoReg, 0x400E10A4U) /**< \brief (PIOC) Output Write Disable */
-#define REG_PIOC_OWSR REG_ACCESS(RoReg, 0x400E10A8U) /**< \brief (PIOC) Output Write Status Register */
-#define REG_PIOC_AIMER REG_ACCESS(WoReg, 0x400E10B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
-#define REG_PIOC_AIMDR REG_ACCESS(WoReg, 0x400E10B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
-#define REG_PIOC_AIMMR REG_ACCESS(RoReg, 0x400E10B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
-#define REG_PIOC_ESR REG_ACCESS(WoReg, 0x400E10C0U) /**< \brief (PIOC) Edge Select Register */
-#define REG_PIOC_LSR REG_ACCESS(WoReg, 0x400E10C4U) /**< \brief (PIOC) Level Select Register */
-#define REG_PIOC_ELSR REG_ACCESS(RoReg, 0x400E10C8U) /**< \brief (PIOC) Edge/Level Status Register */
-#define REG_PIOC_FELLSR REG_ACCESS(WoReg, 0x400E10D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
-#define REG_PIOC_REHLSR REG_ACCESS(WoReg, 0x400E10D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
-#define REG_PIOC_FRLHSR REG_ACCESS(RoReg, 0x400E10D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
-#define REG_PIOC_LOCKSR REG_ACCESS(RoReg, 0x400E10E0U) /**< \brief (PIOC) Lock Status */
-#define REG_PIOC_WPMR REG_ACCESS(RwReg, 0x400E10E4U) /**< \brief (PIOC) Write Protect Mode Register */
-#define REG_PIOC_WPSR REG_ACCESS(RoReg, 0x400E10E8U) /**< \brief (PIOC) Write Protect Status Register */
-/* ========== Register definition for RSTC peripheral ========== */
-#define REG_RSTC_CR REG_ACCESS(WoReg, 0x400E1200U) /**< \brief (RSTC) Control Register */
-#define REG_RSTC_SR REG_ACCESS(RoReg, 0x400E1204U) /**< \brief (RSTC) Status Register */
-#define REG_RSTC_MR REG_ACCESS(RwReg, 0x400E1208U) /**< \brief (RSTC) Mode Register */
-/* ========== Register definition for SUPC peripheral ========== */
-#define REG_SUPC_CR REG_ACCESS(WoReg, 0x400E1210U) /**< \brief (SUPC) Supply Controller Control Register */
-#define REG_SUPC_SMMR REG_ACCESS(RwReg, 0x400E1214U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
-#define REG_SUPC_MR REG_ACCESS(RwReg, 0x400E1218U) /**< \brief (SUPC) Supply Controller Mode Register */
-#define REG_SUPC_WUMR REG_ACCESS(RwReg, 0x400E121CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
-#define REG_SUPC_WUIR REG_ACCESS(RwReg, 0x400E1220U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
-#define REG_SUPC_SR REG_ACCESS(RoReg, 0x400E1224U) /**< \brief (SUPC) Supply Controller Status Register */
-/* ========== Register definition for RTT peripheral ========== */
-#define REG_RTT_MR REG_ACCESS(RwReg, 0x400E1230U) /**< \brief (RTT) Mode Register */
-#define REG_RTT_AR REG_ACCESS(RwReg, 0x400E1234U) /**< \brief (RTT) Alarm Register */
-#define REG_RTT_VR REG_ACCESS(RoReg, 0x400E1238U) /**< \brief (RTT) Value Register */
-#define REG_RTT_SR REG_ACCESS(RoReg, 0x400E123CU) /**< \brief (RTT) Status Register */
-/* ========== Register definition for WDT peripheral ========== */
-#define REG_WDT_CR REG_ACCESS(WoReg, 0x400E1250U) /**< \brief (WDT) Control Register */
-#define REG_WDT_MR REG_ACCESS(RwReg, 0x400E1254U) /**< \brief (WDT) Mode Register */
-#define REG_WDT_SR REG_ACCESS(RoReg, 0x400E1258U) /**< \brief (WDT) Status Register */
-/* ========== Register definition for RTC peripheral ========== */
-#define REG_RTC_CR REG_ACCESS(RwReg, 0x400E1260U) /**< \brief (RTC) Control Register */
-#define REG_RTC_MR REG_ACCESS(RwReg, 0x400E1264U) /**< \brief (RTC) Mode Register */
-#define REG_RTC_TIMR REG_ACCESS(RwReg, 0x400E1268U) /**< \brief (RTC) Time Register */
-#define REG_RTC_CALR REG_ACCESS(RwReg, 0x400E126CU) /**< \brief (RTC) Calendar Register */
-#define REG_RTC_TIMALR REG_ACCESS(RwReg, 0x400E1270U) /**< \brief (RTC) Time Alarm Register */
-#define REG_RTC_CALALR REG_ACCESS(RwReg, 0x400E1274U) /**< \brief (RTC) Calendar Alarm Register */
-#define REG_RTC_SR REG_ACCESS(RoReg, 0x400E1278U) /**< \brief (RTC) Status Register */
-#define REG_RTC_SCCR REG_ACCESS(WoReg, 0x400E127CU) /**< \brief (RTC) Status Clear Command Register */
-#define REG_RTC_IER REG_ACCESS(WoReg, 0x400E1280U) /**< \brief (RTC) Interrupt Enable Register */
-#define REG_RTC_IDR REG_ACCESS(WoReg, 0x400E1284U) /**< \brief (RTC) Interrupt Disable Register */
-#define REG_RTC_IMR REG_ACCESS(RoReg, 0x400E1288U) /**< \brief (RTC) Interrupt Mask Register */
-#define REG_RTC_VER REG_ACCESS(RoReg, 0x400E128CU) /**< \brief (RTC) Valid Entry Register */
-/* ========== Register definition for GPBR peripheral ========== */
-#define REG_GPBR_GPBR0 REG_ACCESS(RwReg, 0x400E1290U) /**< \brief (GPBR) General Purpose Backup Register 0 */
-#define REG_GPBR_GPBR1 REG_ACCESS(RwReg, 0x400E1294U) /**< \brief (GPBR) General Purpose Backup Register 1 */
-#define REG_GPBR_GPBR2 REG_ACCESS(RwReg, 0x400E1298U) /**< \brief (GPBR) General Purpose Backup Register 2 */
-#define REG_GPBR_GPBR3 REG_ACCESS(RwReg, 0x400E129CU) /**< \brief (GPBR) General Purpose Backup Register 3 */
-/*@}*/
-
-/* ***************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR AT91SAM3U */
-/* ***************************************************************************** */
-/** \addtogroup AT91SAM3U_id Peripheral Ids Definitions */
-/*@{*/
-
-#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
-#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
-#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
-#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
-#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
-#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
-#define ID_EFC0 ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */
-#define ID_EFC1 ( 7) /**< \brief Enhanced Embedded Flash Controller 1 (EFC1) */
-#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART) */
-#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */
-#define ID_PIOA (10) /**< \brief Parallel I/O Controller A, (PIOA) */
-#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
-#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */
-#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
-#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
-#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
-#define ID_USART3 (16) /**< \brief USART 3 (USART3) */
-#define ID_HSMCI (17) /**< \brief High Speed Multimedia Card Interface (HSMCI) */
-#define ID_TWI0 (18) /**< \brief Two-Wire Interface 0 (TWI0) */
-#define ID_TWI1 (19) /**< \brief Two-Wire Interface 1 (TWI1) */
-#define ID_SPI (20) /**< \brief Serial Peripheral Interface (SPI) */
-#define ID_SSC (21) /**< \brief Synchronous Serial Controller (SSC) */
-#define ID_TC0 (22) /**< \brief Timer Counter 0 (TC0) */
-#define ID_TC1 (23) /**< \brief Timer Counter 1 (TC1) */
-#define ID_TC2 (24) /**< \brief Timer Counter 2 (TC2) */
-#define ID_PWM (25) /**< \brief Pulse Width Modulation Controller (PWM) */
-#define ID_ADC12B (26) /**< \brief 12-bit ADC Controller (ADC12B) */
-#define ID_ADC (27) /**< \brief 10-bit ADC Controller (ADC) */
-#define ID_DMAC (28) /**< \brief DMA Controller (DMAC) */
-#define ID_UDPHS (29) /**< \brief USB Device High Speed (UDPHS) */
-/*@}*/
-
-/* ***************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR AT91SAM3U */
-/* ***************************************************************************** */
-/** \addtogroup AT91SAM3U_base Peripheral Base Address Definitions */
-/*@{*/
-
-#define HSMCI CAST(Hsmci , 0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC CAST(Ssc , 0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */
-#define TC0 CAST(Tc , 0x40080000U) /**< \brief (TC0 ) Base Address */
-#define TWI0 CAST(Twi , 0x40084000U) /**< \brief (TWI0 ) Base Address */
-#define PDC_TWI0 CAST(Pdc , 0x40084100U) /**< \brief (PDC_TWI0 ) Base Address */
-#define TWI1 CAST(Twi , 0x40088000U) /**< \brief (TWI1 ) Base Address */
-#define PDC_TWI1 CAST(Pdc , 0x40088100U) /**< \brief (PDC_TWI1 ) Base Address */
-#define PWM CAST(Pwm , 0x4008C000U) /**< \brief (PWM ) Base Address */
-#define PDC_PWM CAST(Pdc , 0x4008C100U) /**< \brief (PDC_PWM ) Base Address */
-#define USART0 CAST(Usart , 0x40090000U) /**< \brief (USART0 ) Base Address */
-#define PDC_USART0 CAST(Pdc , 0x40090100U) /**< \brief (PDC_USART0) Base Address */
-#define USART1 CAST(Usart , 0x40094000U) /**< \brief (USART1 ) Base Address */
-#define PDC_USART1 CAST(Pdc , 0x40094100U) /**< \brief (PDC_USART1) Base Address */
-#define USART2 CAST(Usart , 0x40098000U) /**< \brief (USART2 ) Base Address */
-#define PDC_USART2 CAST(Pdc , 0x40098100U) /**< \brief (PDC_USART2) Base Address */
-#define USART3 CAST(Usart , 0x4009C000U) /**< \brief (USART3 ) Base Address */
-#define PDC_USART3 CAST(Pdc , 0x4009C100U) /**< \brief (PDC_USART3) Base Address */
-#define UDPHS CAST(Udphs , 0x400A4000U) /**< \brief (UDPHS ) Base Address */
-#define ADC12B CAST(Adc12b , 0x400A8000U) /**< \brief (ADC12B ) Base Address */
-#define PDC_ADC12B CAST(Pdc , 0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
-#define ADC CAST(Adc , 0x400AC000U) /**< \brief (ADC ) Base Address */
-#define PDC_ADC CAST(Pdc , 0x400AC100U) /**< \brief (PDC_ADC ) Base Address */
-#define DMAC CAST(Dmac , 0x400B0000U) /**< \brief (DMAC ) Base Address */
-#define SMC CAST(Smc , 0x400E0000U) /**< \brief (SMC ) Base Address */
-#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */
-#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */
-#define UART CAST(Uart , 0x400E0600U) /**< \brief (UART ) Base Address */
-#define PDC_UART CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART ) Base Address */
-#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */
-#define EFC0 CAST(Efc , 0x400E0800U) /**< \brief (EFC0 ) Base Address */
-#define EFC1 CAST(Efc , 0x400E0A00U) /**< \brief (EFC1 ) Base Address */
-#define PIOA CAST(Pio , 0x400E0C00U) /**< \brief (PIOA ) Base Address */
-#define PIOB CAST(Pio , 0x400E0E00U) /**< \brief (PIOB ) Base Address */
-#define PIOC CAST(Pio , 0x400E1000U) /**< \brief (PIOC ) Base Address */
-#define RSTC CAST(Rstc , 0x400E1200U) /**< \brief (RSTC ) Base Address */
-#define SUPC CAST(Supc , 0x400E1210U) /**< \brief (SUPC ) Base Address */
-#define RTT CAST(Rtt , 0x400E1230U) /**< \brief (RTT ) Base Address */
-#define WDT CAST(Wdt , 0x400E1250U) /**< \brief (WDT ) Base Address */
-#define RTC CAST(Rtc , 0x400E1260U) /**< \brief (RTC ) Base Address */
-#define GPBR CAST(Gpbr , 0x400E1290U) /**< \brief (GPBR ) Base Address */
-/*@}*/
-
-/* ***************************************************************************** */
-/* PIO DEFINITIONS FOR AT91SAM3U */
-/* ***************************************************************************** */
-/** \addtogroup AT91SAM3U_pio Peripheral Pio Definitions */
-/*@{*/
-
-#define PIO_PA0 (1 << 0) /**< \brief Pin Controlled by PA0 */
-#define PIO_PA1 (1 << 1) /**< \brief Pin Controlled by PA1 */
-#define PIO_PA2 (1 << 2) /**< \brief Pin Controlled by PA2 */
-#define PIO_PA3 (1 << 3) /**< \brief Pin Controlled by PA3 */
-#define PIO_PA4 (1 << 4) /**< \brief Pin Controlled by PA4 */
-#define PIO_PA5 (1 << 5) /**< \brief Pin Controlled by PA5 */
-#define PIO_PA6 (1 << 6) /**< \brief Pin Controlled by PA6 */
-#define PIO_PA7 (1 << 7) /**< \brief Pin Controlled by PA7 */
-#define PIO_PA8 (1 << 8) /**< \brief Pin Controlled by PA8 */
-#define PIO_PA9 (1 << 9) /**< \brief Pin Controlled by PA9 */
-#define PIO_PA10 (1 << 10) /**< \brief Pin Controlled by PA10 */
-#define PIO_PA11 (1 << 11) /**< \brief Pin Controlled by PA11 */
-#define PIO_PA12 (1 << 12) /**< \brief Pin Controlled by PA12 */
-#define PIO_PA13 (1 << 13) /**< \brief Pin Controlled by PA13 */
-#define PIO_PA14 (1 << 14) /**< \brief Pin Controlled by PA14 */
-#define PIO_PA15 (1 << 15) /**< \brief Pin Controlled by PA15 */
-#define PIO_PA16 (1 << 16) /**< \brief Pin Controlled by PA16 */
-#define PIO_PA17 (1 << 17) /**< \brief Pin Controlled by PA17 */
-#define PIO_PA18 (1 << 18) /**< \brief Pin Controlled by PA18 */
-#define PIO_PA19 (1 << 19) /**< \brief Pin Controlled by PA19 */
-#define PIO_PA20 (1 << 20) /**< \brief Pin Controlled by PA20 */
-#define PIO_PA21 (1 << 21) /**< \brief Pin Controlled by PA21 */
-#define PIO_PA22 (1 << 22) /**< \brief Pin Controlled by PA22 */
-#define PIO_PA23 (1 << 23) /**< \brief Pin Controlled by PA23 */
-#define PIO_PA24 (1 << 24) /**< \brief Pin Controlled by PA24 */
-#define PIO_PA25 (1 << 25) /**< \brief Pin Controlled by PA25 */
-#define PIO_PA26 (1 << 26) /**< \brief Pin Controlled by PA26 */
-#define PIO_PA27 (1 << 27) /**< \brief Pin Controlled by PA27 */
-#define PIO_PA28 (1 << 28) /**< \brief Pin Controlled by PA28 */
-#define PIO_PA29 (1 << 29) /**< \brief Pin Controlled by PA29 */
-#define PIO_PA30 (1 << 30) /**< \brief Pin Controlled by PA30 */
-#define PIO_PA31 (1 << 31) /**< \brief Pin Controlled by PA31 */
-#define PIO_PB0 (1 << 0) /**< \brief Pin Controlled by PB0 */
-#define PIO_PB1 (1 << 1) /**< \brief Pin Controlled by PB1 */
-#define PIO_PB2 (1 << 2) /**< \brief Pin Controlled by PB2 */
-#define PIO_PB3 (1 << 3) /**< \brief Pin Controlled by PB3 */
-#define PIO_PB4 (1 << 4) /**< \brief Pin Controlled by PB4 */
-#define PIO_PB5 (1 << 5) /**< \brief Pin Controlled by PB5 */
-#define PIO_PB6 (1 << 6) /**< \brief Pin Controlled by PB6 */
-#define PIO_PB7 (1 << 7) /**< \brief Pin Controlled by PB7 */
-#define PIO_PB8 (1 << 8) /**< \brief Pin Controlled by PB8 */
-#define PIO_PB9 (1 << 9) /**< \brief Pin Controlled by PB9 */
-#define PIO_PB10 (1 << 10) /**< \brief Pin Controlled by PB10 */
-#define PIO_PB11 (1 << 11) /**< \brief Pin Controlled by PB11 */
-#define PIO_PB12 (1 << 12) /**< \brief Pin Controlled by PB12 */
-#define PIO_PB13 (1 << 13) /**< \brief Pin Controlled by PB13 */
-#define PIO_PB14 (1 << 14) /**< \brief Pin Controlled by PB14 */
-#define PIO_PB15 (1 << 15) /**< \brief Pin Controlled by PB15 */
-#define PIO_PB16 (1 << 16) /**< \brief Pin Controlled by PB16 */
-#define PIO_PB17 (1 << 17) /**< \brief Pin Controlled by PB17 */
-#define PIO_PB18 (1 << 18) /**< \brief Pin Controlled by PB18 */
-#define PIO_PB19 (1 << 19) /**< \brief Pin Controlled by PB19 */
-#define PIO_PB20 (1 << 20) /**< \brief Pin Controlled by PB20 */
-#define PIO_PB21 (1 << 21) /**< \brief Pin Controlled by PB21 */
-#define PIO_PB22 (1 << 22) /**< \brief Pin Controlled by PB22 */
-#define PIO_PB23 (1 << 23) /**< \brief Pin Controlled by PB23 */
-#define PIO_PB24 (1 << 24) /**< \brief Pin Controlled by PB24 */
-#define PIO_PB25 (1 << 25) /**< \brief Pin Controlled by PB25 */
-#define PIO_PB26 (1 << 26) /**< \brief Pin Controlled by PB26 */
-#define PIO_PB27 (1 << 27) /**< \brief Pin Controlled by PB27 */
-#define PIO_PB28 (1 << 28) /**< \brief Pin Controlled by PB28 */
-#define PIO_PB29 (1 << 29) /**< \brief Pin Controlled by PB29 */
-#define PIO_PB30 (1 << 30) /**< \brief Pin Controlled by PB30 */
-#define PIO_PB31 (1 << 31) /**< \brief Pin Controlled by PB31 */
-#define PIO_PC0 (1 << 0) /**< \brief Pin Controlled by PC0 */
-#define PIO_PC1 (1 << 1) /**< \brief Pin Controlled by PC1 */
-#define PIO_PC2 (1 << 2) /**< \brief Pin Controlled by PC2 */
-#define PIO_PC3 (1 << 3) /**< \brief Pin Controlled by PC3 */
-#define PIO_PC4 (1 << 4) /**< \brief Pin Controlled by PC4 */
-#define PIO_PC5 (1 << 5) /**< \brief Pin Controlled by PC5 */
-#define PIO_PC6 (1 << 6) /**< \brief Pin Controlled by PC6 */
-#define PIO_PC7 (1 << 7) /**< \brief Pin Controlled by PC7 */
-#define PIO_PC8 (1 << 8) /**< \brief Pin Controlled by PC8 */
-#define PIO_PC9 (1 << 9) /**< \brief Pin Controlled by PC9 */
-#define PIO_PC10 (1 << 10) /**< \brief Pin Controlled by PC10 */
-#define PIO_PC11 (1 << 11) /**< \brief Pin Controlled by PC11 */
-#define PIO_PC12 (1 << 12) /**< \brief Pin Controlled by PC12 */
-#define PIO_PC13 (1 << 13) /**< \brief Pin Controlled by PC13 */
-#define PIO_PC14 (1 << 14) /**< \brief Pin Controlled by PC14 */
-#define PIO_PC15 (1 << 15) /**< \brief Pin Controlled by PC15 */
-#define PIO_PC16 (1 << 16) /**< \brief Pin Controlled by PC16 */
-#define PIO_PC17 (1 << 17) /**< \brief Pin Controlled by PC17 */
-#define PIO_PC18 (1 << 18) /**< \brief Pin Controlled by PC18 */
-#define PIO_PC19 (1 << 19) /**< \brief Pin Controlled by PC19 */
-#define PIO_PC20 (1 << 20) /**< \brief Pin Controlled by PC20 */
-#define PIO_PC21 (1 << 21) /**< \brief Pin Controlled by PC21 */
-#define PIO_PC22 (1 << 22) /**< \brief Pin Controlled by PC22 */
-#define PIO_PC23 (1 << 23) /**< \brief Pin Controlled by PC23 */
-#define PIO_PC24 (1 << 24) /**< \brief Pin Controlled by PC24 */
-#define PIO_PC25 (1 << 25) /**< \brief Pin Controlled by PC25 */
-#define PIO_PC26 (1 << 26) /**< \brief Pin Controlled by PC26 */
-#define PIO_PC27 (1 << 27) /**< \brief Pin Controlled by PC27 */
-#define PIO_PC28 (1 << 28) /**< \brief Pin Controlled by PC28 */
-#define PIO_PC29 (1 << 29) /**< \brief Pin Controlled by PC29 */
-#define PIO_PC30 (1 << 30) /**< \brief Pin Controlled by PC30 */
-#define PIO_PC31 (1 << 31) /**< \brief Pin Controlled by PC31 */
-/* ========== Pio definition for HSMCI peripheral ========== */
-#define PIO_PA4A_MCCDA (1 << 4) /**< \brief Hsmci signal: MCCDA */
-#define PIO_PA3A_MCCK (1 << 3) /**< \brief Hsmci signal: MCCK */
-#define PIO_PA5A_MCDA0 (1 << 5) /**< \brief Hsmci signal: MCDA0 */
-#define PIO_PA6A_MCDA1 (1 << 6) /**< \brief Hsmci signal: MCDA1 */
-#define PIO_PA7A_MCDA2 (1 << 7) /**< \brief Hsmci signal: MCDA2 */
-#define PIO_PA8A_MCDA3 (1 << 8) /**< \brief Hsmci signal: MCDA3 */
-#define PIO_PC28B_MCDA4 (1 << 28) /**< \brief Hsmci signal: MCDA4 */
-#define PIO_PC29B_MCDA5 (1 << 29) /**< \brief Hsmci signal: MCDA5 */
-#define PIO_PC30B_MCDA6 (1 << 30) /**< \brief Hsmci signal: MCDA6 */
-#define PIO_PC31B_MCDA7 (1 << 31) /**< \brief Hsmci signal: MCDA7 */
-/* ========== Pio definition for SSC peripheral ========== */
-#define PIO_PA27A_RD (1 << 27) /**< \brief Ssc signal: RD */
-#define PIO_PA31A_RF (1 << 31) /**< \brief Ssc signal: RF */
-#define PIO_PA29A_RK (1 << 29) /**< \brief Ssc signal: RK */
-#define PIO_PA26A_TD (1 << 26) /**< \brief Ssc signal: TD */
-#define PIO_PA30A_TF (1 << 30) /**< \brief Ssc signal: TF */
-#define PIO_PA28A_TK (1 << 28) /**< \brief Ssc signal: TK */
-/* ========== Pio definition for SPI peripheral ========== */
-#define PIO_PA13A_MISO (1 << 13) /**< \brief Spi signal: MISO */
-#define PIO_PA14A_MOSI (1 << 14) /**< \brief Spi signal: MOSI */
-#define PIO_PA16A_NPCS0 (1 << 16) /**< \brief Spi signal: NPCS0 */
-#define PIO_PA0B_NPCS1 (1 << 0) /**< \brief Spi signal: NPCS1 */
-#define PIO_PC19B_NPCS1 (1 << 19) /**< \brief Spi signal: NPCS1 */
-#define PIO_PC3B_NPCS1 (1 << 3) /**< \brief Spi signal: NPCS1 */
-#define PIO_PA1B_NPCS2 (1 << 1) /**< \brief Spi signal: NPCS2 */
-#define PIO_PC14B_NPCS2 (1 << 14) /**< \brief Spi signal: NPCS2 */
-#define PIO_PC4B_NPCS2 (1 << 4) /**< \brief Spi signal: NPCS2 */
-#define PIO_PA19B_NPCS3 (1 << 19) /**< \brief Spi signal: NPCS3 */
-#define PIO_PC5B_NPCS3 (1 << 5) /**< \brief Spi signal: NPCS3 */
-#define PIO_PA15A_SPCK (1 << 15) /**< \brief Spi signal: SPCK */
-/* ========== Pio definition for TC0 peripheral ========== */
-#define PIO_PA2A_TCLK0 (1 << 2) /**< \brief Tc0 signal: TCLK0 */
-#define PIO_PB4A_TCLK1 (1 << 4) /**< \brief Tc0 signal: TCLK1 */
-#define PIO_PA26B_TCLK2 (1 << 26) /**< \brief Tc0 signal: TCLK2 */
-#define PIO_PA1A_TIOA0 (1 << 1) /**< \brief Tc0 signal: TIOA0 */
-#define PIO_PB5A_TIOA1 (1 << 5) /**< \brief Tc0 signal: TIOA1 */
-#define PIO_PA30B_TIOA2 (1 << 30) /**< \brief Tc0 signal: TIOA2 */
-#define PIO_PA0A_TIOB0 (1 << 0) /**< \brief Tc0 signal: TIOB0 */
-#define PIO_PB6A_TIOB1 (1 << 6) /**< \brief Tc0 signal: TIOB1 */
-#define PIO_PA31B_TIOB2 (1 << 31) /**< \brief Tc0 signal: TIOB2 */
-/* ========== Pio definition for TWI0 peripheral ========== */
-#define PIO_PA10A_TWCK0 (1 << 10) /**< \brief Twi0 signal: TWCK0 */
-#define PIO_PA9A_TWD0 (1 << 9) /**< \brief Twi0 signal: TWD0 */
-/* ========== Pio definition for TWI1 peripheral ========== */
-#define PIO_PA25A_TWCK1 (1 << 25) /**< \brief Twi1 signal: TWCK1 */
-#define PIO_PA24A_TWD1 (1 << 24) /**< \brief Twi1 signal: TWD1 */
-/* ========== Pio definition for PWM peripheral ========== */
-#define PIO_PA11B_PWMFI0 (1 << 11) /**< \brief Pwm signal: PWMFI0 */
-#define PIO_PA12B_PWMFI1 (1 << 12) /**< \brief Pwm signal: PWMFI1 */
-#define PIO_PA18B_PWMFI2 (1 << 18) /**< \brief Pwm signal: PWMFI2 */
-#define PIO_PA28B_PWMH0 (1 << 28) /**< \brief Pwm signal: PWMH0 */
-#define PIO_PA4B_PWMH0 (1 << 4) /**< \brief Pwm signal: PWMH0 */
-#define PIO_PB0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */
-#define PIO_PB13B_PWMH0 (1 << 13) /**< \brief Pwm signal: PWMH0 */
-#define PIO_PC24B_PWMH0 (1 << 24) /**< \brief Pwm signal: PWMH0 */
-#define PIO_PA29B_PWMH1 (1 << 29) /**< \brief Pwm signal: PWMH1 */
-#define PIO_PA5B_PWMH1 (1 << 5) /**< \brief Pwm signal: PWMH1 */
-#define PIO_PB1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */
-#define PIO_PB14B_PWMH1 (1 << 14) /**< \brief Pwm signal: PWMH1 */
-#define PIO_PC25B_PWMH1 (1 << 25) /**< \brief Pwm signal: PWMH1 */
-#define PIO_PA15B_PWMH2 (1 << 15) /**< \brief Pwm signal: PWMH2 */
-#define PIO_PA6B_PWMH2 (1 << 6) /**< \brief Pwm signal: PWMH2 */
-#define PIO_PB15B_PWMH2 (1 << 15) /**< \brief Pwm signal: PWMH2 */
-#define PIO_PB2A_PWMH2 (1 << 2) /**< \brief Pwm signal: PWMH2 */
-#define PIO_PC26B_PWMH2 (1 << 26) /**< \brief Pwm signal: PWMH2 */
-#define PIO_PA20B_PWMH3 (1 << 20) /**< \brief Pwm signal: PWMH3 */
-#define PIO_PB16B_PWMH3 (1 << 16) /**< \brief Pwm signal: PWMH3 */
-#define PIO_PB3A_PWMH3 (1 << 3) /**< \brief Pwm signal: PWMH3 */
-#define PIO_PC27B_PWMH3 (1 << 27) /**< \brief Pwm signal: PWMH3 */
-#define PIO_PA7B_PWML0 (1 << 7) /**< \brief Pwm signal: PWML0 */
-#define PIO_PB17B_PWML0 (1 << 17) /**< \brief Pwm signal: PWML0 */
-#define PIO_PB25B_PWML0 (1 << 25) /**< \brief Pwm signal: PWML0 */
-#define PIO_PC29A_PWML0 (1 << 29) /**< \brief Pwm signal: PWML0 */
-#define PIO_PC6B_PWML0 (1 << 6) /**< \brief Pwm signal: PWML0 */
-#define PIO_PA8B_PWML1 (1 << 8) /**< \brief Pwm signal: PWML1 */
-#define PIO_PB18B_PWML1 (1 << 18) /**< \brief Pwm signal: PWML1 */
-#define PIO_PB26B_PWML1 (1 << 26) /**< \brief Pwm signal: PWML1 */
-#define PIO_PC30A_PWML1 (1 << 30) /**< \brief Pwm signal: PWML1 */
-#define PIO_PC7B_PWML1 (1 << 7) /**< \brief Pwm signal: PWML1 */
-#define PIO_PA9B_PWML2 (1 << 9) /**< \brief Pwm signal: PWML2 */
-#define PIO_PB19B_PWML2 (1 << 19) /**< \brief Pwm signal: PWML2 */
-#define PIO_PB27B_PWML2 (1 << 27) /**< \brief Pwm signal: PWML2 */
-#define PIO_PC31A_PWML2 (1 << 31) /**< \brief Pwm signal: PWML2 */
-#define PIO_PC8B_PWML2 (1 << 8) /**< \brief Pwm signal: PWML2 */
-#define PIO_PA10B_PWML3 (1 << 10) /**< \brief Pwm signal: PWML3 */
-#define PIO_PB20B_PWML3 (1 << 20) /**< \brief Pwm signal: PWML3 */
-#define PIO_PB28B_PWML3 (1 << 28) /**< \brief Pwm signal: PWML3 */
-#define PIO_PC16B_PWML3 (1 << 16) /**< \brief Pwm signal: PWML3 */
-#define PIO_PC9B_PWML3 (1 << 9) /**< \brief Pwm signal: PWML3 */
-/* ========== Pio definition for USART0 peripheral ========== */
-#define PIO_PB8A_CTS0 (1 << 8) /**< \brief Usart0 signal: CTS0 */
-#define PIO_PB11B_DCD0 (1 << 11) /**< \brief Usart0 signal: DCD0 */
-#define PIO_PB10B_DSR0 (1 << 10) /**< \brief Usart0 signal: DSR0 */
-#define PIO_PB9B_DTR0 (1 << 9) /**< \brief Usart0 signal: DTR0 */
-#define PIO_PB12B_RI0 (1 << 12) /**< \brief Usart0 signal: RI0 */
-#define PIO_PB7A_RTS0 (1 << 7) /**< \brief Usart0 signal: RTS0 */
-#define PIO_PA19A_RXD0 (1 << 19) /**< \brief Usart0 signal: RXD0 */
-#define PIO_PA17A_SCK0 (1 << 17) /**< \brief Usart0 signal: SCK0 */
-#define PIO_PA18A_TXD0 (1 << 18) /**< \brief Usart0 signal: TXD0 */
-/* ========== Pio definition for USART1 peripheral ========== */
-#define PIO_PA23B_CTS1 (1 << 23) /**< \brief Usart1 signal: CTS1 */
-#define PIO_PA22B_RTS1 (1 << 22) /**< \brief Usart1 signal: RTS1 */
-#define PIO_PA21A_RXD1 (1 << 21) /**< \brief Usart1 signal: RXD1 */
-#define PIO_PA24B_SCK1 (1 << 24) /**< \brief Usart1 signal: SCK1 */
-#define PIO_PA20A_TXD1 (1 << 20) /**< \brief Usart1 signal: TXD1 */
-/* ========== Pio definition for USART2 peripheral ========== */
-#define PIO_PB22B_CTS2 (1 << 22) /**< \brief Usart2 signal: CTS2 */
-#define PIO_PB21B_RTS2 (1 << 21) /**< \brief Usart2 signal: RTS2 */
-#define PIO_PA23A_RXD2 (1 << 23) /**< \brief Usart2 signal: RXD2 */
-#define PIO_PA25B_SCK2 (1 << 25) /**< \brief Usart2 signal: SCK2 */
-#define PIO_PA22A_TXD2 (1 << 22) /**< \brief Usart2 signal: TXD2 */
-/* ========== Pio definition for USART3 peripheral ========== */
-#define PIO_PC10B_CTS3 (1 << 10) /**< \brief Usart3 signal: CTS3 */
-#define PIO_PC11B_RTS3 (1 << 11) /**< \brief Usart3 signal: RTS3 */
-#define PIO_PC13B_RXD3 (1 << 13) /**< \brief Usart3 signal: RXD3 */
-#define PIO_PC19A_SCK3 (1 << 19) /**< \brief Usart3 signal: SCK3 */
-#define PIO_PC12B_TXD3 (1 << 12) /**< \brief Usart3 signal: TXD3 */
-/* ========== Pio definition for ADC12B peripheral ========== */
-#define PIO_PA2B_AD12BTRG (1 << 2) /**< \brief Adc12b signal: AD12BTRG */
-/* ========== Pio definition for ADC peripheral ========== */
-#define PIO_PA17B_ADTRG (1 << 17) /**< \brief Adc signal: ADTRG */
-/* ========== Pio definition for PMC peripheral ========== */
-#define PIO_PA21B_PCK0 (1 << 21) /**< \brief Pmc signal: PCK0 */
-#define PIO_PA27B_PCK0 (1 << 27) /**< \brief Pmc signal: PCK0 */
-#define PIO_PA3B_PCK1 (1 << 3) /**< \brief Pmc signal: PCK1 */
-#define PIO_PB24B_PCK1 (1 << 24) /**< \brief Pmc signal: PCK1 */
-#define PIO_PB23B_PCK2 (1 << 23) /**< \brief Pmc signal: PCK2 */
-/* ========== Pio definition for UART peripheral ========== */
-#define PIO_PA11A_URXD (1 << 11) /**< \brief Uart signal: URXD */
-#define PIO_PA12A_UTXD (1 << 12) /**< \brief Uart signal: UTXD */
-/*@}*/
-
-/* ***************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR AT91SAM3U */
-/* ***************************************************************************** */
-
-#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */
-#define AT91C_IFLASH (0x00080000) /**< Internal Flash base address */
-//#define AT91C_IFLASH (0x00100000) /**< Internal Flash base address */
-#define AT91C_IROM (0x00180000) /**< Internal ROM base address */
-//#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */
-//#define AT91C_IRAM (0x20080000) /**< Internal RAM base address */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* AT91SAM3U_H */
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/chip.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/chip.h
deleted file mode 100644
index 03133de4..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/chip.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-
-#ifndef CHIP_H
-#define CHIP_H
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Definitions
-//------------------------------------------------------------------------------
-
-
-//ARM core features
-
-// ARM core definition.
-#define cortexm3
-
-// family definition.
-#define at91sam3u
-
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-
-//IP FEATURES
-
-// EFC GPNVM number
-#define CHIP_EFC_NUM_GPNVMS 3
-
-// Indicates chip has an Enhanced EFC.
-#define CHIP_FLASH_EEFC
-
-// DMA channels number
-#define CHIP_DMA_CHANNEL_NUM 4
-
-// Indicate chip has a nandflash controller.
-#define CHIP_NAND_CTRL
-
-//------------------------------------------------------------------------------
-
-
-//Misc
-
-//------------------------------------------------------------------------------
-
-#endif //#ifndef CHIP_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/flash.icf b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/flash.icf
deleted file mode 100644
index a8911758..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/flash.icf
+++ /dev/null
@@ -1,47 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
-/*-Vector table start*/
-define symbol __ICFEDIT_vector_start__ = 0x00080000; /*Add for CMSIS*/
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM0_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM0_end__ = 0x20007FFF;
-define symbol __ICFEDIT_region_RAM1_start__ = 0x20080000;
-define symbol __ICFEDIT_region_RAM1_end__ = 0x20083FFF;
-define symbol __ICFEDIT_region_ROM0_start__ = 0x00080000;
-define symbol __ICFEDIT_region_ROM0_end__ = 0x0009FFFF;
-define symbol __ICFEDIT_region_ROM1_start__ = 0x00100000;
-define symbol __ICFEDIT_region_ROM1_end__ = 0x0011FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x800;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/*-Specials-*/
-/*define symbol __ICFEDIT_region_RAM_VECT_start__ = __ICFEDIT_region_RAM0_start__;*/ /*Referenced for CMSIS*/
-/*define symbol __ICFEDIT_size_vectors__ = 0x100;*/ /*Referenced for CMSIS*/
-/*-Exports-*/
-/*export symbol __ICFEDIT_region_RAM_VECT_start__;*/
-export symbol __ICFEDIT_vector_start__; /*Add for CMSIS*/
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-/*define region RAM_VECT_region = mem:[from __ICFEDIT_region_RAM_VECT_start__ size __ICFEDIT_size_vectors__];*/ /*Referenced for CMSIS*/
-/*define region RAM0_region = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__];*/ /*Referenced for CMSIS*/
-define region RAM0_region = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__];
-define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];
-/*define region RAM_region = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__] |
- mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];*/ /*Referenced for CMSIS*/
-define region ROM0_region = mem:[from __ICFEDIT_region_ROM0_start__ to __ICFEDIT_region_ROM0_end__];
-define region ROM1_region = mem:[from __ICFEDIT_region_ROM1_start__ to __ICFEDIT_region_ROM1_end__];
-
-/*define block RamVect with alignment = 8, size = __ICFEDIT_size_vectors__ { };*/
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-/*place at start of ROM0_region { readonly section .vectors };*/ /*Referenced for CMSIS*/
-place at address mem:__ICFEDIT_vector_start__ { readonly section .vectors }; /*Add for CMSIS*/
-place in ROM0_region { readonly };
-place in RAM0_region { readwrite, block CSTACK, block HEAP };
-/*place in RAM_VECT_region { block RamVect };*/ /*Referenced for CMSIS*/
\ No newline at end of file
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/flash.lds b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/flash.lds
deleted file mode 100644
index 0355f922..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/flash.lds
+++ /dev/null
@@ -1,87 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/*------------------------------------------------------------------------------
- * Linker script for running in internal FLASH on the AT91SAM3U4
- *----------------------------------------------------------------------------*/
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(ResetException)
-
-/* Vector Definition */
-/* vector is put at very begin adress of SRAM0, the preserved size is 0x100 */
-_vect_start = 0x20000000;
-
-/* Memory Spaces Definitions */
-MEMORY
-{
- sram0 (W!RX) : ORIGIN = 0x20000100, LENGTH = 0x00007F00 /* Sram0, 32K */
- sram1 (W!RX) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
- flash0 (W!RX) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
- flash1 (W!RX) : ORIGIN = 0x00100000, LENGTH = 0x00020000 /* Flash1, 128K */
-}
-
-SECTIONS
-{
- .fixed :
- {
- . = ALIGN(4);
- _sfixed = .;
- KEEP(*(.vectors))
- *(.text*)
- *(.rodata*)
- *(.glue_7)
- *(.glue_7t)
- . = ALIGN(4);
- _efixed = .; /* End of text section */
- } >flash0
-
- .relocate : AT (_efixed)
- {
- . = ALIGN(4);
- _srelocate = .;
- *(.ramfunc);
- *(.data);
- . = ALIGN(4);
- _erelocate = .;
- } >sram0
-
- .bss (NOLOAD) : {
- . = ALIGN(4);
- _szero = .;
- *(.bss)
- . = ALIGN(4);
- _ezero = .;
- } >sram0
-
- /* Stack in the end of SRAM0 */
- _estack = 0x20007FFC;
-}
-end = .;
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/flash.sct b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/flash.sct
deleted file mode 100644
index 3ec4fac7..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/flash.sct
+++ /dev/null
@@ -1,58 +0,0 @@
-; * ----------------------------------------------------------------------------
-; * ATMEL Microcontroller Software Support
-; * ----------------------------------------------------------------------------
-; * Copyright (c) 2008, Atmel Corporation
-; *
-; * All rights reserved.
-; *
-; * Redistribution and use in source and binary forms, with or without
-; * modification, are permitted provided that the following conditions are met:
-; *
-; * - Redistributions of source code must retain the above copyright notice,
-; * this list of conditions and the disclaimer below.
-; *
-; * Atmel's name may not be used to endorse or promote products derived from
-; * this software without specific prior written permission.
-; *
-; * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-; * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-; * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-; * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-; * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-; * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-; * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-; * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-; * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-; * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; * ----------------------------------------------------------------------------
-
-; *------------------------------------------------------------------------------
-; * Linker scatter for running in internal SRAM on the AT91SAM3U4
-; *----------------------------------------------------------------------------*/
-
-; /* vector is put at very begin adress of SRAM0, the preserved size is 0x100 */
-Load_region 0x80000 0x20000
-{
- ; Flash 128K
- Vector_region 0x80000
- {
- board_cstartup_keil.o (vectors, +FIRST)
- }
- Fixed_region +0
- {
- .ANY (+RO)
- }
- ; SRAM0 32K
- Relocate_region 0x20000100 (0x8000-0x100)
- {
- .ANY (+RW +ZI)
- }
- ; Configure Stack and Heap
- ARM_LIB_HEAP 0x20007000 EMPTY 0x400
- {
- }
-
- ARM_LIB_STACK 0x20007FFC EMPTY -0x400
- {
- }
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/psram.icf b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/psram.icf
deleted file mode 100644
index bdd5f4d1..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/psram.icf
+++ /dev/null
@@ -1,43 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
-/*-Vector table start*/
-define symbol __ICFEDIT_vector_start__ = 0x60000000; /*Add for CMSIS*/
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM0_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM0_end__ = 0x20007FFF;
-define symbol __ICFEDIT_region_RAM1_start__ = 0x20080000;
-define symbol __ICFEDIT_region_RAM1_end__ = 0x20083FFF;
-define symbol __ICFEDIT_region_PSRAM_start__ = 0x60000000;
-define symbol __ICFEDIT_region_RSRAM_end__ = 0x600FFFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/*-Specials-*/
-/*define symbol __ICFEDIT_region_RAM_VECT_start__ = __ICFEDIT_region_RAM0_start__;*/ /*Referenced for CMSIS*/
-/*define symbol __ICFEDIT_size_vectors__ = 0x100;*/ /*Referenced for CMSIS*/
-/*-Exports-*/
-export symbol __ICFEDIT_region_RAM_VECT_start__; /*Add for CMSIS*/
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-/*define region RAM_VECT_region = mem:[from __ICFEDIT_region_RAM_VECT_start__ size __ICFEDIT_size_vectors__];*/
-/*define region RAM0_region = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__];*/ /*Referenced for CMSIS*/
-define region RAM0_region = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__];
-define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];
-/*define region RAM_region = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__] |
- mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];*/ /*Referenced for CMSIS*/
-define region PSRAM_region = mem:[from __ICFEDIT_region_PSRAM_start__ to __ICFEDIT_region_RSRAM_end__];
-
-/*define block RamVect with alignment = 8, size = __ICFEDIT_size_vectors__ { };*/ /*Referenced for CMSIS*/
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-/*place at start of PSRAM_region { readonly section .vectors };*/ /*Referenced for CMSIS*/
-place at address mem:__ICFEDIT_vector_start__ { readonly section .vectors }; /*Add for CMSIS*/
-place in PSRAM_region { readonly };
-place in PSRAM_region { readwrite, block CSTACK, block HEAP };
-/*place in RAM_VECT_region { block RamVect };*/ /*Referenced for CMSIS*/
\ No newline at end of file
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/psram.lds b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/psram.lds
deleted file mode 100644
index b5b8c8d5..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/psram.lds
+++ /dev/null
@@ -1,86 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/*------------------------------------------------------------------------------
- * Linker script for running in internal PSRAM on the AT91SAM3U4
- *----------------------------------------------------------------------------*/
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(ResetException)
-
-/* Vector Definition */
-/* vector is put at very begin adress of SRAM0, the preserved size is 0x100 */
-_vect_start = 0x20000000;
-
-/* Memory Spaces Definitions */
-MEMORY
-{
- sram0 (W!RX) : ORIGIN = 0x20000100, LENGTH = 0x00007F00 /* Sram0, 32K */
- sram1 (W!RX) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
- psram (W!RX) : ORIGIN = 0x60000000, LENGTH = 0x00100000 /* PSRAM, 1M */
-}
-
-SECTIONS
-{
- .fixed :
- {
- . = ALIGN(4);
- _sfixed = .;
- KEEP(*(.vectors))
- *(.text*)
- *(.rodata*)
- *(.glue_7)
- *(.glue_7t)
- *(.data)
- . = ALIGN(4);
- _efixed = .; /* End of text section */
- } >psram
-
- .relocate : AT (_efixed)
- {
- . = ALIGN(4);
- _srelocate = .;
- *(.ramfunc);
- . = ALIGN(4);
- _erelocate = .;
- } >sram0
-
- .bss (NOLOAD) : {
- . = ALIGN(4);
- _szero = .;
- *(.bss)
- . = ALIGN(4);
- _ezero = .;
- } >psram
-
- /* Stack in the end of SRAM0 */
- _estack = 0x20007FFC;
-}
-end = .;
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/psram.sct b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/psram.sct
deleted file mode 100644
index 162f57b6..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/psram.sct
+++ /dev/null
@@ -1,59 +0,0 @@
-; * ----------------------------------------------------------------------------
-; * ATMEL Microcontroller Software Support
-; * ----------------------------------------------------------------------------
-; * Copyright (c) 2008, Atmel Corporation
-; *
-; * All rights reserved.
-; *
-; * Redistribution and use in source and binary forms, with or without
-; * modification, are permitted provided that the following conditions are met:
-; *
-; * - Redistributions of source code must retain the above copyright notice,
-; * this list of conditions and the disclaimer below.
-; *
-; * Atmel's name may not be used to endorse or promote products derived from
-; * this software without specific prior written permission.
-; *
-; * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-; * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-; * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-; * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-; * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-; * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-; * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-; * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-; * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-; * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; * ----------------------------------------------------------------------------
-
-; *------------------------------------------------------------------------------
-; * Linker scatter for running in internal SRAM on the AT91SAM3U4
-; *----------------------------------------------------------------------------*/
-
-; /* vector is put at very begin adress of SRAM0, the preserved size is 0x100 */
-Load_region 0x60000000 0x100000
-{
- ; PSRAM 1M
- Vector_region 0x60000000
- {
- board_cstartup_keil.o (vectors, +FIRST)
- }
-
- Fixed_region +0
- {
- .ANY (+RO)
- .ANY (+RW +ZI)
- }
-
- ; SRAM0 32K
- IVector_region 0x20000000 0x100 {}
-
- ; Configure Stack and Heap
- ARM_LIB_HEAP 0x20007000 EMPTY 0x400
- {
- }
-
- ARM_LIB_STACK 0x20007FFC EMPTY -0x400
- {
- }
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/sram.icf b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/sram.icf
deleted file mode 100644
index 242942af..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/sram.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
-/*-Vector table start*/
-define symbol __ICFEDIT_vector_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_RAM0_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM0_end__ = 0x20007FFF;
-define symbol __ICFEDIT_region_RAM1_start__ = 0x20080000;
-define symbol __ICFEDIT_region_RAM1_end__ = 0x20083FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/*-Exports-*/
-export symbol __ICFEDIT_vector_start__;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region RAM0_region = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__];
-define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];
-/*define region RAM_region = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__] |
- mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];*/
-
-/* define block RamVect with alignment = 8, size = __ICFEDIT_size_vectors__ { }; */
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_vector_start__ { readonly section .vectors };
-place in RAM0_region { readonly };
-place in RAM1_region { readwrite, block CSTACK, block HEAP };
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/sram.lds b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/sram.lds
deleted file mode 100644
index 12029473..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/sram.lds
+++ /dev/null
@@ -1,84 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/*------------------------------------------------------------------------------
- * Linker script for running in internal SRAM on the AT91SAM3U4
- *----------------------------------------------------------------------------*/
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(ResetException)
-
-/* Vector Definition */
-_vect_start = 0x20000000;
-
-/* Memory Spaces Definitions */
-MEMORY
-{
- sram0 (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* Sram0, 32K */
- sram1 (W!RX) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
-}
-
-SECTIONS
-{
- .fixed :
- {
- . = ALIGN(4);
- _sfixed = .;
- KEEP(*(.vectors))
- *(.text*)
- *(.ramfunc)
- *(.rodata*)
- *(.glue_7)
- *(.glue_7t)
- . = ALIGN(4);
- _efixed = .; /* End of text section */
- } > sram0
-
- .relocate : AT (_efixed)
- {
- . = ALIGN(4);
- _srelocate = .;
- *(.data)
- . = ALIGN(4);
- _erelocate = .;
- } >sram1
-
- .bss (NOLOAD) : {
- . = ALIGN(4);
- _szero = .;
- *(.bss)
- . = ALIGN(4);
- _ezero = .;
- } >sram1
-
- /* Stack in the end of SRAM1 */
- _estack = 0x20083FFC;
-}
-end = .;
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/sram.sct b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/sram.sct
deleted file mode 100644
index f279cf79..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/sram.sct
+++ /dev/null
@@ -1,60 +0,0 @@
-; * ----------------------------------------------------------------------------
-; * ATMEL Microcontroller Software Support
-; * ----------------------------------------------------------------------------
-; * Copyright (c) 2008, Atmel Corporation
-; *
-; * All rights reserved.
-; *
-; * Redistribution and use in source and binary forms, with or without
-; * modification, are permitted provided that the following conditions are met:
-; *
-; * - Redistributions of source code must retain the above copyright notice,
-; * this list of conditions and the disclaimer below.
-; *
-; * Atmel's name may not be used to endorse or promote products derived from
-; * this software without specific prior written permission.
-; *
-; * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-; * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-; * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-; * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-; * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-; * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-; * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-; * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-; * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-; * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; * ----------------------------------------------------------------------------
-
-; *------------------------------------------------------------------------------
-; * Linker scatter for running in internal SRAM on the AT91SAM3U4
-; *----------------------------------------------------------------------------*/
-
-Load_region 0x20000000 0x8000
-{
- ; RAM0 32K
- Vector_region 0x20000000 0x100
- {
- board_cstartup_keil.o (vectors, +FIRST)
- }
-
- Fixed_region +0
- {
- .ANY (+RO)
- }
-
- ; RAM1 16K
- Relocate_region 0x20080000 0x4000
- {
- .ANY (+RW +ZI)
- }
-
- ; Configure Stack and Heap
- ARM_LIB_HEAP 0x20083000 EMPTY 0x400
- {
- }
-
- ARM_LIB_STACK 0x20083FFC EMPTY -0x400
- {
- }
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/sram_samba.lds b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/sram_samba.lds
deleted file mode 100644
index 226b4595..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/sram_samba.lds
+++ /dev/null
@@ -1,92 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/*------------------------------------------------------------------------------
- * Linker script for running in internal SRAM on the AT91SAM3U4
- *----------------------------------------------------------------------------*/
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(entry)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
- romcodesram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x01000
- sram0 (W!RX) : ORIGIN = 0x20001000, LENGTH = 0x00007000 /* Sram0, 32K */
-}
-
-/* Entry point */
-/*ENTRY (ResetException)*/
-
-SECTIONS
-{
- /* startup code in the .isr_vector */
- .text :
- {
- . = ALIGN(4);
- _stext = .;
- KEEP(*(.isr_vector .isr_vector.*))
- *(.mailbox)
- *(.text .text.*)
- *(.rodata .rodata.*)
- *(.glue_7)
- *(.glue_7t)
- *(.gcc_except_table)
- *(.rodata .rodata*)
- *(.gnu.linkonce.r.*)
- . = ALIGN(4);
- _etext = .;
- } > sram0
-
- /* data */
- .data :
- {
- . = ALIGN(4);
- _sidata = .;
- _sdata = .;
-
- *(.data)
- *(.data.*)
- . = ALIGN(4);
- _edata = .;
- } > sram0
-
- .bss (NOLOAD) : {
- _szero = .;
- *(.bss)
- . = ALIGN(4);
- _ezero = .;
- } >sram0
-
- /* Stack in SRAM0 */
- _sstack = 0x20008000;
-}
-end = .;
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board.h
deleted file mode 100644
index 766ae474..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board.h
+++ /dev/null
@@ -1,665 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-/**
- * \page sam3s_ek_board_desc "SAM3S-EK - Board Description"
- *
- * \section
- * A file is dedicated to descibe the AT91SAM3S-EK board.
- *
- * \section Contents
- * - The code for booting the board is provided by board_cstartup.S and
- * board_lowlevel.c.
- * - For using board PIOs, board characteristics (clock, etc.) and external
- * components, see board.h.
- * - For manipulating memories (remapping, SDRAM, etc.), see board_memories.h.
- *
- * To get more software details and the full list of parameters related to the
- * SAM3S-EK board configuration, please have a look at the source file: \n
- * \ref board.h\n
- *
- * This file can be used as a template and modified to fit a custom board, with
- * specific PIOs usage or memory connections.
- **/
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-/// \file board.h
-///
-/// \par Purpose
-///
-/// Definition of AT91SAM3S-EK characteristics, AT91SAM3S-dependant PIOs and
-/// external components interfacing.
-///
-/// \par Usage
-/// -# For operating frequency information, see "SAM3S-EK - Operating frequencies".
-/// -# For using portable PIO definitions, see "SAM3S-EK - PIO definitions".
-/// -# Several USB definitions are included here (see "SAM3S-EK - USB device").
-//------------------------------------------------------------------------------
-
-#ifndef BOARD_H
-#define BOARD_H
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-
-/* These headers were introduced in C99 by working group ISO/IEC JTC1/SC22/WG14. */
-#include
-#include
-
-#if defined(at91sam3s4)
- #include "at91sam3s4/chip.h"
- #include "at91sam3s4/AT91SAM3S4.h"
-#else
- #error Board does not support the specified chip.
-#endif
-
-//------------------------------------------------------------------------------
-// Definitions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// \par
-/// This page lists several definition related to the board description.
-///
-/// Definitions
-/// - BOARD_NAME
-
-/// Name of the board.
-#define BOARD_NAME "AT91SAM3S-EK"
-/// Board definition.
-#define at91sam3sek
-/// Family definition (already defined).
-#define at91sam3s
-/// Core definition
-#define cortexm3
-
-//#define BOARD_REV_A
-#define BOARD_REV_B
-
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// \par sam3s_ek_opfreq "SAM3S-EK - Operating frequencies"
-/// This page lists several definition related to the board operating frequency
-/// (when using the initialization done by board_lowlevel.c).
-///
-/// !Definitions
-/// - BOARD_MAINOSC
-/// - BOARD_MCK
-
-/// Frequency of the board main oscillator.
-#define BOARD_MAINOSC 12000000
-
-/// Master clock frequency (when using board_lowlevel.c).
-//#define BOARD_MCK 48000000
-#define BOARD_MCK 64000000
-
-//------------------------------------------------------------------------------
-// ADC
-//------------------------------------------------------------------------------
-
-/// Startup time max, return from Idle mode (in µs)
-#define ADC_STARTUP_TIME_MAX 15
-/// Track and hold Acquisition Time min (in ns)
-#define ADC_TRACK_HOLD_TIME_MIN 1200
-
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// USB attributes configuration descriptor (bus or self powered, remote wakeup)
-//#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_RWAKEUP
-#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// \par sam3s_ek_piodef "SAM3S-EK - PIO definitions"
-/// This pages lists all the pio definitions contained in board.h. The constants
-/// are named using the following convention: PIN_* for a constant which defines
-/// a single Pin instance (but may include several PIOs sharing the same
-/// controller), and PINS_* for a list of Pin instances.
-///
-/// !ADC
-/// - PIN_ADC0_AD0
-/// - PIN_ADC0_AD1
-/// - PIN_ADC0_AD2
-/// - PIN_ADC0_AD3
-/// - PIN_ADC0_AD4
-/// - PIN_ADC0_AD5
-/// - PIN_ADC0_AD6
-/// - PIN_ADC0_AD7
-/// - PINS_ADC0
-///
-/// !UART
-/// - PINS_UART
-///
-/// !EBI
-/// - PIN_EBI_DATA_BUS
-/// - PIN_EBI_NCS0
-/// - PIN_EBI_NRD
-/// - PIN_EBI_NWE
-/// - PIN_EBI_ADDR_BUS
-/// - PIN_EBI_PSRAM_NBS
-/// - PIN_EBI_A1
-/// - PIN_EBI_LCD_RS
-///
-/// !LEDs
-/// - PIN_LED_0
-/// - PIN_LED_1
-/// - PIN_LED_2
-/// - PINS_LEDS
-///
-/// !MCI
-/// - PINS_MCI
-///
-/// !Push buttons
-/// - PIN_PUSHBUTTON_1
-/// - PIN_PUSHBUTTON_2
-/// - PINS_PUSHBUTTONS
-/// - PUSHBUTTON_BP1
-/// - PUSHBUTTON_BP2
-///
-/// !PWMC
-/// - PIN_PWMC_PWMH0
-/// - PIN_PWMC_PWML0
-/// - PIN_PWMC_PWMH1
-/// - PIN_PWMC_PWML1
-/// - PIN_PWMC_PWMH2
-/// - PIN_PWMC_PWML2
-/// - PIN_PWMC_PWMH3
-/// - PIN_PWMC_PWML3
-/// - PIN_PWM_LED0
-/// - PIN_PWM_LED1
-/// - PIN_PWM_LED2
-/// - CHANNEL_PWM_LED0
-/// - CHANNEL_PWM_LED1
-/// - CHANNEL_PWM_LED2
-///
-/// !SPI
-/// - PIN_SPI_MISO
-/// - PIN_SPI_MOSI
-/// - PIN_SPI_SPCK
-/// - PINS_SPI
-/// - PIN_SPI_NPCS0_PA11
-///
-/// ! SSC
-/// - PIN_SSC_TD
-/// - PIN_SSC_TK
-/// - PIN_SSC_TF
-/// - PINS_SSC_CODEC
-///
-/// ! PCK0
-/// - PIN_PCK0
-///
-/// !TWI
-/// - PIN_TWI_TWD0
-/// - PIN_TWI_TWCK0
-/// - PINS_TWI
-///
-/// !USART0
-/// - PIN_USART0_RXD
-/// - PIN_USART0_TXD
-/// - PIN_USART0_CTS
-/// - PIN_USART0_RTS
-/// - PIN_USART0_SCK
-///
-/// !USB
-/// - PIN_USB_PULLUP
-///
-
-/// ADC_AD0 pin definition.
-#define PIN_ADC0_AD0 {1 << 21, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT}
-/// ADC_AD1 pin definition.
-#define PIN_ADC0_AD1 {1 << 30, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT}
-/// ADC_AD2 pin definition.
-#define PIN_ADC0_AD2 {1 << 3, PIOB, ID_PIOB, PIO_INPUT, PIO_DEFAULT}
-/// ADC_AD3 pin definition.
-#define PIN_ADC0_AD3 {1 << 4, PIOB, ID_PIOB, PIO_INPUT, PIO_DEFAULT}
-/// ADC_AD4 pin definition.
-#define PIN_ADC0_AD4 {1 << 15, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT}
-/// ADC_AD5 pin definition.
-#define PIN_ADC0_AD5 {1 << 16, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT}
-/// ADC_AD6 pin definition.
-#define PIN_ADC0_AD6 {1 << 17, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT}
-/// ADC_AD7 pin definition.
-#define PIN_ADC0_AD7 {1 << 18, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT}
-
-/// Pins ADC
-#define PINS_ADC PIN_ADC0_AD0, PIN_ADC0_AD1, PIN_ADC0_AD2, PIN_ADC0_AD3, PIN_ADC0_AD4, PIN_ADC0_AD5, PIN_ADC0_AD6, PIN_ADC0_AD7
-
-/** UART pins (UTXD0 and URXD0) definitions, PA9,10. */
-#define PINS_UART {0x00000600, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
-
-/// EBI
-#define PIN_EBI_DATA_BUS {0xFF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}
-#define PIN_EBI_NRD {1 << 11, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}
-#define PIN_EBI_NWE {1 << 8, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}
-
-#define PIN_EBI_NCS0 {1 << 20, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_PULLUP}
-#define PIN_EBI_PSRAM_ADDR_BUS {0x3f00fff, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}
-#define PIN_EBI_PSRAM_NBS {1 << 7, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_PULLUP}, \
- {1 << 15, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}
-#define PIN_EBI_A1 {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}
-
-#define PIN_EBI_NCS1 {1 << 15, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} /* LCD CS pin */
-#define PIN_EBI_LCD_RS {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} /* LCD RS pin */
-
-#ifdef BOARD_REV_A
-/** LED #0 pin definition. */
-#define PIN_LED_0 {1 << 20, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT}
-/** LED #1 pin definition. */
-#define PIN_LED_1 {1 << 21, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT}
-/** LED #2 pin definition. */
-#define PIN_LED_2 {1 << 22, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT}
-#endif
-#ifdef BOARD_REV_B
-/** LED #0 pin definition. */
-#define PIN_LED_0 {1 << 19, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}
-/** LED #1 pin definition. */
-#define PIN_LED_1 {1 << 20, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}
-/** LED #2 pin definition. */
-#define PIN_LED_2 {1 << 20, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT}
-#endif
-
-/** List of all LEDs definitions. */
-#define PINS_LEDS PIN_LED_0, PIN_LED_1, PIN_LED_2
-
-/// MCI pins definition.
-#define PINS_MCI {0x1f8, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_PULLUP}, \
- {1 << 3, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
-
-/// MCI pin Card Detect
-#define PIN_MCI_CD \
- {AT91C_PIO_PA25, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP}
-
-/** Push button #0 definition. Attributes = pull-up + debounce + interrupt on rising edge. */
-#define PIN_PUSHBUTTON_1 {1 << 3, PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE}
-/** Push button #1 definition. Attributes = pull-up + debounce + interrupt on falling edge. */
-#define PIN_PUSHBUTTON_2 {1 << 12, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE}
-/** List of all push button definitions. */
-#define PINS_PUSHBUTTONS PIN_PUSHBUTTON_1, PIN_PUSHBUTTON_2
-
-/** Push button #1 index. */
-#define PUSHBUTTON_BP1 0
-/** Push button #2 index. */
-#define PUSHBUTTON_BP2 1
-
-/// Simulated joystick LEFT index.
-#define JOYSTICK_LEFT 0
-/// Simulated joystick RIGHT index.
-#define JOYSTICK_RIGHT 1
-
-/** PWMC PWM0 pin definition. */
-#define PIN_PWMC_PWMH0 {1 << 18, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}
-#define PIN_PWMC_PWML0 {1 << 19, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}
-/** PWMC PWM1 pin definition. */
-#define PIN_PWMC_PWMH1 {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}
-#define PIN_PWMC_PWML1 {1 << 20, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}
-/** PWMC PWM2 pin definition. */
-#define PIN_PWMC_PWMH2 {1 << 20, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}
-#define PIN_PWMC_PWML2 {1 << 16, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT}
-/** PWMC PWM3 pin definition. */
-#define PIN_PWMC_PWMH3 {1 << 21, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}
-#define PIN_PWMC_PWML3 {1 << 15, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT}
-/** PWM pin definition for LED0 */
-#define PIN_PWM_LED0 PIN_PWMC_PWMH0, PIN_PWMC_PWML0
-/** PWM pin definition for LED1 */
-#define PIN_PWM_LED1 PIN_PWMC_PWMH2, PIN_PWMC_PWML2
-/** PWM pin definition for LED2 */
-#define PIN_PWM_LED2 PIN_PWMC_PWMH3, PIN_PWMC_PWML3
-/** PWM channel for LED0 */
-#define CHANNEL_PWM_LED0 0
-/** PWM channel for LED1 */
-#define CHANNEL_PWM_LED1 2
-/** PWM channel for LED2 */
-#define CHANNEL_PWM_LED2 3
-
-/** SPI MISO pin definition. */
-#define PIN_SPI_MISO {1 << 12, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
-/** SPI MOSI pin definition. */
-#define PIN_SPI_MOSI {1 << 13, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
-/** SPI SPCK pin definition. */
-#define PIN_SPI_SPCK {1 << 14, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
-/** SPI chip select pin definition. */
-#define PIN_SPI_NPCS0_PA11 {1 << 11, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
-/** List of SPI pin definitions (MISO, MOSI & SPCK). */
-#define PINS_SPI PIN_SPI_MISO, PIN_SPI_MOSI, PIN_SPI_SPCK
-
-/// SSC pins definition.
-#define PIN_SSC_TD {0x1 << 26, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
-#define PIN_SSC_TK {0x1 << 28, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
-#define PIN_SSC_TF {0x1 << 30, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
-#define PINS_SSC_CODEC PIN_SSC_TD, PIN_SSC_TK, PIN_SSC_TF
-
-/// PCK0
-#define PIN_PCK0 {0x1 << 21, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}
-
-/// TWI pins definition.
-#define TWI_V3XX
-#define PIN_TWI_TWD0 {0x1 << 9, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
-#define PIN_TWI_TWCK0 {0x1 << 10, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
-#define PINS_TWI0 PIN_TWI_TWD0, PIN_TWI_TWCK0
-#define PIN_TWI_TWD1 {0x1 << 24, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
-#define PIN_TWI_TWCK1 {0x1 << 25, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
-#define PINS_TWI1 PIN_TWI_TWD1, PIN_TWI_TWCK1
-
-/// USART0
-#define PIN_USART0_RXD {0x1 << 19, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
-#define PIN_USART0_TXD {0x1 << 18, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
-#define PIN_USART0_CTS {0x1 << 8, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
-#define PIN_USART0_RTS {0x1 << 7, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
-#define PIN_USART0_SCK {0x1 << 17, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
-
-/// USART1
-#define PIN_USART1_RXD {0x1 << 21, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
-#define PIN_USART1_TXD {0x1 << 22, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
-#define PIN_USART1_CTS {0x1 << 25, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
-#define PIN_USART1_RTS {0x1 << 24, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
-#define PIN_USART1_EN {0x1 << 23, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}
-
-
-
-/// USB VBus monitoring pin definition.
-#ifdef BOARD_REV_A
-#define PIN_USB_VBUS {1 << 23, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT}
-#endif
-#ifdef BOARD_REV_B
-#define PIN_USB_VBUS {1 << 21, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT}
-#endif
-
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// \par sam3s_ek_extcomp "SAM3S-EK - External components"
-/// This page lists the definitions related to external on-board components
-/// located in the board.h file for the AT91SAM3S-EK.
-///
-/// !AT45 Dataflash Card
-/// - BOARD_AT45_A_SPI_BASE
-/// - BOARD_AT45_A_SPI_ID
-/// - BOARD_AT45_A_SPI_PINS
-/// - BOARD_AT45_A_SPI
-/// - BOARD_AT45_A_NPCS
-/// - BOARD_AT45_A_NPCS_PIN
-///
-/// !AT45 Dataflash (serial onboard DataFlash)
-/// - BOARD_AT45_B_SPI_BASE
-/// - BOARD_AT45_B_SPI_ID
-/// - BOARD_AT45_B_SPI_PINS
-/// - BOARD_AT45_B_SPI
-/// - BOARD_AT45_B_NPCS
-/// - BOARD_AT45_B_NPCS_PIN
-///
-/// !AT26 Serial Flash
-/// - BOARD_AT26_A_SPI_BASE
-/// - BOARD_AT26_A_SPI_ID
-/// - BOARD_AT26_A_SPI_PINS
-/// - BOARD_AT26_A_SPI
-/// - BOARD_AT26_A_NPCS
-/// - BOARD_AT26_A_NPCS_PIN
-///
-/// !SD Card
-/// - MCI2_INTERFACE
-/// - BOARD_SD_MCI_BASE
-/// - BOARD_SD_MCI_ID
-/// - BOARD_SD_PINS
-/// - BOARD_SD_SLOT
-///
-/// !PSRAM
-/// - BOARD_PSRAM_PINS
-///
-/// !LCD
-/// - BOARD_LCD_ILI9325
-/// - BOARD_LCD_PINS
-/// - BOARD_BACKLIGHT_PIN
-/// - BOARD_LCD_BASE
-/// - BOARD_LCD_RS
-/// - BOARD_LCD_WIDTH
-/// - BOARD_LCD_HEIGHT
-///
-/// !TouchScreen
-/// - BOARD_TSC_ADS7843
-/// - PIN_TCS_IRQ
-/// - PIN_TCS_BUSY
-/// - BOARD_TSC_SPI_BASE
-/// - BOARD_TSC_SPI_ID
-/// - BOARD_TSC_SPI_PINS
-/// - BOARD_TSC_NPCS
-/// - BOARD_TSC_NPCS_PIN
-///
-/// Base address of SPI peripheral connected to the dataflash.
-//#define BOARD_AT45_A_SPI_BASE SPI0
-///// Identifier of SPI peripheral connected to the dataflash.
-//#define BOARD_AT45_A_SPI_ID ID_SPI0
-///// Pins of the SPI peripheral connected to the dataflash.
-//#define BOARD_AT45_A_SPI_PINS PINS_SPI0
-///// Dataflahs SPI number.
-//#define BOARD_AT45_A_SPI 0
-///// Chip select connected to the dataflash.
-//#define BOARD_AT45_A_NPCS 3
-///// Chip select pin connected to the dataflash.
-//#define BOARD_AT45_A_NPCS_PIN PIN_SPI0_NPCS3
-
-/// Base address of SPI peripheral connected to the dataflash.
-//#define BOARD_AT45_B_SPI_BASE SPI1
-///// Identifier of SPI peripheral connected to the dataflash.
-//#define BOARD_AT45_B_SPI_ID ID_SPI1
-///// Pins of the SPI peripheral connected to the dataflash.
-//#define BOARD_AT45_B_SPI_PINS PINS_SPI1
-///// Dataflahs SPI number.
-//#define BOARD_AT45_B_SPI 1
-///// Chip select connected to the dataflash.
-//#define BOARD_AT45_B_NPCS 3
-///// Chip select pin connected to the dataflash.
-//#define BOARD_AT45_B_NPCS_PIN PIN_SPI1_NPCS3
-
-/// Base address of SPI peripheral connected to the serialflash.
-//#define BOARD_AT26_A_SPI_BASE SPI0
-///// Identifier of SPI peripheral connected to the serialflash.
-//#define BOARD_AT26_A_SPI_ID ID_SPI0
-///// Pins of the SPI peripheral connected to the serialflash.
-//#define BOARD_AT26_A_SPI_PINS PINS_SPI0
-///// Serialflash SPI number.
-//#define BOARD_AT26_A_SPI 0
-///// Chip select connected to the serialflash.
-//#define BOARD_AT26_A_NPCS 3
-///// Chip select pin connected to the serialflash.
-//#define BOARD_AT26_A_NPCS_PIN PIN_SPI0_NPCS3
-
-/// ISO7816
-/// - PIN_SMARTCARD_CONNECT
-/// - PIN_ISO7816_RSTMC
-/// - PINS_ISO7816
-
-/// Smartcard detection pin
-//#define PIN_SMARTCARD_CONNECT {1 << 5, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT}
-/// PIN used for reset the smartcard
-//#define PIN_ISO7816_RSTMC {1 << 7, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}
-/// Pins used for connect the smartcard
-//#define PINS_ISO7816 PIN_USART0_TXD, PIN_USART0_SCK, PIN_ISO7816_RSTMC
-
-/// Dma channel number
-#define BOARD_MCI_DMA_CHANNEL 0
-/// MCI0 DMA hardware handshaking ID
-#define DMA_HW_SRC_REQ_ID_MCI0 AT91C_HDMA_SRC_PER_0
-#define DMA_HW_DEST_REQ_ID_MCI0 AT91C_HDMA_DST_PER_0
-/// MCI1 DMA hardware handshaking ID
-#define DMA_HW_SRC_REQ_ID_MCI1 AT91C_HDMA_SRC_PER_13
-#define DMA_HW_DEST_REQ_ID_MCI1 AT91C_HDMA_DST_PER_13
-/// SD DMA hardware handshaking ID
-#define BOARD_SD_DMA_HW_SRC_REQ_ID DMA_HW_SRC_REQ_ID_MCI0
-#define BOARD_SD_DMA_HW_DEST_REQ_ID DMA_HW_DEST_REQ_ID_MCI0
-
-
-/// HS MCI interface
-#define MCI2_INTERFACE
-/// Base address of the MCI peripheral connected to the SD card.
-#define BOARD_SD_MCI_BASE MCI0//MCI
-///// Peripheral identifier of the MCI connected to the SD card.
-#define BOARD_SD_MCI_ID ID_MCI0 //ID_MCI
-///// MCI pins that shall be configured to access the SD card.
-#define BOARD_SD_PINS PINS_MCI
-///// MCI slot to which the SD card is connected to.
-#define BOARD_SD_SLOT MCI_SD_SLOTA
-///// MCI Card Detect pin.
-#define BOARD_SD_PIN_CD PIN_MCI_CD
-
-//#define BOARD_PSRAM_PINS PIN_EBI_DATA_BUS, PIN_EBI_NCS0, PIN_EBI_NRD, PIN_EBI_NWE, \
- PIN_EBI_PSRAM_ADDR_BUS, PIN_EBI_PSRAM_NBS, PIN_EBI_A1
-
-/** Indicates board has an ILI9325 external component to manage LCD. */
-#define BOARD_LCD_ILI9325
-
-/** LCD pins definition. */
-#define BOARD_LCD_PINS PIN_EBI_DATA_BUS, PIN_EBI_NRD, PIN_EBI_NWE, \
- PIN_EBI_NCS1, PIN_EBI_LCD_RS
-/** Backlight pin definition. */
-#define BOARD_BACKLIGHT_PIN {1 << 13, PIOC, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT}
-/** Define ILI9325 base address. */
-#define BOARD_LCD_BASE 0x61000000
-/** Define ILI9325 register select signal. */
-#define BOARD_LCD_RS (1 << 1)
-/** Display width in pixels. */
-#define BOARD_LCD_WIDTH 240
-/** Display height in pixels. */
-#define BOARD_LCD_HEIGHT 320
-
-/** Indicates board has an ADS7843 external component to manage Touch Screen */
-#define BOARD_TSC_ADS7843
-
-#ifdef BOARD_REV_A
-/** Touchscreen controller IRQ pin definition. */
-#define PIN_TCS_IRQ {PIO_PA4, PIOA, ID_PIOA, PIO_INPUT, PIO_DEBOUNCE | PIO_IT_AIME | PIO_IT_EDGE}
-#define PIN_TCS_IRQ_WUP_ID (1 << 3)
-/** Touchscreen controller Busy pin definition. */
-#define PIN_TCS_BUSY {PIO_PA5, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP}
-#endif
-#ifdef BOARD_REV_B
-/** Touchscreen controller IRQ pin definition. */
-#define PIN_TCS_IRQ {PIO_PA16, PIOA, ID_PIOA, PIO_INPUT, PIO_DEBOUNCE | PIO_IT_AIME | PIO_IT_EDGE}
-#define PIN_TCS_IRQ_WUP_ID (1 << 15)
-/** Touchscreen controller Busy pin definition. */
-#define PIN_TCS_BUSY {PIO_PA17, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP}
-#endif
-
-/** Base address of SPI peripheral connected to the touchscreen controller. */
-#define BOARD_TSC_SPI_BASE SPI
-/** Identifier of SPI peripheral connected to the touchscreen controller. */
-#define BOARD_TSC_SPI_ID ID_SPI
-/** Pins of the SPI peripheral connected to the touchscreen controller. */
-#define BOARD_TSC_SPI_PINS PINS_SPI
-/** Chip select connected to the touchscreen controller. */
-#define BOARD_TSC_NPCS 0
-/** Chip select pin connected to the touchscreen controller. */
-#define BOARD_TSC_NPCS_PIN PIN_SPI_NPCS0_PA11
-
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// \par sam3s_ek_mem "SAM3S-EK - Memories"
-/// This page lists definitions related to internal & external on-board memories.
-///
-/// !Embedded Flash
-/// - BOARD_FLASH_EFC
-
-/// Internal SRAM address
-#define AT91C_ISRAM AT91C_IRAM
-#define AT91C_ISRAM_SIZE 0x00008000
-
-#define AT91C_IFLASH_SIZE (0x40000)
-#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH 0 Page Size: 256 bytes
-#define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH 0 Number of Pages: 512
-#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH 0 Lock Region Size: 16 Kbytes
-#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH 0 Number of Lock Bits: 16
-
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-/// \section sam3s_ek_extcomp "SAM3S-EK - External components"
-/// This page lists the definitions related to external on-board components
-/// located in the board.h file for the SAM3S-EK.
-///
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// \par sam3s_ek_chipdef "SAM3S-EK - Individual chip definition"
-/// This page lists the definitions related to different chip's definition
-/// located in the board.h file for the SAM3S-EK.
-
-/// DBGU
-#define BOARD_DBGU_ID ID_DBGU
-
-/// Rtc
-#define BOARD_RTC_ID ID_RTC
-
-/// Twi eeprom
-#define BOARD_ID_TWI_EEPROM ID_TWI1
-#define BOARD_BASE_TWI_EEPROM TWI1
-#define BOARD_PINS_TWI_EEPROM PINS_TWI1
-
-/// USART
-#define BOARD_PIN_USART_RXD PIN_USART1_RXD
-#define BOARD_PIN_USART_TXD PIN_USART1_TXD
-#define BOARD_PIN_USART_CTS PIN_USART1_CTS
-#define BOARD_PIN_USART_RTS PIN_USART1_RTS
-#define BOARD_PIN_USART_EN PIN_USART1_EN
-#define BOARD_USART_BASE USART1
-#define BOARD_ID_USART ID_USART1
-
-//------------------------------------------------------------------------------
-
-
-#define PIN_EBI_NANDOE {1 << 9, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}
-#define PIN_EBI_NANDWE {1 << 10, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}
-#define PIN_EBI_NANDCLE {1 << 17, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}
-#define PIN_EBI_NANDALE {1 << 16, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}
-#define PIN_EBI_NANDIO {0x000000FF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}
-
-/// Nandflash chip enable pin definition.
-#define BOARD_NF_CE_PIN {1 << 14, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT}
-/// Nandflash ready/busy pin definition.
-#define BOARD_NF_RB_PIN {1 << 18, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP}
-
-/// Nandflash controller peripheral pins definition.
-#define PINS_NANDFLASH PIN_EBI_NANDIO, BOARD_NF_CE_PIN, BOARD_NF_RB_PIN, PIN_EBI_NANDOE, \
- PIN_EBI_NANDWE, PIN_EBI_NANDCLE, PIN_EBI_NANDALE
-
-/// Address for transferring command bytes to the nandflash.
-#define BOARD_NF_COMMAND_ADDR 0x60400000
-/// Address for transferring address bytes to the nandflash.
-#define BOARD_NF_ADDRESS_ADDR 0x60200000
-/// Address for transferring data bytes to the nandflash.
-#define BOARD_NF_DATA_ADDR 0x60000000
-
-#endif //#ifndef BOARD_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_cstartup_gnu.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_cstartup_gnu.c
deleted file mode 100644
index 632cdaca..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_cstartup_gnu.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include "board.h"
-#include "exceptions.h"
-#include "board_lowlevel.h"
-
-#include
-
-/*----------------------------------------------------------------------------
- * Exported variables
- *----------------------------------------------------------------------------*/
-
-/* Stack top */
-extern uint32_t _estack;
-
-/* Initialize segments */
-extern uint32_t _sfixed;
-extern uint32_t _sfixed;
-extern uint32_t _efixed;
-extern uint32_t _srelocate;
-extern uint32_t _erelocate;
-extern uint32_t _szero;
-extern uint32_t _ezero;
-
-/*----------------------------------------------------------------------------
- * Definitions
- *----------------------------------------------------------------------------*/
-
-/* The mask of VTOR register */
-#define SCB_VTOR_MASK 0x3FFFFFF8
-
-/*----------------------------------------------------------------------------
- * ProtoTypes
- *----------------------------------------------------------------------------*/
-
-extern int main(void);
-void ResetException(void);
-
-/*----------------------------------------------------------------------------
- * Local variables
- *----------------------------------------------------------------------------*/
-
-/* Exception Table */
-__attribute__((section(".vectors")))
-IntFunc exception_table[] = {
-
- /* Configure Initial Stack Pointer, using linker-generated symbols */
- (IntFunc)&_estack,
- ResetException,
-
- NMI_Handler,
- HardFault_Handler,
- MemManage_Handler,
- BusFault_Handler,
- UsageFault_Handler,
- 0, 0, 0, 0, /* Reserved */
- SVC_Handler,
- DebugMon_Handler,
- 0, /* Reserved */
- PendSV_Handler,
- SysTick_Handler,
-
- /* Configurable interrupts */
- SUPC_IrqHandler, /* 0 Supply Controller */
- RSTC_IrqHandler, /* 1 Reset Controller */
- RTC_IrqHandler, /* 2 Real Time Clock */
- RTT_IrqHandler, /* 3 Real Time Timer */
- WDT_IrqHandler, /* 4 Watchdog Timer */
- PMC_IrqHandler, /* 5 PMC */
- EEFC_IrqHandler, /* 6 EEFC */
- IrqHandlerNotUsed, /* 7 Reserved */
- UART0_IrqHandler, /* 8 UART0 */
- UART1_IrqHandler, /* 9 UART1 */
- SMC_IrqHandler, /* 10 SMC */
- PIOA_IrqHandler, /* 11 Parallel IO Controller A */
- PIOB_IrqHandler, /* 12 Parallel IO Controller B */
- PIOC_IrqHandler, /* 13 Parallel IO Controller C */
- USART0_IrqHandler, /* 14 USART 0 */
- USART1_IrqHandler, /* 15 USART 1 */
- IrqHandlerNotUsed, /* 16 Reserved */
- IrqHandlerNotUsed, /* 17 Reserved */
- MCI_IrqHandler, /* 18 MCI */
- TWI0_IrqHandler, /* 19 TWI 0 */
- TWI1_IrqHandler, /* 20 TWI 1 */
- SPI_IrqHandler, /* 21 SPI */
- SSC_IrqHandler, /* 22 SSC */
- TC0_IrqHandler, /* 23 Timer Counter 0 */
- TC1_IrqHandler, /* 24 Timer Counter 1 */
- TC2_IrqHandler, /* 25 Timer Counter 2 */
- TC3_IrqHandler, /* 26 Timer Counter 3 */
- TC4_IrqHandler, /* 27 Timer Counter 4 */
- TC5_IrqHandler, /* 28 Timer Counter 5 */
- ADC_IrqHandler, /* 29 ADC controller */
- DAC_IrqHandler, /* 30 DAC controller */
- PWM_IrqHandler, /* 31 PWM */
- CRCCU_IrqHandler, /* 32 CRC Calculation Unit */
- ACC_IrqHandler, /* 33 Analog Comparator */
- USBD_IrqHandler, /* 34 USB Device Port */
- IrqHandlerNotUsed /* 35 not used */
-};
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief This is the code that gets called on processor reset.
- * To initialize the device, and call the main() routine.
- */
-void ResetException(void)
-{
- uint32_t *pSrc, *pDest;
-
- LowLevelInit();
-
- /* Initialize the relocate segment */
- pSrc = &_efixed;
- pDest = &_srelocate;
- if (pSrc != pDest) {
- for(; pDest < &_erelocate;) {
-
- *pDest++ = *pSrc++;
- }
- }
-
- /* Clear the zero segment */
- for(pDest = &_szero; pDest < &_ezero;) {
-
- *pDest++ = 0;
- }
-
- /* Set the vector table base address */
- pSrc = (uint32_t *)&_sfixed;
- SCB->VTOR = ((uint32_t)(pSrc)) & 0x2FFFFFF8;
-
- /* Branch to main function */
- main();
-
- /* Infinite loop */
- while(1);
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_cstartup_iar.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_cstartup_iar.c
deleted file mode 100644
index fbfcca21..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_cstartup_iar.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/*------------------------------------------------------------------------------
- * Headers
- *------------------------------------------------------------------------------*/
-
-#include "board.h"
-#include
-
-#include "exceptions.h"
-#include "board_lowlevel.h"
-
-/*------------------------------------------------------------------------------
- * Types
- *------------------------------------------------------------------------------*/
-typedef union { IntFunc __fun; void * __ptr; } IntVector;
-
-/*------------------------------------------------------------------------------
- * ProtoTypes
- *------------------------------------------------------------------------------*/
-extern void __iar_program_start( void );
-
-int __low_level_init( void );
-
-/*------------------------------------------------------------------------------
- * Variables
- *------------------------------------------------------------------------------*/
-extern unsigned int __ICFEDIT_vector_start__;
-
-
-/*------------------------------------------------------------------------------
- * Exception Table
- *------------------------------------------------------------------------------*/
-#pragma language=extended
-#pragma segment="CSTACK"
-
-/* The name "__vector_table" has special meaning for C-SPY: */
-/* it is where the SP start value is found, and the NVIC vector */
-/* table register (VTOR) is initialized to this address if != 0. */
-
-#pragma section = ".vectors"
-#pragma location = ".vectors"
-const IntVector __vector_table[] =
-{
- { .__ptr = __sfe( "CSTACK" ) },
- __iar_program_start,
-
- NMI_Handler,
- HardFault_Handler,
- MemManage_Handler,
- BusFault_Handler,
- UsageFault_Handler,
- 0, 0, 0, 0, /* Reserved */
- SVC_Handler,
- DebugMon_Handler,
- 0, /* Reserved */
- PendSV_Handler,
- SysTick_Handler,
-
- /* Configurable interrupts */
- SUPC_IrqHandler, /* 0 SUPPLY CONTROLLER */
- RSTC_IrqHandler, /* 1 RESET CONTROLLER */
- RTC_IrqHandler, /* 2 REAL TIME CLOCK */
- RTT_IrqHandler, /* 3 REAL TIME TIMER */
- WDT_IrqHandler, /* 4 WATCHDOG TIMER */
- PMC_IrqHandler, /* 5 PMC */
- EEFC_IrqHandler, /* 6 EEFC */
- IrqHandlerNotUsed, /* 7 Reserved */
- UART0_IrqHandler, /* 8 UART0 */
- UART1_IrqHandler, /* 9 UART1 */
- SMC_IrqHandler, /* 10 SMC */
- PIOA_IrqHandler, /* 11 Parallel IO Controller A */
- PIOB_IrqHandler, /* 12 Parallel IO Controller B */
- PIOC_IrqHandler, /* 13 Parallel IO Controller C */
- USART0_IrqHandler, /* 14 USART 0 */
- USART1_IrqHandler, /* 15 USART 1 */
- IrqHandlerNotUsed, /* 16 Reserved */
- IrqHandlerNotUsed, /* 17 Reserved */
- MCI_IrqHandler, /* 18 MCI */
- TWI0_IrqHandler, /* 19 TWI 0 */
- TWI1_IrqHandler, /* 20 TWI 1 */
- SPI_IrqHandler, /* 21 SPI */
- SSC_IrqHandler, /* 22 SSC */
- TC0_IrqHandler, /* 23 Timer Counter 0 */
- TC1_IrqHandler, /* 24 Timer Counter 1 */
- TC2_IrqHandler, /* 25 Timer Counter 2 */
- TC3_IrqHandler, /* 26 Timer Counter 3 */
- TC4_IrqHandler, /* 27 Timer Counter 4 */
- TC5_IrqHandler, /* 28 Timer Counter 5 */
- ADC_IrqHandler, /* 29 ADC controller */
- DAC_IrqHandler, /* 30 DAC controller */
- PWM_IrqHandler, /* 31 PWM */
- CRCCU_IrqHandler, /* 32 CRC Calculation Unit */
- ACC_IrqHandler, /* 33 Analog Comparator */
- USBD_IrqHandler, /* 34 USB Device Port */
- IrqHandlerNotUsed /* 35 not used */
-};
-
-/*------------------------------------------------------------------------------
- * Exception Table
- *------------------------------------------------------------------------------*/
-
-/**------------------------------------------------------------------------------
- * This is the code that gets called on processor reset. To initialize the
- * device.
- *------------------------------------------------------------------------------*/
-int __low_level_init( void )
-{
- unsigned int * src = __section_begin(".vectors");
-
- LowLevelInit();
-
- SCB->VTOR = ((unsigned int)(src)) | (0x0 << 7);
-
- return 1; /* if return 0, the data sections will not be initialized. */
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_cstartup_keil.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_cstartup_keil.c
deleted file mode 100644
index aeb93586..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_cstartup_keil.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-#include "board.h"
-#include "exceptions.h"
-#include "board_lowlevel.h"
-
-//------------------------------------------------------------------------------
-// Definitions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Types
-//------------------------------------------------------------------------------
-typedef union { IntFunc __fun; void * __ptr; } IrqVector;
-
-//------------------------------------------------------------------------------
-// ProtoTypes
-//------------------------------------------------------------------------------
-extern int Image$$ARM_LIB_STACK$$ZI$$Limit;
-extern int Image$$Vector_region$$Base;
-extern int Image$$Vector_region$$Limit;
-
-extern void __main(void);
-void resetHandler( void );
-
-//------------------------------------------------------------------------------
-// Variables
-//------------------------------------------------------------------------------
-
-#pragma arm section rodata="vectors"
-const IrqVector __vector_table[] =
-{
- (IntFunc)&Image$$ARM_LIB_STACK$$ZI$$Limit,
- resetHandler,
-
- NMI_Handler,
- HardFault_Handler,
- MemManage_Handler,
- BusFault_Handler,
- UsageFault_Handler,
- 0, 0, 0, 0, // Reserved
- SVC_Handler,
- DebugMon_Handler,
- 0, // Reserved
- PendSV_Handler,
- SysTick_Handler,
-
- // Configurable interrupts
- SUPC_IrqHandler, // 0 SUPPLY CONTROLLER
- RSTC_IrqHandler, // 1 RESET CONTROLLER
- RTC_IrqHandler, // 2 REAL TIME CLOCK
- RTT_IrqHandler, // 3 REAL TIME TIMER
- WDT_IrqHandler, // 4 WATCHDOG TIMER
- PMC_IrqHandler, // 5 PMC
- EFC0_IrqHandler, // 6 EFC0
- EFC1_IrqHandler, // 7 EFC1
- DBGU_IrqHandler, // 8 DBGU
- HSMC4_IrqHandler, // 9 HSMC4
- PIOA_IrqHandler, // 10 Parallel IO Controller A
- PIOB_IrqHandler, // 11 Parallel IO Controller B
- PIOC_IrqHandler, // 12 Parallel IO Controller C
- USART0_IrqHandler, // 13 USART 0
- USART1_IrqHandler, // 14 USART 1
- USART2_IrqHandler, // 15 USART 2
- USART3_IrqHandler, // 16 USART 3
- MCI0_IrqHandler, // 17 Multimedia Card Interface
- TWI0_IrqHandler, // 18 TWI 0
- TWI1_IrqHandler, // 19 TWI 1
- SPI0_IrqHandler, // 20 Serial Peripheral Interface
- SSC0_IrqHandler, // 21 Serial Synchronous Controller 0
- TC0_IrqHandler, // 22 Timer Counter 0
- TC1_IrqHandler, // 23 Timer Counter 1
- TC2_IrqHandler, // 24 Timer Counter 2
- PWM_IrqHandler, // 25 Pulse Width Modulation Controller
- ADCC0_IrqHandler, // 26 ADC controller0
- ADCC1_IrqHandler, // 27 ADC controller1
- HDMA_IrqHandler, // 28 HDMA
- UDPD_IrqHandler, // 29 USB Device High Speed UDP_HS
- IrqHandlerNotUsed // 30 not used
-};
-#pragma arm section
-
-//------------------------------------------------------------------------------
-/// This is the code that gets called on processor reset. To initialize the
-/// device.
-//------------------------------------------------------------------------------
-void resetHandler( void )
-{
- unsigned int *pSrc = (unsigned int *)&Image$$Vector_region$$Base;
-
- // Low level Initialize
- LowLevelInit();
-
- AT91C_BASE_NVIC->NVIC_VTOFFR = ((unsigned int)(pSrc)) | (0x0 << 7);
-
- // Enter C library entry point
- __main();
-
- /* Infinite loop */
- while(1);
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_lowlevel.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_lowlevel.c
deleted file mode 100644
index 63ce7117..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_lowlevel.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include "board.h"
-#include "board_memories.h"
-#include "board_lowlevel.h"
-#include
-
-/*----------------------------------------------------------------------------
- * Local definitions
- *----------------------------------------------------------------------------*/
-/** Define clock timeout */
-#define CLOCK_TIMEOUT 5000
-
-/*----------------------------------------------------------------------------
- * Local functions
- *----------------------------------------------------------------------------*/
-static void BOARD_ConfigurePmc(void)
-{
-
-#define AT91C_CKGR_MUL_SHIFT 16
-#define AT91C_CKGR_PLLCOUNT_SHIFT 8
-#define AT91C_CKGR_DIV_SHIFT 0
-
-// Settings at 64 MHz for MCK
-
-#define BOARD_OSCOUNT (CKGR_MOR_MOSCXTST & (0x8 << 8))
-
-// PLLA Settings 64 MHz : 12 / 3 * 32
-#define BOARD_PLLAR ((1 << 29) | (0x1F << AT91C_CKGR_MUL_SHIFT) \
- | (0x1 << AT91C_CKGR_PLLCOUNT_SHIFT) | (0x3 << AT91C_CKGR_DIV_SHIFT))
-
-// PLLB Settings 96 MHz
-#define BOARD_PLLBR ((1 << 29) | (0x7 << AT91C_CKGR_MUL_SHIFT) \
- | (0x1 << AT91C_CKGR_PLLCOUNT_SHIFT) | (0x1 << AT91C_CKGR_DIV_SHIFT))
-
-// USB on PLLB, MCK/PCK on PLLA
-#define BOARD_MCKR ( PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK)
-
-// Define clock timeout
-#undef CLOCK_TIMEOUT
-#define CLOCK_TIMEOUT 0xFFFFFFFF
-
- uint32_t timeout = 0;
-
- /* Enable NRST reset
- ************************************/
- //AT91C_BASE_RSTC->RSTC_RMR |= AT91C_RSTC_URSTEN;
-
- /* Initialize main oscillator
- ****************************/
- if(!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL))
- {
-
- PMC->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
- timeout = 0;
- while (!(PMC->PMC_SR & PMC_SR_MOSCXTS) && (timeout++ < CLOCK_TIMEOUT));
-
- }
-
- /* Switch to 3-20MHz Xtal oscillator */
- PMC->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
- timeout = 0;
- while (!(PMC->PMC_SR & PMC_SR_MOSCSELS) && (timeout++ < CLOCK_TIMEOUT));
- PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK;
- timeout = 0;
- while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT));
-
- /** Set 3 WS for Embedded Flash Access */
- EFC->EEFC_FMR = (3 << 8);
-
- /* Initialize PLLA */
- PMC->CKGR_PLLAR = BOARD_PLLAR;
- timeout = 0;
- while (!(PMC->PMC_SR & PMC_SR_LOCKA) && (timeout++ < CLOCK_TIMEOUT));
-
- /* Initialize PLLB */
- PMC->CKGR_PLLBR = BOARD_PLLBR;
- timeout = 0;
- while (!(PMC->PMC_SR & PMC_SR_LOCKB) && (timeout++ < CLOCK_TIMEOUT));
-
- // Set USB clock on PLLB
- REG_PMC_USB = PMC_USB_USBS | (PMC_USB_USBDIV & (1 << 8));
-
- /* Switch to fast clock
- **********************/
- PMC->PMC_MCKR = (BOARD_MCKR & ~PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK;
- timeout = 0;
- while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT));
-
- PMC->PMC_MCKR = BOARD_MCKR;
- timeout = 0;
- while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT));
-
-}
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------------*/
-/**
- * \brief Performs the low-level initialization of the chip. This includes EFC,
- * master clock and watchdog configuration.
- */
-/*----------------------------------------------------------------------------*/
-void LowLevelInit (void)
-{
- /** Configure PMC */
- BOARD_ConfigurePmc();
-}
\ No newline at end of file
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_lowlevel.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_lowlevel.h
deleted file mode 100644
index c7effdf1..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_lowlevel.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-/// \unit
-///
-/// !!!Purpose
-///
-/// Collection of methods for lowlevel.
-///
-//------------------------------------------------------------------------------
-
-#ifndef BOARD_LOWLEVEL_H
-#define BOARD_LOWLEVEL_H
-
-//------------------------------------------------------------------------------
-// Exported functions
-//------------------------------------------------------------------------------
-extern void LowLevelInit(void);
-extern void OptimizeCpuSpeed(void);
-
-#endif // BOARD_LOWLEVEL_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_memories.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_memories.c
deleted file mode 100644
index 6c224263..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_memories.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/*
- Title: Memories implementation
-*/
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-#include
-#include "board_memories.h"
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-
-/**
- * \brief Configures the EBI for NandFlash access.
- *
- */
-extern void BOARD_ConfigureNandFlash( void )
-{
- // Open EBI clock
- PMC->PMC_PCER0 = (1<< ID_SMC);
- // NCS0 is assigned to a NAND Flash (NANDOE and NANWE used for NCS0)
- MATRIX->CCFG_SMCNFCS = CCFG_SMCNFCS_SMC_NFCS0;
-
-#if 0
- SMC->SMC_CS_NUMBER[0].SMC_SETUP = 0
- | ((0 << 0) & SMC_SETUP0_NWE_SETUP)
- | ((1 << 8) & SMC_SETUP0_NCS_WR_SETUP)
- | ((0 << 16) & SMC_SETUP0_NRD_SETUP)
- | ((1 << 24) & SMC_SETUP0_NCS_RD_SETUP);
-
- SMC->SMC_CS_NUMBER[0].SMC_PULSE = 0
- | ((2 << 0) & SMC_PULSE0_NWE_PULSE)
- | ((3 << 8) & SMC_PULSE0_NCS_WR_PULSE)
- | ((4 << 16) & SMC_PULSE0_NRD_PULSE)
- | ((4 << 24) & SMC_PULSE0_NCS_RD_PULSE);
-
- SMC->SMC_CS_NUMBER[0].SMC_CYCLE = 0
- | ((4 << 0) & SMC_CYCLE0_NWE_CYCLE)
- | ((7 << 16) & SMC_CYCLE0_NRD_CYCLE);
-
- SMC->SMC_CS_NUMBER[0].SMC_MODE = SMC_MODE0_READ_MODE | SMC_MODE0_WRITE_MODE;
-#else
- SMC->SMC_CS_NUMBER[0].SMC_SETUP = 0
- | ((0 << 0) & SMC_SETUP0_NWE_SETUP)
- | ((0 << 8) & SMC_SETUP0_NCS_WR_SETUP)
- | ((0 << 16) & SMC_SETUP0_NRD_SETUP)
- | ((0 << 24) & SMC_SETUP0_NCS_RD_SETUP);
-
- SMC->SMC_CS_NUMBER[0].SMC_PULSE = 0
- | ((2 << 0) & SMC_PULSE0_NWE_PULSE)
- | ((2 << 8) & SMC_PULSE0_NCS_WR_PULSE)
- | ((2 << 16) & SMC_PULSE0_NRD_PULSE)
- | ((2 << 24) & SMC_PULSE0_NCS_RD_PULSE);
-
- SMC->SMC_CS_NUMBER[0].SMC_CYCLE = 0
- | ((3 << 0) & SMC_CYCLE0_NWE_CYCLE)
- | ((3 << 16) & SMC_CYCLE0_NRD_CYCLE);
-
- SMC->SMC_CS_NUMBER[0].SMC_MODE = SMC_MODE1_READ_MODE | SMC_MODE1_WRITE_MODE;
-#endif
-
-
-
-}
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_memories.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_memories.h
deleted file mode 100644
index b9f472ff..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_memories.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-/// \unit
-/// !Purpose
-///
-///
-/// !Usage
-///
-//------------------------------------------------------------------------------
-
-#ifndef BOARD_MEMORIES_H
-#define BOARD_MEMORIES_H
-
-//------------------------------------------------------------------------------
-// Exported functions
-//------------------------------------------------------------------------------
-
-extern void BOARD_ConfigureNandFlash( void ) ;
-
-#endif //#ifndef BOARD_MEMORIES_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/exceptions.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/exceptions.c
deleted file mode 100644
index b9b329bf..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/exceptions.c
+++ /dev/null
@@ -1,385 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- * This file contains the default exception handlers.
- *
- * \note
- * The exception handler has weak aliases.
- * As they are weak aliases, any function with the same name will override
- * this definition.
- */
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include "exceptions.h"
-#include
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief Default interrupt handler for not used irq.
- */
-void IrqHandlerNotUsed(void)
-{
- while(1);
-}
-
-/**
- * \brief Default NMI interrupt handler.
- */
-WEAK void NMI_Handler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default HardFault interrupt handler.
- */
-WEAK void HardFault_Handler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default MemManage interrupt handler.
- */
-WEAK void MemManage_Handler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default BusFault interrupt handler.
- */
-WEAK void BusFault_Handler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default UsageFault interrupt handler.
- */
-WEAK void UsageFault_Handler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default SVC interrupt handler.
- */
-WEAK void SVC_Handler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default DebugMon interrupt handler.
- */
-WEAK void DebugMon_Handler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default PendSV interrupt handler.
- */
-WEAK void PendSV_Handler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default SysTick interrupt handler.
- */
-WEAK void SysTick_Handler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default interrupt handler for Supply Controller.
- */
-WEAK void SUPC_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default interrupt handler for Reset Controller.
- */
-WEAK void RSTC_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default interrupt handler for Real Time Clock.
- */
-WEAK void RTC_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default interrupt handler for Real Time Timer.
- */
-WEAK void RTT_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default interrupt handler for Watchdog Timer.
- */
-WEAK void WDT_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default interrupt handler for PMC.
- */
-WEAK void PMC_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default interrupt handler for EEFC.
- */
-WEAK void EEFC_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default interrupt handler for UART0.
- */
-WEAK void UART0_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default interrupt handler for UART1.
- */
-WEAK void UART1_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default interrupt handler for SMC.
- */
-WEAK void SMC_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default interrupt handler for PIOA Controller.
- */
-WEAK void PIOA_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default interrupt handler for PIOB Controller.
- */
-WEAK void PIOB_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default interrupt handler for PIOC Controller.
- */
-WEAK void PIOC_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default interrupt handler for USART0.
- */
-WEAK void USART0_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default interrupt handler for USART1.
- */
-WEAK void USART1_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default interrupt handler for MCI.
- */
-WEAK void MCI_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default interrupt handler for TWI0.
- */
-WEAK void TWI0_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default interrupt handler for TWI1.
- */
-WEAK void TWI1_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default interrupt handler for SPI.
- */
-WEAK void SPI_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default interrupt handler for SSC.
- */
-WEAK void SSC_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default interrupt handler for TC0.
- */
-WEAK void TC0_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default interrupt handler for TC1.
- */
-WEAK void TC1_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default interrupt handler for TC2.
- */
-WEAK void TC2_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default SUPC interrupt handler for TC3.
- */
-WEAK void TC3_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default SUPC interrupt handler for TC4.
- */
-WEAK void TC4_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default SUPC interrupt handler for TC5.
- */
-WEAK void TC5_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default SUPC interrupt handler for ADC.
- */
-WEAK void ADC_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default SUPC interrupt handler for DAC.
- */
-WEAK void DAC_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default SUPC interrupt handler for PWM.
- */
-WEAK void PWM_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default SUPC interrupt handler for CRCCU.
- */
-WEAK void CRCCU_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default SUPC interrupt handler for ACC.
- */
-WEAK void ACC_IrqHandler(void)
-{
- while(1);
-}
-
-/**
- * \brief Default SUPC interrupt handler for USBD.
- */
-WEAK void USBD_IrqHandler(void)
-{
- while(1);
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/exceptions.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/exceptions.h
deleted file mode 100644
index b6b366c6..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/exceptions.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- * Interface for default exception handlers.
- */
-
-#ifndef EXCEPTIONS_H
-#define EXCEPTIONS_H
-
-/*----------------------------------------------------------------------------
- * Types
- *----------------------------------------------------------------------------*/
-
-/* Function prototype for exception table items (interrupt handler). */
-typedef void( *IntFunc )( void );
-
-/* Define WEAK attribute */
-#if defined ( __CC_ARM )
- #define WEAK __attribute__ ((weak))
-#elif defined ( __ICCARM__ )
- #define WEAK __weak
-#elif defined ( __GNUC__ )
- #define WEAK __attribute__ ((weak))
-#endif
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-extern void IrqHandlerNotUsed(void);
-
-extern WEAK void NMI_Handler( void );
-extern WEAK void HardFault_Handler( void );
-extern WEAK void MemManage_Handler( void );
-extern WEAK void BusFault_Handler( void );
-extern WEAK void UsageFault_Handler( void );
-extern WEAK void SVC_Handler( void );
-extern WEAK void DebugMon_Handler( void );
-extern WEAK void PendSV_Handler( void );
-extern WEAK void SysTick_Handler( void );
-
-extern WEAK void SUPC_IrqHandler(void);
-extern WEAK void RSTC_IrqHandler(void);
-extern WEAK void RTC_IrqHandler(void);
-extern WEAK void RTT_IrqHandler(void);
-extern WEAK void WDT_IrqHandler(void);
-extern WEAK void PMC_IrqHandler(void);
-extern WEAK void EEFC_IrqHandler(void);
-extern WEAK void UART0_IrqHandler(void);
-extern WEAK void UART1_IrqHandler(void);
-extern WEAK void SMC_IrqHandler(void);
-extern WEAK void PIOA_IrqHandler(void);
-extern WEAK void PIOB_IrqHandler(void);
-extern WEAK void PIOC_IrqHandler(void);
-extern WEAK void USART0_IrqHandler(void);
-extern WEAK void USART1_IrqHandler(void);
-extern WEAK void MCI_IrqHandler(void);
-extern WEAK void TWI0_IrqHandler(void);
-extern WEAK void TWI1_IrqHandler(void);
-extern WEAK void SPI_IrqHandler(void);
-extern WEAK void SSC_IrqHandler(void);
-extern WEAK void TC0_IrqHandler(void);
-extern WEAK void TC1_IrqHandler(void);
-extern WEAK void TC2_IrqHandler(void);
-extern WEAK void TC3_IrqHandler(void);
-extern WEAK void TC4_IrqHandler(void);
-extern WEAK void TC5_IrqHandler(void);
-extern WEAK void ADC_IrqHandler(void);
-extern WEAK void DAC_IrqHandler(void);
-extern WEAK void PWM_IrqHandler(void);
-extern WEAK void CRCCU_IrqHandler(void);
-extern WEAK void ACC_IrqHandler(void);
-extern WEAK void USBD_IrqHandler(void);
-
-#endif /* #ifndef EXCEPTIONS_H */
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/demo.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/demo.c
deleted file mode 100644
index 0d4ea843..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/demo.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * FreeModbus Libary: Atmel AT91SAM3S Demo Application
- * Copyright (C) 2010 Christian Walter
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * IF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * File: $Id$
- */
-
-/* ----------------------- AT91SAM3S includes -------------------------------*/
-#include
-#include
-
-/* ----------------------- Modbus includes ----------------------------------*/
-#include "mb.h"
-#include "mbport.h"
-
-/* ----------------------- Defines ------------------------------------------*/
-#define REG_INPUT_START ( 1000 )
-#define REG_INPUT_NREGS ( 64 )
-
-#define REG_HOLDING_START ( 1 )
-#define REG_HOLDING_NREGS ( 32 )
-
-/* ----------------------- Static functions ---------------------------------*/
-static void _SetupHardware( void );
-
-/* ----------------------- Static variables ---------------------------------*/
-static USHORT usRegInputStart = REG_INPUT_START;
-static USHORT usRegInputBuf[REG_INPUT_NREGS];
-static USHORT usRegHoldingStart = REG_HOLDING_START;
-static USHORT usRegHoldingBuf[REG_HOLDING_NREGS];
-
-/* ----------------------- Start implementation -----------------------------*/
-int
-main( void )
-{
- _SetupHardware( );
-
- const UCHAR ucSlaveID[] = { 0xAA, 0xBB, 0xCC };
- eMBErrorCode eStatus;
-
- for( ;; )
- {
- if( MB_ENOERR != ( eStatus = eMBInit( MB_RTU, 0x0A, 1, 38400, MB_PAR_EVEN ) ) )
- {
- /* Can not initialize. Add error handling code here. */
- }
- else
- {
- if( MB_ENOERR != ( eStatus = eMBSetSlaveID( 0x34, TRUE, ucSlaveID, 3 ) ) )
- {
- /* Can not set slave id. Check arguments */
- }
- else if( MB_ENOERR != ( eStatus = eMBEnable( ) ) )
- {
- /* Enable failed. */
- }
- else
- {
- usRegHoldingBuf[0] = 1;
- do
- {
- ( void )eMBPoll( );
-
- /* Here we simply count the number of poll cycles. */
- usRegInputBuf[0]++;
- }
- while( usRegHoldingBuf[0] );
- ( void )eMBDisable( );
- ( void )eMBClose( );
- }
- }
- }
- return 1;
-}
-
-void _SetupHardware( void )
-{
- WDT_Disable( );
-
- uint32_t i = 0;
- for( i = 0; i < 35; i++ )
- {
- NVIC_SetPriority( (IRQn_Type)i, 0xF << 4 ) ;
- }
-}
-
-eMBErrorCode
-eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs )
-{
- eMBErrorCode eStatus = MB_ENOERR;
- int iRegIndex;
-
- if( ( usAddress >= REG_INPUT_START )
- && ( usAddress + usNRegs <= REG_INPUT_START + REG_INPUT_NREGS ) )
- {
- iRegIndex = ( int )( usAddress - usRegInputStart );
- while( usNRegs > 0 )
- {
- *pucRegBuffer++ =
- ( unsigned char )( usRegInputBuf[iRegIndex] >> 8 );
- *pucRegBuffer++ =
- ( unsigned char )( usRegInputBuf[iRegIndex] & 0xFF );
- iRegIndex++;
- usNRegs--;
- }
- }
- else
- {
- eStatus = MB_ENOREG;
- }
-
- return eStatus;
-}
-
-eMBErrorCode
-eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, eMBRegisterMode eMode )
-{
- eMBErrorCode eStatus = MB_ENOERR;
- int iRegIndex;
-
- if( ( usAddress >= REG_HOLDING_START ) && ( usAddress + usNRegs <= REG_HOLDING_START + REG_HOLDING_NREGS ) )
- {
- iRegIndex = ( int )( usAddress - usRegHoldingStart );
- switch ( eMode )
- {
- case MB_REG_READ:
- while( usNRegs > 0 )
- {
- *pucRegBuffer++ = ( unsigned char )( usRegHoldingBuf[iRegIndex] >> 8 );
- *pucRegBuffer++ = ( unsigned char )( usRegHoldingBuf[iRegIndex] & 0xFF );
- iRegIndex++;
- usNRegs--;
- }
- break;
-
- case MB_REG_WRITE:
- while( usNRegs > 0 )
- {
- usRegHoldingBuf[iRegIndex] = *pucRegBuffer++ << 8;
- usRegHoldingBuf[iRegIndex] |= *pucRegBuffer++;
- iRegIndex++;
- usNRegs--;
- }
- }
- }
- else
- {
- eStatus = MB_ENOREG;
- }
- return eStatus;
-}
-
-eMBErrorCode
-eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils,
- eMBRegisterMode eMode )
-{
- return MB_ENOREG;
-}
-
-eMBErrorCode
-eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete )
-{
- return MB_ENOREG;
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/demo.ewp b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/demo.ewp
deleted file mode 100644
index 861dd43a..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/demo.ewp
+++ /dev/null
@@ -1,1758 +0,0 @@
-
-
-
- 2
-
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- 1
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- 3
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- 17
- 1
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- 22
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- ICCARM
- 2
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- 22
- 1
- 0
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- AARM
- 2
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- 1
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- 0
-
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-
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- 0
-
-
-
-
- board
-
- $PROJ_DIR$\board\board_cstartup_iar.c
-
-
- $PROJ_DIR$\board\board_lowlevel.c
-
-
- $PROJ_DIR$\board\board_memories.c
-
-
- $PROJ_DIR$\board\exceptions.c
-
-
-
- drivers
-
- $PROJ_DIR$\libraries\drivers\pio\pio.c
-
-
- $PROJ_DIR$\libraries\drivers\pmc\pmc.c
-
-
- $PROJ_DIR$\libraries\drivers\tc\tc.c
-
-
- $PROJ_DIR$\libraries\drivers\usart\usart.c
-
-
- $PROJ_DIR$\libraries\drivers\wdt\wdt.c
-
-
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- modbus
-
- $PROJ_DIR$\..\..\modbus\mb.c
-
-
- $PROJ_DIR$\..\..\modbus\include\mb.h
-
-
- $PROJ_DIR$\..\..\modbus\ascii\mbascii.c
-
-
- $PROJ_DIR$\..\..\modbus\ascii\mbascii.h
-
-
- $PROJ_DIR$\..\..\modbus\include\mbconfig.h
-
-
- $PROJ_DIR$\..\..\modbus\rtu\mbcrc.c
-
-
- $PROJ_DIR$\..\..\modbus\rtu\mbcrc.h
-
-
- $PROJ_DIR$\..\..\modbus\include\mbframe.h
-
-
- $PROJ_DIR$\..\..\modbus\include\mbfunc.h
-
-
- $PROJ_DIR$\..\..\modbus\functions\mbfunccoils.c
-
-
- $PROJ_DIR$\..\..\modbus\functions\mbfuncdiag.c
-
-
- $PROJ_DIR$\..\..\modbus\functions\mbfuncdisc.c
-
-
- $PROJ_DIR$\..\..\modbus\functions\mbfuncholding.c
-
-
- $PROJ_DIR$\..\..\modbus\functions\mbfuncinput.c
-
-
- $PROJ_DIR$\..\..\modbus\functions\mbfuncother.c
-
-
- $PROJ_DIR$\..\..\modbus\include\mbport.h
-
-
- $PROJ_DIR$\..\..\modbus\include\mbproto.h
-
-
- $PROJ_DIR$\..\..\modbus\rtu\mbrtu.c
-
-
- $PROJ_DIR$\..\..\modbus\rtu\mbrtu.h
-
-
- $PROJ_DIR$\..\..\modbus\functions\mbutils.c
-
-
- $PROJ_DIR$\..\..\modbus\include\mbutils.h
-
-
-
- port
-
- $PROJ_DIR$\port\port.h
-
-
- $PROJ_DIR$\port\portevent.c
-
-
- $PROJ_DIR$\port\portother.c
-
-
- $PROJ_DIR$\port\portserial.c
-
-
- $PROJ_DIR$\port\porttimer.c
-
-
-
- $PROJ_DIR$\demo.c
-
-
-
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/demo.eww b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/demo.eww
deleted file mode 100644
index 2b25c134..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/demo.eww
+++ /dev/null
@@ -1,10 +0,0 @@
-
-
-
-
- $WS_DIR$\demo.ewp
-
-
-
-
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/demo_rtu.bat b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/demo_rtu.bat
deleted file mode 100644
index 402b4757..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/demo_rtu.bat
+++ /dev/null
@@ -1 +0,0 @@
-..\..\tools\modpoll.exe -m rtu -a 10 -r 1000 -c 4 -t 3 -b 38400 -d 8 -p even COM1
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/cmsis/core_cm3.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/cmsis/core_cm3.c
deleted file mode 100644
index b3a9a886..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/cmsis/core_cm3.c
+++ /dev/null
@@ -1,804 +0,0 @@
-/******************************************************************************
- * @file: core_cm3.c
- * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Source File
- * @version: V1.10
- * @date: 24. Feb. 2009
- *----------------------------------------------------------------------------
- *
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-
-#include
-
-/* define compiler specific symbols */
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for armcc */
- #define __INLINE __inline /*!< inline keyword for armcc */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for iarcc */
- #define __INLINE inline /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */
- #define __nop __no_operation /*!< no operation intrinsic in iarcc */
-
-#elif defined ( __GNUC__ )
- #define __ASM asm /*!< asm keyword for gcc */
- #define __INLINE inline /*!< inline keyword for gcc */
-#endif
-
-
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @param none
- * @return uint32_t ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-__ASM uint32_t __get_PSP(void)
-{
- mrs r0, psp
- bx lr
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param uint32_t Process Stack Pointer
- * @return none
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
- msr psp, r0
- bx lr
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @param none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-__ASM uint32_t __get_MSP(void)
-{
- mrs r0, msp
- bx lr
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param uint32_t Main Stack Pointer
- * @return none
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
- msr msp, r0
- bx lr
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param uint16_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in unsigned short value
- */
-__ASM uint32_t __REV16(uint16_t value)
-{
- rev16 r0, r0
- bx lr
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param int16_t value to reverse
- * @return int32_t reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-__ASM int32_t __REVSH(int16_t value)
-{
- revsh r0, r0
- bx lr
-}
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * @param none
- * @return none
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-__ASM void __CLREX(void)
-{
- clrex
-}
-
-/**
- * @brief Return the Base Priority value
- *
- * @param none
- * @return uint32_t BasePriority
- *
- * Return the content of the base priority register
- */
-__ASM uint32_t __get_BASEPRI(void)
-{
- mrs r0, basepri
- bx lr
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param uint32_t BasePriority
- * @return none
- *
- * Set the base priority register
- */
-__ASM void __set_BASEPRI(uint32_t basePri)
-{
- msr basepri, r0
- bx lr
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @param none
- * @return uint32_t PriMask
- *
- * Return the state of the priority mask bit from the priority mask
- * register
- */
-__ASM uint32_t __get_PRIMASK(void)
-{
- mrs r0, primask
- bx lr
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param uint32_t PriMask
- * @return none
- *
- * Set the priority mask bit in the priority mask register
- */
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
- msr primask, r0
- bx lr
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @param none
- * @return uint32_t FaultMask
- *
- * Return the content of the fault mask register
- */
-__ASM uint32_t __get_FAULTMASK(void)
-{
- mrs r0, faultmask
- bx lr
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param uint32_t faultMask value
- * @return none
- *
- * Set the fault mask register
- */
-__ASM void __set_FAULTMASK(uint32_t faultMask)
-{
- msr faultmask, r0
- bx lr
-}
-
-/**
- * @brief Return the Control Register value
- *
- * @param none
- * @return uint32_t Control value
- *
- * Return the content of the control register
- */
-__ASM uint32_t __get_CONTROL(void)
-{
- mrs r0, control
- bx lr
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param uint32_t Control value
- * @return none
- *
- * Set the control register
- */
-__ASM void __set_CONTROL(uint32_t control)
-{
- msr control, r0
- bx lr
-}
-
-#endif /* __ARMCC_VERSION */
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-#pragma diag_suppress=Pe940
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @param none
- * @return uint32_t ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void)
-{
- __ASM("mrs r0, psp");
- __ASM("bx lr");
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param uint32_t Process Stack Pointer
- * @return none
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM("msr psp, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @param none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void)
-{
- __ASM("mrs r0, msp");
- __ASM("bx lr");
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param uint32_t Main Stack Pointer
- * @return none
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM("msr msp, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param uint16_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
- __ASM("rev16 r0, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Reverse bit order of value
- *
- * @param uint32_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
- __ASM("rbit r0, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive
- *
- * @param uint8_t* address
- * @return uint8_t value of (*address)
- *
- * Exclusive LDR command
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
- __ASM("ldrexb r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive
- *
- * @param uint16_t* address
- * @return uint16_t value of (*address)
- *
- * Exclusive LDR command
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
- __ASM("ldrexh r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive
- *
- * @param uint32_t* address
- * @return uint32_t value of (*address)
- *
- * Exclusive LDR command
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
- __ASM("ldrex r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive
- *
- * @param uint8_t *address
- * @param uint8_t value to store
- * @return uint32_t successful / failed
- *
- * Exclusive STR command
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
- __ASM("strexb r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive
- *
- * @param uint16_t *address
- * @param uint16_t value to store
- * @return uint32_t successful / failed
- *
- * Exclusive STR command
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
- __ASM("strexh r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive
- *
- * @param uint32_t *address
- * @param uint32_t value to store
- * @return uint32_t successful / failed
- *
- * Exclusive STR command
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
- __ASM("strex r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @param none
- * @return uint32_t ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, psp" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param uint32_t Process Stack Pointer
- * @return none
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) );
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @param none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, msp" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param uint32_t Main Stack Pointer
- * @return none
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) );
-}
-
-/**
- * @brief Return the Base Priority value
- *
- * @param none
- * @return uint32_t BasePriority
- *
- * Return the content of the base priority register
- */
-uint32_t __get_BASEPRI(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param uint32_t BasePriority
- * @return none
- *
- * Set the base priority register
- */
-void __set_BASEPRI(uint32_t value)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @param none
- * @return uint32_t PriMask
- *
- * Return the state of the priority mask bit from the priority mask
- * register
- */
-uint32_t __get_PRIMASK(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param uint32_t PriMask
- * @return none
- *
- * Set the priority mask bit in the priority mask register
- */
-void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @param none
- * @return uint32_t FaultMask
- *
- * Return the content of the fault mask register
- */
-uint32_t __get_FAULTMASK(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param uint32_t faultMask value
- * @return none
- *
- * Set the fault mask register
- */
-void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-/**
- * @brief Reverse byte order in integer value
- *
- * @param uint32_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in integer value
- */
-uint32_t __REV(uint32_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param uint16_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param int32_t value to reverse
- * @return int32_t reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-int32_t __REVSH(int16_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse bit order of value
- *
- * @param uint32_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive
- *
- * @param uint8_t* address
- * @return uint8_t value of (*address)
- *
- * Exclusive LDR command
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
- uint8_t result=0;
-
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive
- *
- * @param uint16_t* address
- * @return uint16_t value of (*address)
- *
- * Exclusive LDR command
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
- uint16_t result=0;
-
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive
- *
- * @param uint32_t* address
- * @return uint32_t value of (*address)
- *
- * Exclusive LDR command
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive
- *
- * @param uint8_t *address
- * @param uint8_t value to store
- * @return uint32_t successful / failed
- *
- * Exclusive STR command
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive
- *
- * @param uint16_t *address
- * @param uint16_t value to store
- * @return uint32_t successful / failed
- *
- * Exclusive STR command
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive
- *
- * @param uint32_t *address
- * @param uint32_t value to store
- * @return uint32_t successful / failed
- *
- * Exclusive STR command
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-/**
- * @brief Return the Control Register value
- *
- * @param none
- * @return uint32_t Control value
- *
- * Return the content of the control register
- */
-uint32_t __get_CONTROL(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param uint32_t Control value
- * @return none
- *
- * Set the control register
- */
-void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-#endif
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/cmsis/core_cm3.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/cmsis/core_cm3.h
deleted file mode 100644
index 59b054de..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/cmsis/core_cm3.h
+++ /dev/null
@@ -1,1265 +0,0 @@
-/******************************************************************************
- * @file: core_cm3.h
- * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version: V1.10
- * @date: 24. Feb. 2009
- *----------------------------------------------------------------------------
- *
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-
-
-#ifndef __CM3_CORE_H__
-#define __CM3_CORE_H__
-
-
-#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x03) /*!< Cortex core */
-
-/**
- * Lint configuration \n
- * ----------------------- \n
- *
- * The following Lint messages will be suppressed and not shown: \n
- * \n
- * --- Error 10: --- \n
- * register uint32_t __regBasePri __asm("basepri"); \n
- * Error 10: Expecting ';' \n
- * \n
- * --- Error 530: --- \n
- * return(__regBasePri); \n
- * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
- * \n
- * --- Error 550: --- \n
- * __regBasePri = (basePri & 0x1ff); \n
- * } \n
- * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
- * \n
- * --- Error 754: --- \n
- * uint32_t RESERVED0[24]; \n
- * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced \n
- * \n
- * --- Error 750: --- \n
- * #define __CM3_CORE_H__ \n
- * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
- * \n
- * --- Error 528: --- \n
- * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
- * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
- * \n
- * --- Error 751: --- \n
- * } InterruptType_Type; \n
- * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
- * \n
- * \n
- * Note: To re-enable a Message, insert a space before 'lint' * \n
- *
- */
-
-/*lint -save */
-/*lint -e10 */
-/*lint -e530 */
-/*lint -e550 */
-/*lint -e754 */
-/*lint -e750 */
-/*lint -e528 */
-/*lint -e751 */
-
-
-#include /* Include standard types */
-
-#if defined (__ICCARM__)
- #include /* IAR Intrinsics */
-#endif
-
-
-#ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
-#endif
-
-
-
-
-/**
- * IO definitions
- *
- * define access restrictions to peripheral registers
- */
-
-#define __I volatile const /*!< defines 'read only' permissions */
-#define __O volatile /*!< defines 'write only' permissions */
-#define __IO volatile /*!< defines 'read / write' permissions */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- ******************************************************************************/
-
-
-/* System Reset */
-#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */
-#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */
-#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */
-#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */
-
-/* Core Debug */
-#define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */
-#define ITM_TCR_ITMENA 1 /*!< ITM enable */
-
-
-
-
-/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */
-typedef struct
-{
- __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */
- uint32_t RESERVED0[24];
- __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */
- uint32_t RSERVED1[24];
- __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */
- uint32_t RESERVED2[24];
- __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */
- uint32_t RESERVED3[24];
- __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */
- uint32_t RESERVED4[56];
- __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */
- uint32_t RESERVED5[644];
- __O uint32_t STIR; /*!< Software Trigger Interrupt Register */
-} NVIC_Type;
-
-
-/* memory mapping struct for System Control Block */
-typedef struct
-{
- __I uint32_t CPUID; /*!< CPU ID Base Register */
- __IO uint32_t ICSR; /*!< Interrupt Control State Register */
- __IO uint32_t VTOR; /*!< Vector Table Offset Register */
- __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */
- __IO uint32_t SCR; /*!< System Control Register */
- __IO uint32_t CCR; /*!< Configuration Control Register */
- __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IO uint32_t SHCSR; /*!< System Handler Control and State Register */
- __IO uint32_t CFSR; /*!< Configurable Fault Status Register */
- __IO uint32_t HFSR; /*!< Hard Fault Status Register */
- __IO uint32_t DFSR; /*!< Debug Fault Status Register */
- __IO uint32_t MMFAR; /*!< Mem Manage Address Register */
- __IO uint32_t BFAR; /*!< Bus Fault Address Register */
- __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */
- __I uint32_t PFR[2]; /*!< Processor Feature Register */
- __I uint32_t DFR; /*!< Debug Feature Register */
- __I uint32_t ADR; /*!< Auxiliary Feature Register */
- __I uint32_t MMFR[4]; /*!< Memory Model Feature Register */
- __I uint32_t ISAR[5]; /*!< ISA Feature Register */
-} SCB_Type;
-
-
-/* memory mapping struct for SysTick */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< SysTick Current Value Register */
- __I uint32_t CALIB; /*!< SysTick Calibration Register */
-} SysTick_Type;
-
-
-/* memory mapping structur for ITM */
-typedef struct
-{
- __O union
- {
- __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */
- __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */
- __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */
- } PORT [32]; /*!< ITM Stimulus Port Registers */
- uint32_t RESERVED0[864];
- __IO uint32_t TER; /*!< ITM Trace Enable Register */
- uint32_t RESERVED1[15];
- __IO uint32_t TPR; /*!< ITM Trace Privilege Register */
- uint32_t RESERVED2[15];
- __IO uint32_t TCR; /*!< ITM Trace Control Register */
- uint32_t RESERVED3[29];
- __IO uint32_t IWR; /*!< ITM Integration Write Register */
- __IO uint32_t IRR; /*!< ITM Integration Read Register */
- __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */
- uint32_t RESERVED4[43];
- __IO uint32_t LAR; /*!< ITM Lock Access Register */
- __IO uint32_t LSR; /*!< ITM Lock Status Register */
- uint32_t RESERVED5[6];
- __I uint32_t PID4; /*!< ITM Product ID Registers */
- __I uint32_t PID5;
- __I uint32_t PID6;
- __I uint32_t PID7;
- __I uint32_t PID0;
- __I uint32_t PID1;
- __I uint32_t PID2;
- __I uint32_t PID3;
- __I uint32_t CID0;
- __I uint32_t CID1;
- __I uint32_t CID2;
- __I uint32_t CID3;
-} ITM_Type;
-
-
-/* memory mapped struct for Interrupt Type */
-typedef struct
-{
- uint32_t RESERVED0;
- __I uint32_t ICTR; /*!< Interrupt Control Type Register */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
- __IO uint32_t ACTLR; /*!< Auxiliary Control Register */
-#else
- uint32_t RESERVED1;
-#endif
-} InterruptType_Type;
-
-
-/* Memory Protection Unit */
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
-typedef struct
-{
- __I uint32_t TYPE; /*!< MPU Type Register */
- __IO uint32_t CTRL; /*!< MPU Control Register */
- __IO uint32_t RNR; /*!< MPU Region RNRber Register */
- __IO uint32_t RBAR; /*!< MPU Region Base Address Register */
- __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */
- __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */
- __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */
- __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */
- __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */
- __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */
- __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-#endif
-
-
-/* Core Debug Register */
-typedef struct
-{
- __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */
- __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */
- __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */
- __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000) /*!< ITM Base Address */
-#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
-
-#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
-#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
- #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
-#endif
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- ******************************************************************************/
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
- #define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */
-
-#elif defined ( __GNUC__ )
- #define __ASM asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#endif
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#define __enable_fault_irq __enable_fiq
-#define __disable_fault_irq __disable_fiq
-
-#define __NOP __nop
-#define __WFI __wfi
-#define __WFE __wfe
-#define __SEV __sev
-#define __ISB() __isb(0)
-#define __DSB() __dsb(0)
-#define __DMB() __dmb(0)
-#define __REV __rev
-#define __RBIT __rbit
-#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
-#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
-#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
-#define __STREXB(value, ptr) __strex(value, ptr)
-#define __STREXH(value, ptr) __strex(value, ptr)
-#define __STREXW(value, ptr) __strex(value, ptr)
-
-
- /* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
- /* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
- /* intrinsic void __enable_irq(); */
- /* intrinsic void __disable_irq(); */
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @param none
- * @return uint32_t ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param uint32_t Process Stack Pointer
- * @return none
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @param none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param uint32_t Main Stack Pointer
- * @return none
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param uint16_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/*
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param int16_t value to reverse
- * @return int32_t reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * @param none
- * @return none
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-extern void __CLREX(void);
-
-/**
- * @brief Return the Base Priority value
- *
- * @param none
- * @return uint32_t BasePriority
- *
- * Return the content of the base priority register
- */
-extern uint32_t __get_BASEPRI(void);
-
-/**
- * @brief Set the Base Priority value
- *
- * @param uint32_t BasePriority
- * @return none
- *
- * Set the base priority register
- */
-extern void __set_BASEPRI(uint32_t basePri);
-
-/**
- * @brief Return the Priority Mask value
- *
- * @param none
- * @return uint32_t PriMask
- *
- * Return the state of the priority mask bit from the priority mask
- * register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param uint32_t PriMask
- * @return none
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief Return the Fault Mask value
- *
- * @param none
- * @return uint32_t FaultMask
- *
- * Return the content of the fault mask register
- */
-extern uint32_t __get_FAULTMASK(void);
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param uint32_t faultMask value
- * @return none
- *
- * Set the fault mask register
- */
-extern void __set_FAULTMASK(uint32_t faultMask);
-
-/**
- * @brief Return the Control Register value
- *
- * @param none
- * @return uint32_t Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief Set the Control Register value
- *
- * @param uint32_t Control value
- * @return none
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-#else /* (__ARMCC_VERSION >= 400000) */
-
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * @param none
- * @return none
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-#define __CLREX __clrex
-
-/**
- * @brief Return the Base Priority value
- *
- * @param none
- * @return uint32_t BasePriority
- *
- * Return the content of the base priority register
- */
-static __INLINE uint32_t __get_BASEPRI(void)
-{
- register uint32_t __regBasePri __ASM("basepri");
- return(__regBasePri);
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param uint32_t BasePriority
- * @return none
- *
- * Set the base priority register
- */
-static __INLINE void __set_BASEPRI(uint32_t basePri)
-{
- register uint32_t __regBasePri __ASM("basepri");
- __regBasePri = (basePri & 0x1ff);
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @param none
- * @return uint32_t PriMask
- *
- * Return the state of the priority mask bit from the priority mask
- * register
- */
-static __INLINE uint32_t __get_PRIMASK(void)
-{
- register uint32_t __regPriMask __ASM("primask");
- return(__regPriMask);
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param uint32_t PriMask
- * @return none
- *
- * Set the priority mask bit in the priority mask register
- */
-static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
- register uint32_t __regPriMask __ASM("primask");
- __regPriMask = (priMask);
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @param none
- * @return uint32_t FaultMask
- *
- * Return the content of the fault mask register
- */
-static __INLINE uint32_t __get_FAULTMASK(void)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- return(__regFaultMask);
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param uint32_t faultMask value
- * @return none
- *
- * Set the fault mask register
- */
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- __regFaultMask = (faultMask & 1);
-}
-
-/**
- * @brief Return the Control Register value
- *
- * @param none
- * @return uint32_t Control value
- *
- * Return the content of the control register
- */
-static __INLINE uint32_t __get_CONTROL(void)
-{
- register uint32_t __regControl __ASM("control");
- return(__regControl);
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param uint32_t Control value
- * @return none
- *
- * Set the control register
- */
-static __INLINE void __set_CONTROL(uint32_t control)
-{
- register uint32_t __regControl __ASM("control");
- __regControl = control;
-}
-
-#endif /* __ARMCC_VERSION */
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
-#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
-
-static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
-static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
-
-static __INLINE void __WFI() { __ASM ("wfi"); }
-static __INLINE void __WFE() { __ASM ("wfe"); }
-static __INLINE void __SEV() { __ASM ("sev"); }
-static __INLINE void __CLREX() { __ASM ("clrex"); }
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @param none
- * @return uint32_t ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param uint32_t Process Stack Pointer
- * @return none
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @param none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param uint32_t Main Stack Pointer
- * @return none
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param uint16_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief Reverse bit order of value
- *
- * @param uint32_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse bit order of value
- */
-extern uint32_t __RBIT(uint32_t value);
-
-/**
- * @brief LDR Exclusive
- *
- * @param uint8_t* address
- * @return uint8_t value of (*address)
- *
- * Exclusive LDR command
- */
-extern uint8_t __LDREXB(uint8_t *addr);
-
-/**
- * @brief LDR Exclusive
- *
- * @param uint16_t* address
- * @return uint16_t value of (*address)
- *
- * Exclusive LDR command
- */
-extern uint16_t __LDREXH(uint16_t *addr);
-
-/**
- * @brief LDR Exclusive
- *
- * @param uint32_t* address
- * @return uint32_t value of (*address)
- *
- * Exclusive LDR command
- */
-extern uint32_t __LDREXW(uint32_t *addr);
-
-/**
- * @brief STR Exclusive
- *
- * @param uint8_t *address
- * @param uint8_t value to store
- * @return uint32_t successful / failed
- *
- * Exclusive STR command
- */
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
-
-/**
- * @brief STR Exclusive
- *
- * @param uint16_t *address
- * @param uint16_t value to store
- * @return uint32_t successful / failed
- *
- * Exclusive STR command
- */
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
-
-/**
- * @brief STR Exclusive
- *
- * @param uint32_t *address
- * @param uint32_t value to store
- * @return uint32_t successful / failed
- *
- * Exclusive STR command
- */
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
-
-
-/* intrinsic void __set_PRIMASK(); */
-/* intrinsic void __get_PRIMASK(); */
-/* intrinsic void __set_FAULTMASK(); */
-/* intrinsic void __get_FAULTMASK(); */
-/* intrinsic uint32_t __REV(uint32_t value); */
-/* intrinsic uint32_t __REVSH(uint32_t value); */
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
-/* intrinsic unsigned long __LDREX(unsigned long *); */
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-static __INLINE void __NOP() { __ASM volatile ("nop"); }
-static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
-static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
-
-static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
-static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
-
-static __INLINE void __WFI() { __ASM volatile ("wfi"); }
-static __INLINE void __WFE() { __ASM volatile ("wfe"); }
-static __INLINE void __SEV() { __ASM volatile ("sev"); }
-static __INLINE void __ISB(arg) { __ASM volatile ("isb"); }
-static __INLINE void __DSB(arg) { __ASM volatile ("dsb"); }
-static __INLINE void __DMB(arg) { __ASM volatile ("dmb"); }
-static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @param none
- * @return uint32_t ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param uint32_t Process Stack Pointer
- * @return none
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @param none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param uint32_t Main Stack Pointer
- * @return none
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Return the Base Priority value
- *
- * @param none
- * @return uint32_t BasePriority
- *
- * Return the content of the base priority register
- */
-extern uint32_t __get_BASEPRI(void);
-
-/**
- * @brief Set the Base Priority value
- *
- * @param uint32_t BasePriority
- * @return none
- *
- * Set the base priority register
- */
-extern void __set_BASEPRI(uint32_t basePri);
-
-/**
- * @brief Return the Priority Mask value
- *
- * @param none
- * @return uint32_t PriMask
- *
- * Return the state of the priority mask bit from the priority mask
- * register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param uint32_t PriMask
- * @return none
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief Return the Fault Mask value
- *
- * @param none
- * @return uint32_t FaultMask
- *
- * Return the content of the fault mask register
- */
-extern uint32_t __get_FAULTMASK(void);
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param uint32_t faultMask value
- * @return none
- *
- * Set the fault mask register
- */
-extern void __set_FAULTMASK(uint32_t faultMask);
-
-/**
- * @brief Return the Control Register value
-*
-* @param none
-* @return uint32_t Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief Set the Control Register value
- *
- * @param uint32_t Control value
- * @return none
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-/**
- * @brief Reverse byte order in integer value
- *
- * @param uint32_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in integer value
- */
-extern uint32_t __REV(uint32_t value);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param uint16_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/*
- * Reverse byte order in signed short value with sign extension to integer
- *
- * @param int16_t value to reverse
- * @return int32_t reversed value
- *
- * @brief Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-/**
- * @brief Reverse bit order of value
- *
- * @param uint32_t value to reverse
- * @return uint32_t reversed value
- *
- * Reverse bit order of value
- */
-extern uint32_t __RBIT(uint32_t value);
-
-/**
- * @brief LDR Exclusive
- *
- * @param uint8_t* address
- * @return uint8_t value of (*address)
- *
- * Exclusive LDR command
- */
-extern uint8_t __LDREXB(uint8_t *addr);
-
-/**
- * @brief LDR Exclusive
- *
- * @param uint16_t* address
- * @return uint16_t value of (*address)
- *
- * Exclusive LDR command
- */
-extern uint16_t __LDREXH(uint16_t *addr);
-
-/**
- * @brief LDR Exclusive
- *
- * @param uint32_t* address
- * @return uint32_t value of (*address)
- *
- * Exclusive LDR command
- */
-extern uint32_t __LDREXW(uint32_t *addr);
-
-/**
- * @brief STR Exclusive
- *
- * @param uint8_t *address
- * @param uint8_t value to store
- * @return uint32_t successful / failed
- *
- * Exclusive STR command
- */
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
-
-/**
- * @brief STR Exclusive
- *
- * @param uint16_t *address
- * @param uint16_t value to store
- * @return uint32_t successful / failed
- *
- * Exclusive STR command
- */
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
-
-/**
- * @brief STR Exclusive
- *
- * @param uint32_t *address
- * @param uint32_t value to store
- * @return uint32_t successful / failed
- *
- * Exclusive STR command
- */
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
-
-
-#endif
-
-
-
-/* ########################## NVIC functions #################################### */
-
-/**
- * @brief Set the Priority Grouping in NVIC Interrupt Controller
- *
- * @param uint32_t priority_grouping is priority grouping field
- * @return
- *
- * Set the priority grouping field using the required unlock sequence.
- * The parameter priority_grouping is assigned to the field
- * SCB->AIRCR [10:8] PRIGROUP field.
- */
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t priority_grouping)
-{
- uint32_t reg_value=0;
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */
- reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (priority_grouping << 8))); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-/**
- * @brief Enable Interrupt in NVIC Interrupt Controller
- *
- * @param IRQn_Type IRQn specifies the interrupt number
- * @return none
- *
- * Enable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
-}
-
-/**
- * @brief Disable the interrupt line for external interrupt specified
- *
- * @param IRQn_Type IRQn is the positive number of the external interrupt
- * @return none
- *
- * Disable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-/**
- * @brief Read the interrupt pending bit for a device specific interrupt source
- *
- * @param IRQn_Type IRQn is the number of the device specifc interrupt
- * @return IRQn_Type Number of pending interrupt or zero
- *
- * Read the pending register in NVIC and return the number of the
- * specified interrupt if its status is pending, otherwise it returns
- * zero. The interrupt number cannot be a negative value.
- */
-static __INLINE IRQn_Type NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((IRQn_Type) (NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))); /* Return Interrupt bit or 'zero' */
-}
-
-/**
- * @brief Set the pending bit for an external interrupt
- *
- * @param IRQn_Type IRQn is the Number of the interrupt
- * @return none
- *
- * Set the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-/**
- * @brief Clear the pending bit for an external interrupt
- *
- * @param IRQn_Type IRQn is the Number of the interrupt
- * @return none
- *
- * Clear the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-/**
- * @brief Read the active bit for an external interrupt
- *
- * @param IRQn_Type IRQn is the Number of the interrupt
- * @return IRQn_Type Number of pending interrupt or zero
- *
- * Read the active register in NVIC and returns the number of the
- * specified interrupt if its status is active, otherwise it
- * returns zero. The interrupt number cannot be a negative value.
- */
-static __INLINE IRQn_Type NVIC_GetActive(IRQn_Type IRQn)
-{
- return((IRQn_Type)(NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))); /* Return Interruptnumber or 'zero' */
-}
-
-/**
- * @brief Set the priority for an interrupt
- *
- * @param IRQn_Type IRQn is the Number of the interrupt
- * @param priority is the priority for the interrupt
- * @return none
- *
- * Set the priority for the specified interrupt. The interrupt
- * number can be positive to specify an external (device specific)
- * interrupt, or negative to specify an internal (core) interrupt. \n
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, int32_t priority)
-{
- if(IRQn < 0) {
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
- else {
- //NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
- NVIC->IP[(uint32_t)(IRQn)] = (priority & 0xff); } /* set Priority for device specific Interrupts */
-}
-
-/**
- * @brief Read the priority for an interrupt
- *
- * @param IRQn_Type IRQn is the Number of the interrupt
- * @return priority is the priority for the interrupt
- *
- * Read the priority for the specified interrupt. The interrupt
- * number can be positive to specify an external (device specific)
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * The returned priority value is automatically aligned to the implemented
- * priority bits of the microcontroller.
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if(IRQn < 0) {
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
- else {
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
-}
-
-
-
-/* ################################## SysTick function ############################################ */
-
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
-
-/* SysTick constants */
-#define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */
-#define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */
-#define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */
-#define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */
-
-/**
- * @brief Initialize and start the SysTick counter and its interrupt.
- *
- * @param uint32_t ticks is the number of ticks between two interrupts
- * @return none
- *
- * Initialise the system tick timer and its interrupt and start the
- * system tick timer / counter in free running mode to generate
- * periodical interrupts.
- */
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */
-
- SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
- SysTick->VAL = (0x00); /* Load the SysTick Counter Value */
- SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<DEMCR & CoreDebug_DEMCR_TRCENA) &&
- (ITM->TCR & ITM_TCR_ITMENA) &&
- (ITM->TER & (1UL << 0)) )
- {
- while (ITM->PORT[0].u32 == 0);
- ITM->PORT[0].u8 = (uint8_t) ch;
- }
- return (ch);
-}
-
-#endif
-
-/*lint -restore */
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/acc/acc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/acc/acc.c
deleted file mode 100644
index 2c3e0080..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/acc/acc.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/** \addtogroup adc_module Working with ACC
- * The ACC driver provides the interface to configure and use the ACC peripheral.\n
- *
- * It converts the analog input to digital format. The converted result could be 12bit
- * or 10bit. The ACC supports up to 16 analog lines.
- *
- * To Enable a ACC conversion,the user has to follow these few steps:
- *
- *
Select an appropriate reference voltage on ADVREF
- *
Configure the ACC according to its requirements and special needs,which could be
- broken down into several parts:
- * -# Select the resolution by setting or clearing ACC_MR_LOWRES bit in ACC_MR (Mode Register)
- * -# Set ACC clock by setting ACC_MR_PRESCAL bits in ACC_MR, the clock is caculated with
- ACCClock = MCK / ( (PRESCAL+1) * 2 )
- * -# Set Startup Time,Tracking Clock cycles and Transfer Clock respeticively in ACC_MR.
-
- *
Start conversion by setting ACC_CR_START in ACC_CR.
- *
- *
- * For more accurate information, please look at the ACC section of the
- * Datasheet.
- *
- * Related files :\n
- * \ref adc.c\n
- * \ref adc.h\n
-*/
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include
-#include
-#include
-
-
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief Initialize the ACC controller
- * \param pAcc Pointer to an Acc instance.
- * \param idAcc ACC identifier
- * \param selplus input connected to inp, 0~7
- * \param selminus input connected to inm,0~7
- * \param ac_en Analog comprator enabled/disabled,use pattern
- * \param edge CF flag triggering mode,use pattern
- * \param invert INVert comparator output,use pattern defined in the device header
- file
-*/
-void ACC_Configure(Acc *pAcc,
- uint8_t idAcc,
- uint8_t selplus,
- uint8_t selminus,
- uint16_t ac_en,
- uint16_t edge,
- uint16_t invert)
-{
-
- /* Enable peripheral clock*/
- PMC->PMC_PCER1 = 1 << (idAcc-32);
-
- /* Reset the controller */
- pAcc->ACC_CR |= ACC_CR_SWRST;
-
- /* Write to the MR register */
- ACC_CfgModeReg( pAcc,
- ( selplus & ACC_MR_SELPLUS)
- | (( selminus<<4) & ACC_MR_SELMINUS)
- | ( ac_en & ACC_MR_ACEN)
- | ( edge & ACC_MR_EDGETYP)
- | ( invert & ACC_MR_INV) );
- //pAcc->ACC_MR |= (ACC_MR_SELFS_OUTPUT|ACC_MR_FE_EN);
-
- pAcc->ACC_ACR = 0x7;
-
- while(pAcc->ACC_ISR & (uint32_t)ACC_ISR_MASK);
-}
-
-
-/**
- * Return the Channel Converted Data
- * \param pAdc Pointer to an Adc instance.
- * \param channel channel to get converted value
- * \return Channel converted data of the specified channel
- */
-void ACC_SetComparisionPair(Acc *pAcc, uint8_t selplus,uint8_t selminus)
-{
-
- uint32_t temp;
-
- ASSERT(selplus < 8 && selminus < 8,"The assigned channel number is invalid!");
-
- temp = pAcc->ACC_MR;
-
- pAcc->ACC_MR = temp & (~ACC_MR_SELMINUS)&(~ACC_MR_SELPLUS);
-
- pAcc->ACC_MR |= ((selplus & ACC_MR_SELPLUS)|((selminus<<4) & ACC_MR_SELMINUS));
-
-}
-/**
- * Return Comparison Result
- * \param pAcc Pointer to an Acc instance.
- * \param status value of ACC_ISR
- */
-uint8_t ACC_GetComparisionResult(Acc *pAcc,uint32_t status)
-{
- uint32_t temp = pAcc->ACC_MR;
- if( (temp & ACC_MR_INV)== ACC_MR_INV)
- {
-
- if( status & ACC_ISR_SCO)
- {
- return 0; /* inn>inp*/
- }
- else return 1;/* inp>inn*/
-
- }
- else
- {
-
- if( status & ACC_ISR_SCO)
- {
- return 1; /* inp>inn*/
- }
- else return 0;/* inn>inp*/
- }
-
-}
-
-
-
-
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/acc/acc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/acc/acc.h
deleted file mode 100644
index 284d8d44..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/acc/acc.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \unit
- *
- * !Purpose
- *
- * Interface for configuration the Analog-to-Digital Converter (ACC) peripheral.
- *
- * !Usage
- *
- * -# Configurate the pins for ACC
- * -# Initialize the ACC with ACC_Initialize().
- * -# Select the active channel using ACC_EnableChannel()
- * -# Start the conversion with ACC_StartConversion()
- * -# Wait the end of the conversion by polling status with ACC_GetStatus()
- * -# Finally, get the converted data using ACC_GetConvertedData()
- *
-*/
-#ifndef ACC_H
-#define ACC_H
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-#include
-
-/*------------------------------------------------------------------------------
- * Definitions
- *------------------------------------------------------------------------------*/
-#define ACC_SELPLUS_AD12B0 0
-#define ACC_SELPLUS_AD12B1 1
-#define ACC_SELPLUS_AD12B2 2
-#define ACC_SELPLUS_AD12B3 3
-#define ACC_SELPLUS_AD12B4 4
-#define ACC_SELPLUS_AD12B5 5
-#define ACC_SELPLUS_AD12B6 6
-#define ACC_SELPLUS_AD12B7 7
-#define ACC_SELMINUS_TS 0
-#define ACC_SELMINUS_ADVREF 1
-#define ACC_SELMINUS_DAC0 2
-#define ACC_SELMINUS_DAC1 3
-#define ACC_SELMINUS_AD12B0 4
-#define ACC_SELMINUS_AD12B1 5
-#define ACC_SELMINUS_AD12B2 6
-#define ACC_SELMINUS_AD12B3 7
-
-
-/*------------------------------------------------------------------------------
- * Macros function of register access
- *------------------------------------------------------------------------------*/
-#define ACC_CfgModeReg(pAcc, mode) { \
- (pAcc)->ACC_MR = (mode);\
- }
-
-#define ACC_GetModeReg(pAcc) ((pAcc)->ACC_MR)
-
-#define ACC_StartConversion(pAcc) ((pAcc)->ACC_CR = ACC_CR_START)
-
-#define ACC_SoftReset(pAcc) ((pAcc)->ACC_CR = ACC_CR_SWRST)
-
-#define ACC_EnableChannel(pAcc, channel) {\
- ASSERT(channel < 16, "ACC Channel not exist");\
- (pAcc)->ACC_CHER = (1 << (channel));\
- }
-
-#define ACC_DisableChannel (pAcc, channel) {\
- ASSERT((channel) < 16, "ACC Channel not exist");\
- (pAcc)->ACC_CHDR = (1 << (channel));\
- }
-
-#define ACC_EnableIt(pAcc, mode) {\
- ASSERT(((mode)&0xFFF00000)== 0, "ACC bad interrupt IER");\
- (pAcc)->ACC_IER = (mode);\
- }
-
-#define ACC_DisableIt(pAcc, mode) {\
- ASSERT(((mode)&0xFFF00000)== 0, "ACC bad interrupt IDR");\
- (pAcc)->ACC_IDR = (mode);\
- }
-
-#define ACC_EnableDataReadyIt(pAcc) ((pAcc)->ACC_IER = AT91C_ACC_DRDY)
-
-#define ACC_GetStatus(pAcc) ((pAcc)->ACC_ISR)
-
-#define ACC_GetChannelStatus(pAcc) ((pAcc)->ACC_CHSR)
-
-#define ACC_GetInterruptMaskStatus(pAcc) ((pAcc)->ACC_IMR)
-
-#define ACC_GetLastConvertedData(pAcc) ((pAcc)->ACC_LCDR)
-
-#define ACC_CfgAnalogCtrlReg(pAcc,mode) {\
- ASSERT(((mode) & 0xFFFCFF3C)==0, "ACC bad analog control config");\
- (pAcc)->ACC_ACR = (mode);\
- }
-
-#define ACC_CfgExtModeReg(pAcc, extmode) {\
- ASSERT(((extmode) & 0xFF00FFFE)==0, "ACC bad extended mode config");\
- (pAcc)->ACC_EMR = (extmode);\
- }
-
-#define ACC_GetAnalogCtrlReg(pAcc) ((pAcc)->ACC_ACR)
-
-/*------------------------------------------------------------------------------
- * Exported functions
- *------------------------------------------------------------------------------*/
-void ACC_Configure(Acc *pAcc,
- uint8_t idAcc,
- uint8_t selplus,
- uint8_t selminus,
- uint16_t ac_en,
- uint16_t edge,
- uint16_t invert);
-
-extern uint8_t ACC_GetComparisionResult(Acc *pAcc,uint32_t status);
-
-#endif //#ifndef ACC_H
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/adc/adc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/adc/adc.c
deleted file mode 100644
index 241a8d93..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/adc/adc.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/** \addtogroup adc_module Working with ADC
- * The ADC driver provides the interface to configure and use the ADC peripheral.
- * \n
- *
- * It converts the analog input to digital format. The converted result could be
- * 12bit or 10bit. The ADC supports up to 16 analog lines.
- *
- * To Enable a ADC conversion,the user has to follow these few steps:
- *
- *
Select an appropriate reference voltage on ADVREF
- *
Configure the ADC according to its requirements and special needs,which
- * could be broken down into several parts:
- * -# Select the resolution by setting or clearing ADC_MR_LOWRES bit in
- * ADC_MR (Mode Register)
- * -# Set ADC clock by setting ADC_MR_PRESCAL bits in ADC_MR, the clock is
- * calculated with ADCClock = MCK / ( (PRESCAL+1) * 2 )
- * -# Set Startup Time,Tracking Clock cycles and Transfer Clock respectively
- * in ADC_MR.
-
- *
Start conversion by setting ADC_CR_START in ADC_CR.
- *
- *
- * For more accurate information, please look at the ADC section of the
- * Datasheet.
- *
- * Related files :\n
- * \ref adc.c\n
- * \ref adc.h\n
-*/
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include
-#include
-#include
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief Initialize the ADC controller
- * \param pAdc Pointer to an Adc instance.
- * \param trgEn trigger mode, software or Hardware
- * \param trgSel hardware trigger selection
- * \param sleepMode sleep mode selection
- * \param resolution resolution selection 10 bits or 12 bits
- * \param mckClock value of MCK in Hz
- * \param adcClock value of the ADC clock in Hz
- * \param startupTime value of the start up time (in ADCClock) (see datasheet)
- * \param trackingt Tracking Time (in ADCClock cycle)
-*/
-void ADC_Initialize(Adc *pAdc, uint8_t idAdc, uint8_t trgEn, uint8_t trgSel,
- uint8_t sleepMode, uint8_t resolution, uint32_t mckClock,
- uint32_t adcClock, uint32_t startup, uint32_t tracking) {
- uint32_t prescal;
- prescal = (mckClock / (2*adcClock)) - 1;
-
- ASSERT( (prescal<0x3F), "ADC Bad PRESCAL\n\r");
-
- TRACE_DEBUG("adcClock:%lu MasterClock:%lu\n\r", (mckClock/((prescal+1)*2)),
- mckClock);
-
- if( adcClock != (mckClock/((prescal+1)*2)) ) {
- TRACE_WARNING("User and calculated adcClocks are different : "
- "user=%lu calc=%lu\n\r",
- adcClock, (mckClock/((prescal+1)*2)));
- }
-
- /* Enable peripheral clock*/
- PMC->PMC_PCER0 = 1 << idAdc;
-
- /* Reset the controller */
- ADC_SoftReset(pAdc);
-
- /* Write to the MR register */
- ADC_CfgModeReg( pAdc,
- ( trgEn & ADC_MR_TRGEN)
- | ( trgSel & ADC_MR_TRGSEL)
- | ( resolution & ADC_MR_LOWRES)
- | ( sleepMode & ADC_MR_SLEEP)
- | ( (prescal<<8) & ADC_MR_PRESCAL)
- | ( (startup<<16) & ADC_MR_STARTUP)
- | ( (tracking<<24) & ADC_MR_TRACKTIM) );
-}
-
-/**
- * Return the Channel Converted Data
- * \param pAdc Pointer to an Adc instance.
- * \param channel channel to get converted value
- */
-uint32_t ADC_GetConvertedData(Adc *pAdc, uint32_t channel) {
- uint32_t data=0;
-
- if (15 >= channel) {
- data = *((RoReg *)((uint32_t)&(pAdc->ADC_CDR0)+ channel*4));
- }
- return data;
-}
-/**
- * Set compare channel
- * \param pAdc Pointer to an Adc instance.
- * \param channel channel number to be set,16 for all channels
- */
-void ADC_SetCompareChannel(Adc *pAdc, uint8_t channel) {
- ASSERT(channel<=16, "Invalid channel number");
- if (channel < 16) {
- pAdc->ADC_EMR &= ~(ADC_EMR_CMPALL);
- pAdc->ADC_EMR &= ~(ADC_EMR_CMPSEL);
- pAdc->ADC_EMR |= (channel << 4);
- } else {
- pAdc->ADC_EMR |= ADC_EMR_CMPALL;
- }
-}
-/**
- * Set compare mode
- * \param pAdc Pointer to an Adc instance.
- * \param mode compare mode
- */
-void ADC_SetCompareMode(Adc *pAdc, uint8_t mode) {
- pAdc->ADC_EMR &= ~(ADC_EMR_CMPMODE);
- pAdc->ADC_EMR |= mode;
-}
-/**
- * Set comparsion window,one thereshold each time
- * \param pAdc Pointer to an Adc instance.
- * \param hi_lo Comparison Window
- */
-void ADC_SetComparisonWindow(Adc *pAdc, uint32_t hi_lo) {
- pAdc->ADC_CWR = hi_lo;
-}
-
-/**----------------------------------------------------------------------------
-* Test if ADC Interrupt is Masked
-* \param pAdc Pointer to an Adc instance.
-* \param flag flag to be tested
-* \return 1 if interrupt is masked, otherwise 0
-*/
-uint32_t ADC_IsInterruptMasked(Adc *pAdc, uint32_t flag) {
- return (ADC_GetInterruptMaskStatus(pAdc) & flag);
-}
-
-/**----------------------------------------------------------------------------
-* Test if ADC Status is Set
-* \param pAdc Pointer to an Adc instance.
-* \param flag flag to be tested
-* \return 1 if the staus is set; 0 otherwise
-*/
-uint32_t ADC_IsStatusSet(Adc *pAdc, uint32_t flag) {
- return (ADC_GetStatus(pAdc) & flag);
-}
-
-/**----------------------------------------------------------------------------
-* Test if ADC channel interrupt Status is Set
-* \param adc_sr Value of SR register
-* \param channel Channel to be tested
-* \return 1 if interrupt status is set, otherwise 0
-*/
-uint8_t ADC_IsChannelInterruptStatusSet(uint32_t adc_sr, uint32_t channel) {
- uint8_t status;
-
- if((adc_sr & (1<ADC_RCR == 0) && (pADC->ADC_RNCR == 0)) {
-
- pADC->ADC_RPR = (uint32_t) pBuffer;
- pADC->ADC_RCR = size;
- pADC->ADC_PTCR = ADC_PTCR_RXTEN;
-
- return 1;
- }
- /* Check if the second PDC bank is free*/
- else if (pADC->ADC_RNCR == 0) {
-
- pADC->ADC_RNPR = (uint32_t) pBuffer;
- pADC->ADC_RNCR = size;
-
- return 1;
- } else {
-
- return 0;
- }
-
-}
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/adc/adc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/adc/adc.h
deleted file mode 100644
index 702143f0..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/adc/adc.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \unit
- *
- * !Purpose
- *
- * Interface for configuration the Analog-to-Digital Converter (ADC) peripheral.
- *
- * !Usage
- *
- * -# Configurate the pins for ADC
- * -# Initialize the ADC with ADC_Initialize().
- * -# Select the active channel using ADC_EnableChannel()
- * -# Start the conversion with ADC_StartConversion()
- * -# Wait the end of the conversion by polling status with ADC_GetStatus()
- * -# Finally, get the converted data using ADC_GetConvertedData()
- *
-*/
-#ifndef ADC_H
-#define ADC_H
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-#include
-
-/*------------------------------------------------------------------------------
- * Definitions
- *------------------------------------------------------------------------------*/
-#define ADC_CHANNEL_0 0
-#define ADC_CHANNEL_1 1
-#define ADC_CHANNEL_2 2
-#define ADC_CHANNEL_3 3
-#define ADC_CHANNEL_4 4
-#define ADC_CHANNEL_5 5
-#define ADC_CHANNEL_6 6
-#define ADC_CHANNEL_7 7
-#define ADC_CHANNEL_8 8
-#define ADC_CHANNEL_9 9
-#define ADC_CHANNEL_10 10
-#define ADC_CHANNEL_11 11
-#define ADC_CHANNEL_12 12
-#define ADC_CHANNEL_13 13
-#define ADC_CHANNEL_14 14
-#define ADC_CHANNEL_15 15
-
-/*------------------------------------------------------------------------------
- * Macros function of register access
- *------------------------------------------------------------------------------*/
-#define ADC_CfgModeReg(pAdc, mode) { \
- ASSERT(((mode)&0xF00000C0)== 0, "ADC Bad configuration ADC MR");\
- (pAdc)->ADC_MR = (mode);\
- }
-
-#define ADC_GetModeReg(pAdc) ((pAdc)->ADC_MR)
-
-#define ADC_StartConversion(pAdc) ((pAdc)->ADC_CR = ADC_CR_START)
-
-#define ADC_SoftReset(pAdc) ((pAdc)->ADC_CR = ADC_CR_SWRST)
-
-#define ADC_EnableChannel(pAdc, channel) {\
- ASSERT(channel < 16, "ADC Channel not exist");\
- (pAdc)->ADC_CHER = (1 << (channel));\
- }
-
-#define ADC_DisableChannel (pAdc, channel) {\
- ASSERT((channel) < 16, "ADC Channel not exist");\
- (pAdc)->ADC_CHDR = (1 << (channel));\
- }
-
-#define ADC_EnableIt(pAdc, mode) {\
- (pAdc)->ADC_IER = (mode);\
- }
-
-#define ADC_DisableIt(pAdc, mode) {\
- (pAdc)->ADC_IDR = (mode);\
- }
-
-#define ADC_EnbaleTS(pAdc,mode) {\
- (pAdc)->ADC_ACR |= mode;\
- }
-
-#define ADC_EnableDataReadyIt(pAdc) ((pAdc)->ADC_IER = AT91C_ADC_DRDY)
-
-#define ADC_GetStatus(pAdc) ((pAdc)->ADC_ISR)
-
-#define ADC_GetCompareMode(pAdc) (((pAdc)->ADC_EMR)& (ADC_EMR_CMPMODE))
-
-#define ADC_GetChannelStatus(pAdc) ((pAdc)->ADC_CHSR)
-
-#define ADC_GetInterruptMaskStatus(pAdc) ((pAdc)->ADC_IMR)
-
-#define ADC_GetLastConvertedData(pAdc) ((pAdc)->ADC_LCDR)
-
-#define ADC_CfgAnalogCtrlReg(pAdc,mode) {\
- ASSERT(((mode) & 0xFFFCFF3C)==0, "ADC bad analog control config");\
- (pAdc)->ADC_ACR = (mode);\
- }
-
-#define ADC_CfgExtModeReg(pAdc, extmode) {\
- ASSERT(((extmode) & 0xFF00FFFE)==0, "ADC bad extended mode config");\
- (pAdc)->ADC_EMR = (extmode);\
- }
-
-#define ADC_GetAnalogCtrlReg(pAdc) ((pAdc)->ADC_ACR)
-
-/*------------------------------------------------------------------------------
- * Exported functions
- *------------------------------------------------------------------------------*/
-extern void ADC_Initialize (Adc *pAdc,
- uint8_t idAdc,
- uint8_t trgEn,
- uint8_t trgSel,
- uint8_t sleepMode,
- uint8_t resolution,
- uint32_t mckClock,
- uint32_t adcClock,
- uint32_t startupTime,
- uint32_t sampleAndHoldTime);
-extern uint32_t ADC_GetConvertedData(Adc *pAdc, uint32_t channel);
-extern void ADC_SetCompareChannel(Adc *pAdc, uint8_t channel);
-extern void ADC_SetCompareMode(Adc *pAdc, uint8_t mode);
-extern void ADC_SetComparisonWindow(Adc *pAdc, uint32_t hi_lo);
-extern uint32_t ADC_IsInterruptMasked(Adc *pAdc, uint32_t flag);
-extern uint32_t ADC_IsStatusSet(Adc *pAdc, uint32_t flag);
-extern uint8_t ADC_IsChannelInterruptStatusSet(uint32_t adc_sr,
- uint32_t channel);
-extern int8_t ADC_ReadBuffer(Adc *pADC,int16_t *pBuffer,int32_t size);
-
-#endif //#ifndef ADC_H
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/async/async.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/async/async.c
deleted file mode 100644
index 65ba73a6..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/async/async.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- *
- * Provide a routine for asynchronos transfer.
- *
- */
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-#include
-#include "async.h"
-
-/*----------------------------------------------------------------------------
- * Global functions
- *----------------------------------------------------------------------------*/
- /**
- * \brief Returns 1 if the given transfer has ended; otherwise returns 0.
- * \param pAsync Pointer to an Async instance.
- */
-uint8_t ASYNC_IsFinished(Async *pAsync)
-{
- return (pAsync->status != ASYNC_STATUS_PENDING);
-}
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/async/async.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/async/async.h
deleted file mode 100644
index af03d0e2..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/async/async.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
- /**
- * \file
- *
- * Provide a routine for asynchronos transfer.
- *
- */
-
-#ifndef ASYNC_H
-#define ASYNC_H
-
-
-/*----------------------------------------------------------------------------
- * Definition
- *----------------------------------------------------------------------------*/
-/** Transfer is still pending.*/
-#define ASYNC_STATUS_PENDING 0xFF
-
-/*----------------------------------------------------------------------------
- * Type
- *----------------------------------------------------------------------------*/
-/** Asynchronous transfer descriptor. */
-typedef struct _Async {
-
- /** Asynchronous transfer status.*/
- volatile uint8_t status;
- /** Callback function to invoke when transfer completes or fails.*/
- void *callback;
- /** Driver storage area; do not use.*/
- uint32_t pStorage[4];
-} Async;
-
-/*----------------------------------------------------------------------------
- * Global functions
- *----------------------------------------------------------------------------*/
-extern uint8_t ASYNC_IsFinished(Async *pAsync);
-
-#endif //#ifndef ASYNC_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/crccu/crccu.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/crccu/crccu.c
deleted file mode 100644
index 0e4acec8..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/crccu/crccu.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/** \addtogroup crccu_module Working with CRCCU
- * The CRCCU driver provides the interface to configure and use the CRCCU
- * peripheral.
- *
- * It performs a CRC computation on a Memory Area. CRC computation is performed
- * from the LSB to MSB bit. Three different polynomials are available:
- * CCIT802.3, CASTAGNOLI and CCIT16.
- *
- * To computes CRC of a buffer, the user has to follow these few steps:
- *
- *
Reset initial CRC by setting RESET bit in CRCCU_CRC_CR,
- *
Configure CRC descriptor and working mode,
- *
Start to compute CRC by setting DMAEN in CRCCU_DMA_EN,
- *
Get CRC value in CRCCU_CRC_SR.
- *
- *
- * For more accurate information, please look at the CRCCU section of the
- * Datasheet.
- *
- * Related files :\n
- * \ref crccu.c\n
- * \ref crccu.h.\n
-*/
-/*@{*/
-/*@}*/
-
-/**
- * \file
- *
- * Implementation of Cyclic Redundancy Check Calculation Unit (CRCCU).
- *
- */
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include
-#include "crccu.h"
-#include
-
-/*----------------------------------------------------------------------------
- * Definitions
- *----------------------------------------------------------------------------*/
-#define CRCCU_TIMEOUT 0xFFFFFFFF
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-/**
- * \brief Reset initial CRC to 0xFFFFFFFF.
- */
-void CRCCU_ResetCrcValue(void)
-{
- Crccu *pCrccu = CRCCU;
-
- pCrccu->CRCCU_CR = CRCCU_CR_RESET;
-}
-
-/**
- * \brief Configure the CRCCU.
- *
- * \param dscrAddr CRC decscriptor address.
- * \param mode CRC work mode
- */
-void CRCCU_Configure(uint32_t dscrAddr, uint32_t mode)
-{
- Crccu *pCrccu = CRCCU;
-
- pCrccu->CRCCU_DSCR = dscrAddr;
- pCrccu->CRCCU_MR = mode;
-}
-
-/**
- * \brief Start to compute the CRC of a buffer.
- *
- * \return The CRC of the buffer.
- */
-uint32_t CRCCU_ComputeCrc(void)
-{
- Crccu *pCrccu = CRCCU;
- uint32_t timeout = 0;
-
- pCrccu->CRCCU_DMA_EN = CRCCU_DMA_EN_DMAEN;
- while (((pCrccu->CRCCU_DMA_SR & CRCCU_DMA_SR_DMASR) == CRCCU_DMA_SR_DMASR)
- && (timeout++ < CRCCU_TIMEOUT));
-
- return (pCrccu->CRCCU_SR);
-}
-
-/**
- * \brief Compare the CRC of a buffer is match to reference CRC.
- *
- * \return if 0 CRC is match, else dismatch.
- */
-uint32_t CRCCU_CompareCrc(void)
-{
- Crccu *pCrccu = CRCCU;
-
- if ((pCrccu->CRCCU_ISR & CRCCU_ISR_ERRISR) == CRCCU_ISR_ERRISR) {
- return 1;
- } else {
- return 0;
- }
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/crccu/crccu.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/crccu/crccu.h
deleted file mode 100644
index 7298f610..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/crccu/crccu.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- *
- * Interface for Cyclic Redundancy Check Calculation Unit (CRCCU).
- */
-
-#ifndef CRCCU_H
-#define CRCCU_H
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include
-#include
-
-/*----------------------------------------------------------------------------
- * Types
- *----------------------------------------------------------------------------*/
-
-typedef struct {
- unsigned int TR_ADDR;
- unsigned int TR_CTRL;
- unsigned int reserved[2];
- unsigned int TR_CRC;
-} CrcDscr;
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-void CRCCU_ResetCrcValue(void);
-void CRCCU_Configure(uint32_t dscrAddr, uint32_t mode);
-uint32_t CRCCU_ComputeCrc(void);
-uint32_t CRCCU_CompareCrc(void);
-
-#endif /* #ifndef CRCCU_H */
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/dacc/dacc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/dacc/dacc.c
deleted file mode 100644
index f576aa49..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/dacc/dacc.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/** \addtogroup dacc_module Working with DACC
- * The DACC driver provides the interface to configure and use the DACC peripheral.\n
- *
- * The DACC(Digital-to-Analog Converter Controller) converts digital code to analog output.
- * The data to be converted are sent in a common register for all channels. It offers up to 2
- * analog outputs.The output voltage ranges from (1/6)ADVREF to (5/6)ADVREF.
- *
- * To Enable a DACC conversion,the user has to follow these few steps:
- *
- *
Select an appropriate reference voltage on ADVREF
- *
Configure the DACC according to its requirements and special needs,which could be
- broken down into several parts:
- * -# Enable DACC in free running mode by clearing TRGEN in DACC_MR;
- * -# Configure Startup Time and Refresh Period through setting STARTUP and REFRESH fields
- * in DACC_MR; The refresh mechanism is used to protect the output analog value from
- * decreasing.
- * -# Enable channels and write digital code to DACC_CDR,in free running mode, the conversion
- * is started right after at least one channel is enabled and data is written .
-
- *
- *
- * For more accurate information, please look at the DACC section of the
- * Datasheet.
- *
- * Related files :\n
- * \ref DACC.c\n
- * \ref DACC.h\n
-*/
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include
-#include
-#include
-
-
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief Initialize the DACC controller
- * \param pDACC Pointer to an DACC instance.
- * \param idDACC identifier of DAC peripheral
- * \param trgEn trigger mode, free running mode or external Hardware trigger
- * \param word transfer size,word or half word
- * \param trgSel hardware trigger selection
- * \param sleepMode sleep mode selection
- * \param mck value of MCK in Hz
- * \param refresh refresh period
- * \param user_sel user channel selection ,0 or 1
- * \param startup value of the start up time (in DACCClock) (see datasheet)
-*/
-void DACC_Initialize (Dacc *pDACC,
- uint8_t idDACC,
- uint8_t trgEn,
- uint8_t trgSel,
- uint8_t word,
- uint8_t sleepMode,
- uint32_t mck,
- uint8_t refresh,/*refresh period*/
- uint8_t user_sel,/*user channel selection*/
- uint32_t startup
- )
-{
- ASSERT(1024*refresh*1000/(mck/2)<20,"Refresh preriod is too big!");
-
-
- /* Enable peripheral clock*/
- PMC->PMC_PCER0 = 1 << idDACC;
-
- /* Reset the controller */
- DACC_SoftReset(pDACC);
-
- /* Write to the MR register */
- DACC_CfgModeReg( pDACC,
- ( trgEn & DACC_MR_TRGEN)
- | ( trgSel & DACC_MR_TRGSEL)
- | ( word & DACC_MR_WORD)
- | ( sleepMode & DACC_MR_SLEEP)
- | ( (refresh<<8) & DACC_MR_REFRESH)
- | ( (user_sel<<16)& DACC_MR_USER_SEL)
- | ( (startup<<24) & DACC_MR_STARTUP));
-}
-
-
-/**
- * Set the Conversion Data
- * \param pDACC Pointer to an Dacc instance.
- * \param channel channel to get converted value
- * \return Channel converted data of the specified channel
- */
-void DACC_SetConversionData(Dacc *pDACC, uint32_t data)
-{
- uint32_t mr = pDACC->DACC_MR;
-
- if(mr & DACC_MR_WORD)
- {
- pDACC->DACC_CDR = data;
- }
- else
- {
- pDACC->DACC_CDR = (data&0xFFFF);
- }
-}
-
-
-/**
- * \brief Write converted data through PDC channel
- * \param pDACC the pointer of DACC peripheral
- * \param pBuffer the destination buffer
- * \param size the size of the buffer
-*/
-int8_t DACC_WriteBuffer(Dacc *pDACC,int16_t *pBuffer,int32_t size)
-{
-
- /* Check if the first PDC bank is free*/
- if ((pDACC->DACC_TCR == 0) && (pDACC->DACC_TNCR == 0)) {
-
- pDACC->DACC_TPR = (uint32_t) pBuffer;
- pDACC->DACC_TCR = size;
- pDACC->DACC_PTCR = DACC_PTCR_RXTEN;
-
- return 1;
- }
- /* Check if the second PDC bank is free*/
- else if (pDACC->DACC_TNCR == 0) {
-
- pDACC->DACC_TNPR = (uint32_t) pBuffer;
- pDACC->DACC_TNCR = size;
-
- return 1;
- }
- else {
-
- return 0;
- }
-
-}
-
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/dacc/dacc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/dacc/dacc.h
deleted file mode 100644
index c2aebada..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/dacc/dacc.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \unit
- *
- * !Purpose
- *
- * Interface for configuration the Analog-to-Digital Converter (DACC) peripheral.
- *
- * !Usage
- *
- * -# Configurate the pins for DACC
- * -# Initialize the DACC with DACC_Initialize().
- * -# Select the active channel using DACC_EnableChannel()
- * -# Start the conversion with DACC_StartConversion()
- * -# Wait the end of the conversion by polling status with DACC_GetStatus()
- * -# Finally, get the converted data using DACC_GetConvertedData()
- *
-*/
-#ifndef DACC_H
-#define DACC_H
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-#include
-
-/*------------------------------------------------------------------------------
- * Definitions
- *------------------------------------------------------------------------------*/
-#define DACC_CHANNEL_0 0
-#define DACC_CHANNEL_1 1
-
-
-/*------------------------------------------------------------------------------
- * Macros function of register access
- *------------------------------------------------------------------------------*/
-#define DACC_CfgModeReg(pDACC, mode) { \
- (pDACC)->DACC_MR = (mode);\
- }
-
-#define DACC_GetModeReg(pDACC) ((pDACC)->DACC_MR)
-
-#define DACC_StartConversion(pDACC) ((pDACC)->DACC_CR = DACC_CR_START)
-
-#define DACC_SoftReset(pDACC) ((pDACC)->DACC_CR = DACC_CR_SWRST)
-
-#define DACC_EnableChannel(pDACC, channel) {\
- (pDACC)->DACC_CHER = (1 << (channel));\
- }
-
-#define DACC_DisableChannel (pDACC, channel) {\
- (pDACC)->DACC_CHDR = (1 << (channel));\
- }
-
-#define DACC_EnableIt(pDACC, mode) {\
- ASSERT(((mode)&0xFFF00000)== 0, "DACC bad interrupt IER");\
- (pDACC)->DACC_IER = (mode);\
- }
-
-#define DACC_DisableIt(pDACC, mode) {\
- ASSERT(((mode)&0xFFF00000)== 0, "DACC bad interrupt IDR");\
- (pDACC)->DACC_IDR = (mode);\
- }
-
-#define DACC_EnableDataReadyIt(pDACC) ((pDACC)->DACC_IER = AT91C_DACC_DRDY)
-
-#define DACC_GetStatus(pDACC) ((pDACC)->DACC_ISR)
-
-#define DACC_GetChannelStatus(pDACC) ((pDACC)->DACC_CHSR)
-
-#define DACC_GetInterruptMaskStatus(pDACC) ((pDACC)->DACC_IMR)
-
-#define DACC_GetLastConvertedData(pDACC) ((pDACC)->DACC_LCDR)
-
-#define DACC_CfgAnalogCtrlReg(pDACC,mode) {\
- ASSERT(((mode) & 0xFFFCFF3C)==0, "DACC bad analog control config");\
- (pDACC)->DACC_ACR = (mode);\
- }
-
-#define DACC_CfgExtModeReg(pDACC, extmode) {\
- ASSERT(((extmode) & 0xFF00FFFE)==0, "DACC bad extended mode config");\
- (pDACC)->DACC_EMR = (extmode);\
- }
-
-#define DACC_GetAnalogCtrlReg(pDACC) ((pDACC)->DACC_ACR)
-
-/*------------------------------------------------------------------------------
- * Exported functions
- *------------------------------------------------------------------------------*/
-extern void DACC_Initialize (Dacc *pDACC,
- uint8_t idDACC,
- uint8_t trgEn,
- uint8_t trgSel,
- uint8_t word,
- uint8_t sleepMode,
- uint32_t mck,
- uint8_t refresh,/*refresh period*/
- uint8_t user_sel,/*user channel selection*/
- uint32_t startup
- );
-
-
-extern void DACC_SetConversionData(Dacc *pDACC, uint32_t data);
-
-#endif //#ifndef DACC_H
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/efc/efc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/efc/efc.c
deleted file mode 100644
index 56ace4b0..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/efc/efc.c
+++ /dev/null
@@ -1,286 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/** \addtogroup efc_module Working with Enhanced Embedded Flash
- * The EEFC driver provides the interface to configure and use the EEFC
- * peripheral.
- *
- * The user needs to set the number of wait states depending on the frequency used.\n
- * Configure number of cycles for flash read/write operations in the FWS field of EEFC_FMR.
- *
- * It offers a function to send flash command to EEFC and waits for the
- * flash to be ready.
- *
- * To send flash command, the user could do in either of following way:
- *
- *
Write a correct key, command and argument in EEFC_FCR.
- *
Or, Use IAP (In Application Programming) function which is executed from
- * ROM directly, this allows flash programming to be done by code running in flash.
- *
Once the command is achieved, it can be detected even by polling EEFC_FSR or interrupt.
- *
- *
- * The command argument could be a page number,GPNVM number or nothing, it depends on
- * the command itself. Some useful functions in this driver could help user tranlate physical
- * flash address into a page number and vice verse.
- *
- * For more accurate information, please look at the EEFC section of the
- * Datasheet.
- *
- * Related files :\n
- * \ref efc.c\n
- * \ref efc.h.\n
-*/
-/*@{*/
-/*@}*/
-
-
-/**
- * \file
- *
- * Implementation of Emhance embedded Flash (EEFC) controller.
- *
- */
-
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-#include
-#include "efc.h"
-#include
-#include
-
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief Enables the flash ready interrupt source on the EEFC peripheral.
- *
- * \param efc Pointer to a Efc instance
- */
-void EFC_EnableFrdyIt(Efc *efc)
-{
- efc->EEFC_FMR |= EEFC_FMR_FRDY;
-}
-
-/**
- * \brief Disables the flash ready interrupt source on the EEFC peripheral.
- *
- * \param efc Pointer to a Efc instance
- */
-
-void EFC_DisableFrdyIt(Efc *efc)
-{
- efc->EEFC_FMR &= ~EEFC_FMR_FRDY;
-}
-
-
-/**
- * \brief Set read/write wait state on the EEFC perpherial.
- *
- * \param efc Pointer to a Efc instance
- * \param cycles the number of wait states in cycle.
- */
-
-void EFC_SetWaitState(Efc *efc, uint8_t cycles)
-{
- uint32_t value;
- value = efc->EEFC_FMR;
- value &= ~EEFC_FMR_FWS;
- value |= cycles << 8;
- efc->EEFC_FMR = value;
-}
-
-/**
- * \brief Returns the current status of the EEFC.
- *
- * \note Keep in mind that this function clears the value of some status bits (LOCKE, PROGE).
- *
- * \param efc Pointer to a Efc instance
- */
-uint32_t EFC_GetStatus(Efc *efc)
-{
- return efc->EEFC_FSR;
-}
-
-/**
- * \brief Returns the result of the last executed command.
- *
- * \param efc Pointer to a Efc instance
- */
-uint32_t EFC_GetResult(Efc *efc) {
-
- return efc->EEFC_FRR;
-}
-
-/**
- * \brief Translates the given address page and offset values.
- * \note The resulting values are stored in the provided variables if they are not null.
- *
- * \param efc Pointer to a Efc instance
- * \param address Address to translate.
- * \param pPage First page accessed.
- * \param pOffset Byte offset in first page.
- */
-void EFC_TranslateAddress(
- Efc **efc,
- uint32_t address,
- unsigned short *pPage,
- unsigned short *pOffset)
-{
- Efc *pEfc;
- unsigned short page;
- unsigned short offset;
-
- SANITY_CHECK(address >= AT91C_IFLASH);
- SANITY_CHECK(address <= (AT91C_IFLASH + AT91C_IFLASH_SIZE));
-
- pEfc = EFC;
- page = (address - AT91C_IFLASH) / AT91C_IFLASH_PAGE_SIZE;
- offset = (address - AT91C_IFLASH) % AT91C_IFLASH_PAGE_SIZE;
-
- TRACE_DEBUG("Translated 0x%08X to page=%d and offset=%d\n\r", address, page, offset);
- // Store values
- if (pEfc) {
- *efc = pEfc;
- }
- if (pPage) {
- *pPage = page;
- }
- if (pOffset) {
- *pOffset = offset;
- }
-}
-
-/**
- * \brief Computes the address of a flash access given the page and offset.
- *
- * \param efc Pointer to a Efc instance
- * \param page Page number.
- * \param offset Byte offset inside page.
- * \param pAddress Computed address (optional).
- */
-void EFC_ComputeAddress(
- Efc *efc,
- unsigned short page,
- unsigned short offset,
- uint32_t *pAddress)
-{
- uint32_t address;
- SANITY_CHECK(efc);
- SANITY_CHECK(page <= AT91C_IFLASH_NB_OF_PAGES);
- SANITY_CHECK(offset < AT91C_IFLASH_PAGE_SIZE);
- // Compute address
- address = AT91C_IFLASH + page * AT91C_IFLASH_PAGE_SIZE + offset;
- // Store result
- if (pAddress) {
- *pAddress = address;
- }
-}
-
-/**
- * \brief Starts the executing the given command on the EEFC and returns as soon as the command is started.
- *
- * \note It does NOT set the FMCN field automatically.
- * \param efc Pointer to a Efc instance
- * \param command Command to execute.
- * \param argument Command argument (should be 0 if not used).
- */
-void EFC_StartCommand(Efc *efc, uint8_t command, unsigned short argument)
-{
- // Check command & argument
- switch (command) {
-
- case EFC_FCMD_WP:
- case EFC_FCMD_WPL:
- case EFC_FCMD_EWP:
- case EFC_FCMD_EWPL:
- case EFC_FCMD_SLB:
- case EFC_FCMD_CLB:
- ASSERT(argument < AT91C_IFLASH_NB_OF_PAGES,
- "-F- Embedded flash has only %d pages\n\r",
- AT91C_IFLASH_NB_OF_PAGES);
- break;
-
- case EFC_FCMD_SFB:
- case EFC_FCMD_CFB:
- ASSERT(argument < 2, "-F- Embedded flash has only %d GPNVMs\n\r", 2);
- break;
-
- case EFC_FCMD_GETD:
- case EFC_FCMD_EA:
- case EFC_FCMD_GLB:
- case EFC_FCMD_GFB:
- case EFC_FCMD_STUI:
- ASSERT(argument == 0, "-F- Argument is meaningless for the given command.\n\r");
- break;
-
- default: ASSERT(0, "-F- Unknown command %d\n\r", command);
- }
-
- // Start command Embedded flash
- ASSERT((efc->EEFC_FSR & EEFC_FMR_FRDY) == EEFC_FMR_FRDY, "-F- EEFC is not ready\n\r");
- efc->EEFC_FCR = (0x5A << 24) | (argument << 8) | command;
-}
-
-/**
- * \brief Performs the given command and wait until its completion (or an error).
- *
- * \param efc Pointer to a Efc instance
- * \param command Command to perform.
- * \param argument Optional command argument.
- * \return 0 if successful, otherwise returns an error code.
- */
-
-uint8_t EFC_PerformCommand(Efc *efc, uint8_t command, unsigned short argument)
-{
-
-#if defined(flash) || defined(USE_IAP_FEATURE)
- // Pointer on IAP function in ROM
- static uint32_t (*IAP_PerformCommand)(uint32_t, uint32_t);
- IAP_PerformCommand = (uint32_t (*)(uint32_t, uint32_t)) *((uint32_t *) CHIP_FLASH_IAP_ADDRESS);
- IAP_PerformCommand(0, (0x5A << 24) | (argument << 8) | command);
- return (efc->EEFC_FSR & (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE));
-
-#else
- uint32_t status;
- efc->EEFC_FCR = (0x5A << 24) | (argument << 8) | command;
- do {
-
- status = efc->EEFC_FSR;
- }
- while ((status & EEFC_FSR_FRDY) != EEFC_FSR_FRDY);
-
- return (status & (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE));
-#endif
-}
-
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/efc/efc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/efc/efc.h
deleted file mode 100644
index 84fabc38..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/efc/efc.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- *
- * \par Purpose
- *
- * Interface for configuration the Enhanced Embedded Flash Controller (EEFC) peripheral.
- *
- * \par Usage
- *
- * -# Enable/disable %flash ready interrupt sources using EFC_EnableFrdyIt()
- * and EFC_DisableFrdyIt().
- * -# Translates the given address into which EEFC, page and offset values
- * for difference density %flash memory using EFC_TranslateAddress().
- * -# Computes the address of a %flash access given the EFC, page and offset
- * for difference density %flash memory using EFC_ComputeAddress().
- * -# Start the executing command with EFC_StartCommand()
- * -# Retrieve the current status of the EFC using EFC_GetStatus().
- * -# Retrieve the result of the last executed command with EFC_GetResult().
- */
-
-#ifndef EFC_H
-#define EFC_H
-
-/*----------------------------------------------------------------------------
- * Definitions
- *----------------------------------------------------------------------------*/
-/* EFC command */
-#define EFC_FCMD_GETD 0x00
-#define EFC_FCMD_WP 0x01
-#define EFC_FCMD_WPL 0x02
-#define EFC_FCMD_EWP 0x03
-#define EFC_FCMD_EWPL 0x04
-#define EFC_FCMD_EA 0x05
-#define EFC_FCMD_SLB 0x08
-#define EFC_FCMD_CLB 0x09
-#define EFC_FCMD_GLB 0x0A
-#define EFC_FCMD_SFB 0x0B
-#define EFC_FCMD_CFB 0x0C
-#define EFC_FCMD_GFB 0x0D
-#define EFC_FCMD_STUI 0x0E
-#define EFC_FCMD_SPUI 0x0F
-
-/* The IAP function entry addreass */
-#define CHIP_FLASH_IAP_ADDRESS (0x00800008)
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-extern void EFC_EnableFrdyIt(Efc *efc);
-
-extern void EFC_DisableFrdyIt(Efc *efc);
-
-extern void EFC_SetWaitState(Efc *efc, uint8_t cycles);
-
-extern void EFC_TranslateAddress(
- Efc **pEfc,
- uint32_t address,
- unsigned short *pPage,
- unsigned short *pOffset);
-
-extern void EFC_ComputeAddress(
- Efc *efc,
- unsigned short page,
- unsigned short offset,
- uint32_t *pAddress);
-
-extern void EFC_StartCommand(
- Efc *efc,
- uint8_t command,
- unsigned short argument);
-
-extern uint8_t EFC_PerformCommand(
- Efc *efc,
- uint8_t command,
- unsigned short argument);
-
-extern uint32_t EFC_GetStatus(Efc *efc);
-
-extern uint32_t EFC_GetResult(Efc *efc);
-
-#endif //#ifndef EFC_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/flash/flashd.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/flash/flashd.c
deleted file mode 100644
index c0e66913..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/flash/flashd.c
+++ /dev/null
@@ -1,494 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/** \addtogroup flashd_module Flash Memory Interface
- * The flash driver manages the programming, erasing, locking and unlocking sequences
- * with dedicated commands.
- *
- * To implement flash programing operation, the user has to follow these few steps :
- *
- *
Configue flash wait states to initializes the flash.
- *
Checks whether a region to be programmed is locked.
- *
Unlocks the user region to be programmed if the region have locked before.
- *
Erases the user page before program (optional).
- *
Writes the user page from the page buffer.
- *
Locks the region of programmed area if any.
- *
- *
- * Writing 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption.
- * A check of this validity and padding for 32-bit alignment should be done in write algorithm.
-
- * Lock/unlock range associated with the user address range is automatically translated.
- *
- * This security bit can be enabled through the command "Set General Purpose NVM Bit 0".
- *
- * A 128-bit factory programmed unique ID could be read to serve several purposes.
- *
- * The driver accesses the flash memory by calling the lowlevel module provided in \ref efc_module.
- * For more accurate information, please look at the EEFC section of the Datasheet.
- *
- * Related files :\n
- * \ref flashd.c\n
- * \ref flashd.h.\n
- * \ref efc.c\n
- * \ref efc.h.\n
-*/
-/*@{*/
-/*@}*/
-
-
-/**
- * \file
- *
- * The flash driver provides the unified interface for flash program operations.
- *
- */
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-#include "flashd.h"
-#include
-
-#include
-#include
-#include
-#include
-
-#include
-
-
-/*----------------------------------------------------------------------------
- * Local functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief Computes the lock range associated with the given address range.
- *
- * \param start Start address of lock range.
- * \param end End address of lock range.
- * \param pActualStart Actual start address of lock range.
- * \param pActualEnd Actual end address of lock range.
- */
-static void ComputeLockRange(
- uint32_t start,
- uint32_t end,
- uint32_t *pActualStart,
- uint32_t *pActualEnd)
-{
- Efc *pStartEfc, *pEndEfc;
- uint16_t startPage, endPage;
- uint16_t numPagesInRegion;
- uint16_t actualStartPage, actualEndPage;
-
- // Convert start and end address in page numbers
- EFC_TranslateAddress(&pStartEfc, start, &startPage, 0);
- EFC_TranslateAddress(&pEndEfc, end, &endPage, 0);
-
- // Find out the first page of the first region to lock
- numPagesInRegion = AT91C_IFLASH_LOCK_REGION_SIZE / AT91C_IFLASH_PAGE_SIZE;
- actualStartPage = startPage - (startPage % numPagesInRegion);
- actualEndPage = endPage;
- if ((endPage % numPagesInRegion) != 0) {
-
- actualEndPage += numPagesInRegion - (endPage % numPagesInRegion);
- }
- // Store actual page numbers
- EFC_ComputeAddress(pStartEfc, actualStartPage, 0, pActualStart);
- EFC_ComputeAddress(pEndEfc, actualEndPage, 0, pActualEnd);
- TRACE_DEBUG("Actual lock range is 0x%06X - 0x%06X\n\r", *pActualStart, *pActualEnd);
-}
-
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief Initializes the flash driver.
- *
- * \param mck Master clock frequency in Hz.
- */
-
-void FLASHD_Initialize(uint32_t mck)
-{
- EFC_DisableFrdyIt(EFC);
- if ((mck/1000000) >= 64) {
- EFC_SetWaitState(EFC, 2);
- }
- else if ((mck/1000000) >= 50) {
- EFC_SetWaitState(EFC, 1);
- }
- else {
- EFC_SetWaitState(EFC, 0);
- }
-}
-
-/**
- * \brief Erases the entire flash.
- *
- * \param address Flash start address.
- * \return 0 if successful; otherwise returns an error code.
- */
-uint8_t FLASHD_Erase(uint32_t address)
-{
- Efc *pEfc;
- uint16_t page;
- uint16_t offset;
- uint8_t error;
- SANITY_CHECK((address >=AT91C_IFLASH) || (address <= (AT91C_IFLASH + AT91C_IFLASH_SIZE)));
- // Translate write address
- EFC_TranslateAddress(&pEfc, address, &page, &offset);
- error = EFC_PerformCommand(pEfc, EFC_FCMD_EA, 0);
- return error;
-}
-
-
-static uint8_t pPageBuffer[AT91C_IFLASH_PAGE_SIZE];
-/**
- * \brief Writes a data buffer in the internal flash
- *
- * \note This function works in polling mode, and thus only returns when the
- * data has been effectively written.
- * \param address Write address.
- * \param pBuffer Data buffer.
- * \param size Size of data buffer in bytes.
- * \return 0 if successful, otherwise returns an error code.
- */
-uint8_t FLASHD_Write(
- uint32_t address,
- const void *pBuffer,
- uint32_t size)
-{
- Efc *pEfc;
- uint16_t page;
- uint16_t offset;
- uint32_t writeSize;
- uint32_t pageAddress;
- uint16_t padding;
- uint8_t error;
-
- uint32_t sizeTmp;
- uint32_t *pAlignedDestination;
- uint32_t *pAlignedSource;
-
- SANITY_CHECK(pBuffer);
- SANITY_CHECK(address >=AT91C_IFLASH);
- SANITY_CHECK((address + size) <= (AT91C_IFLASH + AT91C_IFLASH_SIZE));
- // Translate write address
- EFC_TranslateAddress(&pEfc, address, &page, &offset);
-
- // Write all pages
- while (size > 0) {
-
- // Copy data in temporary buffer to avoid alignment problems
- writeSize = min(AT91C_IFLASH_PAGE_SIZE - offset, size);
- EFC_ComputeAddress(pEfc, page, 0, &pageAddress);
- padding = AT91C_IFLASH_PAGE_SIZE - offset - writeSize;
-
- // Pre-buffer data
- memcpy(pPageBuffer, (void *) pageAddress, offset);
-
- // Buffer data
- memcpy(pPageBuffer + offset, pBuffer, writeSize);
-
- // Post-buffer data
- memcpy(pPageBuffer + offset + writeSize, (void *) (pageAddress + offset + writeSize), padding);
-
- // Write page
- // Writing 8-bit and 16-bit data is not allowed
- // and may lead to unpredictable data corruption
- pAlignedDestination = (uint32_t*)pageAddress;
- pAlignedSource = (uint32_t*)pPageBuffer;
- sizeTmp = AT91C_IFLASH_PAGE_SIZE;
- while (sizeTmp >= 4) {
-
- *pAlignedDestination++ = *pAlignedSource++;
- sizeTmp -= 4;
- }
-
- // Send writing command
- error = EFC_PerformCommand(pEfc, EFC_FCMD_EWP, page);
- if (error) {
-
- return error;
- }
-
- // Progression
- address += AT91C_IFLASH_PAGE_SIZE;
- pBuffer = (void *) ((uint32_t) pBuffer + writeSize);
- size -= writeSize;
- page++;
- offset = 0;
- }
-
- return 0;
-}
-/**
- * \brief Locks all the regions in the given address range. The actual lock range is
- * reported through two output parameters.
- * \param address Start address of lock range.
- * \param end End address of lock range.
- * \param pActualStart Start address of the actual lock range (optional).
- * \param pActualEnd End address of the actual lock range (optional).
- * \return 0 if successful, otherwise returns an error code.
- */
-uint8_t FLASHD_Lock(
- uint32_t start,
- uint32_t end,
- uint32_t *pActualStart,
- uint32_t *pActualEnd)
-{
- Efc *pEfc;
- uint32_t actualStart, actualEnd;
- uint16_t startPage, endPage;
- uint8_t error;
- uint16_t numPagesInRegion = AT91C_IFLASH_LOCK_REGION_SIZE / AT91C_IFLASH_PAGE_SIZE;
-
- // Compute actual lock range and store it
- ComputeLockRange(start, end, &actualStart, &actualEnd);
- if (pActualStart) {
-
- *pActualStart = actualStart;
- }
- if (pActualEnd) {
-
- *pActualEnd = actualEnd;
- }
-
- // Compute page numbers
- EFC_TranslateAddress(&pEfc, actualStart, &startPage, 0);
- EFC_TranslateAddress(0, actualEnd, &endPage, 0);
-
- // Lock all pages
- while (startPage < endPage) {
-
- error = EFC_PerformCommand(pEfc, EFC_FCMD_SLB, startPage);
- if (error) {
-
- return error;
- }
- startPage += numPagesInRegion;
- }
-
- return 0;
-}
-
-/**
- * \brief Unlocks all the regions in the given address range. The actual unlock range is
- * reported through two output parameters.
- * \param address Start address of unlock range.
- * \param end End address of unlock range.
- * \param pActualStart Start address of the actual unlock range (optional).
- * \param pActualEnd End address of the actual unlock range (optional).
- * \return 0 if successful, otherwise returns an error code.
- */
-uint8_t FLASHD_Unlock(
- uint32_t start,
- uint32_t end,
- uint32_t *pActualStart,
- uint32_t *pActualEnd)
-{
- Efc *pEfc;
- uint32_t actualStart, actualEnd;
- uint16_t startPage, endPage;
- uint8_t error;
- uint16_t numPagesInRegion = AT91C_IFLASH_LOCK_REGION_SIZE / AT91C_IFLASH_PAGE_SIZE;
-
- // Compute actual unlock range and store it
- ComputeLockRange(start, end, &actualStart, &actualEnd);
- if (pActualStart) {
-
- *pActualStart = actualStart;
- }
- if (pActualEnd) {
-
- *pActualEnd = actualEnd;
- }
-
- // Compute page numbers
- EFC_TranslateAddress(&pEfc, actualStart, &startPage, 0);
- EFC_TranslateAddress(0, actualEnd, &endPage, 0);
-
- // Unlock all pages
- while (startPage < endPage) {
-
- error = EFC_PerformCommand(pEfc, EFC_FCMD_CLB, startPage);
- if (error) {
-
- return error;
- }
- startPage += numPagesInRegion;
- }
- return 0;
-}
-
-/**
- * \brief Returns the number of locked regions inside the given address range.
- *
- * \param address Start address of range
- * \param end End address of range.
- */
-uint8_t FLASHD_IsLocked(uint32_t start, uint32_t end)
-{
- Efc *pEfc;
- uint16_t startPage, endPage;
- uint8_t startRegion, endRegion;
- uint32_t numPagesInRegion;
- uint32_t status;
- uint8_t error;
- uint32_t numLockedRegions = 0;
-
- SANITY_CHECK(end >= start);
- SANITY_CHECK((start >=AT91C_IFLASH) && (end <= AT91C_IFLASH + AT91C_IFLASH_SIZE));
-
- // Compute page numbers
- EFC_TranslateAddress(&pEfc, start, &startPage, 0);
- EFC_TranslateAddress(0, end, &endPage, 0);
-
- // Compute region numbers
- numPagesInRegion = AT91C_IFLASH_LOCK_REGION_SIZE / AT91C_IFLASH_PAGE_SIZE;
- startRegion = startPage / numPagesInRegion;
- endRegion = endPage / numPagesInRegion;
- if ((endPage % numPagesInRegion) != 0) {
-
- endRegion++;
- }
-
- // Retrieve lock status
- error = EFC_PerformCommand(pEfc, EFC_FCMD_GLB, 0);
- ASSERT(!error, "-F- Error while trying to fetch lock bits status (0x%02X)\n\r", error);
- status = EFC_GetResult(pEfc);
-
- // Check status of each involved region
- while (startRegion < endRegion) {
-
- if ((status & (1 << startRegion)) != 0) {
-
- numLockedRegions++;
- }
- startRegion++;
- }
-
- return numLockedRegions;
-}
-
-/**
- * \brief Check if the given GPNVM bit is set or not.
- *
- * \param gpnvm GPNVM bit index.
- * \returns 1 if the given GPNVM bit is currently set; otherwise returns 0.
- */
-uint8_t FLASHD_IsGPNVMSet(uint8_t gpnvm)
-{
- uint8_t error;
- uint32_t status;
-
- SANITY_CHECK(gpnvm < 2);
-
- // Get GPNVMs status
- error = EFC_PerformCommand(EFC, EFC_FCMD_GFB, 0);
- ASSERT(!error, "-F- Error while trying to fetch GPNVMs status (0x%02X)\n\r", error);
- status = EFC_GetResult(EFC);
-
- // Check if GPNVM is set
- if ((status & (1 << gpnvm)) != 0) {
- return 1;
- }
- else {
- return 0;
- }
-}
-/**
- * \brief Sets the selected GPNVM bit.
- *
- * \param gpnvm GPNVM bit index.
- * \returns 0 if successful; otherwise returns an error code.
- */
-uint8_t FLASHD_SetGPNVM(uint8_t gpnvm)
-{
- SANITY_CHECK(gpnvm < 2);
-
- if (!FLASHD_IsGPNVMSet(gpnvm)) {
-
- return EFC_PerformCommand(EFC, EFC_FCMD_SFB, gpnvm);
- }
- else {
-
- return 0;
- }
-}
-
-/**
- * \brief Clears the selected GPNVM bit.
- *
- * \param gpnvm GPNVM bit index.
- * \returns 0 if successful; otherwise returns an error code.
- */
-uint8_t FLASHD_ClearGPNVM(uint8_t gpnvm)
-{
- SANITY_CHECK(gpnvm < 2);
-
- if (FLASHD_IsGPNVMSet(gpnvm)) {
-
- return EFC_PerformCommand(EFC, EFC_FCMD_CFB, gpnvm);
- }
- else {
-
- return 0;
- }
-}
-/**
- * \brief Read the unique ID.
- *
- * \param uniqueID pointer on a 4bytes char containing the unique ID value.
- * \returns 0 if successful; otherwise returns an error code.
- */
-uint8_t FLASHD_ReadUniqueID (uint32_t * uniqueID)
-{
- uint8_t error;
- SANITY_CHECK(uniqueID != NULL);
-
- uniqueID[0] = 0;
- uniqueID[1] = 0;
- uniqueID[2] = 0;
- uniqueID[3] = 0;
-
- EFC_StartCommand(EFC, EFC_FCMD_STUI, 0);
-
- uniqueID[0] = *(uint32_t *)AT91C_IFLASH;
- uniqueID[1] = *(uint32_t *)(AT91C_IFLASH + 4);
- uniqueID[2] = *(uint32_t *)(AT91C_IFLASH + 8);
- uniqueID[3] = *(uint32_t *)(AT91C_IFLASH + 12);
-
- error = EFC_PerformCommand(EFC, EFC_FCMD_SPUI, 0);
- if (error) return error;
-
- return 0;
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/flash/flashd.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/flash/flashd.h
deleted file mode 100644
index 14b765b2..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/flash/flashd.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
-*/
-
-/**
- * \file
- *
- * The flash driver provides the unified interface for flash program operations.
- *
- */
-
-#ifndef FLASHD_H
-#define FLASHD_H
-
-#include
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-extern void FLASHD_Initialize(uint32_t mck);
-
-extern uint8_t FLASHD_Erase(uint32_t address);
-
-extern uint8_t FLASHD_Write(
- uint32_t address,
- const void *pBuffer,
- uint32_t size);
-
-extern uint8_t FLASHD_Lock(
- uint32_t start,
- uint32_t end,
- uint32_t *pActualStart,
- uint32_t *pActualEnd);
-
-extern uint8_t FLASHD_Unlock(
- uint32_t start,
- uint32_t end,
- uint32_t *pActualStart,
- uint32_t *pActualEnd);
-
-extern uint8_t FLASHD_IsLocked(
- uint32_t start,
- uint32_t end);
-
-extern uint8_t FLASHD_SetGPNVM(uint8_t gpnvm);
-
-extern uint8_t FLASHD_ClearGPNVM(uint8_t gpnvm);
-
-extern uint8_t FLASHD_IsGPNVMSet(uint8_t gpnvm);
-
-#define FLASHD_IsSecurityBitSet() FLASHD_IsGPNVMSet(0)
-
-#define FLASHD_SetSecurityBit() FLASHD_SetGPNVM(0)
-
-extern uint8_t FLASHD_ReadUniqueID(uint32_t * uniqueID);
-
-#endif //#ifndef FLASHD_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/color.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/color.h
deleted file mode 100644
index 3258b82c..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/color.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-#ifndef COLOR_H
-#define COLOR_H
-
-/**
- * \file
- *
- * RGB 24-bits color table definition.
- *
- */
-
-/*
- * RGB 24 Bpp
- * RGB 888
- * R7R6R5R4 R3R2R1R0 G7G6G5G4 G3G2G1G0 B7B6B5B4 B3B2B1B0
- */
-#define COLOR_BLACK 0x000000
-#define COLOR_WHITE 0xFFFFFF
-
-#define COLOR_BLUE 0x0000FF
-#define COLOR_GREEN 0x00FF00
-#define COLOR_RED 0xFF0000
-
-#define COLOR_NAVY 0x000080
-#define COLOR_DARKBLUE 0x00008B
-#define COLOR_DARKGREEN 0x006400
-#define COLOR_DARKCYAN 0x008B8B
-#define COLOR_CYAN 0x00FFFF
-#define COLOR_TURQUOISE 0x40E0D0
-#define COLOR_INDIGO 0x4B0082
-#define COLOR_DARKRED 0x800000
-#define COLOR_OLIVE 0x808000
-#define COLOR_GRAY 0x808080
-#define COLOR_SKYBLUE 0x87CEEB
-#define COLOR_BLUEVIOLET 0x8A2BE2
-#define COLOR_LIGHTGREEN 0x90EE90
-#define COLOR_DARKVIOLET 0x9400D3
-#define COLOR_YELLOWGREEN 0x9ACD32
-#define COLOR_BROWN 0xA52A2A
-#define COLOR_DARKGRAY 0xA9A9A9
-#define COLOR_SIENNA 0xA0522D
-#define COLOR_LIGHTBLUE 0xADD8E6
-#define COLOR_GREENYELLOW 0xADFF2F
-#define COLOR_SILVER 0xC0C0C0
-#define COLOR_LIGHTGREY 0xD3D3D3
-#define COLOR_LIGHTCYAN 0xE0FFFF
-#define COLOR_VIOLET 0xEE82EE
-#define COLOR_AZUR 0xF0FFFF
-#define COLOR_BEIGE 0xF5F5DC
-#define COLOR_MAGENTA 0xFF00FF
-#define COLOR_TOMATO 0xFF6347
-#define COLOR_GOLD 0xFFD700
-#define COLOR_ORANGE 0xFFA500
-#define COLOR_SNOW 0xFFFAFA
-#define COLOR_YELLOW 0xFFFF00
-
-#endif /* #define COLOR_H */
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/draw.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/draw.c
deleted file mode 100644
index 4e1975be..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/draw.c
+++ /dev/null
@@ -1,333 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- *
- * Implementation of draw function on LCD, Include draw text, image
- * and basic shapes (line, rectangle, circle).
- *
- */
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include
-#include
-
-#include "draw.h"
-#include "font.h"
-#include
-#include
-#include
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief Fills the given LCD buffer with a particular color.
- *
- * \param color Fill color.
- */
-void LCDD_Fill(uint32_t color)
-{
- uint32_t i;
-
- LCD_SetCursor(0, 0);
- LCD_WriteRAM_Prepare();
- for (i = 0; i < (BOARD_LCD_WIDTH * BOARD_LCD_HEIGHT); i++) {
-
- LCD_WriteRAM(color);
- }
-}
-
-/**
- * \brief Draw a pixel on LCD of given color.
- *
- * \param x X-coordinate of pixel.
- * \param y Y-coordinate of pixel.
- * \param color Pixel color.
- */
-void LCDD_DrawPixel(
- uint32_t x,
- uint32_t y,
- uint32_t color)
-{
- LCD_SetCursor(x, y);
- LCD_WriteRAM_Prepare();
- LCD_WriteRAM(color);
-}
-
-/**
- * \brief Read a pixel from LCD.
- *
- * \param x X-coordinate of pixel.
- * \param y Y-coordinate of pixel.
- *
- * \return color Readed pixel color.
- */
-uint32_t LCDD_ReadPixel(
- uint32_t x,
- uint32_t y)
-{
- uint32_t color;
-
- LCD_SetCursor(x, y);
- LCD_ReadRAM_Prepare();
- color = LCD_ReadRAM();
-
- return color;
-}
-
-/*
- * \brief Draw a line on LCD, horizontal and vertical line are supported.
- *
- * \param x X-coordinate of line start.
- * \param y Y-coordinate of line start.
- * \param length line length.
- * \param direction line direction: 0 - horizontal, 1 - vertical.
- * \param color Pixel color.
- */
-void LCDD_DrawLine(
- uint32_t x,
- uint32_t y,
- uint32_t length,
- uint32_t direction,
- uint32_t color)
-{
- uint32_t i = 0;
-
- LCD_SetCursor(x, y);
-
- if(direction == DIRECTION_HLINE) {
- LCD_WriteRAM_Prepare();
- for(i = 0; i < length; i++) {
- LCD_WriteRAM(color);
- }
- }
- else {
- for(i = 0; i < length; i++) {
- LCD_WriteRAM_Prepare();
- LCD_WriteRAM(color);
- y++;
- LCD_SetCursor(x, y);
- }
- }
-}
-
-/*
- * \brief Draws a rectangle on LCD, at the given coordinates.
- *
- * \param x X-coordinate of upper-left rectangle corner.
- * \param y Y-coordinate of upper-left rectangle corner.
- * \param width Rectangle width in pixels.
- * \param height Rectangle height in pixels.
- * \param color Rectangle color.
- */
-void LCDD_DrawRectangle(
- uint32_t x,
- uint32_t y,
- uint32_t width,
- uint32_t height,
- uint32_t color)
-{
- LCDD_DrawLine(x, y, width, DIRECTION_HLINE, color);
- LCDD_DrawLine(x, (y + height), width, DIRECTION_HLINE, color);
-
- LCDD_DrawLine(x, y, height, DIRECTION_VLINE, color);
- LCDD_DrawLine((x + width), y, height, DIRECTION_VLINE, color);
-}
-
-/*
- * \brief Draws a rectangle with fill inside on LCD, at the given coordinates.
- *
- * \param x X-coordinate of upper-left rectangle corner.
- * \param y Y-coordinate of upper-left rectangle corner.
- * \param width Rectangle width in pixels.
- * \param height Rectangle height in pixels.
- * \param color Rectangle color.
- */
-void LCDD_DrawRectangleWithFill(
- uint32_t x,
- uint32_t y,
- uint32_t width,
- uint32_t height,
- uint32_t color)
-{
- uint32_t i;
-
- for (i = 0; i < height; i++) {
- LCDD_DrawLine(x, y+i, width, DIRECTION_HLINE, color);
- }
-}
-
-/**
- * \brief Draws a circle on LCD, at the given coordinates.
- *
- * \param x X-coordinate of circle center.
- * \param y Y-coordinate of circle center.
- * \param r circle radius.
- * \param color circle color.
- */
-void LCDD_DrawCircle(
- uint32_t x,
- uint32_t y,
- uint32_t r,
- uint32_t color)
-{
- signed int d; /* Decision Variable */
- uint32_t curX; /* Current X Value */
- uint32_t curY; /* Current Y Value */
-
- d = 3 - (r << 1);
- curX = 0;
- curY = r;
-
- while (curX <= curY)
- {
- LCDD_DrawPixel(x + curX, y + curY, color);
- LCDD_DrawPixel(x + curX, y - curY, color);
- LCDD_DrawPixel(x - curX, y + curY, color);
- LCDD_DrawPixel(x - curX, y - curY, color);
- LCDD_DrawPixel(x + curY, y + curX, color);
- LCDD_DrawPixel(x + curY, y - curX, color);
- LCDD_DrawPixel(x - curY, y + curX, color);
- LCDD_DrawPixel(x - curY, y - curX, color);
-
- if (d < 0) {
- d += (curX << 2) + 6;
- }
- else {
- d += ((curX - curY) << 2) + 10;
- curY--;
- }
- curX++;
- }
-}
-
-/**
- * \brief Draws a string inside a LCD buffer, at the given coordinates. Line breaks
- * will be honored.
- *
- * \param x X-coordinate of string top-left corner.
- * \param y Y-coordinate of string top-left corner.
- * \param pString String to display.
- * \param color String color.
- */
-void LCDD_DrawString(
- uint32_t x,
- uint32_t y,
- const uint8_t *pString,
- uint32_t color)
-{
- unsigned xorg = x;
-
- while (*pString != 0) {
- if (*pString == '\n') {
-
- y += gFont.height + 2;
- x = xorg;
- }
- else {
-
- LCDD_DrawChar(x, y, *pString, color);
- x += gFont.width + 2;
- }
- pString++;
- }
-}
-
-/**
- * \brief Returns the width & height in pixels that a string will occupy on the screen
- * if drawn using LCDD_DrawString.
- *
- * \param pString String.
- * \param pWidth Pointer for storing the string width (optional).
- * \param pHeight Pointer for storing the string height (optional).
- *
- * \return String width in pixels.
- */
-void LCDD_GetStringSize(
- const uint8_t *pString,
- uint32_t *pWidth,
- uint32_t *pHeight)
-{
- uint32_t width = 0;
- uint32_t height = gFont.height;
-
- while (*pString != 0) {
-
- if (*pString == '\n') {
-
- height += gFont.height + 2;
- }
- else {
-
- width += gFont.width + 2;
- }
- pString++;
- }
-
- if (width > 0) width -= 2;
-
- if (pWidth) *pWidth = width;
- if (pHeight) *pHeight = height;
-}
-
-/*
- * \brief Draw a raw image at given position on LCD.
- *
- * \param x X-coordinate of image start.
- * \param y Y-coordinate of image start.
- * \param pImage Image buffer.
- * \param width Image width.
- * \param height Image height.
- */
-void LCDD_DrawImage(
- uint32_t x,
- uint32_t y,
- const uint8_t *pImage,
- uint32_t width,
- uint32_t height)
-{
- uint32_t row, col;
-
- for(row = y; row < (y + height); row++) {
- LCD_SetCursor(x, row);
- LCD_WriteRAM_Prepare();
- for(col = x; col < (x + width); col++) {
- LCD_D() = *pImage++;
- LCD_D() = *pImage++;
- LCD_D() = *pImage++;
- }
- }
-}
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/draw.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/draw.h
deleted file mode 100644
index e7fb7a57..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/draw.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
- /**
- * \file
- *
- * Interface for draw function on LCD.
- *
- */
-
-#ifndef DRAW_H
-#define DRAW_H
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include
-
-/*----------------------------------------------------------------------------
- * Definitions
- *----------------------------------------------------------------------------*/
-
-/** Horizontal direction line definition */
-#define DIRECTION_HLINE 0
-/** Vertical direction line definition */
-#define DIRECTION_VLINE 1
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-extern void LCDD_Fill(uint32_t color);
-
-extern void LCDD_DrawPixel(
- uint32_t x,
- uint32_t y,
- uint32_t c);
-
-extern uint32_t LCDD_ReadPixel(
- uint32_t x,
- uint32_t y);
-
-extern void LCDD_DrawLine(
- uint32_t x,
- uint32_t y,
- uint32_t length,
- uint32_t direction,
- uint32_t color);
-
-extern void LCDD_DrawRectangle(
- uint32_t x,
- uint32_t y,
- uint32_t width,
- uint32_t height,
- uint32_t color);
-
-extern void LCDD_DrawRectangleWithFill(
- uint32_t x,
- uint32_t y,
- uint32_t width,
- uint32_t height,
- uint32_t color);
-
-extern void LCDD_DrawCircle(
- uint32_t x,
- uint32_t y,
- uint32_t r,
- uint32_t color);
-
-extern void LCDD_DrawString(
- uint32_t x,
- uint32_t y,
- const uint8_t *pString,
- uint32_t color);
-
-extern void LCDD_GetStringSize(
- const uint8_t *pString,
- uint32_t *pWidth,
- uint32_t *pHeight);
-
-extern void LCDD_DrawImage(
- uint32_t x,
- uint32_t y,
- const uint8_t *pImage,
- uint32_t width,
- uint32_t height);
-
-#endif /* #ifndef DRAW_H */
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/font.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/font.c
deleted file mode 100644
index 4a161298..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/font.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- *
- * Implementation of draw font on LCD.
- *
- */
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include
-#include "color.h"
-#include "font.h"
-#include "draw.h"
-#include "font10x14.h"
-#include
-
-/*----------------------------------------------------------------------------
- * Local variables
- *----------------------------------------------------------------------------*/
-
-/** Global variable describing the font being instancied. */
-const Font gFont = {10, 14};
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief Draws an ASCII character on LCD.
- *
- * \param x X-coordinate of character upper-left corner.
- * \param y Y-coordinate of character upper-left corner.
- * \param c Character to output.
- * \param color Character color.
-*/
-void LCDD_DrawChar(
- uint32_t x,
- uint32_t y,
- uint8_t c,
- uint32_t color)
-{
- uint32_t row, col;
-
- SANITY_CHECK((c >= 0x20) && (c <= 0x7F));
-
- for (col = 0; col < 10; col++) {
-
- for (row = 0; row < 8; row++) {
-
- if ((pCharset10x14[((c - 0x20) * 20) + col * 2] >> (7 - row)) & 0x1) {
-
- LCDD_DrawPixel(x+col, y+row, color);
- }
- }
- for (row = 0; row < 6; row++) {
-
- if ((pCharset10x14[((c - 0x20) * 20) + col * 2 + 1] >> (7 - row)) & 0x1) {
-
- LCDD_DrawPixel(x+col, y+row+8, color);
- }
- }
- }
-}
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/font.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/font.h
deleted file mode 100644
index d46cf6c4..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/font.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- *
- * Interface for draw font on LCD.
- *
- */
-
-/**
- *
- * \section Purpose
- *
- * The font.h files declares a font structure and a LCDD_DrawChar function
- * that must be implemented by a font definition file to be used with the
- * LCDD_DrawString method of draw.h.
- *
- * The font10x14.c implements the necessary variable and function for a 10x14
- * font.
- *
- * \section Usage
- *
- * -# Declare a gFont global variable with the necessary Font information.
- * -# Implement an LCDD_DrawChar function which displays the specified
- * character on the LCD.
- * -# Use the LCDD_DrawString method defined in draw.h to display a complete
- * string.
- */
-
-#ifndef FONT_H
-#define FONT_H
-
-/*----------------------------------------------------------------------------
- * Types
- *----------------------------------------------------------------------------*/
-
-
-/** Describes the font (width, height, supported characters, etc.) used by
- * the LCD driver draw API.
- */
-typedef struct _Font {
- /* Font width in pixels. */
- uint8_t width;
- /* Font height in pixels. */
- uint8_t height;
-} Font;
-
-/*----------------------------------------------------------------------------
- * Variables
- *----------------------------------------------------------------------------*/
-
-/** Global variable describing the font being instancied. */
-extern const Font gFont;
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-extern void LCDD_DrawChar(
- uint32_t x,
- uint32_t y,
- uint8_t c,
- uint32_t color);
-
-#endif /* #ifndef FONT_H */
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/font10x14.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/font10x14.h
deleted file mode 100644
index 2ce2589e..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/font10x14.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
- /**
- * \file
- *
- * Font 10x14 table definition.
- *
- */
-
-#ifndef LCD_FONT_10x14_H
-#define LCD_FONT_10x14_H
-
-/** Char set of font 10x14 */
-const uint8_t pCharset10x14[] = {
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xCC,
- 0xFF, 0xCC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x0C, 0xC0, 0x0C, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x0C, 0xC0,
- 0x0C, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x0C, 0xC0, 0x0C, 0xC0,
- 0x0C, 0x60, 0x1E, 0x70, 0x3F, 0x30, 0x33, 0x30, 0xFF, 0xFC,
- 0xFF, 0xFC, 0x33, 0x30, 0x33, 0xF0, 0x39, 0xE0, 0x18, 0xC0,
- 0x60, 0x00, 0xF0, 0x0C, 0xF0, 0x3C, 0x60, 0xF0, 0x03, 0xC0,
- 0x0F, 0x00, 0x3C, 0x18, 0xF0, 0x3C, 0xC0, 0x3C, 0x00, 0x18,
- 0x3C, 0xF0, 0x7F, 0xF8, 0xC3, 0x1C, 0xC7, 0x8C, 0xCF, 0xCC,
- 0xDC, 0xEC, 0x78, 0x78, 0x30, 0x30, 0x00, 0xFC, 0x00, 0xCC,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0xEC, 0x00,
- 0xF8, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x0F, 0xC0, 0x3F, 0xF0, 0x78, 0x78,
- 0x60, 0x18, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0x60, 0x18,
- 0x78, 0x78, 0x3F, 0xF0, 0x0F, 0xC0, 0x00, 0x00, 0x00, 0x00,
- 0x0C, 0x60, 0x0E, 0xE0, 0x07, 0xC0, 0x03, 0x80, 0x3F, 0xF8,
- 0x3F, 0xF8, 0x03, 0x80, 0x07, 0xC0, 0x0E, 0xE0, 0x0C, 0x60,
- 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x3F, 0xF0,
- 0x3F, 0xF0, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,
- 0x00, 0x44, 0x00, 0xEC, 0x00, 0xF8, 0x00, 0x70, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,
- 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,
- 0x00, 0x18, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x18, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x0C, 0x00, 0x3C, 0x00, 0xF0, 0x03, 0xC0,
- 0x0F, 0x00, 0x3C, 0x00, 0xF0, 0x00, 0xC0, 0x00, 0x00, 0x00,
- 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0xFC, 0xC1, 0xCC, 0xC3, 0x8C,
- 0xC7, 0x0C, 0xCE, 0x0C, 0xFC, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,
- 0x00, 0x00, 0x00, 0x00, 0x30, 0x0C, 0x70, 0x0C, 0xFF, 0xFC,
- 0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00,
- 0x30, 0x0C, 0x70, 0x1C, 0xE0, 0x3C, 0xC0, 0x7C, 0xC0, 0xEC,
- 0xC1, 0xCC, 0xC3, 0x8C, 0xE7, 0x0C, 0x7E, 0x0C, 0x3C, 0x0C,
- 0x30, 0x30, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,
- 0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x1C, 0x7F, 0xF8, 0x3C, 0xF0,
- 0x03, 0xC0, 0x07, 0xC0, 0x0E, 0xC0, 0x1C, 0xC0, 0x38, 0xC0,
- 0x70, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0xC0, 0x00, 0xC0,
- 0xFC, 0x30, 0xFC, 0x38, 0xCC, 0x1C, 0xCC, 0x0C, 0xCC, 0x0C,
- 0xCC, 0x0C, 0xCC, 0x0C, 0xCE, 0x1C, 0xC7, 0xF8, 0xC3, 0xF0,
- 0x3F, 0xF0, 0x7F, 0xF8, 0xE3, 0x1C, 0xC3, 0x0C, 0xC3, 0x0C,
- 0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x9C, 0x71, 0xF8, 0x30, 0xF0,
- 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC3, 0xFC,
- 0xC7, 0xFC, 0xCE, 0x00, 0xDC, 0x00, 0xF8, 0x00, 0xF0, 0x00,
- 0x3C, 0xF0, 0x7F, 0xF8, 0xE7, 0x9C, 0xC3, 0x0C, 0xC3, 0x0C,
- 0xC3, 0x0C, 0xC3, 0x0C, 0xE7, 0x9C, 0x7F, 0xF8, 0x3C, 0xF0,
- 0x3C, 0x00, 0x7E, 0x00, 0xE7, 0x0C, 0xC3, 0x0C, 0xC3, 0x1C,
- 0xC3, 0x38, 0xC3, 0x70, 0xE7, 0xE0, 0x7F, 0xC0, 0x3F, 0x80,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x60, 0x3C, 0xF0,
- 0x3C, 0xF0, 0x18, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x44, 0x3C, 0xEC,
- 0x3C, 0xF8, 0x18, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x03, 0x00, 0x07, 0x80, 0x0F, 0xC0, 0x1C, 0xE0,
- 0x38, 0x70, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C, 0x00, 0x00,
- 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,
- 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,
- 0x00, 0x00, 0xC0, 0x0C, 0xE0, 0x1C, 0x70, 0x38, 0x38, 0x70,
- 0x1C, 0xE0, 0x0F, 0xC0, 0x07, 0x80, 0x03, 0x00, 0x00, 0x00,
- 0x30, 0x00, 0x70, 0x00, 0xE0, 0x00, 0xC0, 0x00, 0xC1, 0xEC,
- 0xC3, 0xEC, 0xC3, 0x00, 0xE6, 0x00, 0x7E, 0x00, 0x3C, 0x00,
- 0x30, 0xF0, 0x71, 0xF8, 0xE3, 0x9C, 0xC3, 0x0C, 0xC3, 0xFC,
- 0xC3, 0xFC, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,
- 0x3F, 0xFC, 0x7F, 0xFC, 0xE0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0,
- 0xC0, 0xC0, 0xC0, 0xC0, 0xE0, 0xC0, 0x7F, 0xFC, 0x3F, 0xFC,
- 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C,
- 0xC3, 0x0C, 0xC3, 0x0C, 0xE7, 0x9C, 0x7F, 0xF8, 0x3C, 0xF0,
- 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,
- 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x70, 0x38, 0x30, 0x30,
- 0xFF, 0xFC, 0xFF, 0xFC, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C,
- 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,
- 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C,
- 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C,
- 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00,
- 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00, 0xC0, 0x00, 0xC0, 0x00,
- 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,
- 0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x1C, 0x73, 0xF8, 0x33, 0xF0,
- 0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,
- 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0xFF, 0xFC, 0xFF, 0xFC,
- 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xFF, 0xFC,
- 0xFF, 0xFC, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x30, 0x00, 0x38, 0xC0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,
- 0xC0, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0, 0xC0, 0x00, 0xC0, 0x00,
- 0xFF, 0xFC, 0xFF, 0xFC, 0x07, 0x80, 0x07, 0x80, 0x0F, 0xC0,
- 0x1C, 0xE0, 0x38, 0x70, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C,
- 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,
- 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,
- 0xFF, 0xFC, 0xFF, 0xFC, 0x70, 0x00, 0x38, 0x00, 0x1F, 0x00,
- 0x1F, 0x00, 0x38, 0x00, 0x70, 0x00, 0xFF, 0xFC, 0xFF, 0xFC,
- 0xFF, 0xFC, 0xFF, 0xFC, 0x1C, 0x00, 0x0E, 0x00, 0x07, 0x00,
- 0x03, 0x80, 0x01, 0xC0, 0x00, 0xE0, 0xFF, 0xFC, 0xFF, 0xFC,
- 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C,
- 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0,
- 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00,
- 0xC3, 0x00, 0xC3, 0x00, 0xE7, 0x00, 0x7E, 0x00, 0x3C, 0x00,
- 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0xCC,
- 0xC0, 0xEC, 0xC0, 0x7C, 0xE0, 0x38, 0x7F, 0xFC, 0x3F, 0xEC,
- 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x80, 0xC3, 0x80,
- 0xC3, 0xC0, 0xC3, 0xC0, 0xE7, 0x70, 0x7E, 0x3C, 0x3C, 0x1C,
- 0x3C, 0x18, 0x7E, 0x1C, 0xE7, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C,
- 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x9C, 0xE1, 0xF8, 0x60, 0xF0,
- 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xFF, 0xFC,
- 0xFF, 0xFC, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,
- 0xFF, 0xF0, 0xFF, 0xF8, 0x00, 0x1C, 0x00, 0x0C, 0x00, 0x0C,
- 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0,
- 0xFF, 0xC0, 0xFF, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C,
- 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0xFF, 0xE0, 0xFF, 0xC0,
- 0xFF, 0xF0, 0xFF, 0xF8, 0x00, 0x1C, 0x00, 0x3C, 0x00, 0xF8,
- 0x00, 0xF8, 0x00, 0x3C, 0x00, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0,
- 0xF0, 0x3C, 0xF8, 0x7C, 0x1C, 0xE0, 0x0F, 0xC0, 0x07, 0x80,
- 0x07, 0x80, 0x0F, 0xC0, 0x1C, 0xE0, 0xF8, 0x7C, 0xF0, 0x3C,
- 0xFC, 0x00, 0xFE, 0x00, 0x07, 0x00, 0x03, 0x80, 0x01, 0xFC,
- 0x01, 0xFC, 0x03, 0x80, 0x07, 0x00, 0xFE, 0x00, 0xFC, 0x00,
- 0xC0, 0x3C, 0xC0, 0x7C, 0xC0, 0xEC, 0xC1, 0xCC, 0xC3, 0x8C,
- 0xC7, 0x0C, 0xCE, 0x0C, 0xDC, 0x0C, 0xF8, 0x0C, 0xF0, 0x0C,
- 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, 0xC0, 0x0C,
- 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x30, 0x00, 0x30, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x03, 0x00,
- 0x03, 0x00, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x30,
- 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C,
- 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x0C, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0x00, 0xE0, 0x00,
- 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0C, 0x00,
- 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,
- 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C,
- 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0xE0, 0x00, 0x70, 0x00,
- 0x38, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x30, 0x06, 0x78, 0x0E, 0xFC, 0x0C, 0xCC, 0x0C, 0xCC,
- 0x0C, 0xCC, 0x0C, 0xCC, 0x0E, 0xCC, 0x07, 0xFC, 0x03, 0xF8,
- 0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x0C,
- 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x9C, 0x01, 0xF8, 0x00, 0xF0,
- 0x03, 0xF0, 0x07, 0xF8, 0x0E, 0x1C, 0x0C, 0x0C, 0x0C, 0x0C,
- 0x0C, 0x0C, 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0x38, 0x03, 0x30,
- 0x00, 0xF0, 0x01, 0xF8, 0x03, 0x9C, 0x03, 0x0C, 0x03, 0x0C,
- 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x0C, 0xFF, 0xFC, 0xFF, 0xFC,
- 0x03, 0xF0, 0x07, 0xF8, 0x0E, 0xDC, 0x0C, 0xCC, 0x0C, 0xCC,
- 0x0C, 0xCC, 0x0C, 0xCC, 0x0E, 0xDC, 0x07, 0xD8, 0x03, 0x90,
- 0x00, 0x00, 0x03, 0x00, 0x3F, 0xFC, 0x7F, 0xFC, 0xE3, 0x00,
- 0xE3, 0x00, 0x70, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x03, 0x18, 0x07, 0x9C, 0x0F, 0xCC, 0x0C, 0xCC, 0x0C, 0xCC,
- 0x0C, 0xCC, 0x0C, 0xCC, 0x0C, 0xDC, 0x0F, 0xF8, 0x07, 0xF0,
- 0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00,
- 0x03, 0x00, 0x03, 0x80, 0x01, 0xFC, 0x00, 0xFC, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0xFC,
- 0x1B, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x30, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0C,
- 0x00, 0x0C, 0x00, 0x1C, 0xCF, 0xF8, 0xCF, 0xF0, 0x00, 0x00,
- 0x00, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0xE0, 0x01, 0xE0,
- 0x03, 0xF0, 0x07, 0x38, 0x0E, 0x1C, 0x0C, 0x0C, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xFF, 0xFC,
- 0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00,
- 0x0F, 0xFC, 0x0F, 0xFC, 0x0E, 0x00, 0x07, 0x00, 0x03, 0xC0,
- 0x03, 0xC0, 0x07, 0x00, 0x0E, 0x00, 0x0F, 0xFC, 0x0F, 0xFC,
- 0x0F, 0xFC, 0x0F, 0xFC, 0x03, 0x00, 0x07, 0x00, 0x0E, 0x00,
- 0x0C, 0x00, 0x0C, 0x00, 0x0E, 0x00, 0x07, 0xFC, 0x03, 0xFC,
- 0x03, 0xF0, 0x07, 0xF8, 0x0E, 0x1C, 0x0C, 0x0C, 0x0C, 0x0C,
- 0x0C, 0x0C, 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0xF8, 0x03, 0xF0,
- 0x0F, 0xFC, 0x0F, 0xFC, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,
- 0x0C, 0xC0, 0x0C, 0xC0, 0x0F, 0xC0, 0x07, 0x80, 0x03, 0x00,
- 0x03, 0x00, 0x07, 0x80, 0x0F, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0,
- 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0F, 0xFC, 0x0F, 0xFC,
- 0x0F, 0xFC, 0x0F, 0xFC, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00,
- 0x0C, 0x00, 0x0C, 0x00, 0x0E, 0x00, 0x07, 0x00, 0x03, 0x00,
- 0x03, 0x18, 0x07, 0x9C, 0x0F, 0xCC, 0x0C, 0xCC, 0x0C, 0xCC,
- 0x0C, 0xCC, 0x0C, 0xCC, 0x0C, 0xFC, 0x0E, 0x78, 0x06, 0x30,
- 0x00, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0xFF, 0xF0, 0xFF, 0xF8,
- 0x0C, 0x1C, 0x0C, 0x1C, 0x0C, 0x38, 0x0C, 0x30, 0x00, 0x00,
- 0x0F, 0xF0, 0x0F, 0xF8, 0x00, 0x1C, 0x00, 0x0C, 0x00, 0x0C,
- 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x1C, 0x0F, 0xF8, 0x0F, 0xF0,
- 0x0F, 0xC0, 0x0F, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C,
- 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0x0F, 0xE0, 0x0F, 0xC0,
- 0x0F, 0xF0, 0x0F, 0xF8, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0xF8,
- 0x00, 0xF8, 0x00, 0x1C, 0x00, 0x1C, 0x0F, 0xF8, 0x0F, 0xF0,
- 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0x38, 0x03, 0xF0, 0x01, 0xE0,
- 0x01, 0xE0, 0x03, 0xF0, 0x07, 0x38, 0x0E, 0x1C, 0x0C, 0x0C,
- 0x0C, 0x00, 0x0E, 0x00, 0x07, 0x0C, 0x03, 0x9C, 0x01, 0xF8,
- 0x01, 0xF0, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00, 0x0C, 0x00,
- 0x0C, 0x0C, 0x0C, 0x1C, 0x0C, 0x3C, 0x0C, 0x7C, 0x0C, 0xEC,
- 0x0D, 0xCC, 0x0F, 0x8C, 0x0F, 0x0C, 0x0E, 0x0C, 0x0C, 0x0C,
- 0x00, 0x00, 0x03, 0x00, 0x07, 0x80, 0x3F, 0xF0, 0x7C, 0xF8,
- 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00,
- 0x03, 0x0C, 0x03, 0x0C, 0x3F, 0xFC, 0x7F, 0xFC, 0xE3, 0x0C,
- 0xC3, 0x0C, 0xC0, 0x0C, 0xE0, 0x0C, 0x70, 0x0C, 0x30, 0x0C,
- 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C,
- 0x7C, 0xF8, 0x3F, 0xF0, 0x07, 0x80, 0x03, 0x00, 0x00, 0x00,
- 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,
- 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,
- 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC,
- 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC
-};
-
-#endif /* #ifdef _LCD_FONT_10x14_h */
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/lcdd.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/lcdd.c
deleted file mode 100644
index 1d7b158a..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/lcdd.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- *
- * Implementation of LCD driver, Include LCD initialization,
- * LCD on/off and LCD backlight control.
- *
- */
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include
-#include "lcdd.h"
-#include
-#include
-#include
-#include
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief Initializes the LCD controller.
- * Configure SMC to access LCD controller at 64MHz MCK.
- */
-void LCDD_Initialize(void)
-{
- const Pin pPins[] = {BOARD_LCD_PINS};
- Smc *pSmc = SMC;
-
- /* Enable pins */
- PIO_Configure(pPins, PIO_LISTSIZE(pPins));
-
- /* Enable peripheral clock */
- PMC_EnablePeripheral(ID_SMC);
-
- /* EBI SMC Configuration */
- pSmc->SMC_CS_NUMBER[1].SMC_SETUP = 0
- | ((2 << 0) & SMC_SETUP1_NWE_SETUP)
- | ((2 << 8) & SMC_SETUP1_NCS_WR_SETUP)
- | ((2 << 16) & SMC_SETUP1_NRD_SETUP)
- | ((2 << 24) & SMC_SETUP1_NCS_RD_SETUP)
- ;
-
- pSmc->SMC_CS_NUMBER[1].SMC_PULSE = 0
- | ((4 << 0) & SMC_PULSE1_NWE_PULSE)
- | ((4 << 8) & SMC_PULSE1_NCS_WR_PULSE)
- | ((10 << 16) & SMC_PULSE1_NRD_PULSE)
- | ((10 << 24) & SMC_PULSE1_NCS_RD_PULSE)
- ;
-
- pSmc->SMC_CS_NUMBER[1].SMC_CYCLE = 0
- | ((10 << 0) & SMC_CYCLE1_NWE_CYCLE)
- | ((22 << 16) & SMC_CYCLE1_NRD_CYCLE)
- ;
-
- pSmc->SMC_CS_NUMBER[1].SMC_MODE = 0
- | (SMC_MODE1_READ_MODE)
- | (SMC_MODE1_WRITE_MODE)
- | (0) /* Set 8 bit width. TODO: replace with definition in device header file */
- ;
-
- /* Initialize LCD controller */
- LCD_Initialize();
-
- /* Set LCD backlight */
- LCDD_SetBacklight(2);
-}
-
-/**
- * \brief Turn on the LCD.
- */
-void LCDD_On(void)
-{
- LCD_On();
-}
-
-/**
- * \brief Turn off the LCD.
- */
-void LCDD_Off(void)
-{
- LCD_Off();
-}
-
-/**
- * \brief Set the backlight of the LCD.
- *
- * \param level Backlight brightness level [1..16], 1 means maximum brightness.
- */
-void LCDD_SetBacklight (uint32_t level)
-{
- uint32_t i;
- const Pin pPins[] = {BOARD_BACKLIGHT_PIN};
-
- /* Ensure valid level */
- level = (level < 1) ? 1 : level;
- level = (level > 16) ? 16 : level;
-
- /* Enable pins */
- PIO_Configure(pPins, PIO_LISTSIZE(pPins));
-
- /* Switch off backlight */
- PIO_Clear(pPins);
- i = 600 * (BOARD_MCK / 1000000); /* wait for at least 500us */
- while(i--);
-
- /* Set new backlight level */
- for (i = 0; i < level; i++) {
- PIO_Clear(pPins);
- PIO_Clear(pPins);
- PIO_Clear(pPins);
-
- PIO_Set(pPins);
- PIO_Set(pPins);
- PIO_Set(pPins);
- }
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/lcdd.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/lcdd.h
deleted file mode 100644
index 8ba19f05..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/lcdd.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- *
- * Interface for LCD driver.
- *
- */
-
-#ifndef LCDD_H
-#define LCDD_H
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-extern void LCDD_Initialize(void);
-
-extern void LCDD_On(void);
-
-extern void LCDD_Off(void);
-
-extern void LCDD_SetBacklight (uint32_t step);
-
-#endif /* #ifndef LCDD_H */
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio.c
deleted file mode 100644
index db13b2b4..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio.c
+++ /dev/null
@@ -1,464 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/// \file
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-
-#include "pio.h"
-#include
-#include
-
-//------------------------------------------------------------------------------
-// Local Functions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Configures one or more pin(s) of a PIO controller as being controlled by
-/// peripheral A. Optionally, the corresponding internal pull-up(s) can be
-/// enabled.
-/// \param pio Pointer to a PIO controller.
-/// \param mask Bitmask of one or more pin(s) to configure.
-/// \param enablePullUp Indicates if the pin(s) internal pull-up shall be
-/// configured.
-//------------------------------------------------------------------------------
-static void PIO_SetPeripheralA(
- Pio *pio,
- unsigned int mask,
- unsigned char enablePullUp)
-{
- unsigned int abcdsr;
- // Disable interrupts on the pin(s)
- pio->PIO_IDR = mask;
-
- // Enable the pull-up(s) if necessary
- if (enablePullUp) {
- pio->PIO_PUER = mask;
- }
- else {
-
- pio->PIO_PUDR = mask;
- }
-
- abcdsr = pio->PIO_ABCDSR[0];
- pio->PIO_ABCDSR[0] &= (~mask & abcdsr);
- abcdsr = pio->PIO_ABCDSR[1];
- pio->PIO_ABCDSR[1] &= (~mask & abcdsr);
- pio->PIO_PDR = mask;
-}
-
-//------------------------------------------------------------------------------
-/// Configures one or more pin(s) of a PIO controller as being controlled by
-/// peripheral B. Optionally, the corresponding internal pull-up(s) can be
-/// enabled.
-/// \param pio Pointer to a PIO controller.
-/// \param mask Bitmask of one or more pin(s) to configure.
-/// \param enablePullUp Indicates if the pin(s) internal pull-up shall be
-/// configured.
-//------------------------------------------------------------------------------
-static void PIO_SetPeripheralB(
- Pio *pio,
- unsigned int mask,
- unsigned char enablePullUp)
-{
- unsigned int abcdsr;
- // Disable interrupts on the pin(s)
- pio->PIO_IDR = mask;
-
- // Enable the pull-up(s) if necessary
- if (enablePullUp) {
-
- pio->PIO_PUER = mask;
- }
- else {
-
- pio->PIO_PUDR = mask;
- }
-
- abcdsr = pio->PIO_ABCDSR[0];
- pio->PIO_ABCDSR[0] = (mask | abcdsr);
- abcdsr = pio->PIO_ABCDSR[1];
- pio->PIO_ABCDSR[1] &= (~mask & abcdsr);
-
- pio->PIO_PDR = mask;
-}
-
-//------------------------------------------------------------------------------
-/// Configures one or more pin(s) of a PIO controller as being controlled by
-/// peripheral C. Optionally, the corresponding internal pull-up(s) can be
-/// enabled.
-/// \param pio Pointer to a PIO controller.
-/// \param mask Bitmask of one or more pin(s) to configure.
-/// \param enablePullUp Indicates if the pin(s) internal pull-up shall be
-/// configured.
-//------------------------------------------------------------------------------
-static void PIO_SetPeripheralC(
- Pio *pio,
- unsigned int mask,
- unsigned char enablePullUp)
-{
- unsigned int abcdsr;
- // Disable interrupts on the pin(s)
- pio->PIO_IDR = mask;
-
- // Enable the pull-up(s) if necessary
- if (enablePullUp) {
-
- pio->PIO_PUER = mask;
- }
- else {
-
- pio->PIO_PUDR = mask;
- }
-
- abcdsr = pio->PIO_ABCDSR[0];
- pio->PIO_ABCDSR[0] &= (~mask & abcdsr);
- abcdsr = pio->PIO_ABCDSR[1];
- pio->PIO_ABCDSR[1] = (mask | abcdsr);
-
- pio->PIO_PDR = mask;
-}
-
-//------------------------------------------------------------------------------
-/// Configures one or more pin(s) of a PIO controller as being controlled by
-/// peripheral D. Optionally, the corresponding internal pull-up(s) can be
-/// enabled.
-/// \param pio Pointer to a PIO controller.
-/// \param mask Bitmask of one or more pin(s) to configure.
-/// \param enablePullUp Indicates if the pin(s) internal pull-up shall be
-/// configured.
-//------------------------------------------------------------------------------
-static void PIO_SetPeripheralD(
- Pio *pio,
- unsigned int mask,
- unsigned char enablePullUp)
-{
- unsigned int abcdsr;
- // Disable interrupts on the pin(s)
- pio->PIO_IDR = mask;
-
- // Enable the pull-up(s) if necessary
- if (enablePullUp) {
-
- pio->PIO_PUER = mask;
- }
- else {
-
- pio->PIO_PUDR = mask;
- }
-
- abcdsr = pio->PIO_ABCDSR[0];
- pio->PIO_ABCDSR[0] = (mask | abcdsr);
- abcdsr = pio->PIO_ABCDSR[1];
- pio->PIO_ABCDSR[1] = (mask | abcdsr);
-
- pio->PIO_PDR = mask;
-}
-
-//------------------------------------------------------------------------------
-/// Configures one or more pin(s) or a PIO controller as inputs. Optionally,
-/// the corresponding internal pull-up(s) and glitch filter(s) can be
-/// enabled.
-/// \param pio Pointer to a PIO controller.
-/// \param mask Bitmask indicating which pin(s) to configure as input(s).
-/// \param enablePullUp Indicates if the internal pull-up(s) must be enabled.
-/// \param enableFilter Indicates if the glitch filter(s) must be enabled.
-//------------------------------------------------------------------------------
-static void PIO_SetInput(
- Pio *pio,
- unsigned int mask,
- unsigned char attribute)
-{
- // Disable interrupts
- pio->PIO_IDR = mask;
-
- // Enable pull-up(s) if necessary
- if (attribute & PIO_PULLUP)
- pio->PIO_PUER = mask;
- else
- pio->PIO_PUDR = mask;
-
- // Enable de-glitch(s) if necessary
- if (attribute & PIO_DEGLITCH)
- pio->PIO_IFER = mask;
- else
- pio->PIO_IFDR = mask;
-
- // Enable de-bounce if necessary
- if (attribute & PIO_DEBOUNCE) {
- pio->PIO_DIFSR = mask;
- }
-
- // Configure pin as input
- pio->PIO_ODR = mask;
- pio->PIO_PER = mask;
-}
-
-//------------------------------------------------------------------------------
-/// Configures one or more pin(s) of a PIO controller as outputs, with the
-/// given default value. Optionally, the multi-drive feature can be enabled
-/// on the pin(s).
-/// \param pio Pointer to a PIO controller.
-/// \param mask Bitmask indicating which pin(s) to configure.
-/// \param defaultValue Default level on the pin(s).
-/// \param enableMultiDrive Indicates if the pin(s) shall be configured as
-/// open-drain.
-/// \param enablePullUp Indicates if the pin shall have its pull-up activated.
-//------------------------------------------------------------------------------
-static void PIO_SetOutput(
- Pio *pio,
- unsigned int mask,
- unsigned char defaultValue,
- unsigned char enableMultiDrive,
- unsigned char enablePullUp)
-{
- // Disable interrupts
- pio->PIO_IDR = mask;
-
- // Enable pull-up(s) if necessary
- if (enablePullUp) {
-
- pio->PIO_PUER = mask;
- }
- else {
-
- pio->PIO_PUDR = mask;
- }
-
- // Enable multi-drive if necessary
- if (enableMultiDrive) {
-
- pio->PIO_MDER = mask;
- }
- else {
-
- pio->PIO_MDDR = mask;
- }
-
- // Set default value
- if (defaultValue) {
-
- pio->PIO_SODR = mask;
- }
- else {
-
- pio->PIO_CODR = mask;
- }
-
- // Configure pin(s) as output(s)
- pio->PIO_OER = mask;
- pio->PIO_PER = mask;
-}
-
-//------------------------------------------------------------------------------
-/// Configures interrupt mode for input Pins
-/// \param pio Pointer to a PIO controller.
-/// \param mask Bitmask indicating which pin(s) to configure.
-/// \param additionnalItMode Enable Pio Additionnal It Mode.
-/// \param edgeMode Enable the edge mode.
-/// \param risingEdgeOrHighLevel Enable IT on rising edge or high level.
-//------------------------------------------------------------------------------
-static void PIO_SetInterrupt(
- Pio *pio,
- unsigned int mask,
- unsigned char additionnalItMode,
- unsigned char edgeMode,
- unsigned char risingEdgeOrHighLevel)
-{
- /* Configure the Interrupt mode in the PIO controller */
- if (additionnalItMode) {
- /* enable additional interrupt mode */
- pio->PIO_AIMER = mask;
-
- /* if bit field of selected pin is 1, set as Rising Edge/High level detection event */
- if (risingEdgeOrHighLevel)
- pio->PIO_REHLSR = mask;
- else
- pio->PIO_FELLSR = mask;
-
- /* if bit field of selected pin is 1, set as edge detection source */
- if (edgeMode)
- pio->PIO_ESR = mask;
- else
- pio->PIO_LSR = mask;
- } else {
- /* disable additional interrupt mode */
- pio->PIO_AIMDR = mask;
- }
-}
-
-//------------------------------------------------------------------------------
-// Global Functions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Configures a list of Pin instances, each of which can either hold a single
-/// pin or a group of pins, depending on the mask value; all pins are configured
-/// by this function. The size of the array must also be provided and is easily
-/// computed using PIO_LISTSIZE whenever its length is not known in advance.
-/// \param list Pointer to a list of Pin instances.
-/// \param size Size of the Pin list (calculated using PIO_LISTSIZE).
-/// \return 1 if the pins have been configured properly; otherwise 0.
-//------------------------------------------------------------------------------
-unsigned char PIO_Configure(const Pin *list, unsigned int size)
-{
- // Configure pins
- while (size > 0) {
-
- switch (list->type) {
-
- case PIO_PERIPH_A:
- PIO_SetPeripheralA(list->pio,
- list->mask,
- (list->attribute & PIO_PULLUP) ? 1 : 0);
- break;
-
- case PIO_PERIPH_B:
- PIO_SetPeripheralB(list->pio,
- list->mask,
- (list->attribute & PIO_PULLUP) ? 1 : 0);
- break;
-
- case PIO_PERIPH_C:
- PIO_SetPeripheralC(list->pio,
- list->mask,
- (list->attribute & PIO_PULLUP) ? 1 : 0);
- break;
-
- case PIO_PERIPH_D:
- PIO_SetPeripheralD(list->pio,
- list->mask,
- (list->attribute & PIO_PULLUP) ? 1 : 0);
- break;
- case PIO_INPUT:
- PMC_EnablePeripheral(list->id);
- PIO_SetInput(list->pio,
- list->mask,
- list->attribute);
- PIO_SetInterrupt(list->pio,
- list->mask,
- (list->attribute & PIO_IT_AIME) ? 1 : 0,
- (list->attribute & PIO_IT_EDGE) ? 1 : 0,
- (list->attribute & PIO_IT_RE_OR_HL) ? 1 : 0);
- break;
-
- case PIO_OUTPUT_0:
- case PIO_OUTPUT_1:
- PIO_SetOutput(list->pio,
- list->mask,
- (list->type == PIO_OUTPUT_1),
- (list->attribute & PIO_OPENDRAIN) ? 1 : 0,
- (list->attribute & PIO_PULLUP) ? 1 : 0);
- break;
-
- default: return 0;
- }
-
- list++;
- size--;
- }
-
- return 1;
-}
-
-//------------------------------------------------------------------------------
-/// Sets a high output level on all the PIOs defined in the given Pin instance.
-/// This has no immediate effects on PIOs that are not output, but the PIO
-/// controller will memorize the value they are changed to outputs.
-/// \param pin Pointer to a Pin instance describing one or more pins.
-//------------------------------------------------------------------------------
-void PIO_Set(const Pin *pin)
-{
- pin->pio->PIO_SODR = pin->mask;
-}
-
-//------------------------------------------------------------------------------
-/// Sets a low output level on all the PIOs defined in the given Pin instance.
-/// This has no immediate effects on PIOs that are not output, but the PIO
-/// controller will memorize the value they are changed to outputs.
-/// \param pin Pointer to a Pin instance describing one or more pins.
-//------------------------------------------------------------------------------
-void PIO_Clear(const Pin *pin)
-{
- pin->pio->PIO_CODR = pin->mask;
-}
-
-//------------------------------------------------------------------------------
-/// Returns 1 if one or more PIO of the given Pin instance currently have a high
-/// level; otherwise returns 0. This method returns the actual value that is
-/// being read on the pin. To return the supposed output value of a pin, use
-/// PIO_GetOutputDataStatus() instead.
-/// \param pin Pointer to a Pin instance describing one or more pins.
-/// \return 1 if the Pin instance contains at least one PIO that currently has
-/// a high level; otherwise 0.
-//------------------------------------------------------------------------------
-unsigned char PIO_Get(const Pin *pin)
-{
- unsigned int reg;
- if ((pin->type == PIO_OUTPUT_0) || (pin->type == PIO_OUTPUT_1)) {
-
- reg = pin->pio->PIO_ODSR;
- }
- else {
-
- reg = pin->pio->PIO_PDSR;
- }
-
- if ((reg & pin->mask) == 0) {
-
- return 0;
- }
- else {
-
- return 1;
- }
-}
-
-
-//------------------------------------------------------------------------------
-/// Returns 1 if one or more PIO of the given Pin are configured to output a
-/// high level (even if they are not output).
-/// To get the actual value of the pin, use PIO_Get() instead.
-/// \param pin Pointer to a Pin instance describing one or more pins.
-/// \return 1 if the Pin instance contains at least one PIO that is configured
-/// to output a high level; otherwise 0.
-//------------------------------------------------------------------------------
-unsigned char PIO_GetOutputDataStatus(const Pin *pin)
-{
- if ((pin->pio->PIO_ODSR & pin->mask) == 0) {
-
- return 0;
- }
- else {
-
- return 1;
- }
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio.h
deleted file mode 100644
index 52fd593b..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-/// \file
-///
-/// \par Purpose
-///
-/// This file provides a basic API for PIO configuration and usage of
-/// user-controlled pins. Please refer to the board.h file for a list of
-/// available pin definitions.
-///
-/// \par Usage
-///
-/// -# Define a constant pin description array such as the following one, using
-/// the existing definitions provided by the board.h file if possible:
-/// \code
-/// const Pin pPins[] = {PIN_USART0_TXD, PIN_USART0_RXD};
-/// \endcode
-/// Alternatively, it is possible to add new pins by provided the full Pin
-/// structure:
-/// \code
-/// // Pin instance to configure PA10 & PA11 as inputs with the internal
-/// // pull-up enabled.
-/// const Pin pPins = {
-/// (1 << 10) | (1 << 11),
-/// REG_PIOA,
-/// ID_PIOA,
-/// PIO_INPUT,
-/// PIO_PULLUP
-/// };
-/// \endcode
-/// -# Configure a pin array by calling PIO_Configure() with a pointer to the
-/// array and its size (which is computed using the PIO_LISTSIZE macro).
-/// -# Change and get the value of a user-controlled pin using the PIO_Set,
-/// PIO_Clear and PIO_Get methods.
-/// -# Get the level being currently output by a user-controlled pin configured
-/// as an output using PIO_GetOutputDataStatus().
-//------------------------------------------------------------------------------
-
-#ifndef PIO_H
-#define PIO_H
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-
-#include
-
-//------------------------------------------------------------------------------
-// Global Definitions
-//------------------------------------------------------------------------------
-
-/// The pin is controlled by the associated signal of peripheral A.
-#define PIO_PERIPH_A 0
-/// The pin is controlled by the associated signal of peripheral B.
-#define PIO_PERIPH_B 1
-/// The pin is controlled by the associated signal of peripheral C.
-#define PIO_PERIPH_C 2
-/// The pin is controlled by the associated signal of peripheral D.
-#define PIO_PERIPH_D 3
-/// The pin is an input.
-#define PIO_INPUT 4
-/// The pin is an output and has a default level of 0.
-#define PIO_OUTPUT_0 5
-/// The pin is an output and has a default level of 1.
-#define PIO_OUTPUT_1 6
-
-/// Default pin configuration (no attribute).
-#define PIO_DEFAULT (0 << 0)
-/// The internal pin pull-up is active.
-#define PIO_PULLUP (1 << 0)
-/// The internal glitch filter is active.
-#define PIO_DEGLITCH (1 << 1)
-/// The pin is open-drain.
-#define PIO_OPENDRAIN (1 << 2)
-
-/// The internal debouncing filter is active.
-#define PIO_DEBOUNCE (1 << 3)
-
-/// Enable additional interrupt modes.
-#define PIO_IT_AIME (1 << 4)
-
-/// Interrupt High Level/Rising Edge detection is active.
-#define PIO_IT_RE_OR_HL (1 << 5)
-/// Interrupt Edge detection is active.
-#define PIO_IT_EDGE (1 << 6)
-
-/// Low level interrupt is active
-#define PIO_IT_LOW_LEVEL (0 | 0 | PIO_IT_AIME)
-/// High level interrupt is active
-#define PIO_IT_HIGH_LEVEL (PIO_IT_RE_OR_HL | 0 | PIO_IT_AIME)
-/// Falling edge interrupt is active
-#define PIO_IT_FALL_EDGE (0 | PIO_IT_EDGE | PIO_IT_AIME)
-/// Rising edge interrupt is active
-#define PIO_IT_RISE_EDGE (PIO_IT_RE_OR_HL | PIO_IT_EDGE | PIO_IT_AIME)
-
-//------------------------------------------------------------------------------
-// Global Macros
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Calculates the size of an array of Pin instances. The array must be defined
-/// locally (i.e. not a pointer), otherwise the computation will not be correct.
-/// \param pPins Local array of Pin instances.
-/// \return Number of elements in array.
-//------------------------------------------------------------------------------
-#define PIO_LISTSIZE(pPins) (sizeof(pPins) / sizeof(Pin))
-
-//------------------------------------------------------------------------------
-// Global Types
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-/// Describes the type and attribute of one PIO pin or a group of similar pins.
-/// The #type# field can have the following values:
-/// - PIO_PERIPH_A
-/// - PIO_PERIPH_B
-/// - PIO_OUTPUT_0
-/// - PIO_OUTPUT_1
-/// - PIO_INPUT
-///
-/// The #attribute# field is a bitmask that can either be set to PIO_DEFAULt,
-/// or combine (using bitwise OR '|') any number of the following constants:
-/// - PIO_PULLUP
-/// - PIO_DEGLITCH
-/// - PIO_DEBOUNCE
-/// - PIO_OPENDRAIN
-/// - PIO_IT_LOW_LEVEL
-/// - PIO_IT_HIGH_LEVEL
-/// - PIO_IT_FALL_EDGE
-/// - PIO_IT_RISE_EDGE
-//------------------------------------------------------------------------------
-typedef struct {
-
- /// Bitmask indicating which pin(s) to configure.
- unsigned int mask;
- /// Pointer to the PIO controller which has the pin(s).
- Pio *pio;
- /// Peripheral ID of the PIO controller which has the pin(s).
- unsigned char id;
- /// Pin type.
- unsigned char type;
- /// Pin attribute.
- unsigned char attribute;
-} Pin;
-
-//------------------------------------------------------------------------------
-// Global Access Macros
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-/// Configures Glitch or Debouncing filter for input
-/// \param pin Pointer to a Pin instance describing one or more pins.
-/// \param cuttoff Cutt off frequency for debounce filter
-//------------------------------------------------------------------------------
-static inline void PIO_SetDebounceFilter(
- const Pin *pin,
- unsigned int cuttoff)
- {
- Pio *pio = pin->pio;
-
- pio->PIO_DIFSR = pin->mask;//set Debouncing, 0 bit field no effect
- pio->PIO_SCDR = ((32678/(2*(cuttoff))) - 1) & 0x3FFF;//the lowest 14 bits work
-}
-
-
-//------------------------------------------------------------------------------
-// Global Functions
-//------------------------------------------------------------------------------
-
-extern unsigned char PIO_Configure(const Pin *list, unsigned int size);
-
-extern void PIO_Set(const Pin *pin);
-
-extern void PIO_Clear(const Pin *pin);
-
-extern unsigned char PIO_Get(const Pin *pin);
-
-//extern unsigned int PIO_GetISR(const Pin *pin);
-
-extern unsigned char PIO_GetOutputDataStatus(const Pin *pin);
-
-extern void PIO_EnableDebounce(const Pin *pin, unsigned int clkDiv);
-
-#endif //#ifndef PIO_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio_it.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio_it.c
deleted file mode 100644
index e04a07c5..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio_it.c
+++ /dev/null
@@ -1,411 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/// \file
-
-/// Disable traces for this file
-#undef TRACE_LEVEL
-#define TRACE_LEVEL 0
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-
-#include "pio_it.h"
-#include "pio.h"
-#include
-#include
-#include
-#include
-#include
-
-//------------------------------------------------------------------------------
-// Local definitions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Local types
-//------------------------------------------------------------------------------
-/* Define WEAK attribute */
-#if defined ( __CC_ARM )
- #define WEAK __attribute__ ((weak))
-#elif defined ( __ICCARM__ )
- #define WEAK __weak
-#elif defined ( __GNUC__ )
- #define WEAK __attribute__ ((weak))
-#endif
-
-
-//------------------------------------------------------------------------------
-// Local variables
-//------------------------------------------------------------------------------
-typedef void (*PioHandler) (unsigned char id);
-
-/* Default PIO handlers defined as weak functions which have to be redefined by
- * the application */
-WEAK void PIOA_Irq0Handler(unsigned char id) {}
-WEAK void PIOA_Irq1Handler(unsigned char id) {}
-WEAK void PIOA_Irq2Handler(unsigned char id) {}
-WEAK void PIOA_Irq3Handler(unsigned char id) {}
-WEAK void PIOA_Irq4Handler(unsigned char id) {}
-WEAK void PIOA_Irq5Handler(unsigned char id) {}
-WEAK void PIOA_Irq6Handler(unsigned char id) {}
-WEAK void PIOA_Irq7Handler(unsigned char id) {}
-WEAK void PIOA_Irq8Handler(unsigned char id) {}
-WEAK void PIOA_Irq9Handler(unsigned char id) {}
-WEAK void PIOA_Irq10Handler(unsigned char id) {}
-WEAK void PIOA_Irq11Handler(unsigned char id) {}
-WEAK void PIOA_Irq12Handler(unsigned char id) {}
-WEAK void PIOA_Irq13Handler(unsigned char id) {}
-WEAK void PIOA_Irq14Handler(unsigned char id) {}
-WEAK void PIOA_Irq15Handler(unsigned char id) {}
-WEAK void PIOA_Irq16Handler(unsigned char id) {}
-WEAK void PIOA_Irq17Handler(unsigned char id) {}
-WEAK void PIOA_Irq18Handler(unsigned char id) {}
-WEAK void PIOA_Irq19Handler(unsigned char id) {}
-WEAK void PIOA_Irq20Handler(unsigned char id) {}
-WEAK void PIOA_Irq21Handler(unsigned char id) {}
-WEAK void PIOA_Irq22Handler(unsigned char id) {}
-WEAK void PIOA_Irq23Handler(unsigned char id) {}
-WEAK void PIOA_Irq24Handler(unsigned char id) {}
-WEAK void PIOA_Irq25Handler(unsigned char id) {}
-WEAK void PIOA_Irq26Handler(unsigned char id) {}
-WEAK void PIOA_Irq27Handler(unsigned char id) {}
-WEAK void PIOA_Irq28Handler(unsigned char id) {}
-WEAK void PIOA_Irq29Handler(unsigned char id) {}
-WEAK void PIOA_Irq30Handler(unsigned char id) {}
-WEAK void PIOA_Irq31Handler(unsigned char id) {}
-
-
-/** pioAHandlers records ISR routines for each PIO Id for PIO controller A */
-static const PioHandler pioAHandlers[32] = {
- (PioHandler) PIOA_Irq0Handler, /**< PA0 IT Handler */
- (PioHandler) PIOA_Irq1Handler, /**< PA1 IT Handler */
- (PioHandler) PIOA_Irq2Handler, /**< PA2 IT Handler */
- (PioHandler) PIOA_Irq3Handler, /**< PA3 IT Handler */
- (PioHandler) PIOA_Irq4Handler, /**< PA4 IT Handler */
- (PioHandler) PIOA_Irq5Handler, /**< PA5 IT Handler */
- (PioHandler) PIOA_Irq6Handler, /**< PA6 IT Handler */
- (PioHandler) PIOA_Irq7Handler, /**< PA7 IT Handler */
- (PioHandler) PIOA_Irq8Handler, /**< PA8 IT Handler */
- (PioHandler) PIOA_Irq9Handler, /**< PA9 IT Handler */
- (PioHandler) PIOA_Irq10Handler, /**< PA10 IT Handler */
- (PioHandler) PIOA_Irq11Handler, /**< PA11 IT Handler */
- (PioHandler) PIOA_Irq12Handler, /**< PA12 IT Handler */
- (PioHandler) PIOA_Irq13Handler, /**< PA13 IT Handler */
- (PioHandler) PIOA_Irq14Handler, /**< PA14 IT Handler */
- (PioHandler) PIOA_Irq15Handler, /**< PA15 IT Handler */
- (PioHandler) PIOA_Irq16Handler, /**< PA16 IT Handler */
- (PioHandler) PIOA_Irq17Handler, /**< PA17 IT Handler */
- (PioHandler) PIOA_Irq18Handler, /**< PA18 IT Handler */
- (PioHandler) PIOA_Irq19Handler, /**< PA19 IT Handler */
- (PioHandler) PIOA_Irq20Handler, /**< PA20 IT Handler */
- (PioHandler) PIOA_Irq21Handler, /**< PA21 IT Handler */
- (PioHandler) PIOA_Irq22Handler, /**< PA22 IT Handler */
- (PioHandler) PIOA_Irq23Handler, /**< PA23 IT Handler */
- (PioHandler) PIOA_Irq24Handler, /**< PA24 IT Handler */
- (PioHandler) PIOA_Irq25Handler, /**< PA25 IT Handler */
- (PioHandler) PIOA_Irq26Handler, /**< PA26 IT Handler */
- (PioHandler) PIOA_Irq27Handler, /**< PA27 IT Handler */
- (PioHandler) PIOA_Irq28Handler, /**< PA28 IT Handler */
- (PioHandler) PIOA_Irq29Handler, /**< PA29 IT Handler */
- (PioHandler) PIOA_Irq30Handler, /**< PA30 IT Handler */
- (PioHandler) PIOA_Irq31Handler /**< PA31 IT Handler */
-};
-
-/* Default PIO handlers defined as weak functions which have to be redefined by
- * the application */
-WEAK void PIOB_Irq0Handler(unsigned char id) {}
-WEAK void PIOB_Irq1Handler(unsigned char id) {}
-WEAK void PIOB_Irq2Handler(unsigned char id) {}
-WEAK void PIOB_Irq3Handler(unsigned char id) {}
-WEAK void PIOB_Irq4Handler(unsigned char id) {}
-WEAK void PIOB_Irq5Handler(unsigned char id) {}
-WEAK void PIOB_Irq6Handler(unsigned char id) {}
-WEAK void PIOB_Irq7Handler(unsigned char id) {}
-WEAK void PIOB_Irq8Handler(unsigned char id) {}
-WEAK void PIOB_Irq9Handler(unsigned char id) {}
-WEAK void PIOB_Irq10Handler(unsigned char id) {}
-WEAK void PIOB_Irq11Handler(unsigned char id) {}
-WEAK void PIOB_Irq12Handler(unsigned char id) {}
-WEAK void PIOB_Irq13Handler(unsigned char id) {}
-WEAK void PIOB_Irq14Handler(unsigned char id) {}
-WEAK void PIOB_Irq15Handler(unsigned char id) {}
-WEAK void PIOB_Irq16Handler(unsigned char id) {}
-WEAK void PIOB_Irq17Handler(unsigned char id) {}
-WEAK void PIOB_Irq18Handler(unsigned char id) {}
-WEAK void PIOB_Irq19Handler(unsigned char id) {}
-WEAK void PIOB_Irq20Handler(unsigned char id) {}
-WEAK void PIOB_Irq21Handler(unsigned char id) {}
-WEAK void PIOB_Irq22Handler(unsigned char id) {}
-WEAK void PIOB_Irq23Handler(unsigned char id) {}
-WEAK void PIOB_Irq24Handler(unsigned char id) {}
-WEAK void PIOB_Irq25Handler(unsigned char id) {}
-WEAK void PIOB_Irq26Handler(unsigned char id) {}
-WEAK void PIOB_Irq27Handler(unsigned char id) {}
-WEAK void PIOB_Irq28Handler(unsigned char id) {}
-WEAK void PIOB_Irq29Handler(unsigned char id) {}
-WEAK void PIOB_Irq30Handler(unsigned char id) {}
-WEAK void PIOB_Irq31Handler(unsigned char id) {}
-
-
-/** PIOBHandlers records ISR routines for each PIO Id for PIO controller A */
-static const PioHandler pioBHandlers[32] = {
- (PioHandler) PIOB_Irq0Handler, /**< PB0 IT Handler */
- (PioHandler) PIOB_Irq1Handler, /**< PB1 IT Handler */
- (PioHandler) PIOB_Irq2Handler, /**< PB2 IT Handler */
- (PioHandler) PIOB_Irq3Handler, /**< PB3 IT Handler */
- (PioHandler) PIOB_Irq4Handler, /**< PB4 IT Handler */
- (PioHandler) PIOB_Irq5Handler, /**< PB5 IT Handler */
- (PioHandler) PIOB_Irq6Handler, /**< PB6 IT Handler */
- (PioHandler) PIOB_Irq7Handler, /**< PB7 IT Handler */
- (PioHandler) PIOB_Irq8Handler, /**< PB8 IT Handler */
- (PioHandler) PIOB_Irq9Handler, /**< PB9 IT Handler */
- (PioHandler) PIOB_Irq10Handler, /**< PB10 IT Handler */
- (PioHandler) PIOB_Irq11Handler, /**< PB11 IT Handler */
- (PioHandler) PIOB_Irq12Handler, /**< PB12 IT Handler */
- (PioHandler) PIOB_Irq13Handler, /**< PB13 IT Handler */
- (PioHandler) PIOB_Irq14Handler, /**< PB14 IT Handler */
- (PioHandler) PIOB_Irq15Handler, /**< PB15 IT Handler */
- (PioHandler) PIOB_Irq16Handler, /**< PB16 IT Handler */
- (PioHandler) PIOB_Irq17Handler, /**< PB17 IT Handler */
- (PioHandler) PIOB_Irq18Handler, /**< PB18 IT Handler */
- (PioHandler) PIOB_Irq19Handler, /**< PB19 IT Handler */
- (PioHandler) PIOB_Irq20Handler, /**< PB20 IT Handler */
- (PioHandler) PIOB_Irq21Handler, /**< PB21 IT Handler */
- (PioHandler) PIOB_Irq22Handler, /**< PB22 IT Handler */
- (PioHandler) PIOB_Irq23Handler, /**< PB23 IT Handler */
- (PioHandler) PIOB_Irq24Handler, /**< PB24 IT Handler */
- (PioHandler) PIOB_Irq25Handler, /**< PB25 IT Handler */
- (PioHandler) PIOB_Irq26Handler, /**< PB26 IT Handler */
- (PioHandler) PIOB_Irq27Handler, /**< PB27 IT Handler */
- (PioHandler) PIOB_Irq28Handler, /**< PB28 IT Handler */
- (PioHandler) PIOB_Irq29Handler, /**< PB29 IT Handler */
- (PioHandler) PIOB_Irq30Handler, /**< PB30 IT Handler */
- (PioHandler) PIOB_Irq31Handler /**< PB31 IT Handler */
-};
-
-/* Default PIO handlers defined as weak functions which have to be redefined by
- * the application */
-WEAK void PIOC_Irq0Handler(unsigned char id) {}
-WEAK void PIOC_Irq1Handler(unsigned char id) {}
-WEAK void PIOC_Irq2Handler(unsigned char id) {}
-WEAK void PIOC_Irq3Handler(unsigned char id) {}
-WEAK void PIOC_Irq4Handler(unsigned char id) {}
-WEAK void PIOC_Irq5Handler(unsigned char id) {}
-WEAK void PIOC_Irq6Handler(unsigned char id) {}
-WEAK void PIOC_Irq7Handler(unsigned char id) {}
-WEAK void PIOC_Irq8Handler(unsigned char id) {}
-WEAK void PIOC_Irq9Handler(unsigned char id) {}
-WEAK void PIOC_Irq10Handler(unsigned char id) {}
-WEAK void PIOC_Irq11Handler(unsigned char id) {}
-WEAK void PIOC_Irq12Handler(unsigned char id) {}
-WEAK void PIOC_Irq13Handler(unsigned char id) {}
-WEAK void PIOC_Irq14Handler(unsigned char id) {}
-WEAK void PIOC_Irq15Handler(unsigned char id) {}
-WEAK void PIOC_Irq16Handler(unsigned char id) {}
-WEAK void PIOC_Irq17Handler(unsigned char id) {}
-WEAK void PIOC_Irq18Handler(unsigned char id) {}
-WEAK void PIOC_Irq19Handler(unsigned char id) {}
-WEAK void PIOC_Irq20Handler(unsigned char id) {}
-WEAK void PIOC_Irq21Handler(unsigned char id) {}
-WEAK void PIOC_Irq22Handler(unsigned char id) {}
-WEAK void PIOC_Irq23Handler(unsigned char id) {}
-WEAK void PIOC_Irq24Handler(unsigned char id) {}
-WEAK void PIOC_Irq25Handler(unsigned char id) {}
-WEAK void PIOC_Irq26Handler(unsigned char id) {}
-WEAK void PIOC_Irq27Handler(unsigned char id) {}
-WEAK void PIOC_Irq28Handler(unsigned char id) {}
-WEAK void PIOC_Irq29Handler(unsigned char id) {}
-WEAK void PIOC_Irq30Handler(unsigned char id) {}
-WEAK void PIOC_Irq31Handler(unsigned char id) {}
-
-
-/** PIOCHandlers records ISR routines for each PIO Id for PIO controller A */
-static const PioHandler pioCHandlers[32] = {
- (PioHandler) PIOC_Irq0Handler, /**< PC0 IT Handler */
- (PioHandler) PIOC_Irq1Handler, /**< PC1 IT Handler */
- (PioHandler) PIOC_Irq2Handler, /**< PC2 IT Handler */
- (PioHandler) PIOC_Irq3Handler, /**< PC3 IT Handler */
- (PioHandler) PIOC_Irq4Handler, /**< PC4 IT Handler */
- (PioHandler) PIOC_Irq5Handler, /**< PC5 IT Handler */
- (PioHandler) PIOC_Irq6Handler, /**< PC6 IT Handler */
- (PioHandler) PIOC_Irq7Handler, /**< PC7 IT Handler */
- (PioHandler) PIOC_Irq8Handler, /**< PC8 IT Handler */
- (PioHandler) PIOC_Irq9Handler, /**< PC9 IT Handler */
- (PioHandler) PIOC_Irq10Handler, /**< PC10 IT Handler */
- (PioHandler) PIOC_Irq11Handler, /**< PC11 IT Handler */
- (PioHandler) PIOC_Irq12Handler, /**< PC12 IT Handler */
- (PioHandler) PIOC_Irq13Handler, /**< PC13 IT Handler */
- (PioHandler) PIOC_Irq14Handler, /**< PC14 IT Handler */
- (PioHandler) PIOC_Irq15Handler, /**< PC15 IT Handler */
- (PioHandler) PIOC_Irq16Handler, /**< PC16 IT Handler */
- (PioHandler) PIOC_Irq17Handler, /**< PC17 IT Handler */
- (PioHandler) PIOC_Irq18Handler, /**< PC18 IT Handler */
- (PioHandler) PIOC_Irq19Handler, /**< PC19 IT Handler */
- (PioHandler) PIOC_Irq20Handler, /**< PC20 IT Handler */
- (PioHandler) PIOC_Irq21Handler, /**< PC21 IT Handler */
- (PioHandler) PIOC_Irq22Handler, /**< PC22 IT Handler */
- (PioHandler) PIOC_Irq23Handler, /**< PC23 IT Handler */
- (PioHandler) PIOC_Irq24Handler, /**< PC24 IT Handler */
- (PioHandler) PIOC_Irq25Handler, /**< PC25 IT Handler */
- (PioHandler) PIOC_Irq26Handler, /**< PC26 IT Handler */
- (PioHandler) PIOC_Irq27Handler, /**< PC27 IT Handler */
- (PioHandler) PIOC_Irq28Handler, /**< PC28 IT Handler */
- (PioHandler) PIOC_Irq29Handler, /**< PC29 IT Handler */
- (PioHandler) PIOC_Irq30Handler, /**< PC30 IT Handler */
- (PioHandler) PIOC_Irq31Handler /**< PC31 IT Handler */
-};
-
-//------------------------------------------------------------------------------
-/// \brief Generic PIO Handler.
-/// The NVIC branches to the PIOx_IrqHandler() registered in exeption.c
-/// PIOx_IrqHandler() invokes PIO_IrqHandler which scans which id has triggered
-/// an interrupt and call the corresponding routine for the Id (<=> for the pin)
-/// \param pPio PIO controller base address.
-/// \param pPioHandlers Constant table which contains IT routines for each PIO Id
-//------------------------------------------------------------------------------
-static void PIO_IrqHandler(Pio *pPio, const PioHandler *pPioHandlers)
-{
- unsigned int status, id;
-
- status = pPio->PIO_ISR;
- status &= pPio->PIO_IMR;
-
- for (id = 0; id < 32; ++id) {
- if (status & (1 << id)) {
- pPioHandlers[id](id);
- }
- }
-
-}
-
-//------------------------------------------------------------------------------
-// Global functions
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-/// \brief Parallel IO Controller A interrupt handler
-/// Redefined PIOA interrupt handler for NVIC interrupt table.
-//------------------------------------------------------------------------------
-void PIOA_IrqHandler(void)
-{
- PIO_IrqHandler(PIOA, pioAHandlers);
-}
-
-//------------------------------------------------------------------------------
-/// \brief Parallel IO Controller B interrupt handler
-/// Redefined PIOB interrupt handler for NVIC interrupt table.
-//------------------------------------------------------------------------------
-void PIOB_IrqHandler(void)
-{
- PIO_IrqHandler(PIOB, pioBHandlers);
-}
-
-//------------------------------------------------------------------------------
-/// \brief Parallel IO Controller C interrupt handler
-/// Redefined PIOC interrupt handler for NVIC interrupt table.
-//------------------------------------------------------------------------------
-void PIOC_IrqHandler(void)
-{
- PIO_IrqHandler(PIOC, pioCHandlers);
-}
-
-//------------------------------------------------------------------------------
-/// Enables the given interrupt source. The status
-/// register of the corresponding PIO controller is cleared prior to enabling
-/// the interrupt.
-/// \param pPin Interrupt source to enable.
-//------------------------------------------------------------------------------
-void PIO_EnableIt(const Pin *pPin)
-{
- Pio* pio = pPin->pio;
- TRACE_DEBUG("PIO_EnableIt()\n\r");
-
-// SANITY_CHECK(pPin);
-
- /* Enable the interrupt in the PIO controller */
- pio->PIO_ISR;
- pio->PIO_IER = pPin->mask;
-
-
-}
-
-//------------------------------------------------------------------------------
-/// Disables a given interrupt source, with no added side effects.
-/// \param pPin Interrupt source to disable.
-//------------------------------------------------------------------------------
-void PIO_DisableIt(const Pin *pPin)
-{
- Pio* pio = pPin->pio;
- SANITY_CHECK(pPin);
-
- TRACE_DEBUG("PIO_DisableIt()\n\r");
-
- /* Disable the interrupt in the PIO controller */
- pio->PIO_IDR = pPin->mask;
-}
-
-//------------------------------------------------------------------------------
-/// \brief Initializes the PIO interrupt management logic
-/// The desired priority of PIO interrupts must be provided.
-/// Calling this function multiple times result in the reset of currently
-/// configured interrupts.
-/// \param priority PIO controller interrupts priority.
-//------------------------------------------------------------------------------
-void PIO_InitializeInterrupts(unsigned int priority)
-{
- TRACE_DEBUG("PIO_Initialize()\n\r");
-
- // Configure PIO interrupt sources
- TRACE_DEBUG("PIO_Initialize: Configuring PIOA\n\r");
- PIOA->PIO_ISR;
- PIOA->PIO_IDR = 0xFFFFFFFF;
- NVIC_DisableIRQ(PIOA_IRQn);
- NVIC_ClearPendingIRQ(PIOA_IRQn);
- NVIC_SetPriority(PIOA_IRQn, priority);
- NVIC_EnableIRQ(PIOA_IRQn);
-
- TRACE_DEBUG("PIO_Initialize: Configuring PIOB\n\r");
- PIOB->PIO_ISR;
- PIOB->PIO_IDR = 0xFFFFFFFF;
- NVIC_DisableIRQ(PIOB_IRQn);
- NVIC_ClearPendingIRQ(PIOB_IRQn);
- NVIC_SetPriority(PIOB_IRQn, priority);
- NVIC_EnableIRQ(PIOB_IRQn);
-
- TRACE_DEBUG("PIO_Initialize: Configuring PIOC\n\r");
- PIOC->PIO_ISR;
- PIOC->PIO_IDR = 0xFFFFFFFF;
- NVIC_DisableIRQ(PIOC_IRQn);
- NVIC_ClearPendingIRQ(PIOC_IRQn);
- NVIC_SetPriority(PIOC_IRQn, priority);
- NVIC_EnableIRQ(PIOC_IRQn);
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio_it.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio_it.h
deleted file mode 100644
index cc44903a..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio_it.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-/// \file
-///
-/// \par Purpose
-///
-/// Configuration and handling of interrupts on PIO status changes. The API
-/// provided here have several advantages over the traditional PIO interrupt
-/// configuration approach:
-/// - It is highly portable
-/// - It automatically demultiplexes interrupts when multiples pins have been
-/// configured on a single PIO controller
-/// - It allows a group of pins to share the same interrupt
-///
-/// However, it also has several minor drawbacks that may prevent from using it
-/// in particular applications:
-/// - It enables the clocks of all PIO controllers
-/// - PIO controllers all share the same interrupt handler, which does the
-/// demultiplexing and can be slower than direct configuration
-/// - It reserves space for a fixed number of interrupts, which can be
-/// increased by modifying the appropriate constant in pio_it.c.
-///
-/// \par Usage
-///
-/// -# Initialize the PIO interrupt mechanism using PIO_InitializeInterrupts()
-/// with the desired priority (0 ... 7).
-/// -# Configure a status change interrupt on one or more pin(s) with
-/// PIO_ConfigureIt().
-/// -# Enable & disable interrupts on pins using PIO_EnableIt() and
-/// PIO_DisableIt().
-//------------------------------------------------------------------------------
-
-#ifndef PIO_IT_H
-#define PIO_IT_H
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-
-#include "pio.h"
-
-//------------------------------------------------------------------------------
-// Global functions
-//------------------------------------------------------------------------------
-
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/// \file
-
-/// Disable traces for this file
-#undef TRACE_LEVEL
-#define TRACE_LEVEL 0
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-
-#include "pio_it.h"
-#include "pio.h"
-
-//------------------------------------------------------------------------------
-/// \brief Parallel IO Controller A interrupt handler
-/// Redefined PIOA interrupt handler for NVIC interrupt table.
-//------------------------------------------------------------------------------
-extern void PIOA_IrqHandler(void);
-//------------------------------------------------------------------------------
-/// \brief Parallel IO Controller B interrupt handler
-/// Redefined PIOB interrupt handler for NVIC interrupt table.
-//------------------------------------------------------------------------------
-extern void PIOB_IrqHandler(void);
-//------------------------------------------------------------------------------
-/// \brief Parallel IO Controller C interrupt handler
-/// Redefined PIOC interrupt handler for NVIC interrupt table.
-//------------------------------------------------------------------------------
-extern void PIOC_IrqHandler(void);
-//------------------------------------------------------------------------------
-/// Configures and enables the given interrupt source. The status
-/// register of the corresponding PIO controller is cleared prior to enabling
-/// the interrupt.
-/// \param pPin Interrupt source to enable.
-//------------------------------------------------------------------------------
-extern void PIO_EnableIt(const Pin *pPin);
-//------------------------------------------------------------------------------
-/// Disables a given interrupt source, with no added side effects.
-/// \param pPin Interrupt source to disable.
-//------------------------------------------------------------------------------
-extern void PIO_DisableIt(const Pin *pPin);
-//------------------------------------------------------------------------------
-/// \brief Initializes the PIO interrupt management logic
-/// The desired priority of PIO interrupts must be provided.
-/// Calling this function multiple times result in the reset of currently
-/// configured interrupts.
-/// \param priority PIO controller interrupts priority.
-//------------------------------------------------------------------------------
-extern void PIO_InitializeInterrupts(unsigned int priority);
-
-#endif //#ifndef PIO_IT_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio_keypad.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio_keypad.c
deleted file mode 100644
index e0fad267..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio_keypad.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-
-#include
-#include "pio.h"
-#include "pio_keypad.h"
-
-
-//------------------------------------------------------------------------------
-// Global Functions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Configures keypad controller
-/// \param pPIO Pointer to a PIO instance
-/// \param config Configuration data for given pin,see head file for detail
-//------------------------------------------------------------------------------
-void PIO_KeyPadConfig(AT91S_PIO *pPIO, KeyPadConfig *config)
-{
- //enable/disable keypad controller
- pPIO->PIO_KER = config->enable;
-
- //if enable, set keypad matrix and debouncing
- if(config->enable == TRUE) {
- //set key matrix
- pPIO->PIO_KRCR = (config->row | config->col<<8) ;
-
- //set debouncing
- pPIO->PIO_KDR = config->debouncing;
-
- }
-}
-
-
-//------------------------------------------------------------------------------
-/// Get Key Press/Release status
-/// \param pPIO Pointer to a PIO instance
-/// \param event Pointer to a instance of KeyEvent for storing keypad status
-//------------------------------------------------------------------------------
-void PIO_GetKeyStatus(AT91S_PIO *pPIO, KeyEvent *event)
-{
- int i,j;
-
- //get key press event
- event->kdEvent.press = (pPIO->KSR&0x1)?TRUE:FALSE;
- event->kdEvent.keyPressNum = (pPIO->KSR>>8)&0x3;
- j=event->kdEvent.keyPressNum+1;
- for(i=0; ikdEvent.preKeyMatrix[i].row = ((pPIO->KKPR) >> (8*i)) & 0x7;
- event->kdEvent.preKeyMatrix[i].col = ((pPIO->KKPR) >> (8*i+4)) & 0x7;
- }
-
- //get key release event
- event->kuEvent.release = ((pPIO->KSR>>1) & 0x1)?TRUE:FALSE;
- event->kuEvent.keyRelNum = (pPIO->KSR>>16)&0x3;
- j=event->kdEvent.keyPressNum+1;
- for(i=0;ikuEvent.relKeyMatrix[i].row = ((pPIO->KKRR) >> (8*i)) & 0x7;
- event->kuEvent.relKeyMatrix[i].col = ((pPIO->KKRR) >> (8*i+4)) & 0x7;
- }
-
-}
-
-
-//------------------------------------------------------------------------------
-/// Enable keypad interrupt as Key Press Interrupt or Key Release Interrupt or both
-/// \param pPIO Pointer to a PIO instance
-/// \param mode Select key interrupt mode to enable,
-/// 0x1 Key Press Interrupt
-/// 0x2 Key Release Interrupt
-/// 0x3 both of two type
-//------------------------------------------------------------------------------
-void PIO_KeypadEnableIt(AT91S_PIO *pPIO, unsigned int mode)
-{
- switch(mode){
- case 1:PIO_KeyPadEnableKPIt(pPIO);
- break;
-
- case 2:PIO_KeyPadEnableKRIt(pPIO);
- break;
-
- case 3:PIO_KeyPadEnableKPIt(pPIO);
- PIO_KeyPadEnableKRIt(pPIO);
- break;
-
- default:break;
- }
-
-}
-
-//------------------------------------------------------------------------------
-/// Disable Key Press Interrupt or Key Release Interrupt or both of them
-/// \param pPIO Pointer to a PIO instance
-/// \param mode Select key interrupt mode to disable,
-/// 0x1 Key Press Interrupt
-/// 0x2 Key Release Interrupt
-/// 0x3 both of two type
-//------------------------------------------------------------------------------
-void PIO_KeypadDisableIt(AT91S_PIO *pPIO, unsigned int mode)
-{
- switch(mode){
- case 1:PIO_KeyPadDisableKPIt(pPIO);
- break;
-
- case 2:PIO_KeyPadDisableKRIt(pPIO);
- break;
-
- case 3:PIO_KeyPadDisableKPIt(pPIO);
- PIO_KeyPadDisableKRIt(pPIO);
- break;
-
- default:break;
- }
-
-}
-
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio_keypad.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio_keypad.h
deleted file mode 100644
index 54021f6b..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio_keypad.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-#ifndef PIO_KEYPAD_H
-#define PIO_KEYPAD_H
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-
-#include
-
-//------------------------------------------------------------------------------
-// Global Definitions
-//------------------------------------------------------------------------------
-
-
-
-
-//------------------------------------------------------------------------------
-// Global Macros
-//------------------------------------------------------------------------------
-//enable keypad press interrupt
-#define PIO_KeyPadEnableKPIt(pPIO) ((pPIO)->KIER = 1<<0)
-
-//enable keypad release interrupt
-#define PIO_KeyPadEnableKRIt(pPIO) ((pPIO)->KIER = 1<<1)
-
-//disable keypad press interrupt
-#define PIO_KeyPadDisableKPIt(pPIO) ((pPIO)->KIDR = 1<<0)
-
-//disable keypad release interrupt
-#define PIO_KeyPadDisableKRIt(pPIO) ((pPIO)->KIDR = 1<<1)
-
-//enable keypad controller interrupt
-#define PIO_KeyPadEnableIt(pPIO, mode) {switch(mode):\
- case 1:PIO_KeyPadEnableKPIt(pPIO);break;\
- case 2:PIO_KeyPadEnableKRIt(pPIO);break;\
- case 3:PIO_KeyPadEnableKPIt(pPIO);\
- PIO_KeyPadEnableKRIt(pPIO);break;\
- default:break;\
- }
-
-//disable keypad controller interrupt
-#define PIO_KeyPadDisableIt(pPIO, mode) {switch(mode):\
- case 1:PIO_KeyPadDisableKPIt(pPIO);break;\
- case 2:PIO_KeyPadDisableKRIt(pPIO);break;\
- case 3:PIO_KeyPadDisableKPIt(pPIO);\
- PIO_KeyPadDisableKRIt(pPIO);break;\
- default:break;\
- }
-
-//get keypad controller interrupt mask
-#define PIO_KeyPadGetItMask(pPIO) ((pPIO)->PIO_KIMR)
-
-
-//------------------------------------------------------------------------------
-/// Calculates the size of an array of Pin instances. The array must be defined
-/// locally (i.e. not a pointer), otherwise the computation will not be correct.
-/// \param pPins Local array of Pin instances.
-/// \return Number of elements in array.
-//------------------------------------------------------------------------------
-#define PIO_LISTSIZE(pPins) (sizeof(pPins) / sizeof(Pin))
-
-//------------------------------------------------------------------------------
-// Global Types
-//------------------------------------------------------------------------------
-typedef enum {
- FALSE,
- TRUE
-} bool;
-
-typedef struct _KeyPadConfig {
- bool enable;//keypad controller enable or disable
- unsigned char col:3;//config column size
- unsigned char row:3;//config row size
- unsigned int debouncing;//config debouncing
-} KeyPadConfig;
-
-
-typedef struct _KeyColRow {
- unsigned char row:3;
- unsigned char col:3;
-} KeyColRow;
-
-
-typedef struct _KeyDownEvent {
- bool press;//at least 1 pressed key detected, or 0
- unsigned char keyPressNum;//simultaneously pressed key number
- KeyColRow preKeyMatrix[4];//pressed key matrix
-} KeyDownEvent;
-
-
-
-typedef struct _KeyUpEvent {
- bool release;//at least 1 released key detected, or 0
- unsigned char keyRelNum;//simultaneously released key number
- KeyColRow relKeyMatrix[4];//released key matrix
-} KeyUpEvent;
-
-
-
-typedef struct _KeyEvent {
- KeyDownEvent kdEvent;
- KeyUpEvent kuEvent;
-} KeyEvent;
-
-//------------------------------------------------------------------------------
-// Global Access Macros
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Global Functions
-//------------------------------------------------------------------------------
-
-void PIO_KeyPadConfig(AT91S_PIO *pPIO, KeyPadConfig *config);
-
-void PIO_GetKeyStatus(AT91S_PIO *pPIO, KeyEvent *event);
-
-void PIO_KeypadEnableIt(AT91S_PIO *pio, unsigned int mode);
-
-void PIO_KeypadDisableIt(AT91S_PIO *pio, unsigned int mode);
-
-
-#endif //#ifndef PIO_KEYPAD_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pmc/pmc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pmc/pmc.c
deleted file mode 100644
index 2c72eff3..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pmc/pmc.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include "pmc.h"
-#include
-#include
-
-//------------------------------------------------------------------------------
-// Local definitions
-//------------------------------------------------------------------------------
-#define MASK_STATUS0 0xFFFFFFFC
-#define MASK_STATUS1 0xFFFFFFFF
-
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief Enables the clock of a peripheral. The peripheral ID is used
- * to identify which peripheral is targetted.
- * \note The ID must NOT be shifted (i.e. 1 << ID_xxx).
- * \param id Peripheral ID (ID_xxx).
- */
-void PMC_EnablePeripheral(unsigned int id)
-{
- SANITY_CHECK(id < 35);
- if (id < 32) {
- if ((PMC->PMC_PCSR0 & (1 << id)) == (1 << id)) {
-
- TRACE_DEBUG("PMC_EnablePeripheral: clock of peripheral" " %u is already enabled\n\r", id);
- }
- else {
- PMC->PMC_PCER0 = 1 << id;
- }
- }
- else {
- id -= 32;
- if ((PMC->PMC_PCSR1 & (1 << id)) == (1 << id)) {
-
- TRACE_DEBUG("PMC_EnablePeripheral: clock of peripheral" " %u is already enabled\n\r", id + 32);
- }
- else {
- PMC->PMC_PCER1 = 1 << id;
- }
- }
-}
-
-/**
- * \brief Disables the clock of a peripheral. The peripheral ID is used
- * to identify which peripheral is targetted.
- * \note The ID must NOT be shifted (i.e. 1 << ID_xxx).
- * \param id Peripheral ID (ID_xxx).
- */
-void PMC_DisablePeripheral(unsigned int id)
-{
- SANITY_CHECK(id < 35);
- if (id < 32) {
- if ((PMC->PMC_PCSR0 & (1 << id)) != (1 << id)) {
- TRACE_DEBUG("PMC_DisablePeripheral: clock of peripheral" " %u is not enabled\n\r", id);
- }
- else {
- PMC->PMC_PCDR0 = 1 << id;
- }
- }
- else {
- id -= 32;
- if ((PMC->PMC_PCSR1 & (1 << id)) != (1 << id)) {
- TRACE_DEBUG("PMC_DisablePeripheral: clock of peripheral" " %u is not enabled\n\r", id + 32);
- }
- else {
- PMC->PMC_PCDR1 = 1 << id;
- }
- }
-}
-
-/**
- * \brief Enable all the periph clock via PMC
- */
-void PMC_EnableAllPeripherals(void)
-{
- PMC->PMC_PCER0 = MASK_STATUS0;
- while( (PMC->PMC_PCSR0 & MASK_STATUS0) != MASK_STATUS0);
- PMC->PMC_PCER1 = MASK_STATUS1;
- while( (PMC->PMC_PCSR1 & MASK_STATUS1) != MASK_STATUS1);
- TRACE_DEBUG("Enable all periph clocks\n\r");
-}
-/**
- * \brief Disable all the periph clock via PMC
- */
-void PMC_DisableAllPeripherals(void)
-{
- PMC->PMC_PCDR0 = MASK_STATUS0;
- while((PMC->PMC_PCSR0 & MASK_STATUS0) != 0);
- PMC->PMC_PCDR1 = MASK_STATUS1;
- while((PMC->PMC_PCSR1 & MASK_STATUS1) != 0);
- TRACE_DEBUG("Disable all periph clocks\n\r");
-}
-
-/**
- * \brief Get Periph Status for the given peripheral ID.
- * \param id Peripheral ID (ID_xxx).
- */
-unsigned int PMC_IsPeriphEnabled(unsigned int id)
-{
- SANITY_CHECK(id < 35);
- if (id < 32) {
- return (PMC->PMC_PCSR0 & (1 << id));
- }
- else {
- return (PMC->PMC_PCSR1 & (1 << (id - 32)));
- }
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pmc/pmc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pmc/pmc.h
deleted file mode 100644
index 0e5bd33e..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pmc/pmc.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-#ifndef PMC_H
-#define PMC_H
-
-//------------------------------------------------------------------------------
-// Global functions
-//------------------------------------------------------------------------------
-
-#if defined(at91sam7l64) || defined(at91sam7l128)
-extern void PMC_SetFastWakeUpInputs(unsigned int inputs);
-extern void PMC_DisableMainOscillator(void);
-extern
-#ifdef __ICCARM__
-__ramfunc
-#endif //__ICCARM__
-void PMC_DisableMainOscillatorForWaitMode(void);
-#endif // at91sam7l64 at91sam7l128
-
-extern void PMC_DisableProcessorClock(void);
-extern void PMC_EnablePeripheral(unsigned int id);
-extern void PMC_DisablePeripheral(unsigned int id);
-extern void PMC_CPUInIdleMode(void);
-
-
-extern void PMC_EnableAllPeripherals(void);
-
-extern void PMC_DisableAllPeripherals(void);
-
-extern unsigned int PMC_IsAllPeriphEnabled(void);
-
-extern unsigned int PMC_IsPeriphEnabled(unsigned int id);
-
-#endif //#ifndef PMC_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pwmc/pwmc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pwmc/pwmc.c
deleted file mode 100644
index 406a5c8a..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pwmc/pwmc.c
+++ /dev/null
@@ -1,648 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/** \addtogroup pwm_module Working with PWM
- * The PWM driver provides the interface to configure and use the PWM
- * peripheral.
- *
- * The PWM macrocell controls square output waveforms of 4 channels.
- * Characteristics of output waveforms such as period, duty-cycle,
- * dead-time can be configured.\n
- * Some of PWM channels can be linked together as synchronous channel and
- * duty-cycle of synchronous channels can be updated by PDC automaticly.
- *
- * Before enabling the channels, they must have been configured first.
- * The main settings include:
- *
- *
Configuration of the clock generator.
- *
Selection of the clock for each channel.
- *
Configuration of output waveform characteristics, such as period, duty-cycle etc.
- *
Configuration for synchronous channels if needed.
- * - Selection of the synchronous channels.
- * - Selection of the moment when the WRDY flag and the corresponding PDC
- * transfer request are set (PTRM and PTRCS in the PWM_SCM register).
- * - Configuration of the update mode (UPDM in the PWM_SCM register).
- * - Configuration of the update period (UPR in the PWM_SCUP register).
- *
- *
- * After the channels is enabled, the user must use respective update registers
- * to change the wave characteristics to prevent unexpected output waveform.
- * i.e. PWM_CDTYUPDx register should be used if user want to change duty-cycle
- * when the channel is enabled.
- *
- * For more accurate information, please look at the PWM section of the
- * Datasheet.
- *
- * Related files :\n
- * \ref pwmc.c\n
- * \ref pwmc.h.\n
- */
-/*@{*/
-/*@}*/
-
-/**
- * \file
- *
- * Implementation of the Pulse Width Modulation Controller (PWM) peripheral.
- *
- */
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-/* These headers were introduced in C99 by working group ISO/IEC JTC1/SC22/WG14. */
-#include
-
-#include "pwmc.h"
-#include
-#include
-#include
-
-/*----------------------------------------------------------------------------
- * Local functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief Finds a prescaler/divisor couple to generate the desired frequency
- * from MCK.
- *
- * Returns the value to enter in PWM_CLK or 0 if the configuration cannot be
- * met.
- *
- * \param frequency Desired frequency in Hz.
- * \param mck Master clock frequency in Hz.
- */
-static uint16_t FindClockConfiguration(
- uint32_t frequency,
- uint32_t mck)
-{
- uint32_t divisors[11] = {1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024};
- uint8_t divisor = 0;
- uint32_t prescaler;
-
- SANITY_CHECK(frequency < mck);
-
- /* Find prescaler and divisor values */
- prescaler = (mck / divisors[divisor]) / frequency;
- while ((prescaler > 255) && (divisor < 11)) {
-
- divisor++;
- prescaler = (mck / divisors[divisor]) / frequency;
- }
-
- /* Return result */
- if (divisor < 11) {
-
- TRACE_DEBUG("Found divisor=%u and prescaler=%u for freq=%uHz\n\r",
- divisors[divisor], prescaler, frequency);
- return prescaler | (divisor << 8);
- }
- else {
-
- return 0;
- }
-}
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief Configures PWM a channel with the given parameters, basic configure function.
- *
- * The PWM controller must have been clocked in the PMC prior to calling this
- * function.
- * Beware: this function disables the channel. It waits until disable is effective.
- *
- * \param channel Channel number.
- * \param prescaler Channel prescaler.
- * \param alignment Channel alignment.
- * \param polarity Channel polarity.
- */
-void PWMC_ConfigureChannel(
- uint8_t channel,
- uint32_t prescaler,
- uint32_t alignment,
- uint32_t polarity)
-{
- SANITY_CHECK(prescaler < PWM_CMR0_CPRE_MCKB);
- SANITY_CHECK((alignment & ~PWM_CMR0_CALG) == 0);
- SANITY_CHECK((polarity & ~PWM_CMR0_CPOL) == 0);
-
- /* Disable channel (effective at the end of the current period) */
- if ((PWM->PWM_SR & (1 << channel)) != 0) {
- PWM->PWM_DIS = 1 << channel;
- while ((PWM->PWM_SR & (1 << channel)) != 0);
- }
-
- /* Configure channel */
- PWM->PWM_CH_NUM[channel].PWM_CMR = prescaler | alignment | polarity;
-}
-
-/**
- * \brief Configures PWM a channel with the given parameters, extend configure function.
- *
- * The PWM controller must have been clocked in the PMC prior to calling this
- * function.
- * Beware: this function disables the channel. It waits until disable is effective.
- *
- * \param channel Channel number.
- * \param prescaler Channel prescaler.
- * \param alignment Channel alignment.
- * \param polarity Channel polarity.
- * \param countEventSelect Channel counter event selection.
- * \param DTEnable Channel dead time generator enable.
- * \param DTHInverte Channel Dead-Time PWMHx output Inverted.
- * \param DTLInverte Channel Dead-Time PWMHx output Inverted.
- */
-void PWMC_ConfigureChannelExt(
- uint8_t channel,
- uint32_t prescaler,
- uint32_t alignment,
- uint32_t polarity,
- uint32_t countEventSelect,
- uint32_t DTEnable,
- uint32_t DTHInverte,
- uint32_t DTLInverte)
-{
- SANITY_CHECK(prescaler < PWM_CMR0_CPRE_MCKB);
- SANITY_CHECK((alignment & ~PWM_CMR0_CALG) == 0);
- SANITY_CHECK((polarity & ~PWM_CMR0_CPOL) == 0);
- SANITY_CHECK((countEventSelect & ~PWM_CMR0_CES) == 0);
- SANITY_CHECK((DTEnable & ~PWM_CMR0_DTE) == 0);
- SANITY_CHECK((DTHInverte & ~PWM_CMR0_DTHI) == 0);
- SANITY_CHECK((DTLInverte & ~PWM_CMR0_DTLI) == 0);
-
- /* Disable channel (effective at the end of the current period) */
- if ((PWM->PWM_SR & (1 << channel)) != 0) {
- PWM->PWM_DIS = 1 << channel;
- while ((PWM->PWM_SR & (1 << channel)) != 0);
- }
-
- /* Configure channel */
- PWM->PWM_CH_NUM[channel].PWM_CMR = prescaler | alignment | polarity |
- countEventSelect | DTEnable | DTHInverte | DTLInverte;
-}
-
-/**
- * \brief Configures PWM clocks A & B to run at the given frequencies.
- *
- * This function finds the best MCK divisor and prescaler values automatically.
- *
- * \param clka Desired clock A frequency (0 if not used).
- * \param clkb Desired clock B frequency (0 if not used).
- * \param mck Master clock frequency.
- */
-void PWMC_ConfigureClocks(uint32_t clka, uint32_t clkb, uint32_t mck)
-{
- uint32_t mode = 0;
- uint32_t result;
-
- /* Clock A */
- if (clka != 0) {
-
- result = FindClockConfiguration(clka, mck);
- ASSERT(result != 0, "-F- Could not generate the desired PWM frequency (%uHz)\n\r", (unsigned int)clka);
- mode |= result;
- }
-
- /* Clock B */
- if (clkb != 0) {
-
- result = FindClockConfiguration(clkb, mck);
- ASSERT(result != 0, "-F- Could not generate the desired PWM frequency (%uHz)\n\r", (unsigned int)clkb);
- mode |= (result << 16);
- }
-
- /* Configure clocks */
- TRACE_DEBUG("Setting PWM_CLK = 0x%08X\n\r", mode);
- PWM->PWM_CLK = mode;
-}
-
-/**
- * \brief Sets the period value used by a PWM channel.
- *
- * This function writes directly to the CPRD register if the channel is disabled;
- * otherwise, it uses the update register CPRDUPD.
- *
- * \param channel Channel number.
- * \param period Period value.
- */
-void PWMC_SetPeriod(uint8_t channel, uint16_t period)
-{
- /* If channel is disabled, write to CPRD */
- if ((PWM->PWM_SR & (1 << channel)) == 0) {
-
- PWM->PWM_CH_NUM[channel].PWM_CPRD = period;
- }
- /* Otherwise use update register */
- else {
-
- PWM->PWM_CH_NUM[channel].PWM_CPRDUPD = period;
- }
-}
-
-/**
- * \brief Sets the duty cycle used by a PWM channel.
- * This function writes directly to the CDTY register if the channel is disabled;
- * otherwise it uses the update register CDTYUPD.
- * Note that the duty cycle must always be inferior or equal to the channel
- * period.
- *
- * \param channel Channel number.
- * \param duty Duty cycle value.
- */
-void PWMC_SetDutyCycle(uint8_t channel, uint16_t duty)
-{
- SANITY_CHECK(duty <= PWM->PWM_CH_NUM[channel].PWM_CPRD);
-
- /* If channel is disabled, write to CDTY */
- if ((PWM->PWM_SR & (1 << channel)) == 0) {
-
- PWM->PWM_CH_NUM[channel].PWM_CDTY = duty;
- }
- /* Otherwise use update register */
- else {
-
- PWM->PWM_CH_NUM[channel].PWM_CDTYUPD = duty;
- }
-}
-
-/**
- * \brief Sets the dead time used by a PWM channel.
- * This function writes directly to the DT register if the channel is disabled;
- * otherwise it uses the update register DTUPD.
- * Note that the dead time must always be inferior or equal to the channel
- * period.
- *
- * \param channel Channel number.
- * \param timeH Dead time value for PWMHx output.
- * \param timeL Dead time value for PWMLx output.
- */
-void PWMC_SetDeadTime(uint8_t channel, uint16_t timeH, uint16_t timeL)
-{
- SANITY_CHECK(timeH <= PWM->PWM_CH_NUM[channel].PWM_CPRD);
- SANITY_CHECK(timeL <= PWM->PWM_CH_NUM[channel].PWM_CPRD);
-
- /* If channel is disabled, write to DT */
- if ((PWM->PWM_SR & (1 << channel)) == 0) {
-
- PWM->PWM_CH_NUM[channel].PWM_DT = timeH | (timeL << 16);
- }
- /* Otherwise use update register */
- else {
- PWM->PWM_CH_NUM[channel].PWM_DTUPD = timeH | (timeL << 16);
- }
-}
-
-/**
- * \brief Configures Syncronous channel with the given parameters.
- * Beware: At this time, the channels should be disabled.
- *
- * \param channels Bitwise OR of Syncronous channels.
- * \param updateMode Syncronous channel update mode.
- * \param requestMode PDC transfer request mode.
- * \param requestComparisonSelect PDC transfer request comparison selection.
- */
-void PWMC_ConfigureSyncChannel(
- uint32_t channels,
- uint32_t updateMode,
- uint32_t requestMode,
- uint32_t requestComparisonSelect)
-{
- PWM->PWM_SCM = channels | updateMode | requestMode
- | requestComparisonSelect;
-}
-
-/**
- * \brief Sets the update period of the synchronous channels.
- * This function writes directly to the SCUP register if the channel #0 is disabled;
- * otherwise it uses the update register SCUPUPD.
- *
- * \param period update period.
- */
-void PWMC_SetSyncChannelUpdatePeriod(uint8_t period)
-{
- /* If channel is disabled, write to SCUP */
- if ((PWM->PWM_SR & (1 << 0)) == 0) {
-
- PWM->PWM_SCUP = period;
- }
- /* Otherwise use update register */
- else {
-
- PWM->PWM_SCUPUPD = period;
- }
-}
-
-/**
- * \brief Sets synchronous channels update unlock.
- *
- * Note: If the UPDM field is set to 0, writing the UPDULOCK bit to 1
- * triggers the update of the period value, the duty-cycle and
- * the dead-time values of synchronous channels at the beginning
- * of the next PWM period. If the field UPDM is set to 1 or 2,
- * writing the UPDULOCK bit to 1 triggers only the update of
- * the period value and of the dead-time values of synchronous channels.
- * This bit is automatically reset when the update is done.
- */
-void PWMC_SetSyncChannelUpdateUnlock(void)
-{
- PWM->PWM_SCUC = PWM_SCUC_UPDULOCK;
-}
-
-/**
- * \brief Enables the given PWM channel.
- *
- * This does NOT enable the corresponding pin;this must be done in the user code.
- *
- * \param channel Channel number.
- */
-void PWMC_EnableChannel(uint8_t channel)
-{
- PWM->PWM_ENA = 1 << channel;
-}
-
-/**
- * \brief Disables the given PWM channel.
- *
- * Beware, channel will be effectively disabled at the end of the current period.
- * Application can check channel is disabled using the following wait loop:
- * while ((PWM->PWM_SR & (1 << channel)) != 0);
- *
- * \param channel Channel number.
- */
-void PWMC_DisableChannel(uint8_t channel)
-{
- PWM->PWM_DIS = 1 << channel;
-}
-
-/**
- * \brief Enables the period interrupt for the given PWM channel.
- *
- * \param channel Channel number.
- */
-void PWMC_EnableChannelIt(uint8_t channel)
-{
- PWM->PWM_IER1 = 1 << channel;
-}
-
-/**
- * \brief Disables the period interrupt for the given PWM channel.
- *
- * \param channel Channel number.
- */
-void PWMC_DisableChannelIt(uint8_t channel)
-{
- PWM->PWM_IDR1 = 1 << channel;
-}
-
-/**
- * \brief Enables the selected interrupts sources on a PWMC peripheral.
- *
- * \param sources1 Bitwise OR of selected interrupt sources of PWM_IER1.
- * \param sources2 Bitwise OR of selected interrupt sources of PWM_IER2.
- */
-void PWMC_EnableIt(uint32_t sources1, uint32_t sources2)
-{
- PWM->PWM_IER1 = sources1;
- PWM->PWM_IER2 = sources2;
-}
-
-/**
- * \brief Disables the selected interrupts sources on a PWMC peripheral.
- *
- * \param sources1 Bitwise OR of selected interrupt sources of PWM_IDR1.
- * \param sources2 Bitwise OR of selected interrupt sources of PWM_IDR2.
- */
-void PWMC_DisableIt(uint32_t sources1, uint32_t sources2)
-{
- PWM->PWM_IDR1 = sources1;
- PWM->PWM_IDR2 = sources2;
-}
-
-/**
- * \brief Sends the contents of buffer through a PWMC peripheral, using the PDC to
- * take care of the transfer.
- *
- * Note: Duty cycle of syncronous channels can update by PDC
- * when the field UPDM (Update Mode) in the PWM_SCM register is set to 2.
- *
- * \param pwmc Pointer to an Pwm instance.
- * \param buffer Data buffer to send.
- * \param length Length of the data buffer.
- */
-uint8_t PWMC_WriteBuffer(Pwm *pwmc,
- void *buffer,
- uint32_t length)
-{
- /* Check if first bank is free */
- if (pwmc->PWM_TCR == 0) {
-
- pwmc->PWM_TPR = (uint32_t) buffer;
- pwmc->PWM_TCR = length;
- pwmc->PWM_PTCR = PERIPH_PTCR_TXTEN;
- return 1;
- }
- /* Check if second bank is free */
- else if (pwmc->PWM_TNCR == 0) {
-
- pwmc->PWM_TNPR = (uint32_t) buffer;
- pwmc->PWM_TNCR = length;
- return 1;
- }
-
- /* No free banks */
- return 0;
-}
-
-/**
- * \brief Set PWM output override value.
- *
- * \param value Bitwise OR of output override value.
- */
-void PWMC_SetOverrideValue(uint32_t value)
-{
- PWM->PWM_OOV = value;
-}
-
-/**
- * \brief Enalbe override output.
- *
- * \param value Bitwise OR of output selection.
- * \param sync 0: enable the output asyncronously, 1: enable it syncronously
- */
-void PWMC_EnableOverrideOutput(uint32_t value, uint32_t sync)
-{
- if (sync) {
-
- PWM->PWM_OSSUPD = value;
- } else {
-
- PWM->PWM_OSS = value;
- }
-}
-
-/**
- * \brief Disalbe override output.
- *
- * \param value Bitwise OR of output selection.
- * \param sync 0: enable the output asyncronously, 1: enable it syncronously
- */
-void PWMC_DisableOverrideOutput(uint32_t value, uint32_t sync)
-{
- if (sync) {
-
- PWM->PWM_OSCUPD = value;
- } else {
-
- PWM->PWM_OSC = value;
- }
-}
-
-/**
- * \brief Set PWM fault mode.
- *
- * \param mode Bitwise OR of fault mode.
- */
-void PWMC_SetFaultMode(uint32_t mode)
-{
- PWM->PWM_FMR = mode;
-}
-
-/**
- * \brief PWM fault clear.
- *
- * \param fault Bitwise OR of fault to clear.
- */
-void PWMC_FaultClear(uint32_t fault)
-{
- PWM->PWM_FCR = fault;
-}
-
-/**
- * \brief Set PWM fault protection value.
- *
- * \param value Bitwise OR of fault protection value.
- */
-void PWMC_SetFaultProtectionValue(uint32_t value)
-{
- PWM->PWM_FPV = value;
-}
-
-/**
- * \brief Enable PWM fault protection.
- *
- * \param value Bitwise OR of FPEx[y].
- */
-void PWMC_EnableFaultProtection(uint32_t value)
-{
- PWM->PWM_FPE = value;
-}
-
-/**
- * \brief Configure comparison unit.
- *
- * \param x comparison x index
- * \param value comparison x value.
- * \param mode comparison x mode
- */
-void PWMC_ConfigureComparisonUnit(uint32_t x, uint32_t value, uint32_t mode)
-{
- /* If channel is disabled, write to CMPxM & CMPxV */
- if ((PWM->PWM_SR & (1 << 0)) == 0) {
- if (x == 0) {
- PWM->PWM_CMP0M = mode;
- PWM->PWM_CMP0V = value;
- } else if (x == 1) {
- PWM->PWM_CMP1M = mode;
- PWM->PWM_CMP1V = value;
- } else if (x == 2) {
- PWM->PWM_CMP2M = mode;
- PWM->PWM_CMP2V = value;
- } else if (x == 3) {
- PWM->PWM_CMP3M = mode;
- PWM->PWM_CMP3V = value;
- } else if (x == 4) {
- PWM->PWM_CMP4M = mode;
- PWM->PWM_CMP4V = value;
- } else if (x == 5) {
- PWM->PWM_CMP5M = mode;
- PWM->PWM_CMP5V = value;
- } else if (x == 6) {
- PWM->PWM_CMP6M = mode;
- PWM->PWM_CMP6V = value;
- } else if (x == 7) {
- PWM->PWM_CMP7M = mode;
- PWM->PWM_CMP7V = value;
- }
- }
- /* Otherwise use update register */
- else {
- if (x == 0) {
- PWM->PWM_CMP0MUPD = mode;
- PWM->PWM_CMP0VUPD = value;
- } else if (x == 1) {
- PWM->PWM_CMP1MUPD = mode;
- PWM->PWM_CMP1VUPD = value;
- } else if (x == 2) {
- PWM->PWM_CMP2MUPD = mode;
- PWM->PWM_CMP2VUPD = value;
- } else if (x == 3) {
- PWM->PWM_CMP3MUPD = mode;
- PWM->PWM_CMP3VUPD = value;
- } else if (x == 4) {
- PWM->PWM_CMP4MUPD = mode;
- PWM->PWM_CMP4VUPD = value;
- } else if (x == 5) {
- PWM->PWM_CMP5MUPD = mode;
- PWM->PWM_CMP5VUPD = value;
- } else if (x == 6) {
- PWM->PWM_CMP6MUPD = mode;
- PWM->PWM_CMP6VUPD = value;
- } else if (x == 7) {
- PWM->PWM_CMP7MUPD = mode;
- PWM->PWM_CMP7VUPD = value;
- }
- }
-}
-
-/**
- * \brief Configure event line mode.
- *
- * \param x Line x
- * \param mode Bitwise OR of line mode selection
- */
-void PWMC_ConfigureEventLineMode(uint32_t x, uint32_t mode)
-{
- SANITY_CHECK(x < 2);
-
- PWM->PWM_ELxMR[x] = mode;
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pwmc/pwmc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pwmc/pwmc.h
deleted file mode 100644
index 1c0a5b29..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pwmc/pwmc.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- *
- * \par Purpose
- *
- * Interface for configuration the Pulse Width Modulation Controller (PWM) peripheral.
- *
- * \par Usage
- *
- * -# Configures PWM clocks A & B to run at the given frequencies using
- * \ref PWMC_ConfigureClocks().
- * -# Configure PWMC channel using \ref PWMC_ConfigureChannel(), \ref PWMC_ConfigureChannelExt()
- * \ref PWMC_SetPeriod(), \ref PWMC_SetDutyCycle() and \ref PWMC_SetDeadTime().
- * -# Enable & disable channel using \ref PWMC_EnableChannel() and
- * \ref PWMC_DisableChannel().
- * -# Enable & disable the period interrupt for the given PWM channel using
- * \ref PWMC_EnableChannelIt() and \ref PWMC_DisableChannelIt().
- * -# Enable & disable the selected interrupts sources on a PWMC peripheral
- * using \ref PWMC_EnableIt() and \ref PWMC_DisableIt().
- * -# Control syncronous channel using \ref PWMC_ConfigureSyncChannel(),
- * \ref PWMC_SetSyncChannelUpdatePeriod() and \ref PWMC_SetSyncChannelUpdateUnlock().
- * -# Control PWM override output using \ref PWMC_SetOverrideValue(),
- * \ref PWMC_EnableOverrideOutput() and \ref PWMC_DisableOverrideOutput().
- * -# \ref Send data through the transmitter using \ref PWMC_WriteBuffer().
- *
- */
-
-#ifndef PWMC_H
-#define PWMC_H
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include
-
-/*----------------------------------------------------------------------------
- * Definitions
- *----------------------------------------------------------------------------*/
-
-/* PWM sub-bit field definition. begin */
-/* TODO: remove them when AT91SAM3S4.h have the definitions. */
-// PWM_CMRx
-#define PWM_CMR0_CPRE_MCKA (0xB) // (PWMC_CH)
-#define PWM_CMR0_CPRE_MCKB (0xC) // (PWMC_CH)
-#define PWM_CMR1_CPRE_MCKA (0xB) // (PWMC_CH)
-#define PWM_CMR2_CPRE_MCKA (0xB) // (PWMC_CH)
-// PWM_SCM
-#define PWM_SCM_UPDM_MODE0 (0x0 << 16) // (PWMC) Manual write of data and manual trigger of the update
-#define PWM_SCM_UPDM_MODE1 (0x1 << 16) // (PWMC) Manual write of data and automatic trigger of the update
-#define PWM_SCM_UPDM_MODE2 (0x2 << 16) // (PWMC) Automatic write of data and automatic trigger of the update
-/* end */
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-extern void PWMC_ConfigureChannel(
- uint8_t channel,
- uint32_t prescaler,
- uint32_t alignment,
- uint32_t polarity);
-
-extern void PWMC_ConfigureChannelExt(
- uint8_t channel,
- uint32_t prescaler,
- uint32_t alignment,
- uint32_t polarity,
- uint32_t countEventSelect,
- uint32_t DTEnable,
- uint32_t DTHInverte,
- uint32_t DTLInverte);
-
-extern void PWMC_ConfigureClocks
- (uint32_t clka,
- uint32_t clkb,
- uint32_t mck);
-
-extern void PWMC_SetPeriod(uint8_t channel, uint16_t period);
-
-extern void PWMC_SetDutyCycle(uint8_t channel, uint16_t duty);
-
-extern void PWMC_SetDeadTime(uint8_t channel, uint16_t timeH, uint16_t timeL);
-
-extern void PWMC_ConfigureSyncChannel(
- uint32_t channels,
- uint32_t updateMode,
- uint32_t requestMode,
- uint32_t requestComparisonSelect);
-
-extern void PWMC_SetSyncChannelUpdatePeriod(uint8_t period);
-
-extern void PWMC_SetSyncChannelUpdateUnlock(void);
-
-extern void PWMC_EnableChannel(uint8_t channel);
-
-extern void PWMC_DisableChannel(uint8_t channel);
-
-extern void PWMC_EnableChannelIt(uint8_t channel);
-
-extern void PWMC_DisableChannelIt(uint8_t channel);
-
-extern void PWMC_EnableIt(uint32_t sources1, uint32_t sources2);
-
-extern void PWMC_DisableIt(uint32_t sources1, uint32_t sources2);
-
-extern uint8_t PWMC_WriteBuffer(Pwm *pwmc,
- void *buffer,
- uint32_t length);
-
-extern void PWMC_SetOverrideValue(uint32_t value);
-
-extern void PWMC_EnableOverrideOutput(uint32_t value, uint32_t sync);
-
-extern void PWMC_DisableOverrideOutput(uint32_t value, uint32_t sync);
-
-extern void PWMC_SetFaultMode(uint32_t mode);
-
-extern void PWMC_FaultClear(uint32_t fault);
-
-extern void PWMC_SetFaultProtectionValue(uint32_t value);
-
-extern void PWMC_EnableFaultProtection(uint32_t value);
-
-extern void PWMC_ConfigureComparisonUnit(uint32_t x, uint32_t value, uint32_t mode);
-
-extern void PWMC_ConfigureEventLineMode(uint32_t x, uint32_t mode);
-
-#endif /* #ifndef PWMC_H */
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/qtouch/libQTouchIarCfg3SRevABeta1.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/qtouch/libQTouchIarCfg3SRevABeta1.txt
deleted file mode 100644
index a0aa300d..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/qtouch/libQTouchIarCfg3SRevABeta1.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-QTouch library for AT91SAM3S-EK board version A.
-Modified board.
-
-Burst pulses 5 CPU cycles wide.
-
-Slider on pins PA0, PA1, PA2, PA3, PA4, PA5
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/qtouch/libQTouchIarCfg3SRevABeta2.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/qtouch/libQTouchIarCfg3SRevABeta2.txt
deleted file mode 100644
index 3ae67b9d..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/qtouch/libQTouchIarCfg3SRevABeta2.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-QTouch library for AT91SAM3S-EK board version A.
-Modified board.
-
-Burst pulses 5 CPU cycles wide.
-
-A Valid key on pins PC22 and PC23
-A UP key on pins PC24 and PC25
-A Down key on pins PC26 and PC27
-A Left key on pins PC28 and PC29
-A right key on pins PC30 and PC31
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/qtouch/libQTouchIarCfg3SRevB.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/qtouch/libQTouchIarCfg3SRevB.txt
deleted file mode 100644
index b05f3865..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/qtouch/libQTouchIarCfg3SRevB.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-QTouch library for AT91SAM3S-EK board version B.
-
-Burst pulses 5 CPU cycles wide.
-
-Slider on pins PA0, PA1, PA2, PA3, PA4, PA5
-
-A Valid key on pins PC22 and PC23
-A UP key on pins PC24 and PC25
-A Down key on pins PC26 and PC27
-A Left key on pins PC28 and PC29
-A right key on pins PC30 and PC31
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/rtc/rtc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/rtc/rtc.c
deleted file mode 100644
index 8ed4d430..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/rtc/rtc.c
+++ /dev/null
@@ -1,467 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/** \addtogroup rtc_module Working with RTC
- * The RTC driver provides the interface to configure and use the RTC
- * peripheral.
- *
- * It manages date, time, and alarms.\n
- * This timer is clocked by the 32kHz system clock, and is not impacted by
- * power management settings (PMC). To be accurate, it is better to use an
- * external 32kHz crystal instead of the internal 32kHz RC.\n
- *
- * It uses BCD format, and time can be set in AM/PM or 24h mode through a
- * configuration bit in the mode register.\n
- *
- * To update date or time, the user has to follow these few steps :
- *
- *
Set UPDTIM and/or UPDCAL bit(s) in RTC_CR,
- *
Polling or IRQ on the ACKUPD bit of RTC_CR,
- *
Clear ACKUPD bit in RTC_SCCR,
- *
Update Time and/or Calendar values in RTC_TIMR/RTC_CALR (BCD format),
- *
Clear UPDTIM and/or UPDCAL bit in RTC_CR.
- *
- * An alarm can be set to happen on month, date, hours, minutes or seconds,
- * by setting the proper "Enable" bit of each of these fields in the Time and
- * Calendar registers.
- * This allows a large number of configurations to be available for the user.
- * Alarm occurence can be detected even by polling or interrupt.
- *
- * A check of the validity of the date and time format and values written by the user is automatically done.
- * Errors are reported through the Valid Entry Register.
- *
- * For more accurate information, please look at the RTC section of the
- * Datasheet.
- *
- * Related files :\n
- * \ref rtc.c\n
- * \ref rtc.h.\n
-*/
-/*@{*/
-/*@}*/
-
-
-/**
- * \file
- *
- * Implementation of Real Time Clock (RTC) controller.
- *
- */
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-/* These headers were introduced in C99 by working group ISO/IEC JTC1/SC22/WG14. */
-#include
-
-#include "rtc.h"
-#include
-#include
-#include
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief Sets the RTC in either 12 or 24 hour mode.
- *
- * \param mode Hour mode.
- */
-void RTC_SetHourMode(uint32_t mode)
-{
- SANITY_CHECK((mode & 0xFFFFFFFE) == 0);
-
- TRACE_DEBUG("RTC_SetHourMode()\n\r");
-
- RTC->RTC_MR = mode;
-}
-
-/**
- * \brief Gets the RTC mode.
- *
- * \return Hour mode.
- */
-uint32_t RTC_GetHourMode( void )
-{
- uint32_t hmode;
-
- TRACE_DEBUG("RTC_SetHourMode()\n\r");
-
- hmode = RTC->RTC_MR;
- hmode &= 0xFFFFFFFE;
-
- return hmode;
-}
-
-/**
- * \brief Enables the selected interrupt sources of the RTC.
- *
- * \param sources Interrupt sources to enable.
- */
-void RTC_EnableIt(uint32_t sources)
-{
- SANITY_CHECK((sources & ~0x1F) == 0);
-
- TRACE_DEBUG("RTC_EnableIt()\n\r");
-
- RTC->RTC_IER = sources;
-}
-
-/**
-* \brief Disables the selected interrupt sources of the RTC.
-*
-* \param sources Interrupt sources to disable.
-*/
-void RTC_DisableIt(uint32_t sources)
-{
- SANITY_CHECK((sources & ~0x1F) == 0);
-
- TRACE_DEBUG("RTC_DisableIt()\n\r");
-
- RTC->RTC_IDR = sources;
-}
-
-/**
- * \brief Sets the current time in the RTC.
- *
- * \param hour Current hour in 12 or 24 hour mode.
- * \param minute Current minute.
- * \param second Current second.
- * \return 0 sucess, 1 fail to set
- */
-int RTC_SetTime(uint8_t hour, uint8_t minute, uint8_t second)
-{
- uint32_t time=0;
- uint8_t hour_bcd;
- uint8_t min_bcd;
- uint8_t sec_bcd;
-
- TRACE_DEBUG("RTC_SetTime(%02d:%02d:%02d)\n\r", hour, minute, second);
-
- /* if 12-hour mode, set AMPM bit */
- if ((RTC->RTC_MR & RTC_MR_HRMOD) == RTC_MR_HRMOD) {
-
- if (hour > 12) {
-
- hour -= 12;
- time |= RTC_TIMR_AMPM;
- }
- }
- hour_bcd = (hour%10) | ((hour/10)<<4);
- min_bcd = (minute%10) | ((minute/10)<<4);
- sec_bcd = (second%10) | ((second/10)<<4);
-
- /* value overflow */
- if((hour_bcd & (uint8_t)(~RTC_HOUR_BIT_LEN_MASK)) |
- (min_bcd & (uint8_t)(~RTC_MIN_BIT_LEN_MASK)) |
- (sec_bcd & (uint8_t)(~RTC_SEC_BIT_LEN_MASK)))
- return 1;
-
- time = sec_bcd | (min_bcd << 8) | (hour_bcd<<16);
-
- /* Set time */
- while ((RTC->RTC_SR & RTC_SR_SEC) != RTC_SR_SEC); /* wait from previous set */
- RTC->RTC_CR |= RTC_CR_UPDTIM;
- while ((RTC->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD);
- RTC->RTC_SCCR = RTC_SCCR_ACKCLR;
- RTC->RTC_TIMR = time;
- RTC->RTC_CR &= ~RTC_CR_UPDTIM;
- RTC->RTC_SCCR |= RTC_SCCR_SECCLR; /* clear SECENV in SCCR */
-
- return (int)(RTC->RTC_VER & RTC_VER_NVTIM);
-}
-
-/**
- * \brief Retrieves the current time as stored in the RTC in several variables.
- *
- * \param pHour If not null, current hour is stored in this variable.
- * \param pMinute If not null, current minute is stored in this variable.
- * \param pSecond If not null, current second is stored in this variable.
- */
-void RTC_GetTime(
- uint8_t *pHour,
- uint8_t *pMinute,
- uint8_t *pSecond)
-{
- uint32_t time;
-
- TRACE_DEBUG("RTC_GetTime()\n\r");
-
- /* Get current RTC time */
- time = RTC->RTC_TIMR;
- while (time != RTC->RTC_TIMR) {
-
- time = RTC->RTC_TIMR;
- }
-
- /* Hour */
- if (pHour) {
-
- *pHour = ((time & 0x00300000) >> 20) * 10
- + ((time & 0x000F0000) >> 16);
- if ((time & RTC_TIMR_AMPM) == RTC_TIMR_AMPM) {
-
- *pHour += 12;
- }
- }
-
- /* Minute */
- if (pMinute) {
-
- *pMinute = ((time & 0x00007000) >> 12) * 10
- + ((time & 0x00000F00) >> 8);
- }
-
- /* Second */
- if (pSecond) {
-
- *pSecond = ((time & 0x00000070) >> 4) * 10
- + (time & 0x0000000F);
- }
-}
-
-/**
- * \brief Sets a time alarm on the RTC.
- * The match is performed only on the provided variables;
- * Setting all pointers to 0 disables the time alarm.
- *
- * \note In AM/PM mode, the hour value must have bit #7 set for PM, cleared for
- * AM (as expected in the time registers).
- *
- * \param pHour If not null, the time alarm will hour-match this value.
- * \param pMinute If not null, the time alarm will minute-match this value.
- * \param pSecond If not null, the time alarm will second-match this value.
- * \return 0 success, 1 fail to set
- */
-int RTC_SetTimeAlarm(
- uint8_t *pHour,
- uint8_t *pMinute,
- uint8_t *pSecond)
-{
- uint32_t alarm = 0;
-
- TRACE_DEBUG("RTC_SetTimeAlarm()\n\r");
-
- /* Hour */
- if (pHour) {
-
- alarm |= RTC_TIMALR_HOUREN | ((*pHour / 10) << 20) | ((*pHour % 10) << 16);
- }
-
- /* Minute */
- if (pMinute) {
-
- alarm |= RTC_TIMALR_MINEN | ((*pMinute / 10) << 12) | ((*pMinute % 10) << 8);
- }
-
- /* Second */
- if (pSecond) {
-
- alarm |= RTC_TIMALR_SECEN | ((*pSecond / 10) << 4) | (*pSecond % 10);
- }
-
- RTC->RTC_TIMALR = alarm;
-
- return (int)(RTC->RTC_VER & RTC_VER_NVTIMALR);
-}
-
-/**
- * \brief Retrieves the current year, month and day from the RTC.
- * Month, day and week values are numbered starting at 1.
- *
- * \param pYear Current year (optional).
- * \param pMonth Current month (optional).
- * \param pDay Current day (optional).
- * \param pWeek Current day in current week (optional).
- */
-void RTC_GetDate(
- unsigned short *pYear,
- uint8_t *pMonth,
- uint8_t *pDay,
- uint8_t *pWeek)
-{
- uint32_t date;
-
- /* Get current date (multiple reads are necessary to insure a stable value) */
- do {
-
- date = RTC->RTC_CALR;
- }
- while (date != RTC->RTC_CALR);
-
- /* Retrieve year */
- if (pYear) {
-
- *pYear = (((date >> 4) & 0x7) * 1000)
- + ((date & 0xF) * 100)
- + (((date >> 12) & 0xF) * 10)
- + ((date >> 8) & 0xF);
- }
-
- /* Retrieve month */
- if (pMonth) {
-
- *pMonth = (((date >> 20) & 1) * 10) + ((date >> 16) & 0xF);
- }
-
- /* Retrieve day */
- if (pDay) {
-
- *pDay = (((date >> 28) & 0x3) * 10) + ((date >> 24) & 0xF);
- }
-
- /* Retrieve week */
- if (pWeek) {
-
- *pWeek = ((date >> 21) & 0x7);
- }
-}
-
-/**
- * \brief Sets the current year, month and day in the RTC.
- * Month, day and week values must be numbered starting from 1.
- *
- * \param year Current year.
- * \param month Current month.
- * \param day Current day.
- * \param week Day number in current week.
- * \return 0 success, 1 fail to set
- */
-int RTC_SetDate(
- unsigned short year,
- uint8_t month,
- uint8_t day,
- uint8_t week)
-{
- uint32_t date;
- uint8_t cent_bcd;
- uint8_t year_bcd;
- uint8_t month_bcd;
- uint8_t day_bcd;
- uint8_t week_bcd;
-
- cent_bcd = ((year/100)%10) | ((year/1000)<<4);
- year_bcd = (year%10) | (((year/10)%10)<<4);
- month_bcd = ((month%10) | (month/10)<<4);
- day_bcd = ((day%10) | (day/10)<<4);
- week_bcd = ((week%10) | (week/10)<<4);
-
- /* value over flow */
- if((cent_bcd & (uint8_t)(~RTC_CENT_BIT_LEN_MASK)) |
- (year_bcd & (uint8_t)(~RTC_YEAR_BIT_LEN_MASK)) |
- (month_bcd & (uint8_t)(~RTC_MONTH_BIT_LEN_MASK)) |
- (week_bcd & (uint8_t)(~RTC_WEEK_BIT_LEN_MASK)) |
- (day_bcd & (uint8_t)(~RTC_DATE_BIT_LEN_MASK)))
- return 1;
-
-
- /* Convert values to date register value */
- date = cent_bcd |
- (year_bcd << 8) |
- (month_bcd << 16) |
- (week_bcd << 21) |
- (day_bcd << 24);
-
-
- /* Update calendar register */
- while ((RTC->RTC_SR & RTC_SR_SEC) != RTC_SR_SEC); /* wait from previous set */
- RTC->RTC_CR |= RTC_CR_UPDCAL;
- while ((RTC->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD);
- RTC->RTC_SCCR = RTC_SCCR_ACKCLR;
- RTC->RTC_CALR = date;
- RTC->RTC_CR &= ~RTC_CR_UPDCAL;
- RTC->RTC_SCCR |= RTC_SCCR_SECCLR; /* clear SECENV in SCCR */
-
- return (int)(RTC->RTC_VER & RTC_VER_NVCAL);
-}
-
-/**
- * \brief Sets a date alarm in the RTC.
- * The alarm will match only the provided values;
- * Passing a null-pointer disables the corresponding field match.
- *
- * \param pMonth If not null, the RTC alarm will month-match this value.
- * \param pDay If not null, the RTC alarm will day-match this value.
- * \return 0 success, 1 fail to set
- */
-int RTC_SetDateAlarm(uint8_t *pMonth, uint8_t *pDay)
-{
- uint32_t alarm;
-
- alarm = ((pMonth) || (pDay)) ? (0) : (0x01010000);
-
- TRACE_DEBUG("RTC_SetDateAlarm()\n\r");
-
- /* Compute alarm field value */
- if (pMonth) {
-
- alarm |= RTC_CALALR_MTHEN | ((*pMonth / 10) << 20) | ((*pMonth % 10) << 16);
- }
- if (pDay) {
-
- alarm |= RTC_CALALR_DATEEN | ((*pDay / 10) << 28) | ((*pDay % 10) << 24);
- }
-
- /* Set alarm */
- RTC->RTC_CALALR = alarm;
-
- return (int)(RTC->RTC_VER & RTC_VER_NVCALALR);
-}
-
-/**
- * \brief Clear flag bits of status clear command register in the RTC.
- *
- * \param mask Bits mask of cleared events
- */
-void RTC_ClearSCCR(uint32_t mask)
-{
- /* Clear all flag bits in status clear command register */
- mask &= RTC_SCCR_ACKCLR | RTC_SCCR_ALRCLR | RTC_SCCR_SECCLR | \
- RTC_SCCR_TIMCLR | RTC_SCCR_CALCLR;
-
- RTC->RTC_SCCR = mask;
-}
-
-/**
- * \brief Get flag bits of status register in the RTC.
- *
- * \param mask Bits mask of Status Register
- * \return Status register & mask
- */
-uint32_t RTC_GetSR(uint32_t mask)
-{
- uint32_t event;
-
- event = RTC->RTC_SR;
-
- return (event & mask);
-}
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/rtc/rtc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/rtc/rtc.h
deleted file mode 100644
index 5f821d3d..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/rtc/rtc.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- *
- * Interface for Real Time Clock (RTC) controller.
- *
- */
-
-#ifndef RTC_H
-#define RTC_H
-
-/*----------------------------------------------------------------------------
- * Definitions
- *----------------------------------------------------------------------------*/
-
-#define RTC_HOUR_BIT_LEN_MASK 0x3F
-#define RTC_MIN_BIT_LEN_MASK 0x7F
-#define RTC_SEC_BIT_LEN_MASK 0x7F
-#define RTC_CENT_BIT_LEN_MASK 0x7F
-#define RTC_YEAR_BIT_LEN_MASK 0xFF
-#define RTC_MONTH_BIT_LEN_MASK 0x1F
-#define RTC_DATE_BIT_LEN_MASK 0x3F
-#define RTC_WEEK_BIT_LEN_MASK 0x07
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-extern void RTC_SetHourMode(uint32_t mode);
-
-extern uint32_t RTC_GetHourMode( void ) ;
-
-extern void RTC_EnableIt(uint32_t sources);
-
-extern void RTC_DisableIt(uint32_t sources);
-
-extern int RTC_SetTime(
- uint8_t hour,
- uint8_t minute,
- uint8_t second);
-
-extern void RTC_GetTime(
- uint8_t *pHour,
- uint8_t *pMinute,
- uint8_t *pSecond);
-
-extern int RTC_SetTimeAlarm(
- uint8_t *pHour,
- uint8_t *pMinute,
- uint8_t *pSecond);
-
-extern void RTC_GetDate(
- unsigned short *pYear,
- uint8_t *pMonth,
- uint8_t *pDay,
- uint8_t *pWeek);
-
-extern int RTC_SetDate(
- unsigned short year,
- uint8_t month,
- uint8_t day,
- uint8_t week);
-
-extern int RTC_SetDateAlarm(uint8_t *pMonth, uint8_t *pDay);
-
-extern void RTC_ClearSCCR(uint32_t mask);
-
-extern uint32_t RTC_GetSR(uint32_t mask);
-
-#endif /* #ifndef RTC_H */
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/rtt/rtt.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/rtt/rtt.c
deleted file mode 100644
index f225ad35..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/rtt/rtt.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/** \addtogroup rtt_module Working with RTT
- * The RTT driver provides the interface to configure and use the RTT
- * peripheral.
- *
- * The Real-time Timer is used to count elapsed seconds.\n
- * This timer is clocked by the 32kHz system clock divided by a programmable
- * 16-bit balue. To be accurate, it is better to use an
- * external 32kHz crystal instead of the internal 32kHz RC.\n
- *
- * To count elapsed seconds, the user could follow these few steps:
- *
- *
Programming PTPRES in RTT_MR to feeding the timer with a 1Hz signal.
- *
Writing the bit RTTRST in RTT_MR to restart the timer with new settings.
- *
- *
- * An alarm can be set to happen on second by setting alarm value in RTT_AR.
- * Alarm occurence can be detected by polling or interrupt.
- *
- * For more accurate information, please look at the RTT section of the
- * Datasheet.
- *
- * Related files :\n
- * \ref rtt.c\n
- * \ref rtt.h.\n
- */
-/*@{*/
-/*@}*/
-
-/**
- * \file
- *
- * Implementation of Real Time Timer (RTT) controller.
- *
- */
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-/* These headers were introduced in C99 by working group ISO/IEC JTC1/SC22/WG14. */
-#include
-
-#include "rtt.h"
-#include
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief Changes the prescaler value of the given RTT and restarts it.
- *
- * \note This function disables RTT interrupt sources.
- *
- * \param rtt Pointer to a Rtt instance.
- * \param prescaler Prescaler value for the RTT.
- */
-void RTT_SetPrescaler(Rtt *rtt, uint16_t prescaler)
-{
- rtt->RTT_MR = (prescaler | RTT_MR_RTTRST);
-}
-
-/**
- * \brief Returns the current value of the RTT timer value.
- *
- * \param rtt Pointer to a Rtt instance.
- */
-uint32_t RTT_GetTime(Rtt *rtt)
-{
- return rtt->RTT_VR;
-}
-
-/**
- * \brief Enables the specified RTT interrupt sources.
- *
- * \param rtt Pointer to a Rtt instance.
- * \param sources Bitmask of interrupts to enable.
- */
-void RTT_EnableIT(Rtt *rtt, uint32_t sources)
-{
- ASSERT((sources & 0x0004FFFF) == 0,
- "RTT_EnableIT: Wrong sources value.\n\r");
- rtt->RTT_MR |= sources;
-}
-
-/**
- * \brief Returns the status register value of the given RTT.
- *
- * \param rtt Pointer to an Rtt instance.
- */
-uint32_t RTT_GetStatus(Rtt *rtt)
-{
- return rtt->RTT_SR;
-}
-
-/**
- * \brief Configures the RTT to generate an alarm at the given time.
- *
- * \param pRtt Pointer to an Rtt instance.
- * \param time Alarm time.
- */
-void RTT_SetAlarm(Rtt *pRtt, uint32_t time)
-{
- SANITY_CHECK(time > 0);
-
- pRtt->RTT_AR = time - 1;
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/rtt/rtt.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/rtt/rtt.h
deleted file mode 100644
index 13d4b716..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/rtt/rtt.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- *
- * \par Purpose
- *
- * Interface for Real Time Timer (RTT) controller.
- *
- * \par Usage
- *
- * -# Changes the prescaler value of the given RTT and restarts it
- * using \ref RTT_SetPrescaler().
- * -# Get current value of the RTT using \ref RTT_GetTime().
- * -# Enables the specified RTT interrupt using \ref RTT_EnableIT().
- * -# Get the status register value of the given RTT using \ref RTT_GetStatus().
- * -# Configures the RTT to generate an alarm at the given time
- * using \ref RTT_SetAlarm().
- */
-
-#ifndef RTT_H
-#define RTT_H
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include
-
-/*----------------------------------------------------------------------------
- * Definitions
- *----------------------------------------------------------------------------*/
-
-#ifndef AT91C_BASE_RTTC
- #define AT91C_BASE_RTTC RTT
-#endif
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-extern void RTT_SetPrescaler(Rtt *rtt, uint16_t prescaler);
-
-extern uint32_t RTT_GetTime(Rtt *rtt);
-
-extern void RTT_EnableIT(Rtt *rtt, uint32_t sources);
-
-extern uint32_t RTT_GetStatus(Rtt *rtt);
-
-extern void RTT_SetAlarm(Rtt *pRtt, uint32_t time);
-
-#endif /* #ifndef RTT_H */
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/at45d.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/at45d.c
deleted file mode 100644
index 4a608837..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/at45d.c
+++ /dev/null
@@ -1,253 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/** \addtogroup at45d_module AT45 driver.
- * The AT45 Dataflash driver is based on the corresponding AT45 driver.
- * A AT45 instance has to be initialized using the Dataflash levle function
- * AT45_Configure(). AT45 Dataflash can be automatically detected using
- * the AT45_FindDevice() function. Then AT45 dataflash operations such as
- * read, write and erase DF can be launched using AT45_SendCommand function
- * with corresponding AT45 command set.
- *
- * \usage
- *
- *
Reads data from the At45 at the specified address using AT45D_Read().
- *
Writes data on the At45 at the specified address using AT45D_Write().
- *
Erases a page of data at the given address using AT45D_Erase().
- *
Poll until the At45 has completed of corresponding operations using
- * AT45D_WaitReady().
- *
Retrieves and returns the At45 current using AT45D_GetStatus().
- *
- * Related files :\n
- * \ref at45d.c\n
- * \ref at45d.h.\n
- */
- /*@{*/
- /*@}*/
-
-
-/**
- * \file
- *
- * Implementation of At45 driver.
- *
- */
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include "spi_at45.h"
-#include "at45d.h"
-#include
-#include
-
-/*----------------------------------------------------------------------------
- * Local functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief Wait for transfer to finish calling the SPI driver ISR (interrupts are
- * disabled).
- *
- * \param pAt45 Pointer to an AT45 driver instance.
- */
-static void AT45D_Wait(At45 *pAt45)
-{
- SANITY_CHECK(pAt45);
-
- /* Wait for transfer to finish*/
- while (AT45_IsBusy(pAt45)) {
-
- SPID_Handler(pAt45->pSpid);
- }
-}
-
-/*----------------------------------------------------------------------------
- * Global functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief Waits for the At45 to be ready to accept new commands.
- *
- * \param pAt45 Pointer to an AT45 driver instance.
- */
-void AT45D_WaitReady(At45 *pAt45)
-{
- uint8_t ready = 0;
-
- SANITY_CHECK(pAt45);
- /* Poll device until it is ready.*/
- while (!ready) {
- ready = AT45_STATUS_READY(AT45D_GetStatus(pAt45));
- }
-}
-
-/**
- * \brief Retrieves and returns the At45 current status, or 0 if an error happened.
- *
- * \param pAt45 Pointer to an AT45 driver instance.
- */
-uint8_t AT45D_GetStatus(At45 *pAt45)
-{
- uint8_t error;
- uint8_t status;
-
- SANITY_CHECK(pAt45);
-
- /* Issue a status register read command*/
- error = AT45_SendCommand(pAt45, AT45_STATUS_READ, 1, &status, 1, 0, 0, 0);
- ASSERT(!error, "-F- AT45_GetStatus: Failed to issue command.\n\r");
-
- /* Wait for command to terminate*/
- while (AT45_IsBusy(pAt45)) {
- AT45D_Wait(pAt45);
- }
- return status;
-}
-
-/**
- * \brief Reads data from the At45 inside the provided buffer. Since a continuous
- * read command is used, there is no restriction on the buffer size and read address.
- *
- * \param pAt45 Pointer to an AT45 driver instance.
- * \param pBuffer Data buffer.
- * \param size Number of bytes to read.
- * \param address Address at which data shall be read.
- */
-void AT45D_Read(
- At45 *pAt45,
- uint8_t *pBuffer,
- uint32_t size,
- uint32_t address)
-{
- uint8_t error;
-
- SANITY_CHECK(pAt45);
- SANITY_CHECK(pBuffer);
-
- /* Issue a continuous read array command.*/
- error = AT45_SendCommand(pAt45, AT45_CONTINUOUS_READ_LEG, 8, pBuffer, size, address, 0, 0);
- ASSERT(!error, "-F- AT45_Read: Failed to issue command\n\r");
-
- /* Wait for the read command to execute.*/
- while (AT45_IsBusy(pAt45)) {
-
- AT45D_Wait(pAt45);
- }
-}
-
-/**
- * \brief Writes data on the At45 at the specified address. Only one page of
- * data is written that way; if the address is not at the beginning of the
- * page, the data is written starting from this address and wraps around to
- * the beginning of the page.
- * \param pAt45 Pointer to an AT45 driver instance.
- * \param pBuffer Data buffer.
- * \param size Number of bytes to write.
- * \param address Destination address on the At45.
- */
-void AT45D_Write(
- At45 *pAt45,
- uint8_t *pBuffer,
- uint32_t size,
- uint32_t address)
-{
- uint8_t error;
-
- SANITY_CHECK(pAt45);
- SANITY_CHECK(pBuffer);
- SANITY_CHECK(size <= pAt45->pDesc->pageSize);
-
- /* Issue a page write through buffer 1 command. */
- error = AT45_SendCommand(pAt45, AT45_PAGE_WRITE_BUF1, 4, pBuffer, size, address, 0, 0);
- ASSERT(!error, "-F- AT45_Write: Could not issue command.\n\r");
-
- /* Wait until the command is sent. */
- while (AT45_IsBusy(pAt45)) {
-
- AT45D_Wait(pAt45);
- }
-
- /* Wait until the At45 becomes ready again.*/
- AT45D_WaitReady(pAt45);
-}
-
-/**
- * \brief Erases a page of data at the given address in the At45.
- *
- * \param pAt45 Pointer to an AT45 driver instance.
- * \param address Address of page to erase.
- */
-void AT45D_Erase(At45 *pAt45, uint32_t address)
-{
- uint8_t error;
-
- SANITY_CHECK(pAt45);
-
- /* Issue a page erase command. */
- error = AT45_SendCommand(pAt45, AT45_PAGE_ERASE, 4, 0, 0, address, 0, 0);
- ASSERT(!error, "-F- AT45_Erase: Could not issue command.\n\r");
-
- /* Wait for end of transfer. */
- while (AT45_IsBusy(pAt45)) {
-
- AT45D_Wait(pAt45);
- }
-
- /* Poll until the At45 has completed the erase operation.*/
- AT45D_WaitReady(pAt45);
-}
-
-/**
- * \brief Configure power-of-2 binary page size in the At45.
- *
- * \param pAt45 Pointer to an AT45 driver instance.
- */
-void AT45D_BinaryPage(At45 *pAt45)
-{
- uint8_t error;
- uint8_t opcode[3]= {AT45_BINARY_PAGE};
- SANITY_CHECK(pAt45);
-
- /* Issue a binary page command. */
-
- error = AT45_SendCommand(pAt45, AT45_BINARY_PAGE_FIRST_OPCODE, 1, opcode, 3, 0, 0, 0);
-
- ASSERT(!error, "-F- AT45_Erase: Could not issue command.\n\r");
-
- /* Wait for end of transfer.*/
- while (AT45_IsBusy(pAt45)) {
-
- AT45D_Wait(pAt45);
- }
-
- /* Wait until the At45 becomes ready again.*/
- AT45D_WaitReady(pAt45);
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/at45d.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/at45d.h
deleted file mode 100644
index 31a06ab6..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/at45d.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- *
- * Implementation of At45 driver.
- *
- */
-
-
-#ifndef AT45D_H
-#define AT45D_H
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include "spi_at45.h"
-
-/*----------------------------------------------------------------------------
- * Global functions
- *----------------------------------------------------------------------------*/
-
-extern void AT45D_WaitReady(At45 *pAt45);
-
-extern uint8_t AT45D_GetStatus(At45 *pAt45);
-
-extern void AT45D_Read(
- At45 *pAt45,
- uint8_t *pBuffer,
- uint32_t size,
- uint32_t address);
-
-extern void AT45D_Write(
- At45 *pAt45,
- uint8_t *pBuffer,
- uint32_t size,
- uint32_t address);
-
-extern void AT45D_Erase(At45 *pAt45, uint32_t address);
-
-extern void AT45D_BinaryPage(At45 *pAt45);
-
-#endif //#ifndef AT45D_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/spi_at45.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/spi_at45.c
deleted file mode 100644
index 679a7d78..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/spi_at45.c
+++ /dev/null
@@ -1,311 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/** \addtogroup spi_at45_module SPI AT45 driver.
- * The Dataflash driver is based on top of the corresponding Spi driver.
- * A Dataflash structure instance has to be initialized using the DF_Init
- * function. Then basic dataflash operations can be launched using macros such
- * as DF_continuous_read. These macros invoke the DF_Command() function which
- * invokes the DPI low driver using the SPI_SendCommand() function.
- * Beware to compute the dataflash internal address, the dataflash sector
- * description must be known (DataflashDesc). Dataflash can be automatically
- * detected using the DF_Scan() function.
- *
- * \usage
- *
- *
Initializes an AT45 instance and configures SPI chip select pin
- * using AT45_Configure().
- *
Detect DF and returns DF description corresponding to the device
- * connected using AT45_FindDevice().This function shall be called by
- * the application before AT45_SendCommand.
- *
Sends a command to the DF through the SPI using AT45_SendCommand().
- * The command is identified by its command code and the number of
- * bytes to transfer.
- *
Example code for sending command to write a page to DF.
This function does not block; its optional callback will
- * be invoked when the transfer completes.
- *
Check the AT45 driver is ready or not by polling AT45_IsBusy().
- *
- * Related files :\n
- * \ref spi_at45.c\n
- * \ref spi_at45.h.\n
-*/
-/*@{*/
-/*@}*/
-
-
-/**
- * \file
- *
- * Implementation of SPI At45 driver.
- *
- */
-
-
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include "spi_at45.h"
-#include
-#include
-#include
-
-/*----------------------------------------------------------------------------
- * Internal definitions
- *----------------------------------------------------------------------------*/
-
-/** Number of dataflash which can be recognized.*/
-#define NUMDATAFLASH (sizeof(at45Devices) / sizeof(At45Desc))
-
-/*----------------------------------------------------------------------------
- * Local variables
- *----------------------------------------------------------------------------*/
-
-/** indicate if the device is configured as binary page or not.*/
-static uint8_t configuredBinaryPage;
-
-/** At45 device descriptor structure. */
-static const At45Desc at45Devices[] = {
- { 512, 1, 264, 9, 0x0C, "AT45DB011D"},
- { 1024, 1, 264, 9, 0x14, "AT45DB021D"},
- { 2048, 1, 264, 9, 0x1C, "AT45DB041D"},
- { 4096, 1, 264, 9, 0x24, "AT45DB081D"},
- { 4096, 1, 528, 10, 0x2C, "AT45DB161D"},
- { 8192, 1, 528, 10, 0x34, "AT45DB321D"},
- { 8192, 1, 1056, 11, 0x3C, "AT45DB642D"},
- {16384, 1, 1056, 11, 0x10, "AT45DB1282"},
- {16384, 1, 2112, 12, 0x18, "AT45DB2562"},
- {32768, 1, 2112, 12, 0x20, "AT45DB5122"}
-};
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief Initializes an AT45 instance and configures SPI chip select register.
- *
- * \param pAt45 Pointer to the At45 instance to initialize.
- * \param pSpid Pointer to the underlying SPI driver.
- * \param spiCs Chip select value to connect to the At45.
- * \return 0.
- */
-uint8_t AT45_Configure(At45 *pAt45, Spid *pSpid, uint8_t spiCs)
-{
- SpidCmd *pCommand;
-
- /* Sanity checks */
- ASSERT(pSpid, "AT45_Configure: pSpid is 0.\n\r");
- ASSERT(pAt45, "AT45_Configure: pAt45 is 0.\n\r");
-
- /* Initialize the At45 instance */
- pAt45->pSpid = pSpid;
- pAt45->pDesc = 0;
- memset(pAt45->pCmdBuffer, 0, 8);
-
- /* Initialize the spidCmd structure*/
- pCommand = &(pAt45->command);
- pCommand->pCmd = pAt45->pCmdBuffer;
- pCommand->callback = 0;
- pCommand->pArgument = 0;
- pCommand->spiCs = spiCs;
-
- return 0;
-}
-
-/**
- * \brief Check if the At45 driver is in busy.
- *
- * \param pAt45 Pointer to the At45 instance to initialize.
- * \return 1 if the At45 driver is not executing any command,otherwise it returns 0.
- */
-uint8_t AT45_IsBusy(At45 *pAt45)
-{
- return SPID_IsBusy(pAt45->pSpid);
-}
-
-/**
- * \brief Sends a command to the dataflash through the SPI.
- * The command is identified by its command code and the number of bytes to transfer
- * (1 + number of address bytes + number of dummy bytes).If data needs to be received,
- * then a data buffer must be provided.
- * \note This function does not block; its optional callback will be invoked when
- * the transfer completes.
- * \param pAt45 Pointer to the At45 instance to initialize.
- * \param cmd Command code.
- * \param cmdSize Size of command code + address bytes + dummy bytes.
- * \param pData Data buffer.
- * \param dataSize Number of data bytes to send/receive.
- * \param address Address at which the command is performed if meaningful.
- * \param callback Optional callback to invoke at end of transfer.
- * \param pArgument Optional parameter to the callback function.
- * \return 0.
- */
-uint8_t AT45_SendCommand(
- At45 *pAt45,
- uint8_t cmd,
- uint8_t cmdSize,
- uint8_t *pData,
- uint32_t dataSize,
- uint32_t address,
- SpidCallback callback,
- void *pArgument)
-{
- SpidCmd *pCommand;
- const At45Desc *pDesc = pAt45->pDesc;
- uint32_t dfAddress = 0;
-
- /* Sanity checks*/
- ASSERT(pAt45, "AT45_Command: pAt45 is 0.\n\r");
- ASSERT(pDesc || (cmd == AT45_STATUS_READ),
- "AT45_Command: Device has no descriptor, only STATUS_READ command allowed\n\r");
-
- /* Check if the SPI driver is available*/
- if (AT45_IsBusy(pAt45)) {
-
- return AT45_ERROR_LOCK;
- }
-
- /* Compute command pattern*/
- pAt45->pCmdBuffer[0] = cmd;
-
- /* Add address bytes if necessary*/
- if (cmdSize > 1) {
-
- ASSERT(pDesc, "AT45_Command: No descriptor for dataflash.\n\r");
- if (!configuredBinaryPage) {
- dfAddress =
- ((address / (pDesc->pageSize)) << pDesc->pageOffset)
- + (address % (pDesc->pageSize));
- }
- else {
- dfAddress = address;
- }
- /* Write address bytes*/
- if (pDesc->pageNumber >= 16384) {
-
- pAt45->pCmdBuffer[1] = ((dfAddress & 0x0F000000) >> 24);
- pAt45->pCmdBuffer[2] = ((dfAddress & 0x00FF0000) >> 16);
- pAt45->pCmdBuffer[3] = ((dfAddress & 0x0000FF00) >> 8);
- pAt45->pCmdBuffer[4] = ((dfAddress & 0x000000FF) >> 0);
-
- if ((cmd != AT45_CONTINUOUS_READ) && (cmd != AT45_PAGE_READ)) {
-
- cmdSize++;
- }
- }
- else {
-
- pAt45->pCmdBuffer[1] = ((dfAddress & 0x00FF0000) >> 16);
- pAt45->pCmdBuffer[2] = ((dfAddress & 0x0000FF00) >> 8);
- pAt45->pCmdBuffer[3] = ((dfAddress & 0x000000FF) >> 0);
- }
- }
-
- /* Update the SPI Transfer descriptors*/
- pCommand = &(pAt45->command);
- pCommand->cmdSize = cmdSize;
- pCommand->pData = pData;
- pCommand->dataSize = dataSize;
- pCommand->callback = callback;
- pCommand->pArgument = pArgument;
-
- /* Send Command and data through the SPI*/
- if (SPID_SendCommand(pAt45->pSpid, pCommand)) {
-
- return AT45_ERROR_SPI;
- }
-
- return 0;
-}
-
-/**
- * \brief returns the At45Desc structure corresponding to the device connected.
- * It automatically initializes pAt45->pDesc field structure.
- * \note This function shall be called by the application before AT45_SendCommand.
- * \param pAt45 Pointer to the At45 instance to initialize.
- * \param status Device status register value.
- * \return 0 if successful; Otherwise, returns AT45_ERROR_LOCK if the At45
- * driver is in use or AT45_ERROR_SPI if there was an error with the SPI driver.
- */
-const At45Desc * AT45_FindDevice(At45 *pAt45, uint8_t status)
-{
- uint32_t i;
- uint8_t id = AT45_STATUS_ID(status);
-
- /* Check if status is all one; in which case, it is assumed that no device is connected*/
- if (status == 0xFF) {
-
- return 0;
- }
-
- /* Look in device array */
- i = 0;
- pAt45->pDesc = 0;
- while ((i < NUMDATAFLASH) && !(pAt45->pDesc)) {
-
- if (at45Devices[i].id == id) {
-
- pAt45->pDesc = &(at45Devices[i]);
- }
- i++;
- }
- configuredBinaryPage = AT45_STATUS_BINARY(status);
- return pAt45->pDesc;
-}
-
-/**
- * \brief returns the pagesize corresponding to the device connected.
- * \param pAt45 Pointer to the At45 instance to initialize.
- * \param status Device status register value.
- * \return page size.
- */
-uint32_t AT45_PageSize(At45 *pAt45)
-{
- uint32_t pagesize = pAt45->pDesc->pageSize;
- if(((pAt45->pDesc->hasBinaryPage) == 0) || !configuredBinaryPage){
- return pagesize;
- }
- return ((pagesize >> 8) << 8);
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/spi_at45.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/spi_at45.h
deleted file mode 100644
index fc1fca4e..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/spi_at45.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- *
- * Implementation of SPI At45 driver.
- *
- */
-
-#ifndef SPI_AT45_H
-#define SPI_AT45_H
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-#include "spi_pdc.h"
-
-/*----------------------------------------------------------------------------
- * Macros
- *----------------------------------------------------------------------------*/
-/** Returns 1 if the device is ready; otherwise 0.*/
-#define AT45_STATUS_READY(status) (status & 0x80)
-/** Returns the device ID code.*/
-#define AT45_STATUS_ID(status) (status & 0x3c)
-/** Returns 1 if the device is configured in binary page mode; otherwise 0.*/
-#define AT45_STATUS_BINARY(status) (status & 0x01)
-
-#define AT45_PageOffset(pAt45) ((pAt45)->pDesc->pageOffset)
-#define AT45_PageNumber(pAt45) ((pAt45)->pDesc->pageNumber)
-
-/*----------------------------------------------------------------------------
- * Definitions
- *----------------------------------------------------------------------------*/
-
-/** The dataflash driver is currently in use.*/
-#define AT45_ERROR_LOCK 1
-/** There was an error with the SPI driver.*/
-#define AT45_ERROR_SPI 2
-
-/** AT45 dataflash SPI CSR settings given MCK and SPCK.*/
-#define AT45_CSR(mck, spck) (SPI_CSR_NCPHA | SPID_CSR_DLYBCT(mck, 250) | SPID_CSR_DLYBS(mck, 250) | SPID_CSR_SCBR(mck, spck))
-
-/** Main memory page read command code. */
-#define AT45_PAGE_READ 0xD2
-/** Continous array read (legacy) command code.*/
-#define AT45_CONTINUOUS_READ_LEG 0xE8
-/** Continous array read (low frequency) command code.*/
-#define AT45_CONTINUOUS_READ_LF 0x03
-/** Continous array read command code.*/
-#define AT45_CONTINUOUS_READ 0x0B
-/** Buffer 1 read (low frequency) command code.*/
-#define AT45_BUF1_READ_LF 0xD1
-/** Buffer 2 read (low frequency) command code.*/
-#define AT45_BUF2_READ_LF 0xD3
-/** Buffer 1 read (serial) command code.*/
-#define AT45_BUF1_READ_SER 0xD4
-/** Buffer 2 read (serial) command code.*/
-#define AT45_BUF2_READ_SER 0xD6
-/** Buffer 1 read (8-bit) command code.*/
-#define AT45_BUF1_READ_8B 0x54
-/** Buffer 2 read (8-bit) command code.*/
-#define AT45_BUF2_READ_8B 0x56
-
-/** Buffer 1 write command code.*/
-#define AT45_BUF1_WRITE 0x84
-/** Buffer 2 write command code.*/
-#define AT45_BUF2_WRITE 0x87
-/** Buffer 1 to main memory page program with erase command code.*/
-#define AT45_BUF1_MEM_ERASE 0x83
-/** Buffer 2 to main memory page program with erase command code.*/
-#define AT45_BUF2_MEM_ERASE 0x86
-/** Buffer 1 to main memory page program without erase command code.*/
-#define AT45_BUF1_MEM_NOERASE 0x88
-/** Buffer 2 to main memory page program without erase command code.*/
-#define AT45_BUF2_MEM_NOERASE 0x89
-/** Page erase command code.*/
-#define AT45_PAGE_ERASE 0x81
-/** Block erase command code.*/
-#define AT45_BLOCK_ERASE 0x50
-/** Sector erase command code.*/
-#define AT45_SECTOR_ERASE 0x7C
-/** Chip erase command code.*/
-#define AT45_CHIP_ERASE 0xC7, 0x94, 0x80, 0x9A
-/** Main memory page program through buffer 1 command code.*/
-#define AT45_PAGE_WRITE_BUF1 0x82
-/** Main memory page program through buffer 2 command code.*/
-#define AT45_PAGE_WRITE_BUF2 0x85
-
-/** Main memory page to buffer 1 transfer command code.*/
-#define AT45_PAGE_BUF1_TX 0x53
-/** Main memory page to buffer 2 transfer command code.*/
-#define AT45_PAGE_BUF2_TX 0x55
-/** Main memory page to buffer 1 compare command code.*/
-#define AT45_PAGE_BUF1_CMP 0x60
-/** Main memory page to buffer 2 compare command code.*/
-#define AT45_PAGE_BUF2_CMP 0x61
-/** Auto page rewrite through buffer 1 command code.*/
-#define AT45_AUTO_REWRITE_BUF1 0x58
-/** Auto page rewrite through buffer 2 command code.*/
-#define AT45_AUTO_REWRITE_BUF2 0x59
-/** Deep power-down command code.*/
-#define AT45_DEEP_PDOWN 0xB9
-/** Resume from deep power-down command code.*/
-#define AT45_RES_DEEP_PDOWN 0xAB
-/** Status register read command code.*/
-#define AT45_STATUS_READ 0xD7
-/** Manufacturer and device ID read command code.*/
-#define AT45_ID_READ 0x9F
-
-/** Power-of-2 binary page size configuration command code.*/
-#define AT45_BINARY_PAGE_FIRST_OPCODE 0x3D
-#define AT45_BINARY_PAGE 0x2A, 0x80, 0xA6
-
-/*----------------------------------------------------------------------------
- * Types
- *----------------------------------------------------------------------------*/
-
-/** Dataflash description. A constant array of DataflashDesc instance is defined
- in at45.c. The DF_Scan() function returns the corresponding descriptor according
- to the dataflash ID detected. This description (page_size, page_offset) is used
- to compute the internal dataflash address by the DF_Command() function. */
-typedef struct {
- /** dataflash page number. */
- uint32_t pageNumber;
- // indicate if power-of-2 binary page supported.*/
- uint32_t hasBinaryPage;
- /** dataflash page size.*/
- uint32_t pageSize;
- /** page offset in command.*/
- uint32_t pageOffset;
- /** Dataflash ID.*/
- uint8_t id;
- /** Identifier.*/
- const char *name;
-} At45Desc;
-
-/** Dataflash driver structure. It holds the current command being processed.
- This structure is initialized by the DF_Init() command.
- pDfDesc field can be initialized by the DF_Scan() function.
- cmdBuffer is a private driver area used to compute the dataflash address to
- be sent to the dataflash. Beware the PDC master must have access to this area.*/
-typedef struct _Dataflash {
- /** Pointer to Spi Structure (SPI low level driver).*/
- Spid *pSpid;
- /** Current SPI command sent to the SPI low level driver.*/
- SpidCmd command;
- /** Pointer to the dataflash description.*/
- const At45Desc *pDesc;
- /** Buffer to store the current command (opcode + dataflash address.*/
- uint8_t pCmdBuffer[8];
-} At45;
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-extern uint8_t AT45_Configure(At45 *pAt45, Spid *pSpid, uint8_t spiCs);
-
-extern uint8_t AT45_IsBusy(At45 *pAt45);
-
-extern uint8_t AT45_SendCommand(
- At45 *pAt45,
- uint8_t cmd,
- uint8_t cmdSize,
- uint8_t *pData,
- uint32_t dataSize,
- uint32_t address,
- SpidCallback callback,
- void *pArgument);
-
-extern const At45Desc * AT45_FindDevice(At45 *pAt45, uint8_t status);
-
-extern uint32_t AT45_PageSize(At45 *pAt45);
-#endif // #ifndef SPI_AT45_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/spi_pdc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/spi_pdc.c
deleted file mode 100644
index d0998b04..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/spi_pdc.c
+++ /dev/null
@@ -1,275 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/** \addtogroup spi_pdc_module SPI PDC driver
- * The Spi driver is a low level spi driver which performs SPI device Initializes,
- * spi transfer and receive. It can be used by upper SPI driver such as AT45
- * driver and AT26 driver.
- *
- * \usage
- *
- *
Initializes a SPI instance and the corresponding SPI hardware,
- * Configure SPI in Master Mode using SPID_Configure().
- *
Configures the SPI characteristics (such as Clock Polarity, Phase,
- * transfers delay and Baud Rate) for the device corresponding to the
- * chip select using SPID_ConfigureCS().
- *
Starts a SPI master transfer using SPID_SendCommand().
- * The transfer is performed using the PDC channels.
- *
It enable the SPI clock.
- *
Set the corresponding peripheral chip select.
- *
Initialize the two SPI PDC buffers.
- *
Initialize SPI_TPR and SPI_TCR with SPI command data and size
- * to send command data first.
- *
Initialize SPI_RPR and SPI_RCR with SPI command data and size
- * as dummy value.
- *
Initialize SPI_TNPR and SPI_TNCR with rest of the data to be
- * transfered.(if the data specified in cmd structure)
- *
Initialize SPI_RNPR and SPI_RNCR with rest of the data to be
- * received.(if the data specified in cmd structure)
- *
Initialize the callback function if specified.
- *
Enable transmitter and receiver.
- *
Example for sending a command to the dataflash through the SPI.
- * \code
- * /// Build command to be sent.
- * ...
- * // Send Command and data through the SPI
- * if (SPID_SendCommand(pAt45->pSpid, pCommand)) {
- * return AT45_ERROR_SPI;
- * }
- * \endcode
- *
The SPI_Handler() must be called by the SPI Interrupt Service Routine
- * with the corresponding Spi instance. It is invokes to check for pending
- * interrupts.
- *
Example for initializing SPI interrupt handler in upper application.
- * Related files :\n
- * \ref spi_pdc.c\n
- * \ref spi_pdc.h.\n
-*/
-/*@{*/
-/*@}*/
-
-
-/**
- * \file
- *
- * Implementation of SPI PDC driver.
- *
- */
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include "spi_pdc.h"
-#include
-
-/*----------------------------------------------------------------------------
- * Macros
- *----------------------------------------------------------------------------*/
-
-/** Write PMC register*/
-#define WRITE_PMC(pPmc, regName, value) pPmc->regName = (value)
-
-/** Write SPI register*/
-#define WRITE_SPI(pSpi, regName, value) pSpi->regName = (value)
-
-/** Read SPI registers */
-#define READ_SPI(pSpi, regName) (pSpi->regName)
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief Initializes the Spid structure and the corresponding SPI hardware.
- *
- * \param pSpid Pointer to a Spid instance.
- * \param pSpiHw Associated SPI peripheral.
- * \param spiId SPI peripheral identifier.
- * \return 0.
- */
-uint8_t SPID_Configure(Spid *pSpid, Spi *pSpiHw, uint8_t spiId)
-{
- /* Initialize the SPI structure*/
- pSpid->pSpiHw = pSpiHw;
- pSpid->spiId = spiId;
- pSpid->semaphore = 1;
- pSpid->pCurrentCommand = 0;
-
- /* Enable the SPI clock*/
- WRITE_PMC(PMC, PMC_PCER0, (1 << pSpid->spiId));
-
- /* Execute a software reset of the SPI twice */
- WRITE_SPI(pSpiHw, SPI_CR, SPI_CR_SWRST);
- WRITE_SPI(pSpiHw, SPI_CR, SPI_CR_SWRST);
-
- /* Configure SPI in Master Mode with No CS selected !!! */
- WRITE_SPI(pSpiHw, SPI_MR, SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_MR_PCS);
-
- /* Enable the SPI*/
- WRITE_SPI(pSpiHw, SPI_CR, SPI_CR_SPIEN);
-
- /* Enable the SPI clock*/
- WRITE_PMC(PMC, PMC_PCDR0, (1 << pSpid->spiId));
-
- return 0;
-}
-
-/**
- * \brief Configures the parameters for the device corresponding to the cs.
- *
- * \param pSpid Pointer to a Spid instance.
- * \param cs number corresponding to the SPI chip select.
- * \param csr SPI_CSR value to setup.
- */
-void SPID_ConfigureCS(Spid *pSpid, uint8_t cs, uint32_t csr)
-{
- Spi *pSpiHw = pSpid->pSpiHw;
- WRITE_SPI(pSpiHw, SPI_CSR[cs], csr);
-}
-
-/**
- * \brief Starts a SPI master transfer. This is a non blocking function. It will
- * return as soon as the transfer is started.
- *
- * \param pSpid Pointer to a Spid instance.
- * \param pCommand Pointer to the SPI command to execute.
- * \return 0 if the transfer has been started successfully; otherwise returns
- * SPID_ERROR_LOCK is the driver is in use, or SPID_ERROR if the command is not
- * valid.
- */
-uint8_t SPID_SendCommand(Spid *pSpid, SpidCmd *pCommand)
-{
- Spi *pSpiHw = pSpid->pSpiHw;
- uint32_t spiMr;
-
- /* Try to get the dataflash semaphore */
- if (pSpid->semaphore == 0) {
-
- return SPID_ERROR_LOCK;
- }
- pSpid->semaphore--;
-
- /* Enable the SPI clock */
- WRITE_PMC(PMC, PMC_PCER0, (1 << pSpid->spiId));
-
- /* Disable transmitter and receiver*/
- WRITE_SPI(pSpiHw, SPI_PTCR, SPI_PTCR_RXTDIS | SPI_PTCR_TXTDIS);
-
- /* Write to the MR register*/
- spiMr = READ_SPI(pSpiHw, SPI_MR);
- spiMr |= SPI_MR_PCS;
- spiMr &= ~((1 << pCommand->spiCs) << 16);
- WRITE_SPI(pSpiHw, SPI_MR, spiMr);
-
- /* Initialize the two SPI PDC buffer*/
- WRITE_SPI(pSpiHw, SPI_RPR, (int) pCommand->pCmd);
- WRITE_SPI(pSpiHw, SPI_RCR, pCommand->cmdSize);
- WRITE_SPI(pSpiHw, SPI_TPR, (int) pCommand->pCmd);
- WRITE_SPI(pSpiHw, SPI_TCR, pCommand->cmdSize);
-
- WRITE_SPI(pSpiHw, SPI_RNPR, (int) pCommand->pData);
- WRITE_SPI(pSpiHw, SPI_RNCR, pCommand->dataSize);
- WRITE_SPI(pSpiHw, SPI_TNPR, (int) pCommand->pData);
- WRITE_SPI(pSpiHw, SPI_TNCR, pCommand->dataSize);
-
- /* Initialize the callback*/
- pSpid->pCurrentCommand = pCommand;
-
- /* Enable transmitter and receiver*/
- WRITE_SPI(pSpiHw, SPI_PTCR, SPI_PTCR_RXTEN | SPI_PTCR_TXTEN);
-
- /* Enable buffer complete interrupt*/
- WRITE_SPI(pSpiHw, SPI_IER, SPI_IER_RXBUFF);
-
- return 0;
-}
-
-
-/**
- * \brief The SPI_Handler must be called by the SPI Interrupt Service Routine with the
- * corresponding Spi instance.
- *
- * \note The SPI_Handler will unlock the Spi semaphore and invoke the upper application
- * callback.
- * \param pSpid Pointer to a Spid instance.
- */
-void SPID_Handler(Spid *pSpid)
-{
- SpidCmd *pSpidCmd = pSpid->pCurrentCommand;
- Spi *pSpiHw = pSpid->pSpiHw;
- volatile uint32_t spiSr;
-
- /* Read the status register*/
- spiSr = READ_SPI(pSpiHw, SPI_SR);
- if (spiSr & SPI_SR_RXBUFF) {
-
- /* Disable transmitter and receiver */
- WRITE_SPI(pSpiHw, SPI_PTCR, SPI_PTCR_RXTDIS | SPI_PTCR_TXTDIS);
-
- /* Disable the SPI clock*/
- WRITE_PMC(PMC, PMC_PCDR0, (1 << pSpid->spiId));
-
- /* Disable buffer complete interrupt */
- WRITE_SPI(pSpiHw, SPI_IDR, SPI_IDR_RXBUFF);
-
- /* Release the dataflash semaphore*/
- pSpid->semaphore++;
-
- /* Invoke the callback associated with the current command*/
- if (pSpidCmd && pSpidCmd->callback) {
-
- pSpidCmd->callback(0, pSpidCmd->pArgument);
- }
-
- /* Nothing must be done after. A new DF operation may have been started
- in the callback function.*/
- }
-}
-
-/**
- * \brief Returns 1 if the SPI driver is currently busy executing a command; otherwise
- * returns 0.
- * \param pSpid Pointer to a Spid instance.
- */
-uint8_t SPID_IsBusy(const Spid *pSpid)
-{
- if (pSpid->semaphore == 0) {
-
- return 1;
- }
- else {
-
- return 0;
- }
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/spi_pdc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/spi_pdc.h
deleted file mode 100644
index bace9efc..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/spi_pdc.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- *
- * Implementation of SPI PDC driver.
- *
- */
-
-#ifndef SPI_PDC_H
-#define SPI_PDC_H
-
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-#include
-
-/*----------------------------------------------------------------------------
- * Definitions
- *----------------------------------------------------------------------------*/
-
-/** An unspecified error has occured.*/
-#define SPID_ERROR 1
-
-/** SPI driver is currently in use.*/
-#define SPID_ERROR_LOCK 2
-
-/*----------------------------------------------------------------------------
- * Macros
- *----------------------------------------------------------------------------*/
-
-/** Calculates the value of the SCBR field of the Chip Select Register given MCK and SPCK.*/
-#define SPID_CSR_SCBR(mck, spck) ((((mck) / (spck)) << 8) & SPI_CSR_SCBR)
-
-/** Calculates the value of the DLYBS field of the Chip Select Register given delay in ns and MCK.*/
-#define SPID_CSR_DLYBS(mck, delay) ((((((delay) * ((mck) / 1000000)) / 1000) + 1) << 16) & SPI_CSR_DLYBS)
-
-/** Calculates the value of the DLYBCT field of the Chip Select Register given delay in ns and MCK.*/
-#define SPID_CSR_DLYBCT(mck, delay) ((((((delay) / 32 * ((mck) / 1000000)) / 1000) + 1) << 24) & SPI_CSR_DLYBCT)
-
-/*----------------------------------------------------------------------------
- * Types
- *----------------------------------------------------------------------------*/
-
-/** SPI transfer complete callback.*/
-typedef void (*SpidCallback )(uint8_t, void *);
-
-/** Spi Transfer Request prepared by the application upper layer. This structure
- is sent to the SPI_SendCommand function to start the transfer. At the end of
- the transfer, the callback is invoked by the interrupt handler.*/
-typedef struct _SpidCmd {
-
- /** Pointer to the command data.*/
- uint8_t *pCmd;
- /** Command size in bytes.*/
- uint8_t cmdSize;
- /** Pointer to the data to be sent.*/
- uint8_t *pData;
- /** Data size in bytes.*/
- unsigned short dataSize;
- /** SPI chip select.*/
- uint8_t spiCs;
- /** Callback function invoked at the end of transfer.*/
- SpidCallback callback;
- /** Callback arguments.*/
- void *pArgument;
-
-} SpidCmd;
-
-/** Constant structure associated with SPI port. This structure prevents
- client applications to have access in the same time.*/
-typedef struct {
-
- /** Pointer to SPI Hardware registers*/
- Spi *pSpiHw;
- /** SPI Id as defined in the product datasheet*/
- char spiId;
- /** Current SpiCommand being processed*/
- SpidCmd *pCurrentCommand;
- /** Mutual exclusion semaphore.*/
- volatile char semaphore;
-
-} Spid;
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-extern uint8_t SPID_Configure(
- Spid *pSpid,
- Spi *pSpiHw,
- uint8_t spiId);
-
-extern void SPID_ConfigureCS(Spid *pSpid, uint8_t cs, uint32_t csr);
-
-extern uint8_t SPID_SendCommand(
- Spid *pSpid,
- SpidCmd *pCommand);
-
-extern void SPID_Handler(Spid *pSpid);
-
-extern uint8_t SPID_IsBusy(const Spid *pSpid);
-
-#endif // #ifndef SPI_PDC_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi/spi.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi/spi.c
deleted file mode 100644
index 4e6ba29a..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi/spi.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/** \addtogroup spi_module Working with SPI
- * The SPI driver provides the interface to configure and use the SPI
- * peripheral.
- *
- * The Serial Peripheral Interface (SPI) circuit is a synchronous serial
- * data link that provides communication with external devices in Master
- * or Slave Mode.
- *
- * To use the SPI, the user has to follow these few steps:
- * -# Enable the SPI pins required by the application (see pio.h).
- * -# Configure the SPI using the \ref SPI_Configure(). This enables the
- * peripheral clock. The mode register is loaded with the given value.
- * -# Configure all the necessary chip selects with \ref SPI_ConfigureNPCS().
- * -# Enable the SPI by calling \ref SPI_Enable().
- * -# Send/receive data using \ref SPI_Write() and \ref SPI_Read(). Note that \ref SPI_Read()
- * must be called after \ref SPI_Write() to retrieve the last value read.
- * -# Send/receive data using the PDC with the \ref SPI_WriteBuffer() and
- * \ref SPI_ReadBuffer() functions.
- * -# Disable the SPI by calling \ref SPI_Disable().
- *
- * For more accurate information, please look at the SPI section of the
- * Datasheet.
- *
- * Related files :\n
- * \ref spi.c\n
- * \ref spi.h.\n
-*/
-/*@{*/
-/*@}*/
-
-/**
- * \file
- *
- * Implementation of Serial Peripheral Interface (SPI) controller.
- *
- */
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include
-#include "spi.h"
-#include "pmc/pmc.h"
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief Enables a SPI peripheral.
- *
- * \param spi Pointer to an Spi instance.
- */
-void SPI_Enable(Spi *spi)
-{
- spi->SPI_CR = SPI_CR_SPIEN;
-}
-
-/**
- * \brief Disables a SPI peripheral.
- *
- * \param spi Pointer to an Spi instance.
- */
-void SPI_Disable(Spi *spi)
-{
- spi->SPI_CR = SPI_CR_SPIDIS;
-}
-
-/**
- * \brief Configures a SPI peripheral as specified. The configuration can be computed
- * using several macros (see \ref spi_configuration_macros).
- *
- * \param spi Pointer to an Spi instance.
- * \param id Peripheral ID of the SPI.
- * \param configuration Value of the SPI configuration register.
- */
-void SPI_Configure(Spi *spi,
- uint32_t id,
- uint32_t configuration)
-{
- PMC_EnablePeripheral(ID_SPI);
- spi->SPI_CR = SPI_CR_SPIDIS;
-
- /* Execute a software reset of the SPI twice */
- spi->SPI_CR = SPI_CR_SWRST;
- spi->SPI_CR = SPI_CR_SWRST;
- spi->SPI_MR = configuration;
-}
-
-/**
- * \brief Configures a chip select of a SPI peripheral. The chip select configuration
- * is computed using several macros (see \ref spi_configuration_macros).
- *
- * \param spi Pointer to an Spi instance.
- * \param npcs Chip select to configure (0, 1, 2 or 3).
- * \param configuration Desired chip select configuration.
- */
-void SPI_ConfigureNPCS(Spi *spi,
- uint32_t npcs,
- uint32_t configuration)
-{
- spi->SPI_CSR[npcs] = configuration;
-}
-
-/**
- * \brief Sends data through a SPI peripheral. If the SPI is configured to use a fixed
- * peripheral select, the npcs value is meaningless. Otherwise, it identifies
- * the component which shall be addressed.
- *
- * \param spi Pointer to an Spi instance.
- * \param npcs Chip select of the component to address (0, 1, 2 or 3).
- * \param data Word of data to send.
- */
-void SPI_Write(Spi *spi, uint32_t npcs, uint16_t data)
-{
- /* Send data */
- while ((spi->SPI_SR & SPI_SR_TXEMPTY) == 0);
- spi->SPI_TDR = data | SPI_PCS(npcs);
- while ((spi->SPI_SR & SPI_SR_TDRE) == 0);
-}
-
-/**
- * \brief Sends the contents of buffer through a SPI peripheral, using the PDC to
- * take care of the transfer.
- *
- * \param spi Pointer to an Spi instance.
- * \param buffer Data buffer to send.
- * \param length Length of the data buffer.
- */
-uint8_t SPI_WriteBuffer(Spi *spi,
- void *buffer,
- uint32_t length)
-{
- /* Check if first bank is free */
- if (spi->SPI_TCR == 0) {
-
- spi->SPI_TPR = (uint32_t) buffer;
- spi->SPI_TCR = length;
- spi->SPI_PTCR = PERIPH_PTCR_TXTEN;
- return 1;
- }
- /* Check if second bank is free */
- else if (spi->SPI_TNCR == 0) {
-
- spi->SPI_TNPR = (uint32_t) buffer;
- spi->SPI_TNCR = length;
- return 1;
- }
-
- /* No free banks */
- return 0;
-}
-
-/**
- * \brief Check if SPI transfer finish.
- *
- * \param spi Pointer to an Spi instance.
- *
- * \return Returns 1 if there is no pending write operation on the SPI; otherwise
- * returns 0.
- */
-uint8_t SPI_IsFinished(Spi *spi)
-{
- return ((spi->SPI_SR & SPI_SR_TXEMPTY) != 0);
-}
-
-/**
- * \brief Reads and returns the last word of data received by a SPI peripheral. This
- * method must be called after a successful SPI_Write call.
- *
- * \param spi Pointer to an Spi instance.
- *
- * \return readed data.
- */
-uint16_t SPI_Read(Spi *spi)
-{
- while ((spi->SPI_SR & SPI_SR_RDRF) == 0);
- return spi->SPI_RDR & 0xFFFF;
-}
-
-/**
- * \brief Reads data from a SPI peripheral until the provided buffer is filled. This
- * method does NOT need to be called after SPI_Write or SPI_WriteBuffer.
- *
- * \param spi Pointer to an Spi instance.
- * \param buffer Data buffer to store incoming bytes.
- * \param length Length in bytes of the data buffer.
- */
-uint8_t SPI_ReadBuffer(Spi *spi,
- void *buffer,
- uint32_t length)
-{
- /* Check if the first bank is free */
- if (spi->SPI_RCR == 0) {
-
- spi->SPI_RPR = (uint32_t) buffer;
- spi->SPI_RCR = length;
- spi->SPI_PTCR = PERIPH_PTCR_RXTEN;
- return 1;
- }
- /* Check if second bank is free */
- else if (spi->SPI_RNCR == 0) {
-
- spi->SPI_RNPR = (uint32_t) buffer;
- spi->SPI_RNCR = length;
- return 1;
- }
-
- /* No free bank */
- return 0;
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi/spi.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi/spi.h
deleted file mode 100644
index f78a34ba..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi/spi.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- *
- * Interface for Serial Peripheral Interface (SPI) controller.
- *
- */
-
-#ifndef SPI_H
-#define SPI_H
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include
-
-/*----------------------------------------------------------------------------
- * Macros
- *----------------------------------------------------------------------------*/
-
-/**
- * \page spi_configuration_macros SPI configuration macros
- *
- * This page lists several macros which should be used when configuring a SPI
- * peripheral.
- *
- * \par Macros:
- * - \ref SPI_PCS
- * - \ref SPI_SCBR
- * - \ref SPI_DLYBS
- * - \ref SPI_DLYBCT
- */
-
-/** Calculate the PCS field value given the chip select NPCS value */
-#define SPI_PCS(npcs) ((~(1 << npcs) & 0xF) << 16)
-
-/** Calculates the value of the CSR SCBR field given the baudrate and MCK. */
-#define SPI_SCBR(baudrate, masterClock) \
- ((uint32_t) (masterClock / baudrate) << 8)
-
-/** Calculates the value of the CSR DLYBS field given the desired delay (in ns) */
-#define SPI_DLYBS(delay, masterClock) \
- ((uint32_t) (((masterClock / 1000000) * delay) / 1000) << 16)
-
-/** Calculates the value of the CSR DLYBCT field given the desired delay (in ns) */
-#define SPI_DLYBCT(delay, masterClock) \
- ((uint32_t) (((masterClock / 1000000) * delay) / 32000) << 24)
-/*------------------------------------------------------------------------------ */
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-extern void SPI_Enable(Spi *spi);
-extern void SPI_Disable(Spi *spi);
-extern void SPI_Configure(Spi *spi,
- uint32_t id,
- uint32_t configuration);
-extern void SPI_ConfigureNPCS(Spi *spi,
- uint32_t npcs,
- uint32_t configuration);
-extern void SPI_Write(Spi *spi, uint32_t npcs, uint16_t data);
-extern uint8_t SPI_WriteBuffer(Spi *spi,
- void *buffer,
- uint32_t length);
-
-extern uint8_t SPI_IsFinished(Spi *pSpi);
-
-extern uint16_t SPI_Read(Spi *spi);
-extern uint8_t SPI_ReadBuffer(Spi *spi,
- void *buffer,
- uint32_t length);
-
-#endif /* #ifndef SPI_H */
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/ssc/ssc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/ssc/ssc.c
deleted file mode 100644
index 3fb0cc04..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/ssc/ssc.c
+++ /dev/null
@@ -1,248 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/** \addtogroup ssc module Working with SSC
- * The SSC driver provides the interface to configure and use the SSC
- * peripheral.
- *
- * !Usage
- *
- * -# Enable the SSC interface pins.
- * -# Configure the SSC to operate at a specific frequency by calling
- * SSC_Configure(). This function enables the peripheral clock of the SSC,
- * but not its PIOs.
- * -# Configure the transmitter and/or the receiver using the
- * SSC_ConfigureTransmitter() and SSC_ConfigureEmitter() functions.
- * -# Enable the PIOs or the transmitter and/or the received.
- * -# Enable the transmitter and/or the receiver using SSC_EnableTransmitter()
- * and SSC_EnableReceiver()
- * -# Send data through the transmitter using SSC_Write() and SSC_WriteBuffer()
- * -# Receive data from the receiver using SSC_Read() and SSC_ReadBuffer()
- * -# Disable the transmitter and/or the receiver using SSC_DisableTransmitter()
- * and SSC_DisableReceiver()
- *
- * For more accurate information, please look at the RTC section of the
- * Datasheet.
- *
- * Related files :\n
- * \ref ssc.c\n
- * \ref ssc.h.\n
-*/
-/*@{*/
-/*@}*/
-
-
-/**
- * \file
- *
- * Implementation of Synchronous Serial (SSC) controller.
- *
- */
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include
-#include "ssc.h"
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief Configures a SSC peripheral.If the divided clock is not used, the master
- * clock frequency can be set to 0.
- * \note The emitter and transmitter are disabled by this function.
- * \param bitRate bit rate.
- * \param masterClock master clock.
- */
-void SSC_Configure(uint32_t bitRate, uint32_t masterClock)
-{
- /* Enable SSC peripheral clock */
- PMC->PMC_PCER0 = 1 << ID_SSC;
-
- /* Reset, disable receiver & transmitter */
- SSC->SSC_CR = SSC_CR_RXDIS | SSC_CR_TXDIS | SSC_CR_SWRST;
-
- SSC->SSC_PTCR = SSC_PTCR_RXTDIS | SSC_PTCR_TXTDIS;
- /* Configure clock frequency */
- if (bitRate != 0) {
-
- SSC->SSC_CMR = masterClock / (2 * bitRate);
- }
- else {
-
- SSC->SSC_CMR = 0;
- }
-}
-
-/**
- * \brief Configures the transmitter of a SSC peripheral.
- * \param tcmr Transmit Clock Mode Register value.
- * \param tfmr Transmit Frame Mode Register value.
- */
-void SSC_ConfigureTransmitter(uint32_t tcmr, uint32_t tfmr)
-{
- SSC->SSC_TCMR = tcmr;
- SSC->SSC_TFMR = tfmr;
-}
-
-/**
- * \brief Configures the receiver of a SSC peripheral.
- * \param rcmr Receive Clock Mode Register value.
- * \param rfmr Receive Frame Mode Register value.
- */
-void SSC_ConfigureReceiver(uint32_t rcmr, uint32_t rfmr)
-{
- SSC->SSC_RCMR = rcmr;
- SSC->SSC_RFMR = rfmr;
-}
-
-/**
- * \brief Enables the transmitter of a SSC peripheral.
- */
-void SSC_EnableTransmitter(void)
-{
- SSC->SSC_CR = SSC_CR_TXEN;
-}
-
-/**
- * \brief Disables the transmitter of a SSC peripheral.
- */
-void SSC_DisableTransmitter(void)
-{
- SSC->SSC_CR = SSC_CR_TXDIS;
-}
-
-/**
- * \brief Enables the receiver of a SSC peripheral.
- */
-void SSC_EnableReceiver(void)
-{
- SSC->SSC_CR = SSC_CR_RXEN;
-}
-
-/**
- * \brief Disables the receiver of a SSC peripheral.
- */
-void SSC_DisableReceiver(void)
-{
- SSC->SSC_CR = SSC_CR_RXDIS;
-}
-
-/**
- * \brief Enables one or more interrupt sources of a SSC peripheral.
- * \param Bitwise OR of selected interrupt sources.
- */
-void SSC_EnableInterrupts(uint32_t sources)
-{
- SSC->SSC_IER = sources;
-}
-
-/**
- * \brief Disables one or more interrupt sources of a SSC peripheral.
- * \param Bitwise OR of selected interrupt sources.
- */
-void SSC_DisableInterrupts(uint32_t sources)
-{
- SSC->SSC_IDR = sources;
-}
-
-/**
- * \brief Sends one data frame through a SSC peripheral. If another frame is currently
- * being sent, this function waits for the previous transfer to complete.
- * \param frame Data frame to send.
- */
-void SSC_Write(uint32_t frame)
-{
- while ((SSC->SSC_SR & SSC_SR_TXRDY) == 0);
- SSC->SSC_THR = frame;
-}
-
-/**
- * \brief Waits until one frame is received on a SSC peripheral, and returns it.
- */
-uint32_t SSC_Read(void)
-{
- while ((SSC->SSC_SR & SSC_SR_RXRDY) == 0);
- return SSC->SSC_RHR;
-}
-
-/**
- * \brief Sends the contents of a data buffer a SSC peripheral, using the PDC.
- * \param buffer Data buffer to send.
- * \param length Size of the data buffer.
- * \return 1 if the buffer has been queued for transmission; otherwise returns 0.
- */
-uint8_t SSC_WriteBuffer(void *buffer, uint32_t length)
-{
- /* Check if first bank is free*/
- if (SSC->SSC_TCR == 0) {
-
- SSC->SSC_TPR = (uint32_t) buffer;
- SSC->SSC_TCR = length;
- SSC->SSC_PTCR = SSC_PTCR_TXTEN;
- return 1;
- }
- /* Check if second bank is free*/
- else if (SSC->SSC_TNCR == 0) {
-
- SSC->SSC_TNPR = (uint32_t) buffer;
- SSC->SSC_TNCR = length;
- return 1;
- }
- return 0;
-}
-
-/**
- * \brief Reads data coming from a SSC peripheral receiver and stores it into the
- * giving buffer with PDC.
- * \param buffer ata buffer used for reception.
- * \param length Size of the data buffer.
- * \return 1 if the buffer has been queued for reception; otherwise returns 0.
- */
-uint8_t SSC_ReadBuffer(void *buffer, uint32_t length)
-{
- /* Check if the first bank is free*/
- if (SSC->SSC_RCR == 0) {
-
- SSC->SSC_RPR = (uint32_t) buffer;
- SSC->SSC_RCR = length;
- SSC->SSC_PTCR = SSC_PTCR_RXTEN;
- return 1;
- }
- /* Check if second bank is free*/
- else if (SSC->SSC_RNCR == 0) {
- SSC->SSC_RNPR = (uint32_t) buffer;
- SSC->SSC_RNCR = length;
- return 1;
- }
- return 0;
-}
\ No newline at end of file
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/ssc/ssc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/ssc/ssc.h
deleted file mode 100644
index 1dd5185c..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/ssc/ssc.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- *
- * Interface for Synchronous Serial (SSC) controller.
- *
- */
-
-#ifndef SSC_H
-#define SSC_H
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-extern void SSC_Configure(uint32_t bitRate, uint32_t masterClock);
-extern void SSC_ConfigureTransmitter(uint32_t tcmr, uint32_t tfmr);
-extern void SSC_ConfigureReceiver(uint32_t rcmr, uint32_t rfmr);
-extern void SSC_EnableTransmitter(void);
-extern void SSC_DisableTransmitter(void);
-extern void SSC_EnableReceiver(void);
-extern void SSC_DisableReceiver(void);
-extern void SSC_EnableInterrupts(uint32_t sources);
-extern void SSC_DisableInterrupts(uint32_t sources);
-extern void SSC_Write(uint32_t frame);
-extern uint32_t SSC_Read(void);
-extern uint8_t SSC_WriteBuffer(void *buffer, uint32_t length);
-extern uint8_t SSC_ReadBuffer(void *buffer, uint32_t length);
-
-#endif //#ifndef SSC_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tc/tc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tc/tc.c
deleted file mode 100644
index 70ed8fa3..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tc/tc.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/*------------------------------------------------------------------------------
- * Headers
- *------------------------------------------------------------------------------*/
-
-#include "tc.h"
-
-/*------------------------------------------------------------------------------
- * Global functions
- *------------------------------------------------------------------------------*/
-
-/**------------------------------------------------------------------------------
- * \brief Configures a Timer Counter Channel
- * Configures a Timer Counter to operate in the given mode. Timer is stopped
- * after configuration and must be restarted with TC_Start(). All the
- * interrupts of the timer are also disabled.
- * \param pTc Pointer to an AT91S_TC instance.
- * \param channel Channel number.
- * \param mode Operating mode (TC_CMR value).
- *------------------------------------------------------------------------------*/
-void TC_Configure(Tc *pTc, unsigned char channel, unsigned int mode)
-{
- TcChannel *pTcCh = &pTc->TC_CHANNEL[channel];
-
- /* Disable TC clock */
- pTcCh->TC_CCR = TC_CCR0_CLKDIS;
-
- /* Disable interrupts */
- pTcCh->TC_IDR = 0xFFFFFFFF;
-
- /* Clear status register */
- pTcCh->TC_SR;
-
- /* Set mode */
- pTcCh->TC_CMR = mode;
-}
-
-/**------------------------------------------------------------------------------
- * \brief Reset and Start the TC Channel
- * Enables the timer clock and performs a software reset to start the counting.
- * \param pTc Pointer to an AT91S_TC instance.
- * \param channel Channel number.
- *------------------------------------------------------------------------------*/
-void TC_Start(Tc *pTc, unsigned char channel)
-{
- TcChannel *pTcCh = &pTc->TC_CHANNEL[channel];
- pTcCh->TC_CCR = TC_CCR0_CLKEN | TC_CCR0_SWTRG;
-}
-
-/**------------------------------------------------------------------------------
- * \brief Stop TC Channel
- * Disables the timer clock, stopping the counting.
- * \param pTc Pointer to an AT91S_TC instance.
- * \param channel Channel number.
- *------------------------------------------------------------------------------*/
-void TC_Stop(Tc *pTc, unsigned char channel)
-{
- TcChannel *pTcCh = &pTc->TC_CHANNEL[channel];
- pTcCh->TC_CCR = TC_CCR0_CLKDIS;
-}
-
-/**------------------------------------------------------------------------------
- * \brief Find best MCK divisor
- * Finds the best MCK divisor given the timer frequency and MCK. The result
- * is guaranteed to satisfy the following equation:
- * \pre
- * (MCK / (DIV * 65536)) <= freq <= (MCK / DIV)
- * \endpre
- * with DIV being the highest possible value.
- * \param freq Desired timer frequency.
- * \param mck Master clock frequency.
- * \param div Divisor value.
- * \param tcclks TCCLKS field value for divisor.
- * \return 1 if a proper divisor has been found; otherwise 0.
- *------------------------------------------------------------------------------*/
-unsigned char TC_FindMckDivisor(
- unsigned int freq,
- unsigned int mck,
- unsigned int *div,
- unsigned int *tcclks)
-{
- const unsigned int divisors[5] = {2, 8, 32, 128,BOARD_MCK / 32768};
-
- unsigned int index = 0;
-
- /* Satisfy lower bound */
- while (freq < ((mck / divisors[index]) / 65536)) {
-
- index++;
-
- /* If no divisor can be found, return 0 */
- if (index == 5) {
-
- return 0;
- }
- }
-
- /* Try to maximize DIV while satisfying upper bound */
- while (index < 4) {
-
- if (freq > (mck / divisors[index + 1])) {
-
- break;
- }
- index++;
- }
-
- /* Store results */
- if (div) {
-
- *div = divisors[index];
- }
- if (tcclks) {
-
- *tcclks = index;
- }
-
- return 1;
-}
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tc/tc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tc/tc.h
deleted file mode 100644
index 43cb83df..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tc/tc.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**------------------------------------------------------------------------------
- * \unit
- *
- * Purpose
- *
- * API for configuring and using Timer Counter (TC) peripherals.
- *
- * Usage
- * -# Optionally, use TC_FindMckDivisor() to let the program find the best
- * TCCLKS field value automatically.
- * -# Configure a Timer Counter in the desired mode using TC_Configure().
- * -# Start or stop the timer clock using TC_Start() and TC_Stop().
- *------------------------------------------------------------------------------*/
-
-#ifndef TC_H
-#define TC_H
-
-/*------------------------------------------------------------------------------
- * Headers
- *------------------------------------------------------------------------------*/
-
-#include
-
-/*------------------------------------------------------------------------------
- * Global functions
- *------------------------------------------------------------------------------*/
-
-extern void TC_Configure(Tc *pTc, unsigned char ch, unsigned int mode);
-
-extern void TC_Start(Tc *pTc, unsigned char ch);
-
-extern void TC_Stop(Tc *pTc, unsigned char ch);
-
-extern unsigned char TC_FindMckDivisor(
- unsigned int freq,
- unsigned int mck,
- unsigned int *div,
- unsigned int *tcclks);
-
-#endif /* #ifndef TC_H */
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd.h
deleted file mode 100644
index 38f0d8df..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- *
- * Interface for touchscreen driver which includes touchscreen calibration,
- * retrieving measurements etc.
- *
- * \par Usage
- *
- * -# Call TSD_Initialize() whenever the touchscreen should start the
- * calibration process (as it is done in the function).
- * -# Declare a global TSD_PenPressed function anywhere in your code. This
- * function will get called every time the pen is pressed on the screen.
- * -# Declare a global TSD_PenMoved function, which will get called whenever
- * the pen stays in contact with the screen but changes position.
- * -# Declare a global TSD_PenReleased function, which will be invoked as the
- * pen is lifted from the screen.
- */
-
-#ifndef TSD_H
-#define TSD_H
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include "tsd_com.h"
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-extern void TSD_Initialize(int8_t calEn);
-
-extern uint8_t TSD_Calibrate(void);
-
-extern void TSD_Reset(void);
-
-extern void TSD_TimerHandler(void);
-
-#endif /* #ifndef TSD_H */
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd_ads7843.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd_ads7843.c
deleted file mode 100644
index ee0fc869..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd_ads7843.c
+++ /dev/null
@@ -1,302 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- *
- * Implementation of ADS7843 driver.
- */
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include
-#include
-#include
-
-#ifdef BOARD_TSC_ADS7843
-
-#include "tsd.h"
-#include "tsd_com.h"
-#include
-#include
-#include
-#include
-#include
-#include
-#include "tsd/tsd_ads7843.h"
-
-/*----------------------------------------------------------------------------
- * Definitions
- *----------------------------------------------------------------------------*/
-
-/** Delay for pushbutton debouncing (the time-base is 10 ms). */
-#define DEBOUNCE_TIME 6 /* 10 * 6 = 60 ms */
-
-/** Color of calibration points. */
-#define POINTS_COLOR 0x0000FF
-
-/** Size in pixels of calibration points. */
-#define POINTS_SIZE 4
-
-/** Maximum difference in pixels between the test point and the measured point. */
-#define POINTS_MAX_ERROR 5
-
-/*----------------------------------------------------------------------------
- * Types
- *----------------------------------------------------------------------------*/
-
-/** pen state */
-typedef enum {
- STATE_PEN_RELEASED = 0,
- STATE_PEN_PRESSED = 1,
- STATE_PEN_DEBOUNCE = 2
-} e_pen_state;
-
-/*----------------------------------------------------------------------------
- * Local variables
- *----------------------------------------------------------------------------*/
-
-/** Pins used by Interrupt Signal for Touch Screen Controller */
-static const Pin pinPenIRQ = PIN_TCS_IRQ;
-
-/** Global timestamp in milliseconds since start of application. */
-static volatile uint32_t timestamp = 0;
-
-/** last time when the pen is pressed on the touchscreen */
-static volatile uint32_t timePress = 0;
-
-/** last time when the pen is released */
-static volatile uint32_t timeRelease = 0;
-
-/** pen state */
-static volatile e_pen_state penState = STATE_PEN_RELEASED;
-
-/** Touch screen initiallized flag */
-static uint32_t tsInitFlag = 0;
-
-/*----------------------------------------------------------------------------
- * Local functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief Timer handler for touch screen. Increments the timestamp counter.
- * Determine the state "Pen Pressed" or "Pen Released". To change state,
- * the penIRQ has to keep the same value during DEBOUNCE_TIME.
- *
- * \note External timer interrupt should call it per 10ms.
- */
-extern void TSD_TimerHandler( void )
-{
- uint32_t data[2];
- static uint32_t point[2];
-
- if (!tsInitFlag) return;
-
- timestamp++;
- /* Get the current position of the pen if penIRQ has low value (pen pressed) */
- if (PIO_Get(&pinPenIRQ) == 0) {
- /* Get the current position of the pressed pen */
- if(TSDCom_IsCalibrationOk()) {
- TSD_GetRawMeasurement(data);
- TSDCom_InterpolateMeasurement(data, point);
- }
-
- /* call the callback function */
- if(penState == STATE_PEN_PRESSED) {
- if(TSDCom_IsCalibrationOk()) {
- TSD_PenMoved(point[0], point[1]);
- }
- }
- }
-
- /* Determine the pen state */
- if (PIO_Get(&pinPenIRQ) == 0) {
-
- /* reinit the last time when release */
- timeRelease = timestamp;
- if(penState == STATE_PEN_DEBOUNCE) {
- if( (timestamp - timePress) > DEBOUNCE_TIME) {
- /* pen is pressed during an enough time : the state change */
- penState = STATE_PEN_PRESSED;
- /* call the callback function */
- if(TSDCom_IsCalibrationOk()) {
- TSD_PenPressed(point[0], point[1]);
- }
- }
- }
- }
- else {
- /* reinit the last time when release */
- timePress = timestamp;
-
- if(penState == STATE_PEN_DEBOUNCE) {
- if( (timestamp - timeRelease) > DEBOUNCE_TIME) {
- /* pen is released during an enough time : the state change */
- penState = STATE_PEN_RELEASED;
- /* call the callback function */
- if(TSDCom_IsCalibrationOk()) {
- TSD_PenReleased(point[0], point[1]);
- }
- }
- }
- }
-}
-
-/**
- * \breif Interrupt handler for Touchscreen.
- */
-static void ISR_PenIRQ(void)
-{
- /* Check if the pen has been pressed */
- if (!PIO_Get(&pinPenIRQ)) {
- if(penState == STATE_PEN_RELEASED) {
-
- timePress = timestamp;
- penState = STATE_PEN_DEBOUNCE;
- }
- }
- else {
- if(penState == STATE_PEN_PRESSED) {
-
- timeRelease = timestamp;
- penState = STATE_PEN_DEBOUNCE;
- }
- }
-}
-
-/**
- * \brief Configure PENIRQ for interrupt.
- */
-static void ConfigurePenIRQ(void)
-{
- /* Configure pios */
- PIO_Configure(&pinPenIRQ, PIO_LISTSIZE(pinPenIRQ));
-
- /* Initialize interrupts */
- PIO_InitializeInterrupts(0);
- PIO_ConfigureIt(&pinPenIRQ, (void (*)(const Pin *)) ISR_PenIRQ);
-
- /* Enable the interrupt */
- PIO_EnableIt(&pinPenIRQ);
-}
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief Reads and store a touchscreen measurement in the provided array.
- *
- * \param pData Array where the measurements will be stored
- */
-extern void TSD_GetRawMeasurement(uint32_t *pData)
-{
- /* Get the current position of the pressed pen */
- PIO_DisableIt(&pinPenIRQ);
- ADS7843_GetPosition(&pData[0], &pData[1]);
- PIO_EnableIt(&pinPenIRQ);
-}
-
-/**
- * \brief Wait pen pressed.
- */
-extern void TSD_WaitPenPressed( void )
-{
- /* Wait for touch & end of conversion */
- while (penState != STATE_PEN_RELEASED);
- /*while (penState != STATE_PEN_PRESSED); */
- while (penState != STATE_PEN_PRESSED) {
- }
-}
-
-/**
- * \brief Wait pen released.
- */
-extern void TSD_WaitPenReleased( void )
-{
- /* Wait for contact loss */
- while (penState != STATE_PEN_PRESSED);
- while (penState != STATE_PEN_RELEASED);
-}
-
-/**
- * \brief Do calibration.
- *
- * \return 1 if calibration is Ok, 0 else.
- */
-uint8_t TSD_Calibrate(void)
-{
- uint8_t ret = 0;
-
- /* Calibration is done only once */
- if(TSDCom_IsCalibrationOk()) {
- return 1;
- }
-
- /* Do calibration */
- ret = TSDCom_Calibrate();
-
- return ret;
-}
-
-/**
- * \brief Initializes the touchscreen driver and starts the calibration process. When
- * finished, the touchscreen is operational.
- *
- * \note Important: the LCD driver must have been initialized prior to calling this
- * function.
- */
-extern void TSD_Initialize( int8_t calEn )
-{
- ADS7843_Initialize();
- ConfigurePenIRQ();
-
- tsInitFlag = 1;
-
- /* Calibration */
- if(calEn) {
- while (!TSD_Calibrate());
- }
-}
-
-/**
- * \brief Stop the Touchscreen, disable interrupt.
- */
-void TSD_Reset(void)
-{
- /* Disable SPI 0 */
- ADS7843_Reset();
-
- /* Disable the interrupt */
- PIO_DisableIt(&pinPenIRQ);
-}
-
-#endif /* #ifdef BOARD_TSC_ADS7843 */
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd_ads7843.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd_ads7843.h
deleted file mode 100644
index 3f4bf2ef..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd_ads7843.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef _TSD_ADS7843_
-#define _TSD_ADS7843_
-
-/*----------------------------------------------------------------------------
- * External functions
- *----------------------------------------------------------------------------*/
-extern void TSD_PenPressed( uint32_t dwX, uint32_t dwY ) ;
-extern void TSD_PenMoved( uint32_t dwX, uint32_t dwY ) ;
-extern void TSD_PenReleased( uint32_t dwX, uint32_t dwY ) ;
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-extern void TSD_WaitPenPressed( void ) ;
-extern void TSD_WaitPenReleased( void ) ;
-extern void TSD_GetRawMeasurement( uint32_t *pData ) ;
-extern void TSD_Initialize( int8_t calEn ) ;
-
-
-#endif // _TSD_ADS7843_
\ No newline at end of file
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd_com.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd_com.c
deleted file mode 100644
index 2e0360fe..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd_com.c
+++ /dev/null
@@ -1,380 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- *
- * Implementation of touchscreen driver device irrelevance code.
- */
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include
-#include
-
-#include "tsd.h"
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include "tsd/tsd_ads7843.h"
-
-/*----------------------------------------------------------------------------
- * Definitions
- *----------------------------------------------------------------------------*/
-
-/** Size in pixels of calibration points. */
-#define POINTS_SIZE 4
-/** Maximum difference in pixels between the test point and the measured point. */
-#define POINTS_MAX_ERROR 8
-
-/** Delay at the end of calibartion for result display */
-#define DELAY_RESULT_DISPLAY 4000000
-
-/*----------------------------------------------------------------------------
- * Types
- *----------------------------------------------------------------------------*/
-
-/** Point used during the touchscreen calibration process. */
-typedef struct _CalibrationPoint {
-
- /** Coordinate of point along the X-axis of the screen. */
- uint32_t x;
- /** Coordinate of point along the Y-axis of the screen. */
- uint32_t y;
- /** Calibration data of point. */
- uint32_t data[2];
-
-} CalibrationPoint;
-
-/*----------------------------------------------------------------------------
- * Variables
- *----------------------------------------------------------------------------*/
-
-/** indicates if the touch screen has been calibrated. */
-/** If not, Callback functions are not called. */
-static volatile uint8_t bCalibrationOk = 1 ; //0;
-/** Slope for interpoling touchscreen measurements along the X-axis. */
-static int32_t xSlope;
-/** Slope for interpoling touchscreen measurements along the Y-axis. */
-static int32_t ySlope;
-
-/** Calibration points. */
-static CalibrationPoint calibrationPoints[] = {
-
- /* Top-left corner calibration point */
- {
- BOARD_LCD_WIDTH / 10,
- BOARD_LCD_HEIGHT / 10,
- {0, 0}
- },
- /* Top-right corner calibration point */
- {
- BOARD_LCD_WIDTH - BOARD_LCD_WIDTH / 10,
- BOARD_LCD_HEIGHT / 10,
- {0, 0}
- },
- /* Bottom-right corner calibration point */
- {
- BOARD_LCD_WIDTH - BOARD_LCD_WIDTH / 10,
- BOARD_LCD_HEIGHT - BOARD_LCD_HEIGHT / 10,
- {0, 0}
- },
- /* Bottom-left corner calibration point */
- {
- BOARD_LCD_WIDTH / 10,
- BOARD_LCD_HEIGHT - BOARD_LCD_HEIGHT / 10,
- {0, 0}
- }
-};
-
-/** Test point */
-static const CalibrationPoint testPoint = {
- BOARD_LCD_WIDTH / 2,
- BOARD_LCD_HEIGHT / 2,
- {0, 0}
-};
-
-/*----------------------------------------------------------------------------
- * External functions
- *----------------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------------
- * Local functions
- *----------------------------------------------------------------------------*/
-
-/*
- * \brief Display a calibration point on the given buffer.
- *
- * \param pPoint Calibration point to display.
- */
-static void DrawCalibrationPoint(const CalibrationPoint *pPoint)
-{
- LCDD_DrawRectangleWithFill(pPoint->x - POINTS_SIZE / 2,
- pPoint->y - POINTS_SIZE / 2,
- POINTS_SIZE,
- POINTS_SIZE,
- COLOR_RED);
-}
-
-/**
- * \brief Clears a calibration point from the given buffer.
- *
- * \param pPoint Calibration point to clear.
- */
-static void ClearCalibrationPoint(const CalibrationPoint *pPoint)
-{
- LCDD_DrawRectangleWithFill(pPoint->x - POINTS_SIZE / 2,
- pPoint->y - POINTS_SIZE / 2,
- POINTS_SIZE,
- POINTS_SIZE,
- COLOR_WHITE);
-}
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \breif Indicates if the calibration of the touch screen is Ok.
- *
- * \return 1 calibration Ok, 0 if not.
- */
-uint8_t TSDCom_IsCalibrationOk(void)
-{
- if (bCalibrationOk == 1) {
- return 1;
- } else {
- return 0;
- }
-}
-
-/**
- * \brief Interpolates the provided raw measurements using the previously calculated
- * slope. The resulting x and y coordinates are stored in an array.
- *
- * \param pData Raw measurement data, as returned by TSD_GetRawMeasurement().
- * \param pPoint Array in which x and y will be stored.
- */
-void TSDCom_InterpolateMeasurement(const uint32_t *pData, uint32_t *pPoint)
-{
- pPoint[0] = calibrationPoints[0].x
- - (((int32_t) calibrationPoints[0].data[0] - (int32_t) pData[0]) * 1024)
- / xSlope;
-
- pPoint[1] = calibrationPoints[0].y
- - (((int32_t) calibrationPoints[0].data[1] - (int32_t) pData[1]) * 1024)
- / ySlope;
-
- if(pPoint[0] & 0x80000000) /* Is pPoint[0] negative ? */
- {
- pPoint[0] = 0;
- }
-
- if(pPoint[0] > BOARD_LCD_WIDTH) /* Is pPoint[0] bigger than the LCD width ? */
- {
- pPoint[0] = BOARD_LCD_WIDTH;
- }
-
- if(pPoint[1] & 0x80000000) /* Is pPoint[1] negative ? */
- {
- pPoint[1] = 0;
- }
-
- if(pPoint[1] > BOARD_LCD_HEIGHT) /* Is pPoint[1] bigger than the LCD width ? */
- {
- pPoint[1] = BOARD_LCD_HEIGHT;
- }
-}
-
-/**
- * \brief Performs the calibration process using the provided buffer to display
- * information.
- *
- * \return True if calibration was successful; otherwise false.
- */
-uint8_t TSDCom_Calibrate(void)
-{
- volatile uint32_t i; /* to keep the tempo with gcc code optimisation */
- int32_t slope1, slope2;
- CalibrationPoint measuredPoint;
- uint8_t xOk, yOk;
- int32_t xDiff, yDiff;
-
- /* Calibration setup */
- LCDD_Fill(COLOR_WHITE);
- LCDD_DrawString(30, 50, (uint8_t *)"LCD calibration", COLOR_BLACK);
- LCDD_DrawString(1, 140, (uint8_t *)"Touch the dots to\ncalibrate the screen", COLOR_DARKBLUE);
-
- /* Calibration points */
- for (i=0; i < 4; i++) {
-
- DrawCalibrationPoint(&calibrationPoints[i]);
-
- /* Wait for touch & end of conversion */
- TSD_WaitPenPressed();
- TSD_GetRawMeasurement(calibrationPoints[i].data);
- ClearCalibrationPoint(&calibrationPoints[i]);
-
- /* Wait for contact loss */
- TSD_WaitPenReleased();
- }
-
- /**
- * Calculate slopes using the calibration data
- * Theory behind those calculations:
- * - We suppose the touchscreen measurements are linear, so the following equations are true (simple
- * linear regression) for any two 'a' and 'b' points of the screen:
- * dx = (a.data[0] - b.data[0]) / (a.x - b.x)
- * dy = (a.data[1] - b.data[1]) / (a.y - b.y)
- *
- * - We calculate dx and dy (called xslope and yslope here) using the calibration points.
- *
- * - We can then use dx and dy to infer the position of a point 'p' given the measurements performed
- * by the touchscreen ('c' is any of the calibration points):
- * dx = (p.data[0] - c.data[0]) / (p.x - c.x)
- * dy = (p.data[1] - c.data[1]) / (p.y - c.y)
- * Thus:
- * p.x = c.x - (p.data[0] - c.data[0]) / dx
- * p.y = c.y - (p.data[1] - c.data[1]) / dy
- *
- * - Since there are four calibration points, dx and dy can be calculated twice, so we average
- * the two values.
- */
- slope1 = ((int32_t) calibrationPoints[0].data[0]) - ((int32_t) calibrationPoints[1].data[0]);
- slope1 *= 1024;
- slope1 /= ((int32_t) calibrationPoints[0].x) - ((int32_t) calibrationPoints[1].x);
- slope2 = ((int32_t) calibrationPoints[2].data[0]) - ((int32_t) calibrationPoints[3].data[0]);
- slope2 *= 1024;
- slope2 /= ((int32_t) calibrationPoints[2].x) - ((int32_t) calibrationPoints[3].x);
- xSlope = (slope1 + slope2) / 2;
-
- slope1 = ((int32_t) calibrationPoints[0].data[1]) - ((int32_t) calibrationPoints[2].data[1]);
- slope1 *= 1024;
- slope1 /= ((int32_t) calibrationPoints[0].y) - ((int32_t) calibrationPoints[2].y);
- slope2 = ((int32_t) calibrationPoints[1].data[1]) - ((int32_t) calibrationPoints[3].data[1]);
- slope2 *= 1024;
- slope2 /= ((int32_t) calibrationPoints[1].y) - ((int32_t) calibrationPoints[3].y);
- ySlope = (slope1 + slope2) / 2;
-
- /* Test point */
- LCDD_Fill(0xFFFFFF);
- LCDD_DrawString(30, 50, (uint8_t *)"LCD calibration", COLOR_BLACK);
- LCDD_DrawString(1, 100, (uint8_t *)" Touch the point to\nvalidate calibration", COLOR_DARKBLUE);
- DrawCalibrationPoint(&testPoint);
-
- /* Wait for touch & end of conversion */
- TSD_WaitPenPressed();
-
- TSD_GetRawMeasurement(measuredPoint.data);
- TSDCom_InterpolateMeasurement(measuredPoint.data, (uint32_t *) &measuredPoint);
- DrawCalibrationPoint(&measuredPoint);
-
- /* Check resulting x and y */
- xDiff = (int32_t) measuredPoint.x - (int32_t) testPoint.x;
- yDiff = (int32_t) measuredPoint.y - (int32_t) testPoint.y;
- xOk = (xDiff >= -POINTS_MAX_ERROR) && (xDiff <= POINTS_MAX_ERROR);
- yOk = (yDiff >= -POINTS_MAX_ERROR) && (yDiff <= POINTS_MAX_ERROR);
-
- /* Wait for contact loss */
- TSD_WaitPenReleased();
-
- /* Check calibration result */
- if (xOk && yOk) {
-
- bCalibrationOk = 1;
- LCDD_Fill(COLOR_WHITE);
- LCDD_DrawString(30, 50, (uint8_t *)"LCD calibration", COLOR_BLACK);
- LCDD_DrawString(80, 140, (uint8_t *)"Success !", COLOR_GREEN);
-
- }
- else {
-
- bCalibrationOk = 0;
- LCDD_Fill(COLOR_WHITE);
- LCDD_DrawString(30, 50, (uint8_t *)"LCD calibration", COLOR_BLACK);
- LCDD_DrawString(40, 140, (uint8_t *)"Error too big", COLOR_RED);
- }
-
- /* Slight delay */
- for (i = 0; i < DELAY_RESULT_DISPLAY; i++);
-
- return (xOk && yOk);
-}
-
-/**
- * \brief Read calibrate data to buffer.
- *
- * \param pBuffer Data buffer.
- * \param size Size of data buffer in bytes.
- */
-void TSDCom_ReadCalibrateData(void *pBuffer, uint32_t size)
-{
- uint8_t *pDest = (uint8_t *)pBuffer;
-
- SANITY_CHECK((sizeof(bCalibrationOk) + sizeof(xSlope) +
- sizeof(ySlope) + sizeof(calibrationPoints[0].data)) < size);
-
- memcpy(pDest, (void const *)&bCalibrationOk, sizeof(bCalibrationOk));
- pDest += sizeof(bCalibrationOk);
- memcpy(pDest, &xSlope, sizeof(xSlope));
- pDest += sizeof(xSlope);
- memcpy(pDest, &ySlope, sizeof(ySlope));
- pDest += sizeof(ySlope);
- memcpy(pDest, &calibrationPoints[0].data, sizeof(calibrationPoints[0].data));
- pDest += sizeof(calibrationPoints[0].data);
-}
-
-/**
- * \brief Restore calibrate data with buffer data.
- *
- * \param pBuffer Data buffer.
- * \param size Size of data buffer in bytes.
- */
-void TSDCom_RestoreCalibrateData(void *pBuffer, uint32_t size)
-{
- uint8_t *pSrc = (uint8_t *)pBuffer;
-
- SANITY_CHECK((sizeof(bCalibrationOk) + sizeof(xSlope) +
- sizeof(ySlope) + sizeof(calibrationPoints[0].data)) < size);
-
- memcpy((void *)&bCalibrationOk, pSrc, sizeof(bCalibrationOk));
- pSrc += sizeof(bCalibrationOk);
- memcpy(&xSlope, pSrc, sizeof(xSlope));
- pSrc += sizeof(xSlope);
- memcpy(&ySlope, pSrc, sizeof(ySlope));
- pSrc += sizeof(ySlope);
- memcpy(&calibrationPoints[0].data, pSrc, sizeof(calibrationPoints[0].data));
- pSrc += sizeof(calibrationPoints[0].data);
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd_com.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd_com.h
deleted file mode 100644
index ca6f285d..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd_com.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- *
- * Interface for touchscreen driver device irrelevance code.
- */
-
-#ifndef TSD_COM_H
-#define TSD_COM_H
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-extern void TSDCom_InterpolateMeasurement(
- const uint32_t *pData,
- uint32_t *pPoint);
-
-uint8_t TSDCom_Calibrate(void);
-
-uint8_t TSDCom_IsCalibrationOk(void);
-
-void TSDCom_ReadCalibrateData(void *pBuffer, uint32_t size);
-void TSDCom_RestoreCalibrateData(void *pBuffer, uint32_t size);
-
-#endif /* #ifndef TSD_COM_H */
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/twi/twi.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/twi/twi.c
deleted file mode 100644
index 5de7b2ee..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/twi/twi.c
+++ /dev/null
@@ -1,377 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/** \addtogroup twi_module Working with TWI
- * The TWI driver provides the interface to configure and use the TWI
- * peripheral.
- *
- * \usage
- *
- *
Configures a TWI peripheral to operate in master mode, at the given
- * frequency (in Hz) using TWI_Configure().
- *
Sends a STOP condition on the TWI using TWI_Stop().
- *
Starts a read operation on the TWI bus with the specified slave using
- * TWI_StartRead(). Data must then be read using TWI_ReadByte() whenever
- * a byte is available (poll using TWI_ByteReceived()).
- *
Starts a write operation on the TWI to access the selected slave using
- * TWI_StartWrite(). A byte of data must be provided to start the write;
- * other bytes are written next.
- *
Sends a byte of data to one of the TWI slaves on the bus using TWI_WriteByte().
- * This function must be called once before TWI_StartWrite() with the first byte of data
- * to send, then it shall be called repeatedly after that to send the remaining bytes.
- *
Check if a byte has been received and can be read on the given TWI
- * peripheral using TWI_ByteReceived().<
- * Check if a byte has been sent using TWI_ByteSent().
- *
Check if the current transmission is complete (the STOP has been sent)
- * using TWI_TransferComplete().
- *
Enables & disable the selected interrupts sources on a TWI peripheral
- * using TWI_EnableIt() and TWI_DisableIt().
- *
Get current status register of the given TWI peripheral using
- * TWI_GetStatus(). Get current status register of the given TWI peripheral, but
- * masking interrupt sources which are not currently enabled using
- * TWI_GetMaskedStatus().
- *
- * For more accurate information, please look at the TWI section of the
- * Datasheet.
- *
- * Related files :\n
- * \ref twi.c\n
- * \ref twi.h.\n
-*/
-/*@{*/
-/*@}*/
-
-
-/**
- * \file
- *
- * Implementation of Two Wire Interface (TWI).
- *
- */
-
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include
-#include "twi.h"
-#include
-#include
-#include
-
-/*----------------------------------------------------------------------------
- * Exported functions
- *----------------------------------------------------------------------------*/
-
-/**
- * \brief Configures a TWI peripheral to operate in master mode, at the given
- * frequency (in Hz). The duty cycle of the TWI clock is set to 50%.
- * \param pTwi Pointer to an Twi instance.
- * \param twck Desired TWI clock frequency.
- * \param mck Master clock frequency.
- */
-void TWI_ConfigureMaster(Twi *pTwi, uint32_t twck, uint32_t mck)
-{
- uint32_t ckdiv = 0;
- uint32_t cldiv;
- uint8_t ok = 0;
-
- TRACE_DEBUG("TWI_ConfigureMaster()\n\r");
- SANITY_CHECK(pTwi);
-
- /* SVEN: TWI Slave Mode Enabled */
- pTwi->TWI_CR = TWI_CR_SVEN;
- /* Reset the TWI*/
- pTwi->TWI_CR = TWI_CR_SWRST;
- pTwi->TWI_RHR;
-
- /* TWI Slave Mode Disabled, TWI Master Mode Disabled. */
- pTwi->TWI_CR = TWI_CR_SVDIS;
- pTwi->TWI_CR = TWI_CR_MSDIS;
-
- /* Set master mode */
- pTwi->TWI_CR = TWI_CR_MSEN;
-
- /* Configure clock */
- while (!ok) {
- cldiv = ((mck / (2 * twck)) - 3) / power(2, ckdiv);
- if (cldiv <= 255) {
- ok = 1;
- }
- else {
- ckdiv++;
- }
- }
- ASSERT(ckdiv < 8, "-F- Cannot find valid TWI clock parameters\n\r");
- TRACE_DEBUG("Using CKDIV = %u and CLDIV/CHDIV = %u\n\r", ckdiv, cldiv);
- pTwi->TWI_CWGR = 0;
- pTwi->TWI_CWGR = (ckdiv << 16) | (cldiv << 8) | cldiv;
-}
-
-/**
- * \brief Configures a TWI peripheral to operate in slave mode.
- * \param pTwi Pointer to an Twi instance.
- * \param slaveAddress Slave address.
- */
-void TWI_ConfigureSlave(Twi *pTwi, uint8_t slaveAddress)
-{
- uint32_t i;
-
- /* TWI software reset */
- pTwi->TWI_CR = TWI_CR_SWRST;
- pTwi->TWI_RHR;
-
- /* Wait at least 10 ms */
- for (i=0; i < 1000000; i++);
-
- /* TWI Slave Mode Disabled, TWI Master Mode Disabled*/
- pTwi->TWI_CR = TWI_CR_SVDIS | TWI_CR_MSDIS;
-
- /* Configure slave address. */
- pTwi->TWI_SMR = 0;
- pTwi->TWI_SMR = (slaveAddress << 16) & TWI_SMR_SADR;
-
- /* SVEN: TWI Slave Mode Enabled */
- pTwi->TWI_CR = TWI_CR_SVEN;
-
- /* Wait at least 10 ms */
- for (i=0; i < 1000000; i++);
- ASSERT( (pTwi->TWI_CR & TWI_CR_SVDIS)!= TWI_CR_SVDIS, "Can't configure TWI slave mode");
-}
-
-/**
- * \brief Sends a STOP condition on the TWI.
- * \param pTwi Pointer to an Twi instance.
- */
-void TWI_Stop(Twi *pTwi)
-{
- SANITY_CHECK(pTwi);
- pTwi->TWI_CR = TWI_CR_STOP;
-}
-
-/**
- * \brief Starts a read operation on the TWI bus with the specified slave, it returns
- * immediately. Data must then be read using TWI_ReadByte() whenever a byte is
- * available (poll using TWI_ByteReceived()).
- * \param pTwi Pointer to an Twi instance.
- * \param address Slave address on the bus.
- * \param iaddress Optional internal address bytes.
- * \param isize Number of internal address bytes.
- */
-void TWI_StartRead(
- Twi *pTwi,
- uint8_t address,
- uint32_t iaddress,
- uint8_t isize)
-{
- SANITY_CHECK(pTwi);
- SANITY_CHECK((address & 0x80) == 0);
- SANITY_CHECK((iaddress & 0xFF000000) == 0);
- SANITY_CHECK(isize < 4);
-
- /* Set slave address and number of internal address bytes. */
- pTwi->TWI_MMR = 0;
- pTwi->TWI_MMR = (isize << 8) | TWI_MMR_MREAD | (address << 16);
-
- /* Set internal address bytes */
- pTwi->TWI_IADR = 0;
- pTwi->TWI_IADR = iaddress;
-
- /* Send START condition */
- pTwi->TWI_CR = TWI_CR_START;
-}
-
-/**
- * \brief Reads a byte from the TWI bus. The read operation must have been started
- * using TWI_StartRead() and a byte must be available (check with TWI_ByteReceived()).
- * \param pTwi Pointer to an Twi instance.
- * \return byte read.
- */
-uint8_t TWI_ReadByte(Twi *pTwi)
-{
- SANITY_CHECK(pTwi);
-
- return pTwi->TWI_RHR;
-}
-
-/**
- * \brief Sends a byte of data to one of the TWI slaves on the bus.
- * \note This function must be called once before TWI_StartWrite() with
- * the first byte of data to send, then it shall be called repeatedly
- * after that to send the remaining bytes.
- * \param pTwi Pointer to an Twi instance.
- * \param byte Byte to send.
- */
-void TWI_WriteByte(Twi *pTwi, uint8_t byte)
-{
- SANITY_CHECK(pTwi);
-
- pTwi->TWI_THR = byte;
-}
-
-/**
- * \brief Starts a write operation on the TWI to access the selected slave, then
- * returns immediately. A byte of data must be provided to start the write;
- * other bytes are written next.
- * after that to send the remaining bytes.
- * \param pTwi Pointer to an Twi instance.
- * \param address Address of slave to acccess on the bus.
- * \param iaddress Optional slave internal address.
- * \param isize Number of internal address bytes.
- * \param byte First byte to send.
- */
-void TWI_StartWrite(
- Twi *pTwi,
- uint8_t address,
- uint32_t iaddress,
- uint8_t isize,
- uint8_t byte)
-{
- SANITY_CHECK(pTwi);
- SANITY_CHECK((address & 0x80) == 0);
- SANITY_CHECK((iaddress & 0xFF000000) == 0);
- SANITY_CHECK(isize < 4);
-
- /* Set slave address and number of internal address bytes. */
- pTwi->TWI_MMR = 0;
- pTwi->TWI_MMR = (isize << 8) | (address << 16);
-
- /* Set internal address bytes. */
- pTwi->TWI_IADR = 0;
- pTwi->TWI_IADR = iaddress;
-
- /* Write first byte to send.*/
- TWI_WriteByte(pTwi, byte);
-}
-
-/**
- * \brief Check if a byte have been receiced from TWI.
- * \param pTwi Pointer to an Twi instance.
- * \return 1 if a byte has been received and can be read on the given TWI
- * peripheral; otherwise, returns 0. This function resets the status register.
- */
-uint8_t TWI_ByteReceived(Twi *pTwi)
-{
- return ((pTwi->TWI_SR & TWI_SR_RXRDY) == TWI_SR_RXRDY);
-}
-
-/**
- * \brief Check if a byte have been sent to TWI.
- * \param pTwi Pointer to an Twi instance.
- * \return 1 if a byte has been sent so another one can be stored for
- * transmission; otherwise returns 0. This function clears the status register.
- */
-uint8_t TWI_ByteSent(Twi *pTwi)
-{
- return ((pTwi->TWI_SR & TWI_SR_TXRDY) == TWI_SR_TXRDY);
-}
-
-/**
- * \brief Check if current transmission is complet.
- * \param pTwi Pointer to an Twi instance.
- * \return 1 if the current transmission is complete (the STOP has been sent);
- * otherwise returns 0.
- */
-uint8_t TWI_TransferComplete(Twi *pTwi)
-{
- return ((pTwi->TWI_SR & TWI_SR_TXCOMP) == TWI_SR_TXCOMP);
-}
-
-/**
- * \brief Enables the selected interrupts sources on a TWI peripheral.
- * \param pTwi Pointer to an Twi instance.
- * \param sources Bitwise OR of selected interrupt sources.
- */
-void TWI_EnableIt(Twi *pTwi, uint32_t sources)
-{
- SANITY_CHECK(pTwi);
- SANITY_CHECK((sources & 0xFFFFF088) == 0);
-
- pTwi->TWI_IER = sources;
-}
-
-/**
- * \brief Disables the selected interrupts sources on a TWI peripheral.
- * \param pTwi Pointer to an Twi instance.
- * \param sources Bitwise OR of selected interrupt sources.
- */
-void TWI_DisableIt(Twi *pTwi, uint32_t sources)
-{
- SANITY_CHECK(pTwi);
- SANITY_CHECK((sources & 0xFFFFF088) == 0);
-
- pTwi->TWI_IDR = sources;
-}
-
-/**
- * \brief Get the current status register of the given TWI peripheral.
- * \note This resets the internal value of the status register, so further
- * read may yield different values.
- * \param pTwi Pointer to an Twi instance.
- * \return TWI status register.
- */
-uint32_t TWI_GetStatus(Twi *pTwi)
-{
- SANITY_CHECK(pTwi);
-
- return pTwi->TWI_SR;
-}
-
-/**
- * \brief Returns the current status register of the given TWI peripheral, but
- * masking interrupt sources which are not currently enabled.
- * \note This resets the internal value of the status register, so further
- * read may yield different values.
- * \param pTwi Pointer to an Twi instance.
- */
-uint32_t TWI_GetMaskedStatus(Twi *pTwi)
-{
- uint32_t status;
-
- SANITY_CHECK(pTwi);
-
- status = pTwi->TWI_SR;
- status &= pTwi->TWI_IMR;
-
- return status;
-}
-
-/**
- * \brief Sends a STOP condition. STOP Condition is sent just after completing
- * the current byte transmission in master read mode.
- * \param pTwi Pointer to an Twi instance.
- */
-void TWI_SendSTOPCondition(Twi *pTwi)
-{
- SANITY_CHECK(pTwi);
-
- pTwi->TWI_CR |= TWI_CR_STOP;
-}
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/twi/twi.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/twi/twi.h
deleted file mode 100644
index a2374048..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/twi/twi.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- *
- * Interface for configuration the Two Wire Interface (TWI) peripheral.
- *
- */
-
-#ifndef TWI_H
-#define TWI_H
-
-/*----------------------------------------------------------------------------
- * Macros
- *----------------------------------------------------------------------------*/
-/* Returns 1 if the TXRDY bit (ready to transmit data) is set in the given status register value.*/
-#define TWI_STATUS_TXRDY(status) ((status & TWI_SR_TXRDY) == TWI_SR_TXRDY)
-
-/* Returns 1 if the RXRDY bit (ready to receive data) is set in the given status register value.*/
-#define TWI_STATUS_RXRDY(status) ((status & TWI_SR_RXRDY) == TWI_SR_RXRDY)
-
-/* Returns 1 if the TXCOMP bit (transfer complete) is set in the given status register value.*/
-#define TWI_STATUS_TXCOMP(status) ((status & TWI_SR_TXCOMP) == TWI_SR_TXCOMP)
-
-/*----------------------------------------------------------------------------
- * External function
- *----------------------------------------------------------------------------*/
-
-extern void TWI_ConfigureMaster(Twi *pTwi, uint32_t twck, uint32_t mck);
-
-extern void TWI_ConfigureSlave(Twi *pTwi, uint8_t slaveAddress);
-
-extern void TWI_Stop(Twi *pTwi);
-
-extern void TWI_StartRead(
- Twi *pTwi,
- uint8_t address,
- uint32_t iaddress,
- uint8_t isize);
-
-extern uint8_t TWI_ReadByte(Twi *pTwi);
-
-extern void TWI_WriteByte(Twi *pTwi, uint8_t byte);
-
-extern void TWI_StartWrite(
- Twi *pTwi,
- uint8_t address,
- uint32_t iaddress,
- uint8_t isize,
- uint8_t byte);
-
-extern uint8_t TWI_ByteReceived(Twi *pTwi);
-
-extern uint8_t TWI_ByteSent(Twi *pTwi);
-
-extern uint8_t TWI_TransferComplete(Twi *pTwi);
-
-extern void TWI_EnableIt(Twi *pTwi, uint32_t sources);
-
-extern void TWI_DisableIt(Twi *pTwi, uint32_t sources);
-
-extern uint32_t TWI_GetStatus(Twi *pTwi);
-
-extern uint32_t TWI_GetMaskedStatus(Twi *pTwi);
-
-extern void TWI_SendSTOPCondition(Twi *pTwi);
-
-#endif //#ifndef TWI_H
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/twi/twid.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/twi/twid.c
deleted file mode 100644
index 6d1774de..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/twi/twid.c
+++ /dev/null
@@ -1,342 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-
-
-
-
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include "twid.h"
-#include
-#include
-#include
-
-/*----------------------------------------------------------------------------
- * Definition
- *----------------------------------------------------------------------------*/
-#define TWITIMEOUTMAX 50000
-
-/*----------------------------------------------------------------------------
- * Types
- *----------------------------------------------------------------------------*/
-
-/** TWI driver callback function.*/
-typedef void (*TwiCallback)(Async *);
-
-/** TWI asynchronous transfer descriptor.*/
-typedef struct _AsyncTwi {
-
- /** Asynchronous transfer status. */
- volatile uint8_t status;
- // Callback function to invoke when transfer completes or fails.*/
- TwiCallback callback;
- /** Pointer to the data buffer.*/
- uint8_t *pData;
- /** Total number of bytes to transfer.*/
- uint32_t num;
- /** Number of already transferred bytes.*/
- uint32_t transferred;
-
-} AsyncTwi;
-
-/*----------------------------------------------------------------------------
- * Global functions
- *----------------------------------------------------------------------------*/
-/**
- * \brief Initializes a TWI driver instance, using the given TWI peripheral.
- * \note The peripheral must have been initialized properly before calling this function.
- * \param pTwid Pointer to the Twid instance to initialize.
- * \param pTwi Pointer to the TWI peripheral to use.
- */
-void TWID_Initialize(Twid *pTwid, Twi *pTwi)
-{
- TRACE_DEBUG("TWID_Initialize()\n\r");
- SANITY_CHECK(pTwid);
- SANITY_CHECK(pTwi);
-
- /* Initialize driver. */
- pTwid->pTwi = pTwi;
- pTwid->pTransfer = 0;
-}
-
-
-/**
- * \brief Interrupt handler for a TWI peripheral. Manages asynchronous transfer
- * occuring on the bus. This function MUST be called by the interrupt service
- * routine of the TWI peripheral if asynchronous read/write are needed.
- * \param pTwid Pointer to a Twid instance.
- */
-void TWID_Handler(Twid *pTwid)
-{
- uint8_t status;
- AsyncTwi *pTransfer = (AsyncTwi *) pTwid->pTransfer;
- Twi *pTwi = pTwid->pTwi;
-
- SANITY_CHECK(pTwid);
-
- /* Retrieve interrupt status */
- status = TWI_GetMaskedStatus(pTwi);
-
- /* Byte received */
- if (TWI_STATUS_RXRDY(status)) {
-
- pTransfer->pData[pTransfer->transferred] = TWI_ReadByte(pTwi);
- pTransfer->transferred++;
-
- /* check for transfer finish */
- if (pTransfer->transferred == pTransfer->num) {
-
- TWI_DisableIt(pTwi, TWI_IDR_RXRDY);
- TWI_EnableIt(pTwi, TWI_IER_TXCOMP);
- }
- /* Last byte? */
- else if (pTransfer->transferred == (pTransfer->num - 1)) {
-
- TWI_Stop(pTwi);
- }
- }
- /* Byte sent*/
- else if (TWI_STATUS_TXRDY(status)) {
-
- /* Transfer finished ? */
- if (pTransfer->transferred == pTransfer->num) {
-
- TWI_DisableIt(pTwi, TWI_IDR_TXRDY);
- TWI_EnableIt(pTwi, TWI_IER_TXCOMP);
- TWI_SendSTOPCondition(pTwi);
- }
- /* Bytes remaining */
- else {
-
- TWI_WriteByte(pTwi, pTransfer->pData[pTransfer->transferred]);
- pTransfer->transferred++;
- }
- }
- /* Transfer complete*/
- else if (TWI_STATUS_TXCOMP(status)) {
-
- TWI_DisableIt(pTwi, TWI_IDR_TXCOMP);
- pTransfer->status = 0;
- if (pTransfer->callback) {
-
- pTransfer->callback((Async *) pTransfer);
- }
- pTwid->pTransfer = 0;
- }
-}
-
-/**
- * \brief Asynchronously reads data from a slave on the TWI bus. An optional
- * callback function is triggered when the transfer is complete.
- * \param pTwid Pointer to a Twid instance.
- * \param address TWI slave address.
- * \param iaddress Optional slave internal address.
- * \param isize Internal address size in bytes.
- * \param pData Data buffer for storing received bytes.
- * \param num Number of bytes to read.
- * \param pAsync Asynchronous transfer descriptor.
- * \return 0 if the transfer has been started; otherwise returns a TWI error code.
- */
-uint8_t TWID_Read(
- Twid *pTwid,
- uint8_t address,
- uint32_t iaddress,
- uint8_t isize,
- uint8_t *pData,
- uint32_t num,
- Async *pAsync)
-{
- Twi *pTwi = pTwid->pTwi;
- AsyncTwi *pTransfer = (AsyncTwi *) pTwid->pTransfer;
- uint32_t timeout;
-
- SANITY_CHECK(pTwid);
- SANITY_CHECK((address & 0x80) == 0);
- SANITY_CHECK((iaddress & 0xFF000000) == 0);
- SANITY_CHECK(isize < 4);
-
- /* Check that no transfer is already pending*/
- if (pTransfer) {
-
- TRACE_ERROR("TWID_Read: A transfer is already pending\n\r");
- return TWID_ERROR_BUSY;
- }
-
- /* Set STOP signal if only one byte is sent*/
- if (num == 1) {
-
- TWI_Stop(pTwi);
- }
-
- /* Asynchronous transfer*/
- if (pAsync) {
-
- /* Update the transfer descriptor */
- pTwid->pTransfer = pAsync;
- pTransfer = (AsyncTwi *) pAsync;
- pTransfer->status = ASYNC_STATUS_PENDING;
- pTransfer->pData = pData;
- pTransfer->num = num;
- pTransfer->transferred = 0;
-
- /* Enable read interrupt and start the transfer */
- TWI_EnableIt(pTwi, TWI_IER_RXRDY);
- TWI_StartRead(pTwi, address, iaddress, isize);
- }
- /* Synchronous transfer*/
- else {
-
- /* Start read*/
- TWI_StartRead(pTwi, address, iaddress, isize);
-
- /* Read all bytes, setting STOP before the last byte*/
- while (num > 0) {
-
- /* Last byte ?*/
- if (num == 1) {
-
- TWI_Stop(pTwi);
- }
-
- /* Wait for byte then read and store it*/
- timeout = 0;
- while( !TWI_ByteReceived(pTwi) && (++timeoutpTwi;
- AsyncTwi *pTransfer = (AsyncTwi *) pTwid->pTransfer;
- uint32_t timeout;
-
- SANITY_CHECK(pTwi);
- SANITY_CHECK((address & 0x80) == 0);
- SANITY_CHECK((iaddress & 0xFF000000) == 0);
- SANITY_CHECK(isize < 4);
-
- /* Check that no transfer is already pending */
- if (pTransfer) {
-
- TRACE_ERROR("TWI_Write: A transfer is already pending\n\r");
- return TWID_ERROR_BUSY;
- }
-
- /* Asynchronous transfer */
- if (pAsync) {
-
- /* Update the transfer descriptor */
- pTwid->pTransfer = pAsync;
- pTransfer = (AsyncTwi *) pAsync;
- pTransfer->status = ASYNC_STATUS_PENDING;
- pTransfer->pData = pData;
- pTransfer->num = num;
- pTransfer->transferred = 1;
-
- /* Enable write interrupt and start the transfer */
- TWI_StartWrite(pTwi, address, iaddress, isize, *pData);
- TWI_EnableIt(pTwi, TWI_IER_TXRDY);
- }
- /* Synchronous transfer*/
- else {
-
- // Start write
- TWI_StartWrite(pTwi, address, iaddress, isize, *pData++);
- num--;
-
- /* Send all bytes */
- while (num > 0) {
-
- /* Wait before sending the next byte */
- timeout = 0;
- while( !TWI_ByteSent(pTwi) && (++timeout
-#include
-
-/*----------------------------------------------------------------------------
- * Definition
- *----------------------------------------------------------------------------*/
-
-/** TWI driver is currently busy. */
-#define TWID_ERROR_BUSY 1
-
-/*----------------------------------------------------------------------------
- * Types
- *----------------------------------------------------------------------------*/
-
-/** TWI driver structure. Holds the internal state of the driver.*/
-typedef struct _Twid {
- /** Pointer to the underlying TWI peripheral.*/
- Twi *pTwi;
- /** Current asynchronous transfer being processed.*/
- Async *pTransfer;
-
-} Twid;
-
-/*----------------------------------------------------------------------------
- * Export functions
- *----------------------------------------------------------------------------*/
-extern void TWID_Initialize(Twid *pTwid, Twi *pTwi);
-
-extern void TWID_Handler(Twid *pTwid);
-
-extern uint8_t TWID_Read(
- Twid *pTwid,
- uint8_t address,
- uint32_t iaddress,
- uint8_t isize,
- uint8_t *pData,
- uint32_t num,
- Async *pAsync);
-
-extern uint8_t TWID_Write(
- Twid *pTwid,
- uint8_t address,
- uint32_t iaddress,
- uint8_t isize,
- uint8_t *pData,
- uint32_t num,
- Async *pAsync);
-
-#endif //#ifndef TWID_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/usart/uart_console.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/usart/uart_console.c
deleted file mode 100644
index 07eaeec3..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/usart/uart_console.c
+++ /dev/null
@@ -1,288 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- *
- * Implements UART console.
- *
- */
-
-/*----------------------------------------------------------------------------
- * Headers
- *----------------------------------------------------------------------------*/
-
-#include
-#include
-#include
-#include
-#include
-#include
-
-#include "usart/uart_console.h"
-
-/*----------------------------------------------------------------------------
- * Definitions
- *----------------------------------------------------------------------------*/
-
-/** Console baudrate always using 115200. */
-#define CONSOLE_BAUDRATE 115200
-/** Usart Hw interface used by the console (UART0). */
-#define CONSOLE_USART UART0
-/** Usart Hw ID used by the console (UART0). */
-#define CONSOLE_ID ID_UART0
-/** Pins description corresponding to Rxd,Txd, (UART pins) */
-#define CONSOLE_PINS {PINS_UART}
-
-/*----------------------------------------------------------------------------
- * Variables
- *----------------------------------------------------------------------------*/
-
-/** Is Console Initialized. */
-static uint8_t isConsolInitialized = 0;
-
-/**
- * \brief Configures an USART peripheral with the specified parameters.
- *
- * \param baudrate Baudrate at which the USART should operate (in Hz).
- * \param masterClock Frequency of the system master clock (in Hz).
- */
-static void UART_Configure( uint32_t baudrate,
- uint32_t masterClock)
-{
- const Pin pPins[] = CONSOLE_PINS;
- Uart *pUart = CONSOLE_USART;
-
- /* Configure PIO */
- PIO_Configure(pPins, PIO_LISTSIZE(pPins));
-
- /* Configure PMC */
- PMC->PMC_PCER0 = 1 << CONSOLE_ID;
-
- /* Reset and disable receiver & transmitter */
- pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX
- | UART_CR_RXDIS | UART_CR_TXDIS;
-
- /* Configure mode */
- pUart->UART_MR = (0x4 << 9); /* TODO: Change with new symbols: AT91C_UART_CHRL_8_BITS | AT91C_UART_PAR_NONE */
-
- /* Configure baudrate */
- /* Asynchronous, no oversampling */
- pUart->UART_BRGR = (masterClock / baudrate) / 16;
-
- /* Disable PDC channel */
- pUart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS;
-
- /* Enable receiver and transmitter */
- pUart->UART_CR = UART_CR_RXEN | UART_CR_TXEN;
-
- isConsolInitialized = 1;
-}
-
-/**
- * \brief Outputs a character on the UART line.
- *
- * \note This function is synchronous (i.e. uses polling).
- * \param c Character to send.
- */
-void UART_PutChar(uint8_t c)
-{
- Uart *pUart = CONSOLE_USART;
-
- if (!isConsolInitialized)
- UART_Configure(CONSOLE_BAUDRATE, BOARD_MCK);
-
- /* Wait for the transmitter to be ready */
- while ((pUart->UART_SR & UART_SR_TXEMPTY) == 0);
-
- /* Send character */
- pUart->UART_THR = c;
-
-}
-
-/**
- * \brief Input a character from the UART line.
- *
- * \note This function is synchronous
- * \return character received.
- */
-uint8_t UART_GetChar(void)
-{
- Uart *pUart = CONSOLE_USART;
-
- if (!isConsolInitialized)
- UART_Configure(CONSOLE_BAUDRATE, BOARD_MCK);
-
- while((pUart->UART_SR & UART_SR_RXRDY) == 0);
- return pUart->UART_RHR;
-}
-
-/**
- * \brief Check if there is Input from UART line.
- *
- * \return true if there is Input.
- */
-bool UART_IsRxReady(void)
-{
- Uart *pUart = CONSOLE_USART;
-
- if (!isConsolInitialized)
- UART_Configure(CONSOLE_BAUDRATE, BOARD_MCK);
-
- return (pUart->UART_SR & UART_SR_RXRDY) > 0;
-}
-
-/* \cond NOFPUT */
-#ifndef NOFPUT
-#include
-#include
-/**
- * \brief Implementation of fputc using the UART as the standard output. Required
- * for printf().
- *
- * \param c Character to write.
- * \param pStream Output stream.
- *
- * \return The character written if successful, or -1 if the output stream is
- * not stdout or stderr.
- */
-int fputc ( int c, FILE * pStream )
-{
- if ((pStream == stdout) || (pStream == stderr)) {
- UART_PutChar(c);
- return c;
- }
- else {
-
- return EOF;
- }
-}
-
-/**
- * \brief Implementation of fputs using the UART as the standard output. Required
- * for printf(). Does NOT currently use the PDC.
- *
- * \param pStr String to write.
- * \param pStream Output stream.
- *
- * \return Number of characters written if successful, or -1 if the output
- * stream is not stdout or stderr.
- */
-signed int fputs(const char *pStr, FILE *pStream)
-{
- signed int num = 0;
-
- while (*pStr != 0) {
-
- if (fputc(*pStr, pStream) == -1) {
-
- return -1;
- }
- num++;
- pStr++;
- }
-
- return num;
-}
-
-#undef putchar
-
-/**
- * \brief Outputs a character on the UART.
- *
- * \param c Character to output.
- *
- * \return The character that was output.
- */
-signed int putchar(signed int c)
-{
- return fputc(c, stdout);
-}
-
-/* The char which has been ungotten, or EOF. */
-static int _UngetChar = EOF;
-
-/**
- * \brief Implementation of fputc using the UART as the standard output. Required
- * for printf().
- *
- * \param c Character to write.
- * \param pStream Output stream.
- *
- * \return The character written if successful, or -1 if the output stream is
- * not stdout or stderr.
- */
-int fgetc (FILE * pStream )
-{
- int c;
-
- if (pStream == stdin) {
- c = UART_GetChar();
- return c;
- }
- else {
-
- return EOF;
- }
-}
-
-#undef getchar
-/**
- * \brief Get a character from UART.
- *
- * \return The character received.
- */
-signed int getchar(void)
-{
- if (_UngetChar != EOF)
- {
- int res = _UngetChar;
- _UngetChar = EOF;
- return res;
- }
- else
- {
- return fgetc(stdin);
- }
-}
-
-#undef __ungetchar
-/**
- * \brief Unget a character from stdin.
- *
- * \return The unget character.
- */
-signed int __ungetchar(int c)
-{
- _UngetChar = c;
- return c;
-}
-
-#endif /* #ifndef NOFPUT */
-/* \endcond */
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/usart/uart_console.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/usart/uart_console.h
deleted file mode 100644
index dfa19217..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/usart/uart_console.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-
-#ifndef UART_CONSOLE_H_
-#define UART_CONSOLE_H_
-
-extern void UART_PutChar(uint8_t c);
-extern uint8_t UART_GetChar(void);
-extern bool UART_IsRxReady(void);
-
-#endif /* UART_CONSOLE_H_ */
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/usart/usart.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/usart/usart.c
deleted file mode 100644
index 5aa10e5d..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/usart/usart.c
+++ /dev/null
@@ -1,395 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/** \addtogroup usart_module Working with USART
- * The USART driver provides the interface to configure and use the USART peripheral.\n
- *
- * The USART supports several kinds of comminication modes such as full-duplex asynchronous/
- * synchronous serial commnunication,RS485 with driver control signal,ISO7816,SPI and Test modes.
- *
- * To start a USART transfer with \ref AT91SAM3S_PDC "PDC" support, the user could follow these steps:
- *
- *
Configure USART with expected mode and baudrate(see \ref USART_Configure), which could be done by:
- * -# Resetting and disabling transmitter and receiver by setting US_CR(Control Register).
- * -# Conifguring the USART in a specific mode by setting USART_MODE bits in US_MR(Mode Register)
- * -# Setting baudrate which is different from mode to mode.
-
- *
Enable transmitter or receiver respectively by set US_CR_TXEN or US_CR_RXEN in US_CR.
- *
Read from or write to the peripheral with \ref USART_ReadBuffer or \ref USART_WriteBuffer.
- These operations could be done by polling or interruption.
- *
For polling, check the status bit US_CSR_ENDRX/US_CSR_RXBUFF (READ) or US_CSR_ENDTX/
- US_CSR_TXBUFE (WRITE).
- *
For interruption,"enable" the status bit through US_IER and
- realize the hanler with USARTx_IrqHandler according to IRQ vector
- table which is defined in board_cstartup_.c
- To enable the interruption of USART,it should be configured with priority and enabled first through
- NVIC .
- *
- *
- * For more accurate information, please look at the USART section of the
- * Datasheet.
- *
- * Related files :\n
- * \ref usart.c\n
- * \ref usart.h\n
-*/
-
-
-
-/**
- * \file
- *
- * Implementation of USART (Universal Synchronous Asynchronous Receiver Transmitter)
- * controller.
- *
- */
-/*------------------------------------------------------------------------------
- * Headers
- *------------------------------------------------------------------------------*/
-#include
-
-#include "usart.h"
-#include
-#include
-
-/*----------------------------------------------------------------------------
- * Local definitions
- *----------------------------------------------------------------------------*/
-
-
-/*------------------------------------------------------------------------------
- * Exported functions
- *------------------------------------------------------------------------------*/
-
-/**
- * \brief Configures an USART peripheral with the specified parameters.
- *
- *
- * \param usart Pointer to the USART peripheral to configure.
- * \param mode Desired value for the USART mode register (see the datasheet).
- * \param baudrate Baudrate at which the USART should operate (in Hz).
- * \param masterClock Frequency of the system master clock (in Hz).
- */
-void USART_Configure(Usart *usart,
- uint32_t mode,
- uint32_t baudrate,
- uint32_t masterClock)
-{
- /* Reset and disable receiver & transmitter*/
- usart->US_CR = US_CR_RSTRX | US_CR_RSTTX
- | US_CR_RXDIS | US_CR_TXDIS;
-
- /* Configure mode*/
- usart->US_MR = mode;
-
- /* Configure baudrate*/
- /* Asynchronous, no oversampling*/
- if (((mode & US_MR_SYNC__CPHA) == 0)
- && ((mode & US_MR_OVER) == 0)) {
-
- usart->US_BRGR = (masterClock / baudrate) / 16;
- }
- /* TODO other modes*/
-}
-/**
- * \brief Enables or disables the transmitter of an USART peripheral.
- *
- *
- * \param usart Pointer to an USART peripheral
- * \param enabled If true, the transmitter is enabled; otherwise it is
- * disabled.
- */
-void USART_SetTransmitterEnabled(Usart *usart, uint8_t enabled)
-{
- if (enabled) {
-
- usart->US_CR = US_CR_TXEN;
- }
- else {
-
- usart->US_CR = US_CR_TXDIS;
- }
-}
-
-/**
- * \brief Enables or disables the receiver of an USART peripheral
- *
- *
- * \param usart Pointer to an USART peripheral
- * \param enabled If true, the receiver is enabled; otherwise it is disabled.
- */
-void USART_SetReceiverEnabled(Usart *usart,
- uint8_t enabled)
-{
- if (enabled) {
-
- usart->US_CR = US_CR_RXEN;
- }
- else {
-
- usart->US_CR = US_CR_RXDIS;
- }
-}
-
-/**
- * \brief Sends one packet of data through the specified USART peripheral. This
- * function operates synchronously, so it only returns when the data has been
- * actually sent.
- *
- *
- * \param usart Pointer to an USART peripheral.
- * \param data Data to send including 9nth bit and sync field if necessary (in
- * the same format as the US_THR register in the datasheet).
- * \param timeOut Time out value (0 = no timeout).
- */
-void USART_Write(
- Usart *usart,
- uint16_t data,
- volatile uint32_t timeOut)
-{
- if (timeOut == 0) {
-
- while ((usart->US_CSR & US_CSR_TXEMPTY) == 0);
- }
- else {
-
- while ((usart->US_CSR & US_CSR_TXEMPTY) == 0) {
-
- if (timeOut == 0) {
-
- TRACE_ERROR("USART_Write: Timed out.\n\r");
- return;
- }
- timeOut--;
- }
- }
-
- usart->US_THR = data;
-}
-
-/**
- * \brief Sends the contents of a data buffer through the specified USART peripheral.
- * This function returns immediately (1 if the buffer has been queued, 0
- * otherwise); poll the ENDTX and TXBUFE bits of the USART status register
- * to check for the transfer completion.
- *
- * \param usart Pointer to an USART peripheral.
- * \param buffer Pointer to the data buffer to send.
- * \param size Size of the data buffer (in bytes).
- */
-uint8_t USART_WriteBuffer(
- Usart *usart,
- void *buffer,
- uint32_t size)
-{
- /* Check if the first PDC bank is free*/
- if ((usart->US_TCR == 0) && (usart->US_TNCR == 0)) {
-
- usart->US_TPR = (uint32_t) buffer;
- usart->US_TCR = size;
- usart->US_PTCR = US_PTCR_TXTEN;
-
- return 1;
- }
- /* Check if the second PDC bank is free*/
- else if (usart->US_TNCR == 0) {
-
- usart->US_TNPR = (uint32_t) buffer;
- usart->US_TNCR = size;
-
- return 1;
- }
- else {
-
- return 0;
- }
-}
-
-
-/**
- * \brief Reads and return a packet of data on the specified USART peripheral. This
- * function operates asynchronously, so it waits until some data has been
- * received.
- *
- * \param usart Pointer to an USART peripheral.
- * \param timeOut Time out value (0 -> no timeout).
- */
-uint16_t USART_Read(
- Usart *usart,
- volatile uint32_t timeOut)
-{
- if (timeOut == 0) {
-
- while ((usart->US_CSR & US_CSR_RXRDY) == 0);
- }
- else {
-
- while ((usart->US_CSR & US_CSR_RXRDY) == 0) {
-
- if (timeOut == 0) {
-
- TRACE_ERROR("USART_Read: Timed out.\n\r");
- return 0;
- }
- timeOut--;
- }
- }
-
- return usart->US_RHR;
-}
-
-/**
- * \brief Reads data from an USART peripheral, filling the provided buffer until it
- * becomes full. This function returns immediately with 1 if the buffer has
- * been queued for transmission; otherwise 0.
- *
- * \param usart Pointer to an USART peripheral.
- * \param buffer Pointer to the buffer where the received data will be stored.
- * \param size Size of the data buffer (in bytes).
- */
-uint8_t USART_ReadBuffer(Usart *usart,
- void *buffer,
- uint32_t size)
-{
- /* Check if the first PDC bank is free*/
- if ((usart->US_RCR == 0) && (usart->US_RNCR == 0)) {
-
- usart->US_RPR = (uint32_t) buffer;
- usart->US_RCR = size;
- usart->US_PTCR = US_PTCR_RXTEN;
-
- return 1;
- }
- /* Check if the second PDC bank is free*/
- else if (usart->US_RNCR == 0) {
-
- usart->US_RNPR = (uint32_t) buffer;
- usart->US_RNCR = size;
-
- return 1;
- }
- else {
-
- return 0;
- }
-}
-
-/**
- * \brief Returns 1 if some data has been received and can be read from an USART;
- * otherwise returns 0.
- *
- * \param usart Pointer to an Usart instance.
- */
-uint8_t USART_IsDataAvailable(Usart *usart)
-{
- if ((usart->US_CSR & US_CSR_RXRDY) != 0) {
-
- return 1;
- }
- else {
-
- return 0;
- }
-}
-
-/**
- * \brief Sets the filter value for the IRDA demodulator.
- *
- * \param pUsart Pointer to an Usart instance.
- * \param filter Filter value.
- */
-void USART_SetIrdaFilter(Usart *pUsart, uint8_t filter)
-{
- SANITY_CHECK(pUsart);
-
- pUsart->US_IF = filter;
-}
-
-/**
- * \brief Sends one packet of data through the specified USART peripheral. This
- * function operates synchronously, so it only returns when the data has been
- * actually sent.
- *
- * \param usart Pointer to an USART peripheral.
- * \param c Character to send
- */
-void USART_PutChar(
- Usart *usart,
- uint8_t c)
-{
- /* Wait for the transmitter to be ready*/
- while ((usart->US_CSR & US_CSR_TXEMPTY) == 0);
-
- /* Send character*/
- usart->US_THR = c;
-
- /* Wait for the transfer to complete*/
- while ((usart->US_CSR & US_CSR_TXEMPTY) == 0);
-}
-
-/**
- * \brief Return 1 if a character can be read in USART
- */
-uint32_t USART_IsRxReady(Usart *usart)
-{
- return (usart->US_CSR & US_CSR_RXRDY);
-}
-/**
- * \brief Get present status
- */
-uint32_t USART_GetStatus(Usart *usart)
-{
- return usart->US_CSR;
-}
-/**
- * \brief Enable interrupt
- */
-void USART_EnableIt(Usart *usart,uint32_t mode)
-{
- usart->US_IER = mode;
-}
-/**
- * \brief Disable interrupt
- */
-void USART_DisableIt(Usart *usart,uint32_t mode)
-{
- usart->US_IDR = mode;
-}
-/**
- * \brief Reads and returns a character from the USART.
- *
- * \note This function is synchronous (i.e. uses polling).
- * \param usart Pointer to an USART peripheral.
- * \return Character received.
- */
-uint8_t USART_GetChar(Usart *usart)
-{
- while ((usart->US_CSR & US_CSR_RXRDY) == 0);
- return usart->US_RHR;
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/usart/usart.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/usart/usart.h
deleted file mode 100644
index 8c50f87e..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/usart/usart.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- *
- * \par Purpose
- *
- * This module provides several definitions and methods for using an USART
- * peripheral.
- *
- * \par Usage
- *
- * -# Enable the USART peripheral clock in the PMC.
- * -# Enable the required USART PIOs (see pio.h).
- * -# Configure the UART by calling USART_Configure.
- * -# Enable the transmitter and/or the receiver of the USART using
- * USART_SetTransmitterEnabled and USART_SetReceiverEnabled.
- * -# Send data through the USART using the USART_Write and
- * USART_WriteBuffer methods.
- * -# Receive data from the USART using the USART_Read and
- * USART_ReadBuffer functions; the availability of data can be polled
- * with USART_IsDataAvailable.
- * -# Disable the transmitter and/or the receiver of the USART with
- * USART_SetTransmitterEnabled and USART_SetReceiverEnabled.
- */
-
-#ifndef USART_H
-#define USART_H
-
-/*------------------------------------------------------------------------------
- * Headers
- *------------------------------------------------------------------------------*/
-
-#include
-
-/*------------------------------------------------------------------------------
- * Definitions
- *------------------------------------------------------------------------------*/
-
-/** \section USART_mode USART modes
- * This section lists several common operating modes for an USART peripheral.
- *
- * \b Modes
- * - USART_MODE_ASYNCHRONOUS
- * - USART_MODE_IRDA
- */
-
-/** Basic asynchronous mode, i.e. 8 bits no parity.*/
-#define USART_MODE_ASYNCHRONOUS (AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE)
-
-/** IRDA mode*/
-#define USART_MODE_IRDA (AT91C_US_USMODE_IRDA | AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE | AT91C_US_FILTER)
-
-
-/*------------------------------------------------------------------------------*/
-/* Exported functions*/
-/*------------------------------------------------------------------------------*/
-
-extern void USART_Configure(
- Usart *usart,
- uint32_t mode,
- uint32_t baudrate,
- uint32_t masterClock);
-extern uint32_t USART_GetStatus(Usart *usart);
-extern void USART_EnableIt(Usart *usart,uint32_t mode);
-extern void USART_DisableIt(Usart *usart,uint32_t mode);
-extern void USART_SetTransmitterEnabled(Usart *usart, uint8_t enabled);
-
-extern void USART_SetReceiverEnabled(Usart *usart, uint8_t enabled);
-
-extern void USART_Write(
- Usart *usart,
- uint16_t data,
- volatile uint32_t timeOut);
-
-extern uint8_t USART_WriteBuffer(
- Usart *usart,
- void *buffer,
- uint32_t size);
-
-extern uint16_t USART_Read(
- Usart *usart,
- volatile uint32_t timeOut);
-
-extern uint8_t USART_ReadBuffer(
- Usart *usart,
- void *buffer,
- uint32_t size);
-
-extern uint8_t USART_IsDataAvailable(Usart *usart);
-
-extern void USART_SetIrdaFilter(Usart *pUsart, uint8_t filter);
-
-extern void USART_PutChar(Usart *usart, uint8_t c);
-
-extern uint32_t USART_IsRxReady(Usart *usart);
-
-extern uint8_t USART_GetChar(Usart *usart);
-
-
-#endif /*#ifndef USART_H*/
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/assert.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/assert.h
deleted file mode 100644
index 5c21781d..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/assert.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-/// \unit
-///
-/// !Purpose
-///
-/// Definition of the ASSERT() and SANITY_CHECK() macros, which are used for
-/// runtime condition & parameter verifying.
-///
-/// !Usage
-///
-/// -# Use ASSERT() in your code to check the value of function parameters,
-/// return values, etc. *Warning:* the ASSERT() condition must not have
-/// any side-effect; otherwise, the program may not work properly
-/// anymore when assertions are disabled.
-/// -# Use SANITY_CHECK() to perform checks with a default error message
-/// (outputs the file and line number where the error occured). This
-/// reduces memory overhead caused by assertion error strings.
-/// -# Initialize the dbgu to see failed assertions at run-time.
-/// -# Assertions can be entirely disabled by defining the NOASSERT symbol
-/// at compilation time.
-//------------------------------------------------------------------------------
-
-#ifndef ASSERT_H
-#define ASSERT_H
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-
-#include
-#include "trace.h"
-
-//------------------------------------------------------------------------------
-// Definitions
-//------------------------------------------------------------------------------
-#if defined(NOASSERT)
- #define ASSERT(...)
- #define SANITY_CHECK(...)
-#else
-
- #if (TRACE_LEVEL == 0)
- /// Checks that the given condition is true,
- /// otherwise stops the program execution.
- /// \param condition Condition to verify.
- #define ASSERT(condition, ...) { \
- if (!(condition)) { \
- while (1); \
- } \
- }
-
- /// Performs the same duty as the ASSERT() macro
- /// \param condition Condition to verify.
- #define SANITY_CHECK(condition) ASSERT(condition, ...)
-
- #else
- /// Checks that the given condition is true, otherwise displays an error
- /// message and stops the program execution.
- /// \param condition Condition to verify.
- #define ASSERT(condition, ...) { \
- if (!(condition)) { \
- printf("-F- ASSERT: "); \
- printf(__VA_ARGS__); \
- while (1); \
- } \
- }
- #define SANITY_ERROR "Sanity check failed at %s:%d\n\r"
-
- /// Performs the same duty as the ASSERT() macro, except a default error
- /// message is output if the condition is false.
- /// \param condition Condition to verify.
- #define SANITY_CHECK(condition) ASSERT(condition, SANITY_ERROR, __FILE__, __LINE__)
- #endif
-#endif
-
-
-
-
-
-
-
-
-
-
-#endif //#ifndef ASSERT_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/bitbanding.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/bitbanding.h
deleted file mode 100644
index 8ef5976c..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/bitbanding.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-#ifndef BITBANDING_H
-#define BITBANDING_H
-
-//------------------------------------------------------------------------------
-/// \file bitbanding.h
-/// Include Defines & macros for bit-banding.
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Header files
-//------------------------------------------------------------------------------
-
-#include
-
-//------------------------------------------------------------------------------
-// Global Macros
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// \def IS_BITBAND_SRAM_ADDR(x)
-/// \brief Check if the address is in bit banding sram region.
-/// \note The address should be in area of 0x2000000 ~ 0x200FFFFF
-/// \param x The address to check.
-//------------------------------------------------------------------------------
-#define IS_BITBAND_SRAM_ADDR(x) \
- ( ((uint32_t)(x)) >= 0x20000000 && \
- ((uint32_t)(x)) < (0x20000000+0x100000) )
-
-//------------------------------------------------------------------------------
-/// \def IS_BITBAND_PERIPH_ADDR(x)
-/// \brief Check if the address is in bit banding peripheral region
-/// \note The address should be in area of 0x4000000 ~ 0x400FFFFF
-/// \param x The address to check
-//------------------------------------------------------------------------------
-#define IS_BITBAND_PERIPH_ADDR(x) \
- ( ((uint32_t)(x)) >= 0x40000000 && \
- ((uint32_t)(x)) < (0x40000000+0x100000) )
-
-//------------------------------------------------------------------------------
-/// \def BITBAND_ALIAS_ADDRESS(addr, bit)
-/// \brief Calculate bit band alias address.
-///
-/// Calculate the bit band alias address and return a pointer address to word.
-/// \param addr The byte address of bitbanding bit.
-/// \param bit The bit position of bitbanding bit.
-/// \callergraph
-//------------------------------------------------------------------------------
-#define BITBAND_ALIAS_ADDRESS(addr, bit) \
- ((volatile uint32_t*)((((uint32_t)(addr) & 0xF0000000) + 0x02000000) \
- +((((uint32_t)(addr)&0xFFFFF)*32)\
- +( (uint32_t)(bit)*4))))
-
-//------------------------------------------------------------------------------
-/// \def WRITE_BITBANDING(addr32, bit, val)
-/// \brief Bit write through bit banding.
-/// \param addr32 32-bit aligned byte address where the bit exists.
-/// \param bit Bit position.
-/// \param val The value that the bit is set to.
-/// \callergraph
-//------------------------------------------------------------------------------
-#define WRITE_BITBANDING(addr32, bit, val) do {\
- *BITBAND_ALIAS_ADDRESS(addr32,bit) = (val); \
- } while (0);
-
-//------------------------------------------------------------------------------
-/// \def TOGGLE_BITBANDING(addr32, bit)
-/// \brief Toggle bit through bit banding
-/// \param addr32 32-bit aligned byte address where the bit exists.
-/// \param bit Bit position.
-//------------------------------------------------------------------------------
-#define TOGGLE_BITBANDING(addr32, bit) do {\
- volatile uint32_t * p = \
- BITBAND_ALIAS_ADDRESS(addr32,bit); \
- if (*p) *p = 0; \
- else *p = 1; \
- }while(0);
-
-#endif //#ifndef BITBANDING_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/bmp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/bmp.c
deleted file mode 100644
index fe305875..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/bmp.c
+++ /dev/null
@@ -1,322 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-
-#include "bmp.h"
-#include
-#include
-
-#include
-
-//-----------------------------------------------------------------------------
-// Define
-//-----------------------------------------------------------------------------
-/// BMP offset for header
-#define IMAGE_OFFSET 0x100
-
-
-//------------------------------------------------------------------------------
-// Internal constants
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Internal types
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Describe the BMP palette
-//------------------------------------------------------------------------------
-struct BMPPaletteEntry {
-
- /// Blue value
- unsigned char b;
- /// Green value
- unsigned char g;
- /// Red value
- unsigned char r;
- /// Filler character value
- unsigned char filler;
-};
-
-//------------------------------------------------------------------------------
-// Exported functions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Test if BMP is valid
-/// \param file Buffer holding the file to examinate.
-/// \return 1 if the header of a BMP file is valid; otherwise returns 0.
-//------------------------------------------------------------------------------
-unsigned char BMP_IsValid(void *file)
-{
- return ((struct BMPHeader *) file)->type == BMP_TYPE;
-}
-
-//------------------------------------------------------------------------------
-/// Returns the size of a BMP image given at least its header (the file does
-/// not have to be complete).
-/// \param file Pointer to the buffer which holds the BMP file.
-/// \return size of BMP image
-//------------------------------------------------------------------------------
-unsigned int BMP_GetFileSize(void *file)
-{
- return ((struct BMPHeader *) file)->fileSize;
-}
-
-//-----------------------------------------------------------------------------
-/// Write a BMP header
-/// \param pAddressHeader Begin address of the BMP
-/// \param bmpHSize BMP heigth size
-/// \param bmpVSize BMP width size
-/// \param bmpRgb Type of BMP (YUV or RGB)
-/// \param nbByte_Pixels Number of byte per pixels
-//-----------------------------------------------------------------------------
-void WriteBMPheader(unsigned int* pAddressHeader,
- unsigned int bmpHSize,
- unsigned int bmpVSize,
- unsigned char bmpRgb,
- unsigned char nbByte_Pixels)
-{
- unsigned int i;
- unsigned int* fill;
- struct BMPHeader *Header;
-
- fill = pAddressHeader;
- for (i=0; itype = BMP_TYPE;
- Header->fileSize = (bmpHSize * bmpVSize * nbByte_Pixels) + IMAGE_OFFSET;
- Header->reserved1 = 0;
- Header->reserved2 = 0;
- Header->offset = IMAGE_OFFSET;
- Header->headerSize = BITMAPINFOHEADER;
- Header->width = bmpHSize;
- Header->height = bmpVSize;
- Header->planes = 1;
- Header->bits = nbByte_Pixels * 8;
- Header->compression = 0;
- Header->imageSize = bmpHSize * bmpVSize * nbByte_Pixels;
- Header->xresolution = 0;
- Header->yresolution = 0;
- Header->ncolours = 0;
- Header->importantcolours = 0;
-}
-
-
-//------------------------------------------------------------------------------
-/// debug function, dislay BMP header
-/// \param pAddressHeader Address of the BMP
-//------------------------------------------------------------------------------
-void BMP_displayHeader(unsigned int* pAddressHeader)
-{
- struct BMPHeader *header;
-
- header = (struct BMPHeader*) pAddressHeader;
-
- TRACE_INFO("BMP\n\r");
- TRACE_INFO("type 0x%X \n\r", header->type);
- TRACE_INFO("fileSize %d \n\r", header->fileSize);
- TRACE_INFO("reserved1 %d \n\r", header->reserved1);
- TRACE_INFO("reserved2 %d \n\r", header->reserved2);
- TRACE_INFO("offset %d \n\r", header->offset);
- TRACE_INFO("headerSize %d \n\r", header->headerSize);
- TRACE_INFO("width %d \n\r", header->width);
- TRACE_INFO("height %d \n\r", header->height);
- TRACE_INFO("planes %d \n\r", header->planes);
- TRACE_INFO("bits %d \n\r", header->bits);
- TRACE_INFO("compression %d \n\r", header->compression);
- TRACE_INFO("imageSize %d \n\r", header->imageSize);
- TRACE_INFO("xresolution %d \n\r", header->xresolution);
- TRACE_INFO("yresolution %d \n\r", header->yresolution);
- TRACE_INFO("ncolours %d \n\r", header->ncolours);
- TRACE_INFO("importantcolours %d\n\r", header->importantcolours);
-}
-
-
-//------------------------------------------------------------------------------
-/// Loads a BMP image located at the given address, decodes it and stores the
-/// resulting image inside the provided buffer. Image must have the specified
-/// width & height.
-/// If no buffer is provided, this function simply checks if it is able to
-/// decode the image.
-/// \param file Buffer which holds the BMP file.
-/// \param buffer Buffer in which to store the decoded image.
-/// \param width Buffer width in pixels.
-/// \param height Buffer height in pixels.
-/// \param bpp Number of bits per pixels that the buffer stores.
-/// \return 0 if the image has been loaded; otherwise returns an error code.
-//------------------------------------------------------------------------------
-unsigned char BMP_Decode(
- void *file,
- unsigned char *buffer,
- unsigned int width,
- unsigned int height,
- unsigned char bpp)
-{
- struct BMPHeader *header;
- unsigned int i, j;
- unsigned char r, g, b;
- unsigned char *image;
-
- // Read header information
- header = (struct BMPHeader *) file;
-
- // Verify that the file is valid
- if (!BMP_IsValid(file)) {
-
- TRACE_ERROR("BMP_Decode: File type is not 'BM' (0x%04X).\n\r",header->type);
- return 1;
- }
-
- // Check that parameters match
- if ((header->compression != 0)
- || (header->width != width)
- || (header->height != height)) {
-
- TRACE_ERROR("BMP_Decode: File format not supported\n\r");
- TRACE_ERROR(" -> .compression = %u\n\r", header->compression);
- TRACE_ERROR(" -> .width = %u\n\r", header->width);
- TRACE_ERROR(" -> .height = %u\n\r", header->height);
- TRACE_ERROR(" -> .bits = %d\n\r", header->bits);
- return 2;
- }
-
- // Get image data
- image = (unsigned char *) ((unsigned int) file + header->offset);
-
- // Check that the bpp resolution is supported
- // Only a 24-bit output & 24- or 8-bit input are supported
- if (bpp != 24) {
-
- TRACE_ERROR("BMP_Decode: Output resolution not supported\n\r");
- return 3;
- }
- else if (header->bits == 24) {
-
- // Decoding is ok
- if (!buffer) return 0;
-
- // Get image data (swapping red & blue)
- for (i=0; i < height; i++) {
- for (j=0; j < width; j++) {
-
- r = image[((height - i - 1) * width + j) * 3 + 2];
- g = image[((height - i - 1) * width + j) * 3 + 1];
- b = image[((height - i - 1) * width + j) * 3];
-
-#if defined(BOARD_LCD_RGB565)
- // Interlacing
- r = ((r << 1) & 0xF0) | ((g & 0x80) >> 4) | ((r & 0x80) >> 5);
- g = (g << 1) & 0xF8;
- b = b & 0xF8;
-
- buffer[(i * width + j) * 3] = b;
- buffer[(i * width + j) * 3 + 1] = g;
- buffer[(i * width + j) * 3 + 2] = r;
-
-#else
- buffer[(i * width + j) * 3] = r;
- buffer[(i * width + j) * 3 + 1] = g;
- buffer[(i * width + j) * 3 + 2] = b;
-#endif //#if defined(BOARD_LCD_RGB565)
- }
- }
- }
- else if (header->bits == 8) {
-
- // Decoding is ok
- if (!buffer) return 0;
-
- // Retrieve palette
- struct BMPPaletteEntry palette[256];
- memcpy(palette,
- (unsigned char *) ((unsigned int) file + sizeof(struct BMPHeader)),
- header->offset - sizeof(struct BMPHeader));
-
- // Decode image (reversing row order)
- for (i=0; i < height; i++) {
- for (j=0; j < width; j++) {
-
- r = palette[image[(height - i - 1) * width + j]].r;
- g = palette[image[(height - i - 1) * width + j]].g;
- b = palette[image[(height - i - 1) * width + j]].b;
-
- buffer[(i * width + j) * 3] = r;
- buffer[(i * width + j) * 3 + 1] = g;
- buffer[(i * width + j) * 3 + 2] = b;
- }
- }
- }
- else {
-
- TRACE_ERROR("BMP_Decode: Input resolution not supported\n\r");
- TRACE_INFO("header->bits 0x%X \n\r", header->bits);
- return 4;
- }
-
- return 0;
-}
-
-//------------------------------------------------------------------------------
-/// Convert RGB 565 to RGB 555 (RGB 555 is adapted to LCD)
-/// \param fileSource Buffer which holds the RGB file
-/// \param fileDestination Buffer in which to store the decoded image
-/// \param width Buffer width in pixels.
-/// \param height Buffer height in pixels.
-/// \param bpp Number of bits per pixels that the buffer stores.
-//------------------------------------------------------------------------------
-void RGB565toBGR555(
- unsigned char *fileSource,
- unsigned char *fileDestination,
- unsigned int width,
- unsigned int height,
- unsigned char bpp)
-{
- unsigned int i;
- unsigned int j;
- unsigned int row;
-
- for (i=0; i < height*(bpp/8); i++) {
- row = (i*width*(bpp/8));
- for (j=0; j <= width*(bpp/8); j+=2) {
- fileDestination[row+j] = ((fileSource[row+j+1]>>3)&0x1F)
- | (fileSource[row+j]&0xE0);
- fileDestination[row+j+1] = (fileSource[row+j+1]&0x03)
- | ((fileSource[row+j]&0x1F)<<2);
- }
- }
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/bmp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/bmp.h
deleted file mode 100644
index 81280b22..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/bmp.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-/// \unit
-///
-/// !!!Purpose
-///
-/// Utility for BMP
-///
-//------------------------------------------------------------------------------
-
-#ifndef BMP_H
-#define BMP_H
-
-/// BMP magic number ('BM').
-#define BMP_TYPE 0x4D42
-
-/// headerSize must be set to 40
-#define BITMAPINFOHEADER 40
-
-//------------------------------------------------------------------------------
-// Exported types
-//------------------------------------------------------------------------------
-
-#ifdef __ICCARM__ // IAR
-#pragma pack(1) // IAR
-#define __attribute__(...) // IAR
-#endif // IAR
-
-// BMP (Windows) Header Format
-struct BMPHeader {
- /// signature, must be 4D42 hex
- unsigned short type;
- /// size of BMP file in bytes (unreliable)
- unsigned int fileSize;
- /// reserved, must be zero
- unsigned short reserved1;
- /// reserved, must be zero
- unsigned short reserved2;
- /// offset to start of image data in bytes
- unsigned int offset;
- /// size of BITMAPINFOHEADER structure, must be 40
- unsigned int headerSize;
- /// image width in pixels
- unsigned int width;
- /// image height in pixels
- unsigned int height;
- /// number of planes in the image, must be 1
- unsigned short planes;
- /// number of bits per pixel (1, 4, 8, 16, 24, 32)
- unsigned short bits;
- /// compression type (0=none, 1=RLE-8, 2=RLE-4)
- unsigned int compression;
- /// size of image data in bytes (including padding)
- unsigned int imageSize;
- /// horizontal resolution in pixels per meter (unreliable)
- unsigned int xresolution;
- /// vertical resolution in pixels per meter (unreliable)
- unsigned int yresolution;
- /// number of colors in image, or zero
- unsigned int ncolours;
- /// number of important colors, or zero
- unsigned int importantcolours;
-
-} __attribute__ ((packed)); // GCC
-
-#ifdef __ICCARM__ // IAR
-#pragma pack() // IAR
-#endif // IAR
-
-//------------------------------------------------------------------------------
-// Exported functions
-//------------------------------------------------------------------------------
-
-extern unsigned char BMP_IsValid(void *file);
-
-extern unsigned int BMP_GetFileSize(void *file);
-
-extern unsigned char BMP_Decode(
- void *file,
- unsigned char *buffer,
- unsigned int width,
- unsigned int height,
- unsigned char bpp);
-
-extern void WriteBMPheader(unsigned int* pAddressHeader,
- unsigned int bmpHSize,
- unsigned int bmpVSize,
- unsigned char bmpRgb,
- unsigned char nbByte_Pixels);
-
-extern void BMP_displayHeader(unsigned int* pAddressHeader);
-
-extern void RGB565toBGR555(
- unsigned char *fileSource,
- unsigned char *fileDestination,
- unsigned int width,
- unsigned int height,
- unsigned char bpp);
-
-
-#endif //#ifndef BMP_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/clock.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/clock.c
deleted file mode 100644
index c298fb79..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/clock.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-
-#include "clock.h"
-#include
-#include
-
-//------------------------------------------------------------------------------
-// Internal types
-//------------------------------------------------------------------------------
-int currentConfig = 0; // 0 have to be the default configuration
-
-//------------------------------------------------------------------------------
-/// Describes a possible clock configuration (processor clock & master clock),
-/// including the necessary register values.
-//------------------------------------------------------------------------------
-struct ClockConfiguration {
-
- /// Processor clock frequency (in MHz).
- unsigned short pck;
- /// Master clock frequency (in MHz).
- unsigned short mck;
- /// CKGR_PLL reqister value.
- unsigned int pllr;
- /// PMC_MCKR register value.
- unsigned int mckr;
-};
-
-//------------------------------------------------------------------------------
-// Internal variables
-//------------------------------------------------------------------------------
-
-// Clock configurations for the AT91SAM9263-EK
-#if defined(at91sam9263)
-
-#define AT91C_CKGR_PLLR AT91C_CKGR_PLLAR
-#define AT91C_PMC_LOCK AT91C_PMC_LOCKA
-
-static const struct ClockConfiguration clockConfigurations[] = {
- // PCK = 200 MHz, MCK = 100 MHz
- {200, 100, 0x206DBF09, 0x00000102},
- // PCK = 240 MHz, MCK = 120 MHz
- {240, 120, 0x202BC003, 0x00000102},
- // PCK = 120 MHz, MCK = 120 MHz
- {120, 120, 0x20156003, 0x00000002},
- // PCK = 96 MHz, MCK = 48 MHz
- {96, 48, 0x2057400F, 0x00000102},
- // PCK = 48 MHz, MCK = 48 MHz
- {48, 48, 0x2057400F, 0x00000006}
-};
-
-// Clock configurations for the AT91SAM9G20-EK
-#elif defined(at91sam9g20)
-
-#define AT91C_CKGR_PLLR AT91C_CKGR_PLLAR
-#define AT91C_PMC_LOCK AT91C_PMC_LOCKA
-
-static const struct ClockConfiguration clockConfigurations[] = {
-
- // PCK = 400 MHz, MCK = 133 MHz
- {400, 133, 0x202A0101, 0x00001302},
- // PCK = 200 MHz, MCK = 100 MHz
- {200, 100, 0x202A3F01, 0x0000010A},
- // PCK = 96 MHz, MCK = 48 MHz
- {96, 48, 0x207C3F03, 0x0000010E},
- // PCK = 48 MHz, MCK = 48 MHz
- {48, 48, 0x207C3F03, 0x00000012}
-};
-
-// Clock configurations for the AT91SAM9XE-EK, AT91SAM9261-EK
-#elif defined(at91sam9xe128) || \
- defined(at91sam9xe256) || \
- defined(at91sam9xe512) || \
- defined(at91sam9261)
-
-#define AT91C_CKGR_PLLR AT91C_CKGR_PLLAR
-#define AT91C_PMC_LOCK AT91C_PMC_LOCKA
-
-static const struct ClockConfiguration clockConfigurations[] = {
-
- // PCK = 200 MHz, MCK = 100 MHz
- {200, 100, 0x208CBF0D, 0x00000102},
- // PCK = 100 MHz, MCK = 100 MHz
- {100, 100, 0x20273F07, 0x00000002},
- // PCK = 96 MHz, MCK = 48 MHz
- {96, 48, 0x20483F0E, 0x00000102},
- // PCK = 48 MHz, MCK = 48 MHz
- {48, 48, 0x20483F0E, 0x00000006}
-};
-
-// Clock configurations for the AT91SAM9RL64-EK, AT91CAP9-DK, AT91CAP9-STK
-#elif defined(at91sam9rl64) || \
- defined(at91cap9)
-
-#define AT91C_CKGR_PLLR AT91C_CKGR_PLLAR
-#define AT91C_PMC_LOCK AT91C_PMC_LOCKA
-
-static const struct ClockConfiguration clockConfigurations[] = {
-
- // PCK = 200 MHz, MCK = 100 MHz
- {200, 100, 0x2031BF03, 0x00000102},
- // PCK = 100 MHz, MCK = 100 MHz
- {100, 100, 0x20183F03, 0x00000002},
- // PCK = 96 MHz, MCK = 48 MHz
- {96, 48, 0x20073F01, 0x00000102},
- // PCK = 48 MHz, MCK = 48 MHz
- {48, 48, 0x20073F01, 0x00000006}
-};
-
-// Clock configuration for the AT91SAM7X-EK, AT91SAM7S-EK, AT91SAM7SE-EK
-#elif defined(at91sam7x128) || defined(at91sam7x256) || defined(at91sam7x512) \
- || defined(at91sam7xc128) || defined(at91sam7xc256) || defined(at91sam7xc512) \
- || defined(at91sam7s16) || defined(at91sam7s161) || defined(at91sam7s32) \
- || defined(at91sam7s321) || defined(at91sam7s64) || defined(at91sam7s128) \
- || defined(at91sam7s256) || defined(at91sam7s512) || defined(at91sam7se32) \
- || defined(at91sam7se256) || defined(at91sam7se512)
-
-static const struct ClockConfiguration clockConfigurations[] = {
-
- // PCK = 55 MHz, MCK = 55 MHz
- {55, 55, 0x006A3F12, 0x00000007},
- // PCK = 48 MHz, MCK = 48 MHz
- {48, 48, 0x00483F0E, 0x00000007},
-};
-
-// Clock configuration for the AT91SAM7A3
-#elif defined(at91sam7a3)
-
-static const struct ClockConfiguration clockConfigurations[] = {
-
- // PCK = 60 MHz, MCK = 60 MHz
- {60, 60, 0x000C3F02, 0x00000007},
- // PCK = 48 MHz, MCK = 48 MHz
- {48, 48, 0x00483F0E, 0x00000007}
-};
-
-// No clock configuration
-#else
- #error No clock configuration for this board.
-#endif
-
-/// Number of available clock configurations
-#define NB_CLOCK_CONFIGURATION (sizeof(clockConfigurations)/sizeof(clockConfigurations[0]))
-
-//------------------------------------------------------------------------------
-// Global Functions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Sets the specified clock configuration.
-/// \param configuration Index of the configuration to set.
-//------------------------------------------------------------------------------
-void CLOCK_SetConfig(unsigned char configuration)
-{
- printf("Setting clock configuration #%d ... ", configuration);
- currentConfig = configuration;
-
- // Switch to main oscillator in two operations
- PMC->PMC_MCKR = (PMC->PMC_MCKR & ~AT91C_PMC_CSS) | AT91C_PMC_CSS_MAIN_CLK;
- while ((PMC->PMC_SR & AT91C_PMC_MCKRDY) == 0);
-
- // Configure PLL
- *AT91C_CKGR_PLLAR = clockConfigurations[configuration].pllr;
- while ((PMC->PMC_SR & AT91C_PMC_LOCKA) == 0);
-
- // Configure master clock in two operations
- PMC->PMC_MCKR = (clockConfigurations[configuration].mckr & ~AT91C_PMC_CSS) | AT91C_PMC_CSS_MAIN_CLK;
- while ((PMC->PMC_SR & AT91C_PMC_MCKRDY) == 0);
- PMC->PMC_MCKR = clockConfigurations[configuration].mckr;
- while ((PMC->PMC_SR & AT91C_PMC_MCKRDY) == 0);
-
- // DBGU reconfiguration
- DBGU_Configure(DBGU_STANDARD, 115200, clockConfigurations[configuration].mck*1000000);
- printf("done.\n\r");
-}
-
-//------------------------------------------------------------------------------
-/// Display the user menu on the DBGU.
-//------------------------------------------------------------------------------
-void CLOCK_DisplayMenu(void)
-{
- unsigned int i;
-
- printf("\n\rMenu Clock configuration:\n\r");
- for (i = 0; i < NB_CLOCK_CONFIGURATION; i++) {
-
- printf(" %d: Set PCK = %3d MHz, MCK = %3d MHz %s\n\r",
- i,
- clockConfigurations[i].pck,
- clockConfigurations[i].mck,
- (currentConfig==i)?"(curr)":"");
- }
-}
-
-//------------------------------------------------------------------------------
-/// Get the current MCK
-//------------------------------------------------------------------------------
-unsigned short CLOCK_GetCurrMCK(void)
-{
- return clockConfigurations[currentConfig].mck;
-}
-
-//------------------------------------------------------------------------------
-/// Get the current PCK
-//------------------------------------------------------------------------------
-unsigned short CLOCK_GetCurrPCK(void)
-{
- return clockConfigurations[currentConfig].pck;
-}
-
-//------------------------------------------------------------------------------
-/// Change clock configuration.
-//------------------------------------------------------------------------------
-void CLOCK_UserChangeConfig(void)
-{
- unsigned char key = 0;
-
- while (1)
- {
- CLOCK_DisplayMenu();
- key = DBGU_GetChar();
-
- if ((key >= '0') && (key <= ('0' + NB_CLOCK_CONFIGURATION - 1)))
- {
- CLOCK_SetConfig(key - '0');
- break;
- }
- }
-}
\ No newline at end of file
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/clock.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/clock.h
deleted file mode 100644
index 54083008..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/clock.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-#ifndef CLOCK_H
-#define CLOCK_H
-
-//------------------------------------------------------------------------------
-// Global Functions
-//------------------------------------------------------------------------------
-
-extern void CLOCK_SetConfig(unsigned char configuration);
-
-extern void CLOCK_DisplayMenu(void);
-
-extern void CLOCK_UserChangeConfig(void);
-
-extern unsigned short CLOCK_GetCurrMCK(void);
-
-extern unsigned short CLOCK_GetCurrPCK(void);
-
-#endif //#ifndef FREQCONF_H
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/aes_hardware.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/aes_hardware.c
deleted file mode 100644
index 1501afef..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/aes_hardware.c
+++ /dev/null
@@ -1,316 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-// Function: Firmware encryption using hardware acceleration
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include "aes_hardware.h"
-
-#if defined(USE_ENCRYPTION) && defined(ENCRYPTION_AES_HARD)
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-//------------------------------------------------------------------------------
-// Inline functions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Converts an ASCII value to an hexadecimal one
-/// \param ASCII string
-/// \param Buffer to store integer value
-/// \param Length of string
-//------------------------------------------------------------------------------
-static inline void ASCII2Hex(const unsigned char * ascii,
- unsigned char * binary,
- unsigned int length)
-{
- unsigned int i;
-
- for (i=0; i < length; i++) {
- if (ascii[i*2] >= 'A') {
- binary[i] = ascii[i*2] - 'A' + 10;
- }
- else {
- binary[i] = ascii[i*2] - '0';
- }
- binary[i] <<= 4;
- if (ascii[i*2+1] >= 'A') {
- binary[i] += ascii[i*2+1] - 'A' + 10;
- }
- else {
- binary[i] += ascii[i*2+1] - '0';
- }
- }
-}
-
-//------------------------------------------------------------------------------
-// Functions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Initializes the AES peripheral
-//------------------------------------------------------------------------------
-#ifdef ONLY_ONE_ENCRYPTION
-void aes_hard_init(void)
-{
- unsigned char key[16];
-
-#if defined(ENCRYPTION_CTR) || defined(ENCRYPTION_CBC)
- unsigned char IV[16];
-#endif
-
- TRACE_DEBUG("AES/HARD: Initializing ...\n\r");
-
- // Activate peripheral clock
-#ifdef AT91C_ID_AES
- PMC_EnablePeripheral( AT91C_ID_AES );
-#elif AT91C_ID_AESTDES
- PMC_EnablePeripheral( AT91C_ID_AESTDES );
-#elif AT91C_ID_TDES
- PMC_EnablePeripheral( AT91C_ID_TDES );
-#else
-#error AES undefined
-#endif
-
- // Load mode
-#if defined(ENCRYPTION_ECB)
- //AES_Configure(AT91C_AES_CIPHER, AT91C_AES_SMOD_PDC, AT91C_AES_OPMOD_ECB);
-
- AT91C_BASE_AES->AES_MR = AT91C_AES_SMOD_PDC | AT91C_AES_OPMOD_ECB;
-#elif defined(ENCRYPTION_CBC)
- AT91C_BASE_AES->AES_MR = AT91C_AES_SMOD_PDC | AT91C_AES_OPMOD_CBC;
-#elif defined(ENCRYPTION_CTR)
- AT91C_BASE_AES->AES_MR = AT91C_AES_SMOD_PDC | AT91C_AES_OPMOD_CTR;
-#endif
-
- // Convert and load key
- ASCII2Hex((unsigned char*)ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH);
-
- AES_SetKey((unsigned int*)key);
-
- // Convert and load IV
-#if defined(ENCRYPTION_CTR) || defined(ENCRYPTION_CBC)
- ASCII2Hex((unsigned char*)ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH);
-
- AES_SetVector((unsigned int*)IV);
-#endif
-
- TRACE_DEBUG("AES/HARD: Initialization done.\n\r");
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Initializes the AES peripheral for CBC mode
-//------------------------------------------------------------------------------
-#ifndef ONLY_ONE_ENCRYPTION
-#if defined(ENCRYPTION_CBC)
-void aes_hard_init_CBC(void)
-{
- unsigned char key[16];
- unsigned char IV[16];
-
- TRACE_DEBUG("aes_hard_init_CBC\n\r");
-
- // Activate peripheral clock
-#ifdef AT91C_ID_AES
- PMC_EnablePeripheral( AT91C_ID_AES );
-#elif AT91C_ID_AESTDES
- PMC_EnablePeripheral( AT91C_ID_AESTDES );
-#elif AT91C_ID_TDES
- PMC_EnablePeripheral( AT91C_ID_TDES );
-#else
-#error AES undefined
-#endif
-
- // Load mode
- AT91C_BASE_AES->AES_MR = AT91C_AES_SMOD_PDC | AT91C_AES_OPMOD_CBC;
-
- // Convert and load key
- ASCII2Hex((unsigned char*)ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH);
-
- AES_SetKey((unsigned int*)key);
-
- // Convert and load IV
- ASCII2Hex((unsigned char*)ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH);
-
- AES_SetVector((unsigned int*)IV);
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Initializes the AES peripheral for CTR mode
-//------------------------------------------------------------------------------
-#if defined(ENCRYPTION_CTR)
-void aes_hard_init_CTR(void)
-{
- unsigned char key[16];
- unsigned char IV[16];
-
- TRACE_DEBUG("aes_hard_init_CTR\n\r");
-
- // Activate peripheral clock
-#ifdef AT91C_ID_AES
- PMC_EnablePeripheral( AT91C_ID_AES );
-#elif AT91C_ID_AESTDES
- PMC_EnablePeripheral( AT91C_ID_AESTDES );
-#elif AT91C_ID_TDES
- PMC_EnablePeripheral( AT91C_ID_TDES );
-#else
-#error AES undefined
-#endif
-
- // Load mode
- AT91C_BASE_AES->AES_MR = AT91C_AES_SMOD_PDC | AT91C_AES_OPMOD_CTR;
-
- // Convert and load key
- ASCII2Hex((unsigned char*)ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH);
-
- AES_SetKey((unsigned int*)key);
-
- // Convert and load IV
- ASCII2Hex((unsigned char*)ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH);
-
- AES_SetVector((unsigned int*)IV);
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Initializes the AES peripheral for ECB mode
-//------------------------------------------------------------------------------
-#if defined(ENCRYPTION_ECB)
-void aes_hard_init_ECB(void)
-{
- unsigned char key[16];
-
- TRACE_DEBUG("aes_hard_init_ECB\n\r");
-
- // Activate peripheral clock
-#ifdef AT91C_ID_AES
- PMC_EnablePeripheral( AT91C_ID_AES );
-#elif AT91C_ID_AESTDES
- PMC_EnablePeripheral( AT91C_ID_AESTDES );
-#elif AT91C_ID_TDES
- PMC_EnablePeripheral( AT91C_ID_TDES );
-#else
-#error AES undefined
-#endif
-
- // Load mode
- //AES_Configure(AT91C_AES_CIPHER, AT91C_AES_SMOD_MANUAL, AT91C_AES_OPMOD_ECB);
- AT91C_BASE_AES->AES_MR = AT91C_AES_SMOD_PDC | AT91C_AES_OPMOD_ECB;
-
- // Convert and load key
- ASCII2Hex((unsigned char*)ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH);
-
- AES_SetKey((unsigned int*)key);
-}
-#endif
-#endif // ONLY_ONE_ENCRYPTION
-
-//------------------------------------------------------------------------------
-/// Cleans up the AES peripheral
-//------------------------------------------------------------------------------
-void aes_hard_cleanup(void)
-{
- TRACE_DEBUG("AES/HARD: Cleaning up ...\n\r");
-
- AT91C_BASE_AES->AES_MR = 0;
-
-#ifdef AT91C_ID_AES
- PMC_DisablePeripheral( AT91C_ID_AES );
-#elif AT91C_ID_AESTDES
- PMC_DisablePeripheral( AT91C_ID_AESTDES );
-#elif AT91C_ID_TDES
- PMC_DisablePeripheral( AT91C_ID_TDES );
-#else
-#error AES undefined
-#endif
-
- // Close PDC
- AT91C_BASE_PDC_AES->PDC_PTCR = AT91C_PDC_RXTDIS;
- AT91C_BASE_PDC_AES->PDC_PTCR = AT91C_PDC_TXTDIS;
-
- // Reset all Counter register Next buffer first
- AT91C_BASE_PDC_AES->PDC_TNPR = 0;
- AT91C_BASE_PDC_AES->PDC_TNCR = 0;
- AT91C_BASE_PDC_AES->PDC_RPR = 0;
- AT91C_BASE_PDC_AES->PDC_RCR = 0;
- AT91C_BASE_PDC_AES->PDC_TPR = 0;
- AT91C_BASE_PDC_AES->PDC_TCR = 0;
- AT91C_BASE_PDC_AES->PDC_RPR = 0;
- AT91C_BASE_PDC_AES->PDC_RCR = 0;
-
- TRACE_DEBUG("AES/HARD: Cleanup done.\n\r");
-}
-
-//------------------------------------------------------------------------------
-/// Decrypts a variable-length cipher text
-/// \param pCipherText text to decrypt
-/// \param pPlainText to store plain text
-/// \param length of cipher text (in bytes)
-/// \return: 1 if ok, 0 if error
-//------------------------------------------------------------------------------
-int aes_hard_decrypt(const unsigned char *pCipherText,
- unsigned char *pPlainText,
- unsigned int length)
-{
- TRACE_DEBUG("aes_hard_decrypt\n\r");
-
- // Check parameters
- if ((pCipherText == NULL) || (pPlainText == NULL)) {
- return 0;
- }
-
- // Set source and destination buffers in PDC
- AT91C_BASE_PDC_AES->PDC_TPR = (unsigned int) pCipherText;
- AT91C_BASE_PDC_AES->PDC_RPR = (unsigned int) pPlainText;
-
- AT91C_BASE_PDC_AES->PDC_TCR = length >> 2;
- AT91C_BASE_PDC_AES->PDC_RCR = length >> 2;
-
- // Start decryption and wait
- AT91C_BASE_PDC_AES->PDC_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN;
- while (((AES_GetStatus()) & AT91C_AES_ENDRX) == 0);
-
- return 1;
-}
-
-#endif // defined(USE_ENCRYPTION) && defined(ENCRYPTION_AES_HARD)
-
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/aes_hardware.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/aes_hardware.h
deleted file mode 100644
index 62f38a7f..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/aes_hardware.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-/// \unit
-///
-/// !Purpose
-///
-/// Firmware encryption using AES hardware acceleration
-/// This code is based on the AES reference implementation published by Paulo
-/// Barreto and Vincent Rijmen.
-///
-/// !Usage
-///
-/// -# aes_hard_init: Initialize AES hardware
-/// -# aes_hard_init_CBC: for the CBC mode
-/// -# aes_hard_init_CTR: for the CTR mode
-/// -# aes_hard_init_ECB: for the ECB mode
-/// -# aes_hard_cleanup: Cleans up AES
-/// -# aes_hard_decrypt: Decrypts a variable-length cipher text
-//------------------------------------------------------------------------------
-
-#ifndef BOOTLOADER_AES_HARDWARE_H
-#define BOOTLOADER_AES_HARDWARE_H
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include "config.h"
-
-#if defined(USE_ENCRYPTION) && defined(ENCRYPTION_AES_HARD)
-
-//------------------------------------------------------------------------------
-// Check configuration
-//------------------------------------------------------------------------------
-#if (ENCRYPTION_KEY_LENGTH != 16)
- #error Hardware AES acceleration only supports 128 bits keys.
-#endif
-
-#if (ENCRYPTION_BLOCK_LENGTH != 16)
- #error Hardware AES acceleration only supports 128 bits blocks.
-#endif
-
-#if !defined(ENCRYPTION_ECB) && \
- !defined(ENCRYPTION_CBC) && \
- !defined(ENCRYPTION_CTR)
- #error Only ECB, CBC & CTR modes are supported.
-#endif
-
-//------------------------------------------------------------------------------
-// Definitions
-//------------------------------------------------------------------------------
-#ifdef ONLY_ONE_ENCRYPTION
-#define ENCRYPTION_INIT aes_hard_init
-#define ENCRYPTION_CLEANUP aes_hard_cleanup
-#define ENCRYPTION_DECRYPT aes_hard_decrypt
-#endif
-
-//------------------------------------------------------------------------------
-// Exported functions
-//------------------------------------------------------------------------------
-extern void aes_hard_init(void);
-#ifndef ONLY_ONE_ENCRYPTION
-extern void aes_hard_init_CBC(void);
-extern void aes_hard_init_CTR(void);
-extern void aes_hard_init_ECB(void);
-#endif
-extern void aes_hard_cleanup(void);
-extern int aes_hard_decrypt(const unsigned char *, unsigned char *, unsigned int);
-
-#endif // defined(USE_ENCRYPTION) && defined(ENCRYPTION_AES_HARD)
-#endif // BOOTLOADER_AES_HARDWARE_H
-
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/aes_reference.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/aes_reference.c
deleted file mode 100644
index a94844ab..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/aes_reference.c
+++ /dev/null
@@ -1,801 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-// Firmware encryption using AES reference implementation
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include "aes_reference.h"
-
-#if defined(USE_ENCRYPTION) && defined(ENCRYPTION_AES_REF)
-#include
-#include
-#include
-#include
-#include
-#include
-
-//------------------------------------------------------------------------------
-// Global variables
-//------------------------------------------------------------------------------
-#define word8 static unsigned char
-#define word32 static unsigned int
-
-#include "boxes-ref.dat"
-
-static unsigned char shifts[3][2][4] = {
- {{0,1,2,3}, {0,3,2,1}},
- {{0,1,2,3}, {0,5,4,3}},
- {{0,7,5,5}, {0,1,3,4}}
-};
-
-static unsigned char key[KC][4];
-static unsigned char expandedKey[ROUNDS+1][BC][4];
-static unsigned int T0[256], T1[256], T2[256], T3[256], TF[256];
-
-#if defined(ENCRYPTION_CBC) || defined(ENCRYPTION_CTR)
-static unsigned char IV[BC][4];
-#endif
-
-//------------------------------------------------------------------------------
-// Inline functions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Multiply two elements of GF(2^m) needed for MixColumn and InvMixColumn
-/// \param a first element
-/// \param b second element
-/// \return result of operation
-//------------------------------------------------------------------------------
-static unsigned char mul(unsigned char a, unsigned char b)
-{
- if (a && b) {
- return Alogtable[(Logtable[a] + Logtable[b])%255];
- }
- else {
- return 0;
- }
-}
-
-//------------------------------------------------------------------------------
-/// Returns the minimum between two numbers
-/// \param First number
-/// \param Second number
-/// \return Minimum between the two operands
-//------------------------------------------------------------------------------
-#if defined(ENCRYPTION_CTR)
-static unsigned int min(unsigned int number1, unsigned int number2)
-{
- if (number1 > number2) {
- return number2;
- }
- else {
- return number1;
- }
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// XOR text and round key together
-/// \param Plain text
-/// \param Round key
-//------------------------------------------------------------------------------
-static inline void addRoundKey(unsigned char a[BC][4], const unsigned char rk[BC][4])
-{
- unsigned int i;
-
- for (i=0; i < BC; i++) {
- ((int *) a)[i] ^= ((int *) rk)[i];
- }
-}
-
-//------------------------------------------------------------------------------
-/// Performs the AES key schedule
-/// \param Key to use
-/// \param Buffer to store expanded key schedule
-//------------------------------------------------------------------------------
-static inline void keySchedule(unsigned char k[KC][4], unsigned char W[ROUNDS+1][BC][4])
-{
- int t;
- int rconpointer = 0;
- unsigned int j;
- unsigned char tk[KC][4];
-
- for(j=0; j < KC; j++) {
- ((int *) tk)[j] = ((int *) k)[j];
- }
-
- t = 0;
- /* copy values into round key array */
- for(j=0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) {
- ((int *) W[t / BC])[t%BC] = ((int *) tk)[j];
- }
-
- while (t < (ROUNDS+1)*BC) {
-
- tk[0][0] ^= S[tk[KC-1][1]] ^ rcon[rconpointer++];
- tk[0][1] ^= S[tk[KC-1][2]];
- tk[0][2] ^= S[tk[KC-1][3]];
- tk[0][3] ^= S[tk[KC-1][0]];
-
- if (KC != 8) {
- for(j=1; j < KC; j++) {
- ((int *) tk)[j] ^= ((int *) tk)[j-1];
- }
- }
- else {
- for(j=1; j < KC/2; j++) {
- ((int *) tk)[j] ^= ((int *) tk)[j-1];
- }
- tk[KC/2][0] ^= S[tk[KC/2 - 1][0]];
- tk[KC/2][1] ^= S[tk[KC/2 - 1][1]];
- tk[KC/2][2] ^= S[tk[KC/2 - 1][2]];
- tk[KC/2][3] ^= S[tk[KC/2 - 1][3]];
-
- for(j=KC/2+1; j < KC; j++) {
- ((int *) tk)[j] ^= ((int *) tk)[j-1];
- }
- }
-
- // copy values into round key array
- for(j=0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) {
- ((int *) W[t/BC])[t%BC] = ((int *) tk)[j];
- }
- }
-}
-
-//------------------------------------------------------------------------------
-/// Performs the AES inverse key schedule
-/// \param Key to use
-/// \param Buffer to store expanded key schedule
-//------------------------------------------------------------------------------
-#if defined(ENCRYPTION_ECB) || defined(ENCRYPTION_CBC)
-static inline void invKeySchedule(unsigned char k[KC][4],
- unsigned char W[ROUNDS+1][BC][4])
-{
- unsigned int r;
- unsigned int j;
- unsigned char tmp[4];
-
- // Expand key normally
- keySchedule(k, W);
-
- // Apply invMixColumns to all rounds except first and last one
- for (r=1; r < ROUNDS; r++) {
- for (j=0; j < BC; j++) {
- tmp[0] = mul(0x0E, W[r][j][0]) ^ mul(0x0B, W[r][j][1]) ^
- mul(0x0D, W[r][j][2]) ^ mul(0x09, W[r][j][3]);
- tmp[1] = mul(0x0E, W[r][j][1]) ^ mul(0x0B, W[r][j][2]) ^
- mul(0x0D, W[r][j][3]) ^ mul(0x09, W[r][j][0]);
- tmp[2] = mul(0x0E, W[r][j][2]) ^ mul(0x0B, W[r][j][3]) ^
- mul(0x0D, W[r][j][0]) ^ mul(0x09, W[r][j][1]);
- tmp[3] = mul(0x0E, W[r][j][3]) ^ mul(0x0B, W[r][j][0]) ^
- mul(0x0D, W[r][j][1]) ^ mul(0x09, W[r][j][2]);
- W[r][j][0] = tmp[0];
- W[r][j][1] = tmp[1];
- W[r][j][2] = tmp[2];
- W[r][j][3] = tmp[3];
- }
- }
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Perform the RotBytes operation needed by the AES cipher
-/// \param input to rotate
-/// \return Rotated word
-//------------------------------------------------------------------------------
-static inline unsigned int rotBytes(unsigned int input)
-{
- return ((input << 8) | (input >> 24));
-}
-
-//------------------------------------------------------------------------------
-/// Generates the lookup tables needed for encryption
-/// \param Pointer to t0
-/// \param Pointer to t1
-/// \param Pointer to t2
-/// \param Pointer to t3
-/// \param Pointer to tf
-/// \param Box
-//------------------------------------------------------------------------------
-#if defined(ENCRYPTION_CTR)
-static inline void generateEncryptionLUTs(unsigned int * t0,
- unsigned int * t1,
- unsigned int * t2,
- unsigned int * t3,
- unsigned int * tf,
- unsigned char box[256])
-{
- unsigned int a;
-
- for (a=0; a <= 255; a++) {
- // Calc t0
- t0[a] = (mul(2, box[a])) |
- (box[a] << 8) |
- (box[a] << 16) |
- (mul(3, box[a]) << 24);
-
- // Calc t1, t2, t3
- t1[a] = rotBytes(t0[a]);
- t2[a] = rotBytes(t1[a]);
- t3[a] = rotBytes(t2[a]);
-
- // Calc tf
- tf[a] = box[a] | (box[a] << 8) | (box[a] << 16) | (box[a] << 24);
- }
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Generates the lookup tables needed for decryption
-/// \param Pointer to t0
-/// \param Pointer to t1
-/// \param Pointer to t2
-/// \param Pointer to t3
-/// \param Pointer to tf
-/// \param Box
-//------------------------------------------------------------------------------
-#if defined(ENCRYPTION_ECB) || defined(ENCRYPTION_CBC)
-static inline void generateDecryptionLUTs(unsigned int * t0,
- unsigned int * t1,
- unsigned int * t2,
- unsigned int * t3,
- unsigned int * tf,
- unsigned char box[256])
-{
- unsigned int a;
-
- for (a=0; a <= 255; a++) {
-
- // Calc t0
- t0[a] = (mul(0x0E, box[a])) |
- (mul(0x09, box[a]) << 8) |
- (mul(0x0D, box[a]) << 16) |
- (mul(0x0B, box[a]) << 24);
-
- // Calc t1, t2, t3
- t1[a] = rotBytes(t0[a]);
- t2[a] = rotBytes(t1[a]);
- t3[a] = rotBytes(t2[a]);
-
- // Calc tf
- tf[a] = box[a] | (box[a] << 8) | (box[a] << 16) | (box[a] << 24);
- }
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Copies a block to a buffer
-/// \param Block to copy
-/// \param Buffer to store copy
-//------------------------------------------------------------------------------
-#if defined(ENCRYPTION_CTR)
-static void copyBlock(unsigned char input[BC][4], unsigned char output[BC][4])
-{
- unsigned int j;
-
- for (j=0; j < BC; j++) {
- ((int *) output)[j] = ((int *) input)[j];
- }
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Encrypts a block of plain text using precalculated LUTs
-/// \param Block of plain text to encrypt
-/// \param Expanded key
-/// \param Pointer to t0
-/// \param Pointer to t1
-/// \param Pointer to t2
-/// \param Pointer to t3
-/// \param Pointer to tf
-//------------------------------------------------------------------------------
-#if defined(ENCRYPTION_CTR)
-static inline void encrypt(unsigned char a[BC][4],
- const unsigned char rk[ROUNDS+1][BC][4],
- unsigned int * t0,
- unsigned int * t1,
- unsigned int * t2,
- unsigned int * t3,
- unsigned int * tf)
-{
- unsigned char b[BC][4];
- unsigned int r;
- unsigned int j;
-
- // First key addition
- addRoundKey(a, rk[0]);
-
- // ROUNDS-1 ordinary rounds
- for(r=1; r < ROUNDS; r++) {
- for (j=0; j < BC; j++) {
-
- ((int *) b)[j] = t0[a[j][0]] ^
- t1[a[(j+shifts[SC][0][1])%BC][1]] ^
- t2[a[(j+shifts[SC][0][2])%BC][2]] ^
- t3[a[(j+shifts[SC][0][3])%BC][3]] ^
- ((int *) rk[r])[j];
- }
- if ((++r) == ROUNDS) {
- break;
- }
- for (j=0; j < BC; j++) {
- ((int *) a)[j] = t0[b[j][0]] ^
- t1[b[(j+shifts[SC][0][1])%BC][1]] ^
- t2[b[(j+shifts[SC][0][2])%BC][2]] ^
- t3[b[(j+shifts[SC][0][3])%BC][3]] ^
- ((int *) rk[r])[j];
- }
- }
-
- // Last round (no MixColumns)
- for (j=0; j < BC; j++) {
- ((int *) a)[j] = (t0f[b[j][0]]) ^
- (t1f[b[(j+shifts[SC][0][1])%BC][1]]) ^
- (t2f[b[(j+shifts[SC][0][2])%BC][2]]) ^
- (t3f[b[(j+shifts[SC][0][3])%BC][3]]) ^
- ((int *) rk[ROUNDS])[j];
- }
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Decrypts a block of plain text using precalculated LUTs
-/// \param Block of cipher text to decrypt
-/// \param Expanded key
-/// \param Pointer to t0
-/// \param Pointer to t1
-/// \param Pointer to t2
-/// \param Pointer to t3
-/// \param Pointer to tf
-//------------------------------------------------------------------------------
-#if defined(ENCRYPTION_ECB) || defined(ENCRYPTION_CBC)
-static inline void decrypt(unsigned char a[BC][4],
- const unsigned char rk[ROUNDS+1][BC][4],
- unsigned int * t0,
- unsigned int * t1,
- unsigned int * t2,
- unsigned int * t3,
- unsigned int * tf)
-{
- unsigned char b[BC][4];
- unsigned int r;
- unsigned int j;
-
- // First key addition
- addRoundKey(a, rk[ROUNDS]);
-
- // ROUNDS-1 ordinary rounds
- for(r=ROUNDS-1; r > 0; r--) {
- for (j=0; j < BC; j++) {
- ((int *) b)[j] = t0[a[j][0]] ^
- t1[a[(j+shifts[SC][1][1])%BC][1]] ^
- t2[a[(j+shifts[SC][1][2])%BC][2]] ^
- t3[a[(j+shifts[SC][1][3])%BC][3]] ^
- ((int *) rk[r])[j];
- }
- if ((--r) == 0) {
- break;
- }
- for (j=0; j < BC; j++) {
- ((int *) a)[j] = t0[b[j][0]] ^
- t1[b[(j+shifts[SC][1][1])%BC][1]] ^
- t2[b[(j+shifts[SC][1][2])%BC][2]] ^
- t3[b[(j+shifts[SC][1][3])%BC][3]] ^
- ((int *) rk[r])[j];
- }
- }
- // Last round (no MixColumns)
- for (j=0; j < BC; j++) {
- ((int *) a)[j] = (t0f[b[j][0]]) ^
- (t1f[b[(j+shifts[SC][1][1])%BC][1]]) ^
- (t2f[b[(j+shifts[SC][1][2])%BC][2]]) ^
- (t3f[b[(j+shifts[SC][1][3])%BC][3]]) ^
- ((int *) rk[0])[j];
- }
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Converts an ASCII hexadecimal representation to a raw binary one
-/// \param ASCII value
-/// \param Buffer to store binary value
-/// \param Size of value
-//------------------------------------------------------------------------------
-static void ASCII2RawHex(const unsigned char * ascii,
- unsigned char * binary,
- unsigned int length)
-{
- unsigned char * ptr;
- unsigned int i;
-
- ptr = (unsigned char *) binary;
- for (i=0; i < length; i++, ptr++, ascii++) {
- if (*ascii >= 'A') {
- *ptr = *ascii - 'A' + 10;
- }
- else {
- *ptr = *ascii - '0';
- }
- *ptr <<= 4;
- ascii++;
- if (*ascii >= 'A') {
- *ptr += *ascii - 'A' + 10;
- }
- else {
- *ptr += *ascii - '0';
- }
- }
-}
-
-//------------------------------------------------------------------------------
-/// Decrypts a cipher text using ECB mode
-/// \param Cipher text to decrypt
-/// \param Buffer to store plain text
-/// \param Length of cipher text
-/// \param Expanded key to use
-/// \return 0 if successful, 0 otherwise
-//------------------------------------------------------------------------------
-#if defined(ENCRYPTION_ECB)
-static unsigned int ecb_decrypt(const unsigned char * cipherText,
- unsigned char * plainText,
- unsigned int length,
- unsigned char expandedKey[ROUNDS+1][BC][4])
-{
- unsigned char block[BC][4];
- unsigned int i;
- unsigned int l;
-
- // Check input parameters
- if ((cipherText == NULL) || (plainText == NULL) || (expandedKey == NULL)) {
- TRACE_DEBUG("AES/REF: NULL parameter(s).\n\r");
- return 0;
- }
- if (length%ENCRYPTION_BLOCK_LENGTH != 0) {
- TRACE_DEBUG("AES/REF: Data length must be a multiple of the cipher block size.\n\r");
- return 0;
- }
- // ECB decryption
- for (l=0; l < length;) {
- // Copy cipher text block, decrypt it and copy result
- for (i=0; i < ENCRYPTION_BLOCK_LENGTH; i++) {
- ((char *) block)[i] = cipherText[l+i];
- }
- decrypt(block, expandedKey, T0, T1, T2, T3, TF);
- for (i=0; i < ENCRYPTION_BLOCK_LENGTH; i++) {
- plainText[l+i] = ((char *) block)[i];
- }
- l += ENCRYPTION_BLOCK_LENGTH;
- }
-
- return 1;
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Decrypts a cipher text using CBC mode
-/// \param Cipher text to decrypt
-/// \param Buffer to store plain text
-/// \param Length of cipher text (in bytes)
-/// \param Expanded key to use
-/// \param Initialization vector to use
-/// \return 1 if successful, 0 otherwise */
-//------------------------------------------------------------------------------
-#if defined(ENCRYPTION_CBC)
-static unsigned int cbc_decrypt(const unsigned char * cipherText,
- unsigned char * plainText,
- unsigned int length,
- const unsigned char expandedKey[ROUNDS+1][BC][4],
- unsigned char IV[BC][4])
-{
- unsigned char block[BC][4];
- unsigned int i;
- unsigned int l;
-
- // Check input parameters
- if ((cipherText == NULL) || (plainText == NULL)) {
- TRACE_DEBUG("AES/REF: NULL parameter(s).\n\r");
- return 0;
- }
- if (length%ENCRYPTION_BLOCK_LENGTH != 0) {
- TRACE_DEBUG("AES/REF: Cipher text length must be a multiple of the cipher block length.\n\r");
- return 0;
- }
- // Decrypt data
- for (l=0; l < length;) {
- // Copy and decrypt a block of cipher text
- for (i=0; i < BC; i++) {
- ((int *) block)[i] = ((int *) &cipherText[l])[i];
- }
- decrypt(block, expandedKey, T0, T1, T2, T3, TF);
- // Xor decrypted text & IV, copy new IV
- for (i=0; i < BC; i++) {
- unsigned int tmp = ((int *) block)[i] ^ ((int *) IV)[i];
- ((int *) IV)[i] = ((int *) &cipherText[l])[i];
- ((int *) &plainText[l])[i] = tmp;
- }
-
- // Loop progression
- l += ENCRYPTION_BLOCK_LENGTH;
- }
- return 1;
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Decrypts a cipher text using CTR mode
-/// \param Cipher text to decrypt
-/// \param Buffer to store plain text
-/// \param Length of cipher text
-/// \param Expanded key to use
-/// \param Initialization vector to use
-/// \return 1 if successful, 0 otherwise
-//------------------------------------------------------------------------------
-#if defined(ENCRYPTION_CTR)
-static unsigned int ctr_decrypt(const unsigned char * cipherText,
- unsigned char * plainText,
- unsigned int length,
- const unsigned char expandedKey[ROUNDS+1][BC][4],
- unsigned char IV[BC][4])
-{
- unsigned char block[BC][4];
- unsigned int bytes;
- unsigned int i;
- unsigned int l;
- int k;
-
- // Check input parameters
- if ((cipherText == NULL) || (plainText == NULL)) {
- return 0;
- }
- for (l=0; l < length;) {
- // Copy counter and encrypt it
- copyBlock(IV, block);
- encrypt(block, expandedKey, T0, T1, T2, T3, TF);
-
- // XOR current plain text block with encrypted counter
- bytes = min(length - l, ENCRYPTION_BLOCK_LENGTH);
-
- for (i=0; i < bytes; i++) {
- plainText[l+i] = cipherText[l+i] ^ ((char *) block)[i];
- }
- // Increment counter (big-endian) and number of encrypted bytes
- for (k=ENCRYPTION_BLOCK_LENGTH-1; k >= 0; k--) {
- if (++((char *) IV)[k] != 0) {
- break;
- }
- }
- l += bytes;
- }
- return 1;
-}
-#endif
-
-//------------------------------------------------------------------------------
-// Functions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Initializes the AES algorithm
-//------------------------------------------------------------------------------
-#ifdef ONLY_ONE_ENCRYPTION
-void aes_ref_init(void)
-{
- TRACE_DEBUG("AES/REF: Initializing ...\n\r");
-
- ASCII2RawHex((unsigned char*)ENCRYPTION_KEY, (unsigned char*)key, ENCRYPTION_KEY_LENGTH);
-
-#if defined(ENCRYPTION_ECB) || defined(ENCRYPTION_CBC)
-
- // Initialize key schedule
- invKeySchedule(key, expandedKey);
-
- // Generate lookup tables
- generateDecryptionLUTs(T0, T1, T2, T3, TF, Si);
-
-#elif defined(ENCRYPTION_CTR)
-
- // Initialize key schedule
- keySchedule(key, expandedKey);
-
- // Generate lookup tables
- generateEncryptionLUTs(T0, T1, T2, T3, TF, S);
-#endif
-
-#if defined(ENCRYPTION_CBC) || defined(ENCRYPTION_CTR)
- // Initialize counter
- ASCII2RawHex((unsigned char*)ENCRYPTION_IV, (unsigned char*)IV, ENCRYPTION_BLOCK_LENGTH);
-#endif
-
- TRACE_DEBUG("AES/REF: Initialization done.\n\r");
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Initializes the AES algorithm mode CBC
-//------------------------------------------------------------------------------
-#ifndef ONLY_ONE_ENCRYPTION
-#if defined(ENCRYPTION_CBC)
-void aes_ref_init_CBC(void)
-{
- TRACE_DEBUG("aes_ref_init_CBC\n\r");
-
- ASCII2RawHex((unsigned char*)ENCRYPTION_KEY, (unsigned char*)key, ENCRYPTION_KEY_LENGTH);
-
- // Initialize key schedule
- invKeySchedule(key, expandedKey);
-
- // Generate lookup tables
- generateDecryptionLUTs(T0, T1, T2, T3, TF, Si);
-
- // Initialize counter
- ASCII2RawHex((unsigned char*)ENCRYPTION_IV, (unsigned char*)IV, ENCRYPTION_BLOCK_LENGTH);
-
- TRACE_DEBUG("AES/REF: Initialization done.\n\r");
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Initializes the AES algorithm mode ECB
-//------------------------------------------------------------------------------
-#if defined(ENCRYPTION_ECB)
-void aes_ref_init_ECB(void)
-{
- TRACE_DEBUG("aes_ref_init_ECB\n\r");
-
- ASCII2RawHex((unsigned char*)ENCRYPTION_KEY, (unsigned char*)key, ENCRYPTION_KEY_LENGTH);
-
- // Initialize key schedule
- invKeySchedule(key, expandedKey);
-
- // Generate lookup tables
- generateDecryptionLUTs(T0, T1, T2, T3, TF, Si);
-
- TRACE_DEBUG("AES/REF: Initialization done.\n\r");
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Initializes the AES algorithm mode CTR
-//------------------------------------------------------------------------------
-#if defined(ENCRYPTION_CTR)
-void aes_ref_init_CTR(void)
-{
- TRACE_DEBUG("aes_ref_init_CTR\n\r");
-
- ASCII2RawHex((unsigned char*)ENCRYPTION_KEY, (unsigned char*)key, ENCRYPTION_KEY_LENGTH);
-
- // Initialize key schedule
- keySchedule(key, expandedKey);
-
- // Generate lookup tables
- generateEncryptionLUTs(T0, T1, T2, T3, TF, S);
-
- // Initialize counter
- ASCII2RawHex((unsigned char*)ENCRYPTION_IV, (unsigned char*)IV, ENCRYPTION_BLOCK_LENGTH);
-
- TRACE_DEBUG("AES/REF: Initialization done.\n\r");
-}
-#endif
-#endif // ONLY_ONE_ENCRYPTION
-
-//------------------------------------------------------------------------------
-/// Cleanup the AES algorithm
-//------------------------------------------------------------------------------
-void aes_ref_cleanup(void)
-{
- TRACE_DEBUG("AES/REF: Cleaning up ...\n\r");
- TRACE_DEBUG("AES/REF: Cleanup done.\n\r");
-}
-
-//------------------------------------------------------------------------------
-/// Decrypt a cipher text of variable length
-/// \param Cipher text to decrypt
-/// \param Buffer to store plain text
-/// \param Length of cipher text (in bytes)
-/// \return 1 if decryption was successful, 0 otherwise.
-//------------------------------------------------------------------------------
-#ifdef ONLY_ONE_ENCRYPTION
-int aes_ref_decrypt(const unsigned char * cipherText,
- unsigned char * plainText,
- unsigned int length)
-{
- TRACE_DEBUG("aes_ref_decrypt\n\r");
-#if defined(ENCRYPTION_ECB)
- return ecb_decrypt(cipherText, plainText, length, expandedKey);
-#elif defined(ENCRYPTION_CBC)
- return cbc_decrypt(cipherText, plainText, length, expandedKey, IV);;
-#elif defined(ENCRYPTION_CTR)
- return ctr_decrypt(cipherText, plainText, length, expandedKey, IV);
-#endif
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Decrypt a cipher text of variable length, mode CBC
-/// \param Cipher text to decrypt
-/// \param Buffer to store plain text
-/// \param Length of cipher text (in bytes)
-/// \return 1 if decryption was successful, 0 otherwise.
-//------------------------------------------------------------------------------
-#ifndef ONLY_ONE_ENCRYPTION
-#if defined(ENCRYPTION_CBC)
-int aes_ref_decrypt_CBC(const unsigned char * cipherText,
- unsigned char * plainText,
- unsigned int length)
-{
- TRACE_DEBUG("aes_ref_decrypt_CBC\n\r");
- return cbc_decrypt(cipherText, plainText, length, expandedKey, IV);;
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Decrypt a cipher text of variable length, mode ECB
-/// \param Cipher text to decrypt
-/// \param Buffer to store plain text
-/// \param Length of cipher text (in bytes)
-/// \return 1 if decryption was successful, 0 otherwise.
-//------------------------------------------------------------------------------
-#if defined(ENCRYPTION_ECB)
-int aes_ref_decrypt_ECB(const unsigned char * cipherText,
- unsigned char * plainText,
- unsigned int length)
-{
- TRACE_DEBUG("aes_ref_decrypt_ECB\n\r");
- return ecb_decrypt(cipherText, plainText, length, expandedKey);
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Decrypt a cipher text of variable length, mode CTR
-/// \param Cipher text to decrypt
-/// \param Buffer to store plain text
-/// \param Length of cipher text (in bytes)
-/// \return 1 if decryption was successful, 0 otherwise.
-//------------------------------------------------------------------------------
-#if defined(ENCRYPTION_CTR)
-int aes_ref_decrypt_CTR(const unsigned char * cipherText,
- unsigned char * plainText,
- unsigned int length)
-{
- TRACE_DEBUG("aes_ref_decrypt_CTR\n\r");
- return ctr_decrypt(cipherText, plainText, length, expandedKey, IV);
-}
-#endif
-
-#endif // ONLY_ONE_ENCRYPTION
-
-#endif // defined(USE_ENCRYPTION) && defined(ENCRYPTION_AES_REF)
-
-
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/aes_reference.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/aes_reference.h
deleted file mode 100644
index a47907bd..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/aes_reference.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-/// \unit
-///
-/// !Purpose
-///
-/// Firmware encryption using AES reference implementation
-///
-/// !Usage
-///
-/// -# aes_ref_init: Initialize AES hardware
-/// -# aes_ref_init_CBC: for the CBC mode
-/// -# aes_ref_init_ECB: for the CTR mode
-/// -# aes_ref_init_CTR: for the ECB mode
-/// -# aes_ref_cleanup: Cleans up AES
-/// -# aes_ref_decrypt: Decrypts a variable-length cipher text
-/// -# aes_ref_decrypt_CBC: for CBC mode
-/// -# aes_ref_decrypt_ECB: for ECB mode
-/// -# aes_ref_decrypt_CTR: for CTR mode
-//------------------------------------------------------------------------------
-
-#ifndef BOOTLOADER_AES_REFERENCE_H
-#define BOOTLOADER_AES_REFERENCE_H
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include "config.h"
-
-
-#if defined(USE_ENCRYPTION) && defined(ENCRYPTION_AES_REF)
-
-//------------------------------------------------------------------------------
-// Check configuration
-//------------------------------------------------------------------------------
-
-// Supported modes
-#if !defined(ENCRYPTION_ECB) && \
- !defined(ENCRYPTION_CBC) && \
- !defined(ENCRYPTION_CTR)
- #error No other mode than ECB, CBC & CTR are supported.
-#endif
-
-// Supported key length
-#if (ENCRYPTION_KEY_LENGTH != 16) && \
- (ENCRYPTION_KEY_LENGTH != 24) && \
- (ENCRYPTION_KEY_LENGTH != 32)
- #error Only key lengths of 128, 192 or 256 bits are supported.
-#endif
-
-// Supported block length
-#if (ENCRYPTION_BLOCK_LENGTH != 16)
- #error Only block length of 128 bits is supported.
-#endif
-
-//------------------------------------------------------------------------------
-// Definitions
-//------------------------------------------------------------------------------
-#define BC (ENCRYPTION_BLOCK_LENGTH / 4)
-#define SC ((BC - 4) >> 1)
-#define KC (ENCRYPTION_KEY_LENGTH / 4)
-#define t0f 0x000000FF & tf
-#define t1f 0x0000FF00 & tf
-#define t2f 0x00FF0000 & tf
-#define t3f 0xFF000000 & tf
-
-#if (KC >= BC)
- #define ROUNDS (KC + 6)
-#else
- #define ROUNDS (BC + 6)
-#endif
-
-#ifdef ONLY_ONE_ENCRYPTION
-#define ENCRYPTION_INIT aes_ref_init
-#define ENCRYPTION_CLEANUP aes_ref_cleanup
-#define ENCRYPTION_DECRYPT aes_ref_decrypt
-#endif
-
-//------------------------------------------------------------------------------
-// Prototypes
-//------------------------------------------------------------------------------
-extern void aes_ref_init(void);
-extern void aes_ref_init_CBC(void);
-extern void aes_ref_init_ECB(void);
-extern void aes_ref_init_CTR(void);
-extern void aes_ref_cleanup(void);
-extern int aes_ref_decrypt(const unsigned char * cipherText,
- unsigned char * plainText,
- unsigned int length);
-extern int aes_ref_decrypt_CBC(const unsigned char * cipherText,
- unsigned char * plainText,
- unsigned int length);
-extern int aes_ref_decrypt_ECB(const unsigned char * cipherText,
- unsigned char * plainText,
- unsigned int length);
-extern int aes_ref_decrypt_CTR(const unsigned char * cipherText,
- unsigned char * plainText,
- unsigned int length);
-
-#endif // defined(USE_ENCRYPTION) && defined(ENCRYPTION_AES_REF)
-
-#endif // BOOTLOADER_AES_REFERENCE_H
-
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/encryption.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/encryption.h
deleted file mode 100644
index 8b285009..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/encryption.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-/// \unit
-///
-/// !Purpose
-///
-/// Firmware encryption
-///
-/// !Usage
-///
-/// This file must include the header of every encryption module implemented for
-/// the bootloader. It is also responsible for defining mock functions if no
-/// encryption module is selected, as well as checking that parameters are
-/// correctly set.
-//
-/// An encryption module must define the following functions:
-/// -# void encryption_init(void);
-/// -# void encryption_cleanup(void);
-/// -# int encryption_decrypt(const unsigned char *, unsigned char *, unsigned int)
-//------------------------------------------------------------------------------
-
-#ifndef BOOTLOADER_ENCRYPTION_H
-#define BOOTLOADER_ENCRYPTION_H
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include "config.h"
-
-
-//------------------------------------------------------------------------------
-// Check configuration
-//------------------------------------------------------------------------------
-#ifdef ONLY_ONE_ENCRYPTION
-#if !defined(ENCRYPTION_INIT) && !defined(USE_ENCRYPTION)
- #define ENCRYPTION_INIT();
- #define ENCRYPTION_CLEANUP();
- #define ENCRYPTION_DECRYPT(...) 1
-
-#elif !defined(ENCRYPTION_INIT) && defined(USE_ENCRYPTION)
- #error USE_ENCRYPTION defined but no encryption method selected.
-
-#elif !defined(ENCRYPTION_AES_LTC) && \
- !defined(ENCRYPTION_AES_REF) && \
- !defined(ENCRYPTION_AES_HARD) && \
- !defined(ENCRYPTION_3DES_LTC) && \
- !defined(ENCRYPTION_3DES_HARD)
- #error No algorithm selected.
-
-#elif !defined(ENCRYPTION_ECB) && \
- !defined(ENCRYPTION_CBC) && \
- !defined(ENCRYPTION_CTR)
- #error No encryption mode selected.
-
-#elif !defined(ENCRYPTION_KEY)
- #error No key defined.
-
-#elif !defined(ENCRYPTION_KEY_LENGTH)
- #error No key length selected.
-
-#elif !defined(ENCRYPTION_IV)
- #error No initialization vector defined.
-
-#elif !defined(ENCRYPTION_BLOCK_LENGTH)
- #error No block length selected.
-
-#endif
-#endif // ONLY_ONE_ENCRYPTION
-#endif // BOOTLOADER_ENCRYPTION_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/libtomcrypt.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/libtomcrypt.c
deleted file mode 100644
index c21b20c9..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/libtomcrypt.c
+++ /dev/null
@@ -1,445 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-// Function: Firmware encryption using libTomCrypt
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include "libtomcrypt.h"
-#include
-#include
-#include "config.h"
-
-#if defined(USE_ENCRYPTION) && (defined(ENCRYPTION_AES_LTC) || defined(ENCRYPTION_3DES_LTC))
-#include
-#include
-#include
-#include
-#include
-
-//------------------------------------------------------------------------------
-// Global variables
-//------------------------------------------------------------------------------
-
-#if defined(ENCRYPTION_ECB)
- symmetric_ECB sECB;
-#endif
-#if defined(ENCRYPTION_CBC)
- symmetric_CBC sCBC;
-#endif
-#if defined(ENCRYPTION_CTR)
- symmetric_CTR sCTR;
-#endif
-
-//------------------------------------------------------------------------------
-// Inline functions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Converts an ASCII string to an hexadecimal value
-/// \param ASCII string to convert
-/// \param Buffer to store converted value
-/// \param Length of buffer
-//------------------------------------------------------------------------------
-static inline void ASCII2Hex(const char * ascii, unsigned char * binary, unsigned int length)
-{
- unsigned int i;
-
- for (i=0; i < length; i++) {
- if (ascii[i*2] >= 'A') {
- binary[i] = ascii[i*2] - 'A' + 10;
- }
- else {
- binary[i] = ascii[i*2] - '0';
- }
- binary[i] <<= 4;
- if (ascii[i*2+1] >= 'A') {
- binary[i] += ascii[i*2+1] - 'A' + 10;
- }
- else {
- binary[i] += ascii[i*2+1] - '0';
- }
- }
-}
-
-//------------------------------------------------------------------------------
-// Functions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Initializes the decryption process
-//------------------------------------------------------------------------------
-#ifdef ONLY_ONE_ENCRYPTION
-void ltc_init(void)
-{
- int cipherID;
- unsigned char key[ENCRYPTION_KEY_LENGTH];
-
-#if defined(ENCRYPTION_CTR) || defined(ENCRYPTION_CBC)
- unsigned char IV[ENCRYPTION_BLOCK_LENGTH];
-#endif
-
- TRACE_DEBUG("LTC: Initializing ...\n\r");
-
- // Register cipher
- register_cipher(&CIPHER_DESC);
- cipherID = find_cipher(CIPHER_NAME);
-
- // Load key
- ASCII2Hex(ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH);
-
-#if defined(ENCRYPTION_CTR) || defined(ENCRYPTION_CBC)
- // Load IV
- ASCII2Hex(ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH);
-#endif
-
- // Start decryption mode
-#if defined(ENCRYPTION_ECB)
- ecb_start(cipherID, key, ENCRYPTION_KEY_LENGTH, 0, &sECB);
-#elif defined(ENCRYPTION_CBC)
- cbc_start(cipherID, IV, key, ENCRYPTION_KEY_LENGTH, 0, &sCBC);
-#elif defined(ENCRYPTION_CTR)
- ctr_start(cipherID, IV, key, ENCRYPTION_KEY_LENGTH, 0, CTR_COUNTER_BIG_ENDIAN, &sCTR);
-#endif
-
- TRACE_DEBUG("LTC: Initialization done.\n\r");
-}
-#endif // ONLY_ONE_ENCRYPTION
-
-//------------------------------------------------------------------------------
-/// Initializes the decryption process for AES, mode CBC
-//------------------------------------------------------------------------------
-#ifndef ONLY_ONE_ENCRYPTION
-#if defined(ENCRYPTION_CBC)
-void ltc_init_AES_CBC(void)
-{
- int cipherID;
- unsigned char key[ENCRYPTION_KEY_LENGTH];
- unsigned char IV[ENCRYPTION_BLOCK_LENGTH];
-
- TRACE_DEBUG("LTC: Initializing CBC...\n\r");
-
- // Register cipher
- register_cipher(&rijndael_desc);
- cipherID = find_cipher("rijndael");
-
- // Load key
- ASCII2Hex(ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH);
-
- // Load IV
- ASCII2Hex(ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH);
-
- // Start decryption mode
- cbc_start(cipherID, IV, key, ENCRYPTION_KEY_LENGTH, 0, &sCBC);
-
- TRACE_DEBUG("LTC: Initialization done.\n\r");
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Initializes the decryption process for AES, mode CTR
-//------------------------------------------------------------------------------
-#if defined(ENCRYPTION_CTR)
-void ltc_init_AES_CTR(void)
-{
- int cipherID;
- unsigned char key[ENCRYPTION_KEY_LENGTH];
- unsigned char IV[ENCRYPTION_BLOCK_LENGTH];
-
- TRACE_DEBUG("LTC: Initializing CTR...\n\r");
-
- // Register cipher
- register_cipher(&rijndael_desc);
- cipherID = find_cipher("rijndael");
-
- // Load key
- ASCII2Hex(ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH);
-
- // Load IV
- ASCII2Hex(ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH);
-
- // Start decryption mode
- ctr_start(cipherID, IV, key, ENCRYPTION_KEY_LENGTH, 0, CTR_COUNTER_BIG_ENDIAN, &sCTR);
-
- TRACE_DEBUG("LTC: Initialization done.\n\r");
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Initializes the decryption process for AES, mode ECB
-//------------------------------------------------------------------------------
-#if defined(ENCRYPTION_ECB)
-void ltc_init_AES_ECB(void)
-{
- int cipherID;
- unsigned char key[ENCRYPTION_KEY_LENGTH];
-
- TRACE_DEBUG("LTC: Initializing ECB...\n\r");
-
- // Register cipher
- register_cipher(&rijndael_desc);
- cipherID = find_cipher("rijndael");
-
- // Load key
- ASCII2Hex(ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH);
-
- // Start decryption mode
- ecb_start(cipherID, key, ENCRYPTION_KEY_LENGTH, 0, &sECB);
-
- TRACE_DEBUG("LTC: Initialization done.\n\r");
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Initializes the decryption process for 3DES, mode CBC
-//------------------------------------------------------------------------------
-#if defined(ENCRYPTION_CBC)
-void ltc_init_3DES_CBC(void)
-{
- int cipherID;
- unsigned char key[ENCRYPTION_KEY_LENGTH];
- unsigned char IV[ENCRYPTION_BLOCK_LENGTH];
-
- TRACE_DEBUG("LTC: Initializing CBC...\n\r");
-
- // Register cipher
- register_cipher(&des3_desc);
- cipherID = find_cipher("3des");
-
- // Load key
- ASCII2Hex(ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH);
-
- // Load IV
- ASCII2Hex(ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH);
-
- // Start decryption mode
- cbc_start(cipherID, IV, key, ENCRYPTION_KEY_LENGTH, 0, &sCBC);
-
- TRACE_DEBUG("LTC: Initialization done.\n\r");
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Initializes the decryption process for 3DES, mode CTR
-//------------------------------------------------------------------------------
-#if defined(ENCRYPTION_CTR)
-void ltc_init_3DES_CTR(void)
-{
- int cipherID;
- unsigned char key[ENCRYPTION_KEY_LENGTH];
- unsigned char IV[ENCRYPTION_BLOCK_LENGTH];
-
- TRACE_DEBUG("LTC: Initializing CTR...\n\r");
-
- // Register cipher
- register_cipher(&des3_desc);
- cipherID = find_cipher("3des");
-
- // Load key
- ASCII2Hex(ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH);
-
- // Load IV
- ASCII2Hex(ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH);
-
- // Start decryption mode
- ctr_start(cipherID, IV, key, ENCRYPTION_KEY_LENGTH, 0, CTR_COUNTER_BIG_ENDIAN, &sCTR);
-
- TRACE_DEBUG("LTC: Initialization done.\n\r");
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Initializes the decryption process for 3DES, mode ECB
-//------------------------------------------------------------------------------
-#if defined(ENCRYPTION_ECB)
-void ltc_init_3DES_ECB(void)
-{
- int cipherID;
- unsigned char key[ENCRYPTION_KEY_LENGTH];
-
- TRACE_DEBUG("LTC: Initializing ECB...\n\r");
-
- // Register cipher
- register_cipher(&des3_desc);
- cipherID = find_cipher("3des");
-
- // Load key
- ASCII2Hex(ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH);
-
- // Start decryption mode
- ecb_start(cipherID, key, ENCRYPTION_KEY_LENGTH, 0, &sECB);
-
- TRACE_DEBUG("LTC: Initialization done.\n\r");
-}
-#endif
-#endif // ONLY_ONE_ENCRYPTION
-
-
-//------------------------------------------------------------------------------
-/// Terminates the decryption process
-//------------------------------------------------------------------------------
-#ifdef ONLY_ONE_ENCRYPTION
-void ltc_cleanup(void)
-{
- TRACE_DEBUG("LTC: Cleaning up ...\n\r");
-
-#if defined(ENCRYPTION_ECB)
- ecb_done(&sECB);
-#elif defined(ENCRYPTION_CBC)
- cbc_done(&sCBC);
-#elif defined(ENCRYPTION_CTR)
- ctr_done(&sCTR);
-#endif
-
- TRACE_DEBUG("LTC: Cleanup done.\n\r");
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Terminates the decryption process for mode CBC
-//------------------------------------------------------------------------------
-#ifndef ONLY_ONE_ENCRYPTION
-#if defined(ENCRYPTION_CBC)
-void ltc_cleanup_CBC(void)
-{
- TRACE_DEBUG("LTC: Cleaning up CBC...\n\r");
- cbc_done(&sCBC);
- TRACE_DEBUG("LTC: Cleanup done.\n\r");
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Terminates the decryption process for mode CTR
-//------------------------------------------------------------------------------
-#if defined(ENCRYPTION_CTR)
-void ltc_cleanup_CTR(void)
-{
- TRACE_DEBUG("LTC: Cleaning up CTR...\n\r");
- ctr_done(&sCTR);
- TRACE_DEBUG("LTC: Cleanup done.\n\r");
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Terminates the decryption process for mode ECB
-//------------------------------------------------------------------------------
-#if defined(ENCRYPTION_ECB)
-void ltc_cleanup_ECB(void)
-{
- TRACE_DEBUG("LTC: Cleaning up ECB...\n\r");
- ecb_done(&sECB);
- TRACE_DEBUG("LTC: Cleanup done.\n\r");
-}
-#endif
-#endif // ONLY_ONE_ENCRYPTION
-
-//------------------------------------------------------------------------------
-/// Decrypts a block of data
-/// \param Data to decrypt
-/// \param Buffer to store decrypted data
-/// \param Length of data
-/// \return 1 if successful, 0 otherwise.
-//------------------------------------------------------------------------------
-#ifdef ONLY_ONE_ENCRYPTION
-int ltc_decrypt(const unsigned char * cipherText, unsigned char * plainText, unsigned int length)
-{
-#if defined(ENCRYPTION_ECB)
- if (ecb_decrypt(cipherText, plainText, length, &sECB) != CRYPT_OK) {
-#elif defined(ENCRYPTION_CBC)
- if (cbc_decrypt(cipherText, plainText, length, &sCBC) != CRYPT_OK) {
-#elif defined(ENCRYPTION_CTR)
- if (ctr_decrypt(cipherText, plainText, length, &sCTR) != CRYPT_OK) {
-#endif
- return 0;
- }
- else {
- return 1;
- }
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Decrypts a block of data in CBC mode
-/// \param Data to decrypt
-/// \param Buffer to store decrypted data
-/// \param Length of data
-/// \return 1 if successful, 0 otherwise.
-//------------------------------------------------------------------------------
-#ifndef ONLY_ONE_ENCRYPTION
-int ltc_decrypt_CBC(const unsigned char * cipherText, unsigned char * plainText, unsigned int length)
-{
- if (cbc_decrypt(cipherText, plainText, length, &sCBC) != CRYPT_OK) {
- return 0;
- }
- else {
- return 1;
- }
-}
-
-//------------------------------------------------------------------------------
-/// Decrypts a block of data in CTR mode
-/// \param Data to decrypt
-/// \param Buffer to store decrypted data
-/// \param Length of data
-/// \return 1 if successful, 0 otherwise.
-//------------------------------------------------------------------------------
-int ltc_decrypt_CTR(const unsigned char * cipherText, unsigned char * plainText, unsigned int length)
-{
- if (ctr_decrypt(cipherText, plainText, length, &sCTR) != CRYPT_OK) {
- return 0;
- }
- else {
- return 1;
- }
-}
-
-//------------------------------------------------------------------------------
-/// Decrypts a block of data in ECB mode
-/// \param Data to decrypt
-/// \param Buffer to store decrypted data
-/// \param Length of data
-/// \return 1 if successful, 0 otherwise.
-//------------------------------------------------------------------------------
-int ltc_decrypt_ECB(const unsigned char * cipherText, unsigned char * plainText, unsigned int length)
-{
- if (ecb_decrypt(cipherText, plainText, length, &sECB) != CRYPT_OK) {
- return 0;
- }
- else {
- return 1;
- }
-}
-#endif // ONLY_ONE_ENCRYPTION
-
-#endif // defined(USE_ENCRYPTION) && (defined(ENCRYPTION_AES_LTC) || defined(ENCRYPTION_3DES_LTC))
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/libtomcrypt.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/libtomcrypt.h
deleted file mode 100644
index 317b79f2..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/libtomcrypt.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-/// \unit
-///
-/// !Purpose
-///
-/// Firmware encryption using libTomCrypt
-///
-/// !Usage
-///
-/// -# ltc_init: Initialize LibTomCrypt
-/// -# ltc_init_AES_CBC
-/// -# ltc_init_AES_CTR
-/// -# ltc_init_AES_ECB
-/// -# ltc_init_3DES_CBC
-/// -# ltc_init_3DES_CTR
-/// -# ltc_init_3DES_ECB
-/// -# ltc_cleanup
-/// -# ltc_cleanup_CBC
-/// -# ltc_cleanup_CTR
-/// -# ltc_cleanup_ECB
-/// -# ltc_decrypt
-/// -# ltc_decrypt_CBC
-/// -# ltc_decrypt_CTR
-/// -# ltc_decrypt_ECB
-//------------------------------------------------------------------------------
-
-#ifndef BOOTLOADER_LIBTOMCRYPT_H
-#define BOOTLOADER_LIBTOMCRYPT_H
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include "config.h"
-
-#if defined(USE_ENCRYPTION) && (defined(ENCRYPTION_AES_LTC) || defined(ENCRYPTION_3DES_LTC))
-
-//------------------------------------------------------------------------------
-// Check configuration
-//------------------------------------------------------------------------------
-
-// Supported modes
-#if !defined(ENCRYPTION_CTR) && \
- !defined(ENCRYPTION_CBC) && \
- !defined(ENCRYPTION_ECB)
- #error No other mode than ECB, CBC & CTR are supported.
-#endif
-
-// Supported key length
-#if defined(ENCRYPTION_AES_LTC)
- #if (ENCRYPTION_KEY_LENGTH != 16) && \
- (ENCRYPTION_KEY_LENGTH != 24) && \
- (ENCRYPTION_KEY_LENGTH != 32)
- #error Only a key length of 128, 192 or 256 bits are supported with AES.
- #endif
-#elif defined(ENCRYPTION_3DES_LTC)
- #if (ENCRYPTION_KEY_LENGTH != 16) && \
- (ENCRYPTION_KEY_LENGTH != 24)
- #error Only a key length of 128 or 192 bits are supported with Triple-DES.
- #endif
-#endif
-
-// Supported block length
-#if defined(ENCRYPTION_AES_LTC)
- #if (ENCRYPTION_BLOCK_LENGTH != 16)
- #error Only a block length of 128 bits is supported with AES.
- #endif
-#elif defined(ENCRYPTION_3DES_LTC)
- #if (ENCRYPTION_BLOCK_LENGTH != 8)
- #error Only a block length of 64 bits is supported with Triple-DES.
- #endif
-#endif
-
-//------------------------------------------------------------------------------
-// Definitions
-//------------------------------------------------------------------------------
-
-// Functions
-#ifdef ONLY_ONE_ENCRYPTION
-#define ENCRYPTION_INIT ltc_init
-#define ENCRYPTION_CLEANUP ltc_cleanup
-#define ENCRYPTION_DECRYPT ltc_decrypt
-
-#if defined(ENCRYPTION_AES_LTC)
- #define CIPHER_NAME "rijndael"
- #define CIPHER_DESC rijndael_desc
-#elif defined(ENCRYPTION_3DES_LTC)
- #define CIPHER_NAME "3des"
- #define CIPHER_DESC des3_desc
-#endif
-#endif
-
-//------------------------------------------------------------------------------
-// Prototypes
-//------------------------------------------------------------------------------
-
-#ifdef ONLY_ONE_ENCRYPTION
-extern void ltc_init(void);
-#endif
-extern void ltc_init_AES_CBC(void);
-extern void ltc_init_AES_CTR(void);
-extern void ltc_init_AES_ECB(void);
-extern void ltc_init_3DES_CBC(void);
-extern void ltc_init_3DES_CTR(void);
-extern void ltc_init_3DES_ECB(void);
-
-extern void ltc_cleanup(void);
-extern void ltc_cleanup_CBC(void);
-extern void ltc_cleanup_CTR(void);
-extern void ltc_cleanup_ECB(void);
-
-extern int ltc_decrypt(const unsigned char * cipherText, unsigned char * plainText, unsigned int length);
-extern int ltc_decrypt_CBC(const unsigned char * cipherText, unsigned char * plainText, unsigned int length);
-extern int ltc_decrypt_CTR(const unsigned char * cipherText, unsigned char * plainText, unsigned int length);
-extern int ltc_decrypt_ECB(const unsigned char * cipherText, unsigned char * plainText, unsigned int length);
-
-#endif // defined(USE_ENCRYPTION) && (defined(ENCRYPTION_AES_LTC) || defined(ENCRYPTION_3DES_LTC))
-#endif // BOOTLOADER_AES_LIBTOMCRYPT_H
-
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/tdes_hardware.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/tdes_hardware.c
deleted file mode 100644
index 7b570103..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/tdes_hardware.c
+++ /dev/null
@@ -1,520 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-// Function: Firmware encryption using TDES hardware acceleration
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include "tdes_hardware.h"
-
-#if defined(USE_ENCRYPTION) && defined(ENCRYPTION_3DES_HARD)
-#include
-#include
-#include
-#include
-#include
-#include
-
-//------------------------------------------------------------------------------
-// Global variables
-//------------------------------------------------------------------------------
-
-#ifdef ENCRYPTION_CTR
- unsigned char CTR[ENCRYPTION_BLOCK_LENGTH];
-#endif
-
-//------------------------------------------------------------------------------
-// Inline functions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Converts an ASCII value to an hexadecimal one
-/// \param ASCII string
-/// \param Buffer to store integer value
-/// \param Length of string
-//------------------------------------------------------------------------------
-static inline void ASCII2Hex(const unsigned char * ascii, unsigned char * binary, unsigned int length)
-{
- unsigned int i;
-
- for (i=0; i < length; i++) {
- if (ascii[i*2] >= 'A') {
- binary[i] = ascii[i*2] - 'A' + 10;
- }
- else {
- binary[i] = ascii[i*2] - '0';
- }
- binary[i] <<= 4;
- if (ascii[i*2+1] >= 'A') {
- binary[i] += ascii[i*2+1] - 'A' + 10;
- }
- else {
- binary[i] += ascii[i*2+1] - '0';
- }
- }
-}
-//------------------------------------------------------------------------------
-// Functions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Initializes the TDES peripheral
-//------------------------------------------------------------------------------
-#ifdef ONLY_ONE_ENCRYPTION
-void tdes_hard_init(void)
-{
- unsigned char key[ENCRYPTION_KEY_LENGTH];
-
- TRACE_DEBUG("TDES/HARD: Initializing ...\n\r");
-
- // Activate peripheral clock
-#ifdef AT91C_ID_AES
- PMC_EnablePeripheral( AT91C_ID_AES );
-#elif AT91C_ID_AESTDES
- PMC_EnablePeripheral( AT91C_ID_AESTDES );
-#elif AT91C_ID_TDES
- PMC_EnablePeripheral( AT91C_ID_TDES );
-#else
-#error AES/TDES undefined
-#endif
-
- // Load mode
-#if (ENCRYPTION_KEY_LENGTH == 24)
- AT91C_BASE_TDES->TDES_MR = AT91C_TDES_SMOD_MANUAL | TDES_MODE
- | AT91C_TDES_TDESMOD | TDES_CIPHER;
-#else
- AT91C_BASE_TDES->TDES_MR = AT91C_TDES_SMOD_MANUAL | TDES_MODE | AT91C_TDES_KEYMOD
- | AT91C_TDES_TDESMOD | TDES_CIPHER;
-#endif
-
- // Convert and load key
- ASCII2Hex((unsigned char*)ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH);
-
- AT91C_BASE_TDES->TDES_KEY1WxR[0] = ((int *) key)[0];
- AT91C_BASE_TDES->TDES_KEY1WxR[1] = ((int *) key)[1];
- AT91C_BASE_TDES->TDES_KEY2WxR[0] = ((int *) key)[2];
- AT91C_BASE_TDES->TDES_KEY2WxR[1] = ((int *) key)[3];
-
-#if (ENCRYPTION_KEY_LENGTH == 24)
- AT91C_BASE_TDES->TDES_KEY3WxR[0] = ((int *) key)[4];
- AT91C_BASE_TDES->TDES_KEY3WxR[1] = ((int *) key)[5];
-#endif
-
-#if defined(ENCRYPTION_CBC)
- unsigned char IV[8];
- ASCII2Hex((unsigned char*)ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH);
-
- AT91C_BASE_TDES->TDES_IVxR[0] = ((int *) IV)[0];
- AT91C_BASE_TDES->TDES_IVxR[1] = ((int *) IV)[1];
-
-#elif defined(ENCRYPTION_CTR)
- // Convert IV
- ASCII2Hex((unsigned char*)ENCRYPTION_IV, CTR, ENCRYPTION_BLOCK_LENGTH);
-#endif
-
- TRACE_DEBUG("TDES/HARD: Initialization done.\n\r");
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Initializes the DES peripheral for CBC mode
-//------------------------------------------------------------------------------
-#ifndef ONLY_ONE_ENCRYPTION
-void tdes_hard_init_CBC(void)
-{
- unsigned char key[TDES_ENCRYPTION_KEY_LENGTH];
-
- TRACE_DEBUG("tdes_hard_init_CBC\n\r");
-
- // Activate peripheral clock
-#ifdef AT91C_ID_AES
- PMC_EnablePeripheral( AT91C_ID_AES );
-#elif AT91C_ID_AESTDES
- PMC_EnablePeripheral( AT91C_ID_AESTDES );
-#elif AT91C_ID_TDES
- PMC_EnablePeripheral( AT91C_ID_TDES );
-#else
-#error AES undefined
-#endif
-
- // Load mode
-#if (TDES_ENCRYPTION_KEY_LENGTH == 24)
- AT91C_BASE_TDES->TDES_MR = AT91C_TDES_SMOD_MANUAL | AT91C_TDES_OPMOD_CBC
- | AT91C_TDES_TDESMOD | 0;
-#else
- AT91C_BASE_TDES->TDES_MR = AT91C_TDES_SMOD_MANUAL | AT91C_TDES_OPMOD_CBC | AT91C_TDES_KEYMOD
- | AT91C_TDES_TDESMOD | 0;
-#endif
-
- // Convert and load key
- ASCII2Hex((unsigned char*)TDES_ENCRYPTION_KEY, key, TDES_ENCRYPTION_KEY_LENGTH);
-
- AT91C_BASE_TDES->TDES_KEY1WxR[0] = ((int *) key)[0];
- AT91C_BASE_TDES->TDES_KEY1WxR[1] = ((int *) key)[1];
- AT91C_BASE_TDES->TDES_KEY2WxR[0] = ((int *) key)[2];
- AT91C_BASE_TDES->TDES_KEY2WxR[1] = ((int *) key)[3];
-
-#if (TDES_ENCRYPTION_KEY_LENGTH == 24)
- AT91C_BASE_TDES->TDES_KEY3WxR[0] = ((int *) key)[4];
- AT91C_BASE_TDES->TDES_KEY3WxR[1] = ((int *) key)[5];
-#endif
-
- unsigned char IV[8];
- ASCII2Hex((unsigned char*)ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH);
-
- AT91C_BASE_TDES->TDES_IVxR[0] = ((int *) IV)[0];
- AT91C_BASE_TDES->TDES_IVxR[1] = ((int *) IV)[1];
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Initializes the DES peripheral for CTR mode
-//------------------------------------------------------------------------------
-#ifndef ONLY_ONE_ENCRYPTION
-void tdes_hard_init_CTR(void)
-{
- unsigned char key[TDES_ENCRYPTION_KEY_LENGTH];
-
- TRACE_DEBUG("tdes_hard_init_CTR\n\r");
-
- // Activate peripheral clock
-#ifdef AT91C_ID_AES
- PMC_EnablePeripheral( AT91C_ID_AES );
-#elif AT91C_ID_AESTDES
- PMC_EnablePeripheral( AT91C_ID_AESTDES );
-#elif AT91C_ID_TDES
- PMC_EnablePeripheral( AT91C_ID_TDES );
-#else
-#error AES undefined
-#endif
-
- // Load mode
-#if (TDES_ENCRYPTION_KEY_LENGTH == 24)
- AT91C_BASE_TDES->TDES_MR = AT91C_TDES_SMOD_MANUAL | AT91C_TDES_OPMOD_ECB
- | AT91C_TDES_TDESMOD | AT91C_TDES_CIPHER;
-#else
- AT91C_BASE_TDES->TDES_MR = AT91C_TDES_SMOD_MANUAL | AT91C_TDES_OPMOD_ECB | AT91C_TDES_KEYMOD
- | AT91C_TDES_TDESMOD | AT91C_TDES_CIPHER;
-#endif
-
- // Convert and load key
- ASCII2Hex((unsigned char*)TDES_ENCRYPTION_KEY, key, TDES_ENCRYPTION_KEY_LENGTH);
-
- AT91C_BASE_TDES->TDES_KEY1WxR[0] = ((int *) key)[0];
- AT91C_BASE_TDES->TDES_KEY1WxR[1] = ((int *) key)[1];
- AT91C_BASE_TDES->TDES_KEY2WxR[0] = ((int *) key)[2];
- AT91C_BASE_TDES->TDES_KEY2WxR[1] = ((int *) key)[3];
-
-#if (TDES_ENCRYPTION_KEY_LENGTH == 24)
- AT91C_BASE_TDES->TDES_KEY3WxR[0] = ((int *) key)[4];
- AT91C_BASE_TDES->TDES_KEY3WxR[1] = ((int *) key)[5];
-#endif
-
- // Convert IV
- ASCII2Hex((unsigned char*)ENCRYPTION_IV, CTR, ENCRYPTION_BLOCK_LENGTH);
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Initializes the DES peripheral for ECB mode
-//------------------------------------------------------------------------------
-#ifndef ONLY_ONE_ENCRYPTION
-void tdes_hard_init_ECB(void)
-{
- unsigned char key[TDES_ENCRYPTION_KEY_LENGTH];
-
- TRACE_DEBUG("tdes_hard_init_ECB\n\r");
-
- // Activate peripheral clock
-#ifdef AT91C_ID_AES
- PMC_EnablePeripheral( AT91C_ID_AES );
-#elif AT91C_ID_AESTDES
- PMC_EnablePeripheral( AT91C_ID_AESTDES );
-#elif AT91C_ID_TDES
- PMC_EnablePeripheral( AT91C_ID_TDES );
-#else
-#error AES undefined
-#endif
-
- // Load mode
-#if (TDES_ENCRYPTION_KEY_LENGTH == 24)
- AT91C_BASE_TDES->TDES_MR = AT91C_TDES_SMOD_MANUAL | AT91C_TDES_OPMOD_ECB
- | AT91C_TDES_TDESMOD | 0;
-#else
- AT91C_BASE_TDES->TDES_MR = AT91C_TDES_SMOD_MANUAL | AT91C_TDES_OPMOD_ECB | AT91C_TDES_KEYMOD
- | AT91C_TDES_TDESMOD | 0;
-#endif
-
- // Convert and load key
- ASCII2Hex((unsigned char*)TDES_ENCRYPTION_KEY, key, TDES_ENCRYPTION_KEY_LENGTH);
-
- AT91C_BASE_TDES->TDES_KEY1WxR[0] = ((int *) key)[0];
- AT91C_BASE_TDES->TDES_KEY1WxR[1] = ((int *) key)[1];
- AT91C_BASE_TDES->TDES_KEY2WxR[0] = ((int *) key)[2];
- AT91C_BASE_TDES->TDES_KEY2WxR[1] = ((int *) key)[3];
-
-#if (TDES_ENCRYPTION_KEY_LENGTH == 24)
- AT91C_BASE_TDES->TDES_KEY3WxR[0] = ((int *) key)[4];
- AT91C_BASE_TDES->TDES_KEY3WxR[1] = ((int *) key)[5];
-#endif
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Cleans up the DES peripheral
-//------------------------------------------------------------------------------
-void tdes_hard_cleanup(void)
-{
- TRACE_DEBUG("TDES/HARD: Cleaning up ...\n\r");
- AT91C_BASE_TDES->TDES_MR = 0;
-#ifdef AT91C_ID_AES
- PMC_DisablePeripheral( AT91C_ID_AES );
-#elif AT91C_ID_AESTDES
- PMC_DisablePeripheral( AT91C_ID_AESTDES );
-#elif AT91C_ID_TDES
- PMC_DisablePeripheral( AT91C_ID_TDES );
-#else
-#error AES undefined
-#endif
- TRACE_DEBUG("TDES/HARD: Cleanup done.\n\r");
-}
-
-//------------------------------------------------------------------------------
-/// Decrypts a variable-length cipher text
-/// \param Cipher text to decrypt
-/// \param Buffer to store plain text
-/// \param Length of cipher text (in bytes)
-//------------------------------------------------------------------------------
-#ifdef ONLY_ONE_ENCRYPTION
-int tdes_hard_decrypt(const unsigned char * cipherText,
- unsigned char * plainText,
- unsigned int length)
-{
- unsigned int l;
-
- TRACE_DEBUG("tdes_hard_decrypt\n\r");
-
-#if defined(ENCRYPTION_ECB) || defined(ENCRYPTION_CBC)
- for (l=0; l < length;) {
-
- // Load counter and encrypt it
- AT91C_BASE_TDES->TDES_IDATAxR[0] = ((int *) &cipherText[l])[0];
- AT91C_BASE_TDES->TDES_IDATAxR[1] = ((int *) &cipherText[l])[1];
-
- // Start processing
- AT91C_BASE_TDES->TDES_CR = AT91C_TDES_START;
-
- while (!((AT91C_BASE_TDES->TDES_ISR) & AT91C_TDES_DATRDY));
-
- ((int *) &plainText[l])[0] = AT91C_BASE_TDES->TDES_ODATAxR[0];
- ((int *) &plainText[l])[1] = AT91C_BASE_TDES->TDES_ODATAxR[1];
-
- l += ENCRYPTION_BLOCK_LENGTH;
- }
-
-#elif defined(ENCRYPTION_CTR)
- unsigned int bytes;
- unsigned char block[ENCRYPTION_BLOCK_LENGTH];
- unsigned int e;
- unsigned int i;
- int k;
-
- // Decrypt
- for (e=0; e < length;) {
-
- // Load counter and encrypt it
- AT91C_BASE_TDES->TDES_IDATAxR[0] = ((int *) CTR)[0];
- AT91C_BASE_TDES->TDES_IDATAxR[1] = ((int *) CTR)[1];
-
- AT91C_BASE_TDES->TDES_CR = AT91C_TDES_START;
- while (!(AT91C_BASE_TDES->TDES_ISR & AT91C_TDES_DATRDY));
-
- ((int *) block)[0] = AT91C_BASE_TDES->TDES_ODATAxR[0];
- ((int *) block)[1] = AT91C_BASE_TDES->TDES_ODATAxR[1];
-
- // XOR current plain text block with encrypted counter
- if ((length-e) < ENCRYPTION_BLOCK_LENGTH) {
- bytes = length - e;
- }
- else {
- bytes = ENCRYPTION_BLOCK_LENGTH;
- }
-
- for (i=0; i < bytes; i++) {
- plainText[e+i] = cipherText[e+i] ^ ((char *) block)[i];
- }
-
- // Increment counter (big-endian) and number of encrypted bytes
- for (k=ENCRYPTION_BLOCK_LENGTH-1; k >= 0; k--) {
- if (++((char *) CTR)[k] != 0) {
- break;
- }
- }
- e += bytes;
- }
-#endif // ENCRYPTION_CTR
-
- return 1;
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Decrypts a variable-length cipher text for CBC mode
-/// \param Cipher text to decrypt
-/// \param Buffer to store plain text
-/// \param Length of cipher text (in bytes)
-//------------------------------------------------------------------------------
-#ifndef ONLY_ONE_ENCRYPTION
-int tdes_hard_decrypt_CBC(const unsigned char * cipherText,
- unsigned char * plainText,
- unsigned int length)
-{
- unsigned int l;
-
- TRACE_DEBUG("tdes_hard_decrypt_CBC\n\r");
-
- for (l=0; l < length;) {
- // Load counter and encrypt it
- AT91C_BASE_TDES->TDES_IDATAxR[0] = ((int *) &cipherText[l])[0];
- AT91C_BASE_TDES->TDES_IDATAxR[1] = ((int *) &cipherText[l])[1];
-
- // Start processing
- AT91C_BASE_TDES->TDES_CR = AT91C_TDES_START;
-
- while (!((AT91C_BASE_TDES->TDES_ISR) & AT91C_TDES_DATRDY));
-
- ((int *) &plainText[l])[0] = AT91C_BASE_TDES->TDES_ODATAxR[0];
- ((int *) &plainText[l])[1] = AT91C_BASE_TDES->TDES_ODATAxR[1];
-
- l += ENCRYPTION_BLOCK_LENGTH;
- }
- return 1;
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Decrypts a variable-length cipher text for CTR mode
-/// \param Cipher text to decrypt
-/// \param Buffer to store plain text
-/// \param Length of cipher text (in bytes)
-//------------------------------------------------------------------------------
-#ifndef ONLY_ONE_ENCRYPTION
-int tdes_hard_decrypt_CTR(const unsigned char * cipherText,
- unsigned char * plainText,
- unsigned int length)
-{
- unsigned int bytes;
- unsigned char block[ENCRYPTION_BLOCK_LENGTH];
- unsigned int e;
- unsigned int i;
- int k;
-
- TRACE_DEBUG("tdes_hard_decrypt_CTR\n\r");
-
- // Decrypt
- for (e=0; e < length;) {
-
- // Load counter and encrypt it
- AT91C_BASE_TDES->TDES_IDATAxR[0] = ((int *) CTR)[0];
- AT91C_BASE_TDES->TDES_IDATAxR[1] = ((int *) CTR)[1];
-
- AT91C_BASE_TDES->TDES_CR = AT91C_TDES_START;
- while (!(AT91C_BASE_TDES->TDES_ISR & AT91C_TDES_DATRDY));
-
- ((int *) block)[0] = AT91C_BASE_TDES->TDES_ODATAxR[0];
- ((int *) block)[1] = AT91C_BASE_TDES->TDES_ODATAxR[1];
-
- // XOR current plain text block with encrypted counter
- if ((length-e) < ENCRYPTION_BLOCK_LENGTH) {
- bytes = length - e;
- }
- else {
- bytes = ENCRYPTION_BLOCK_LENGTH;
- }
-
- for (i=0; i < bytes; i++) {
- plainText[e+i] = cipherText[e+i] ^ ((char *) block)[i];
- }
-
- // Increment counter (big-endian) and number of encrypted bytes
- for (k=ENCRYPTION_BLOCK_LENGTH-1; k >= 0; k--) {
- if (++((char *) CTR)[k] != 0) {
- break;
- }
- }
- e += bytes;
- }
-
- return 1;
-}
-#endif
-
-//------------------------------------------------------------------------------
-/// Decrypts a variable-length cipher text for ECB mode
-/// \param Cipher text to decrypt
-/// \param Buffer to store plain text
-/// \param Length of cipher text (in bytes)
-//------------------------------------------------------------------------------
-#ifndef ONLY_ONE_ENCRYPTION
-int tdes_hard_decrypt_ECB(const unsigned char * cipherText,
- unsigned char * plainText,
- unsigned int length)
-{
- unsigned int l;
-
- TRACE_DEBUG("tdes_hard_decrypt_ECB\n\r");
-
- for (l=0; l < length;) {
-
- // Load counter and encrypt it
- AT91C_BASE_TDES->TDES_IDATAxR[0] = ((int *) &cipherText[l])[0];
- AT91C_BASE_TDES->TDES_IDATAxR[1] = ((int *) &cipherText[l])[1];
-
- // Start processing
- AT91C_BASE_TDES->TDES_CR = AT91C_TDES_START;
-
- while (!((AT91C_BASE_TDES->TDES_ISR) & AT91C_TDES_DATRDY));
-
- ((int *) &plainText[l])[0] = AT91C_BASE_TDES->TDES_ODATAxR[0];
- ((int *) &plainText[l])[1] = AT91C_BASE_TDES->TDES_ODATAxR[1];
-
- l += ENCRYPTION_BLOCK_LENGTH;
- }
- return 1;
-}
-#endif
-
-#endif // defined(USE_ENCRYPTION) && defined(ENCRYPTION_3DES_HARD)
-
-
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/tdes_hardware.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/tdes_hardware.h
deleted file mode 100644
index 28fb774b..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/tdes_hardware.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-/// \unit
-///
-/// !Purpose
-///
-/// Firmware encryption using TDES hardware acceleration
-///
-/// !Usage
-///
-/// -# tdes_hard_init: Initialize TDES hardware
-/// -# tdes_hard_init_CBC: for the CBC mode
-/// -# tdes_hard_init_ECB: for the CTR mode
-/// -# tdes_hard_init_CTR: for the ECB mode
-/// -# tdes_hard_cleanup: Cleans up DES
-/// -# tdes_hard_decrypt: Decrypts a variable-length cipher text
-/// -# tdes_hard_decrypt_CBC: for CBC mode
-/// -# tdes_hard_decrypt_ECB: for ECB mode
-/// -# tdes_hard_decrypt_CTR: for CTR mode
-//------------------------------------------------------------------------------
-#ifndef BOOTLOADER_TDES_HARDWARE_H
-#define BOOTLOADER_TDES_HARDWARE_H
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include "config.h"
-
-#if defined(USE_ENCRYPTION) && defined(ENCRYPTION_3DES_HARD)
-
-//------------------------------------------------------------------------------
-// Check configuration
-//------------------------------------------------------------------------------
-
-#ifdef ONLY_ONE_ENCRYPTION
-#if (ENCRYPTION_KEY_LENGTH != 16) && (ENCRYPTION_KEY_LENGTH != 24)
- #error Triple-DES hardware acceleration only supports 128 and 192 bits keys.
-#endif
-
-#if (ENCRYPTION_BLOCK_LENGTH != 8)
- #error Triple-DES hardware acceleration only supports 64 bits blocks.
-#endif
-
-#if !defined(ENCRYPTION_ECB) && \
- !defined(ENCRYPTION_CBC) && \
- !defined(ENCRYPTION_CTR)
- #error Only ECB, CBC & CTR mode are supported.
-#endif
-
-//------------------------------------------------------------------------------
-// Definitions
-//------------------------------------------------------------------------------
-#define ENCRYPTION_INIT tdes_hard_init
-#define ENCRYPTION_CLEANUP tdes_hard_cleanup
-#define ENCRYPTION_DECRYPT tdes_hard_decrypt
-
-#if defined(ENCRYPTION_ECB)
- #define TDES_MODE AT91C_TDES_OPMOD_ECB
- #define TDES_CIPHER 0
-#elif defined(ENCRYPTION_CBC)
- #define TDES_MODE AT91C_TDES_OPMOD_CBC
- #define TDES_CIPHER 0
-#elif defined(ENCRYPTION_CTR)
- #define TDES_MODE AT91C_TDES_OPMOD_ECB
- #define TDES_CIPHER AT91C_TDES_CIPHER
-#endif
-
-#endif // ONLY_ONE_ENCRYPTION
-
-//------------------------------------------------------------------------------
-// Exported functions
-//------------------------------------------------------------------------------
-#ifdef ONLY_ONE_ENCRYPTION
-extern void tdes_hard_init(void);
-#endif
-extern void tdes_hard_init_CBC(void);
-extern void tdes_hard_init_CTR(void);
-extern void tdes_hard_init_ECB(void);
-extern void tdes_hard_cleanup(void);
-extern int tdes_hard_decrypt(const unsigned char * cipherText,
- unsigned char * plainText,
- unsigned int length);
-extern int tdes_hard_decrypt_CBC(const unsigned char * cipherText,
- unsigned char * plainText,
- unsigned int length);
-extern int tdes_hard_decrypt_CTR(const unsigned char * cipherText,
- unsigned char * plainText,
- unsigned int length);
-extern int tdes_hard_decrypt_ECB(const unsigned char * cipherText,
- unsigned char * plainText,
- unsigned int length);
-
-
-#endif // defined(USE_ENCRYPTION) && defined(ENCRYPTION_3DES_HARD)
-#endif // BOOTLOADER_DES_HARDWARE_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/hamming.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/hamming.c
deleted file mode 100644
index 2b1b8905..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/hamming.c
+++ /dev/null
@@ -1,335 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-
-#include "hamming.h"
-#include
-#include
-
-//------------------------------------------------------------------------------
-// Internal function
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Counts and return the number of bits set to '1' in the given byte.
-/// \param byte Byte to count.
-//------------------------------------------------------------------------------
-static unsigned char CountBitsInByte(unsigned char byte)
-{
- unsigned char count = 0;
- while (byte > 0) {
-
- if (byte & 1) {
-
- count++;
- }
- byte >>= 1;
- }
-
- return count;
-}
-
-//------------------------------------------------------------------------------
-/// Counts and return the number of bits set to '1' in the given hamming code.
-/// \param code Hamming code.
-//------------------------------------------------------------------------------
-static unsigned char CountBitsInCode256(unsigned char *code)
-{
- return CountBitsInByte(code[0])
- + CountBitsInByte(code[1])
- + CountBitsInByte(code[2]);
-}
-
-//------------------------------------------------------------------------------
-/// Calculates the 22-bit hamming code for a 256-bytes block of data.
-/// \param data Data buffer to calculate code for.
-/// \param code Pointer to a buffer where the code should be stored.
-//------------------------------------------------------------------------------
-static void Compute256(const unsigned char *data, unsigned char *code)
-{
- unsigned int i;
- unsigned char columnSum = 0;
- unsigned char evenLineCode = 0;
- unsigned char oddLineCode = 0;
- unsigned char evenColumnCode = 0;
- unsigned char oddColumnCode = 0;
-
- // Xor all bytes together to get the column sum;
- // At the same time, calculate the even and odd line codes
- for (i=0; i < 256; i++) {
-
- columnSum ^= data[i];
-
- // If the xor sum of the byte is 0, then this byte has no incidence on
- // the computed code; so check if the sum is 1.
- if ((CountBitsInByte(data[i]) & 1) == 1) {
-
- // Parity groups are formed by forcing a particular index bit to 0
- // (even) or 1 (odd).
- // Example on one byte:
- //
- // bits (dec) 7 6 5 4 3 2 1 0
- // (bin) 111 110 101 100 011 010 001 000
- // '---'---'---'----------.
- // |
- // groups P4' ooooooooooooooo eeeeeeeeeeeeeee P4 |
- // P2' ooooooo eeeeeee ooooooo eeeeeee P2 |
- // P1' ooo eee ooo eee ooo eee ooo eee P1 |
- // |
- // We can see that: |
- // - P4 -> bit 2 of index is 0 --------------------'
- // - P4' -> bit 2 of index is 1.
- // - P2 -> bit 1 of index if 0.
- // - etc...
- // We deduce that a bit position has an impact on all even Px if
- // the log2(x)nth bit of its index is 0
- // ex: log2(4) = 2, bit2 of the index must be 0 (-> 0 1 2 3)
- // and on all odd Px' if the log2(x)nth bit of its index is 1
- // ex: log2(2) = 1, bit1 of the index must be 1 (-> 0 1 4 5)
- //
- // As such, we calculate all the possible Px and Px' values at the
- // same time in two variables, evenLineCode and oddLineCode, such as
- // evenLineCode bits: P128 P64 P32 P16 P8 P4 P2 P1
- // oddLineCode bits: P128' P64' P32' P16' P8' P4' P2' P1'
- //
- evenLineCode ^= (255 - i);
- oddLineCode ^= i;
- }
- }
-
- // At this point, we have the line parities, and the column sum. First, We
- // must caculate the parity group values on the column sum.
- for (i=0; i < 8; i++) {
-
- if (columnSum & 1) {
-
- evenColumnCode ^= (7 - i);
- oddColumnCode ^= i;
- }
- columnSum >>= 1;
- }
-
- // Now, we must interleave the parity values, to obtain the following layout:
- // Code[0] = Line1
- // Code[1] = Line2
- // Code[2] = Column
- // Line = Px' Px P(x-1)- P(x-1) ...
- // Column = P4' P4 P2' P2 P1' P1 PadBit PadBit
- code[0] = 0;
- code[1] = 0;
- code[2] = 0;
-
- for (i=0; i < 4; i++) {
-
- code[0] <<= 2;
- code[1] <<= 2;
- code[2] <<= 2;
-
- // Line 1
- if ((oddLineCode & 0x80) != 0) {
-
- code[0] |= 2;
- }
- if ((evenLineCode & 0x80) != 0) {
-
- code[0] |= 1;
- }
-
- // Line 2
- if ((oddLineCode & 0x08) != 0) {
-
- code[1] |= 2;
- }
- if ((evenLineCode & 0x08) != 0) {
-
- code[1] |= 1;
- }
-
- // Column
- if ((oddColumnCode & 0x04) != 0) {
-
- code[2] |= 2;
- }
- if ((evenColumnCode & 0x04) != 0) {
-
- code[2] |= 1;
- }
-
- oddLineCode <<= 1;
- evenLineCode <<= 1;
- oddColumnCode <<= 1;
- evenColumnCode <<= 1;
- }
-
- // Invert codes (linux compatibility)
- code[0] = ~code[0];
- code[1] = ~code[1];
- code[2] = ~code[2];
-
- TRACE_DEBUG("Computed code = %02X %02X %02X\n\r",
- code[0], code[1], code[2]);
-}
-
-//------------------------------------------------------------------------------
-/// Verifies and corrects a 256-bytes block of data using the given 22-bits
-/// hamming code.
-/// Returns 0 if there is no error, otherwise returns a HAMMING_ERROR code.
-/// \param data Data buffer to check.
-/// \param originalCode Hamming code to use for verifying the data.
-//------------------------------------------------------------------------------
-static unsigned char Verify256(
- unsigned char *data,
- const unsigned char *originalCode)
-{
- // Calculate new code
- unsigned char computedCode[3];
- unsigned char correctionCode[3];
- Compute256(data, computedCode);
-
- // Xor both codes together
- correctionCode[0] = computedCode[0] ^ originalCode[0];
- correctionCode[1] = computedCode[1] ^ originalCode[1];
- correctionCode[2] = computedCode[2] ^ originalCode[2];
-
- TRACE_DEBUG("Correction code = %02X %02X %02X\n\r",
- correctionCode[0], correctionCode[1], correctionCode[2]);
-
- // If all bytes are 0, there is no error
- if ((correctionCode[0] == 0)
- && (correctionCode[1] == 0)
- && (correctionCode[2] == 0)) {
-
- return 0;
- }
- // If there is a single bit error, there are 11 bits set to 1
- if (CountBitsInCode256(correctionCode) == 11) {
-
- // Get byte and bit indexes
- unsigned char byte = correctionCode[0] & 0x80;
- byte |= (correctionCode[0] << 1) & 0x40;
- byte |= (correctionCode[0] << 2) & 0x20;
- byte |= (correctionCode[0] << 3) & 0x10;
-
- byte |= (correctionCode[1] >> 4) & 0x08;
- byte |= (correctionCode[1] >> 3) & 0x04;
- byte |= (correctionCode[1] >> 2) & 0x02;
- byte |= (correctionCode[1] >> 1) & 0x01;
-
- unsigned char bit = (correctionCode[2] >> 5) & 0x04;
- bit |= (correctionCode[2] >> 4) & 0x02;
- bit |= (correctionCode[2] >> 3) & 0x01;
-
- // Correct bit
- TRACE_DEBUG("Correcting byte #%d at bit %d\n\r", byte, bit);
- data[byte] ^= (1 << bit);
-
- return Hamming_ERROR_SINGLEBIT;
- }
- // Check if ECC has been corrupted
- if (CountBitsInCode256(correctionCode) == 1) {
-
- return Hamming_ERROR_ECC;
- }
- // Otherwise, this is a multi-bit error
- else {
-
- return Hamming_ERROR_MULTIPLEBITS;
- }
-}
-
-//------------------------------------------------------------------------------
-// Exported functions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Computes 3-bytes hamming codes for a data block whose size is multiple of
-/// 256 bytes. Each 256 bytes block gets its own code.
-/// \param data Data to compute code for.
-/// \param size Data size in bytes.
-/// \param code Codes buffer.
-//------------------------------------------------------------------------------
-void Hamming_Compute256x(
- const unsigned char *data,
- unsigned int size,
- unsigned char *code)
-{
- TRACE_DEBUG("Hamming_Compute256x()\n\r");
-
- while (size > 0) {
-
- Compute256(data, code);
- data += 256;
- code += 3;
- size -= 256;
- }
-}
-
-//------------------------------------------------------------------------------
-/// Verifies 3-bytes hamming codes for a data block whose size is multiple of
-/// 256 bytes. Each 256-bytes block is verified with its own code.
-/// Returns 0 if the data is correct, Hamming_ERROR_SINGLEBIT if one or more
-/// block(s) have had a single bit corrected, or either Hamming_ERROR_ECC
-/// or Hamming_ERROR_MULTIPLEBITS.
-/// \param data Data buffer to verify.
-/// \param size Size of the data in bytes.
-/// \param code Original codes.
-//------------------------------------------------------------------------------
-unsigned char Hamming_Verify256x(
- unsigned char *data,
- unsigned int size,
- const unsigned char *code)
-{
- unsigned char error;
- unsigned char result = 0;
-
- TRACE_DEBUG("Hamming_Verify256x()\n\r");
-
- while (size > 0) {
-
- error = Verify256(data, code);
- if (error == Hamming_ERROR_SINGLEBIT) {
-
- result = Hamming_ERROR_SINGLEBIT;
- }
- else if (error) {
-
- return error;
- }
-
- data += 256;
- code += 3;
- size -= 256;
- }
-
- return result;
-}
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/hamming.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/hamming.h
deleted file mode 100644
index 6e0125d9..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/hamming.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-#ifndef HAMMING_H
-#define HAMMING_H
-
-//------------------------------------------------------------------------------
-// Defines
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// \page "Hamming Code Errors"
-/// These are the possible errors when trying to verify a block of data encoded
-/// using a Hamming code:
-///
-/// !Errors:
-/// - Hamming_ERROR_SINGLEBIT
-/// - Hamming_ERROR_ECC
-/// - Hamming_ERROR_MULTIPLEBITS
-
-/// A single bit was incorrect but has been recovered.
-#define Hamming_ERROR_SINGLEBIT 1
-
-/// The original code has been corrupted.
-#define Hamming_ERROR_ECC 2
-
-/// Multiple bits are incorrect in the data and they cannot be corrected.
-#define Hamming_ERROR_MULTIPLEBITS 3
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Exported functions
-//------------------------------------------------------------------------------
-
-extern void Hamming_Compute256x(
- const unsigned char *data,
- unsigned int size,
- unsigned char *code);
-
-extern unsigned char Hamming_Verify256x(
- unsigned char *data,
- unsigned int size,
- const unsigned char *code);
-
-#endif //#ifndef HAMMING_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/iap.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/iap.c
deleted file mode 100644
index c4657e22..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/iap.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/*
- Title: IAP implementation
-
- About: Purpose
- IAP feature is avalaible on ATMEL chip with internal FLASH. This allows
- the FLASH memory to be programmed even when the code is also running in
- FLASH, without writing some SRAM relocated functions.
- The IAP function entry point is written in the 3rd exception vector
- (SWI at 0x300008), and is retrieved just by reading the value at this
- address.
-
- ROM function algorithm :
- // Send Command
- AT91_BASE_MC->MC_FCR = FlashCmd
- // Wait Flash is ready
- while ((AT91C_BASE_MC->MC_FSR & AT91C_MC_FRDY) != AT91C_MC_FRDY)
- return
-*/
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-
-#include "iap.h"
-#include
-#include
-
-//------------------------------------------------------------------------------
-// Internal variables
-//------------------------------------------------------------------------------
-
-
-
-//------------------------------------------------------------------------------
-// Exported functions
-//------------------------------------------------------------------------------
-/*
- Function: IAP_PerformCmd
- Perform a FLASH command through the IAP function.
-
- Returns:
- 0 if the IAP function has executed correctly.
- -1 if the IAP feature is not implemented in the ROM code.
-*/
-unsigned long IAP_PerformCmd(unsigned long FlashCmd)
-{
- // Pointer on IAP function in ROM
- static void (*IAP_Function)(unsigned int) = 0;
-
- if (IAP_Function == 0) {
-
- IAP_Function = (void (*)(unsigned int)) (*((unsigned int *) IAP_FUNC_ADDR));
- TRACE_DEBUG("IAP_PerformCmd : IAP function address in ROM : 0x%08X\n\r", (unsigned int) IAP_Function);
-
- /* Check if IAP function is implemented (opcode in SWI != 'b' or 'ldr') */
- if ((((((unsigned long)IAP_Function >> 24) & 0xFF) == 0xEA) ||
- (((unsigned long)IAP_Function >> 24) & 0xFF) == 0xE5)) {
- TRACE_ERROR("IAP_PerformCmd : no IAP function address found in ROM\n\r");
- IAP_Function = 0;
- return -1;
- }
- }
-
- /* Perform FLASH command */
- IAP_Function(FlashCmd);
-
- return 0;
-}
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/iap.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/iap.h
deleted file mode 100644
index 87a6bcd5..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/iap.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/*
- Title: IAP
-
- About: Purpose
- Small function for using IAP feature.
-
- About: Usage
- Perform a FLASH command using .
-
-*/
-
-#ifndef IAP_H
-#define IAP_H
-
-//------------------------------------------------------------------------------
-// Exported functions
-//------------------------------------------------------------------------------
-
-extern unsigned long IAP_PerformCmd (unsigned long FlashCmd);
-
-#endif //#ifndef IAP_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/led.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/led.c
deleted file mode 100644
index a216b2a0..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/led.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/// \file
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-
-#include "led.h"
-#include
-#include
-
-//------------------------------------------------------------------------------
-// Local Variables
-//------------------------------------------------------------------------------
-
-#ifdef PINS_LEDS
-static const Pin pinsLeds[] = {PINS_LEDS};
-static const unsigned int numLeds = PIO_LISTSIZE(pinsLeds);
-#endif
-
-//------------------------------------------------------------------------------
-// Global Functions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Configures the pin associated with the given LED number. If the LED does
-/// not exist on the board, the function does nothing.
-/// \param led Number of the LED to configure.
-/// \return 1 if the LED exists and has been configured; otherwise 0.
-//------------------------------------------------------------------------------
-unsigned char LED_Configure(unsigned int led)
-{
-#ifdef PINS_LEDS
- // Check that LED exists
- if (led >= numLeds) {
-
- return 0;
- }
-
- // Configure LED
- return (PIO_Configure(&pinsLeds[led], 1));
-#else
- return 0;
-#endif
-}
-
-//------------------------------------------------------------------------------
-/// Turns the given LED on if it exists; otherwise does nothing.
-/// \param led Number of the LED to turn on.
-/// \return 1 if the LED has been turned on; 0 otherwise.
-//------------------------------------------------------------------------------
-unsigned char LED_Set(unsigned int led)
-{
-#ifdef PINS_LEDS
- // Check if LED exists
- if (led >= numLeds) {
-
- return 0;
- }
-
- // Turn LED on
- if (pinsLeds[led].type == PIO_OUTPUT_0) {
-
- PIO_Set(&pinsLeds[led]);
- }
- else {
-
- PIO_Clear(&pinsLeds[led]);
- }
-
- return 1;
-#else
- return 0;
-#endif
-}
-
-//------------------------------------------------------------------------------
-/// Turns a LED off.
-/// \param led Number of the LED to turn off.
-/// \param 1 if the LED has been turned off; 0 otherwise.
-//------------------------------------------------------------------------------
-unsigned char LED_Clear(unsigned int led)
-{
-#ifdef PINS_LEDS
- // Check if LED exists
- if (led >= numLeds) {
-
- return 0;
- }
-
- // Turn LED off
- if (pinsLeds[led].type == PIO_OUTPUT_0) {
-
- PIO_Clear(&pinsLeds[led]);
- }
- else {
-
- PIO_Set(&pinsLeds[led]);
- }
-
- return 1;
-#else
- return 0;
-#endif
-}
-
-//------------------------------------------------------------------------------
-/// Toggles the current state of a LED.
-/// \param led Number of the LED to toggle.
-/// \return 1 if the LED has been toggled; otherwise 0.
-//------------------------------------------------------------------------------
-unsigned char LED_Toggle(unsigned int led)
-{
-#ifdef PINS_LEDS
- // Check if LED exists
- if (led >= numLeds) {
-
- return 0;
- }
-
- // Toggle LED
- if (PIO_GetOutputDataStatus(&pinsLeds[led])) {
-
- PIO_Clear(&pinsLeds[led]);
- }
- else {
-
- PIO_Set(&pinsLeds[led]);
- }
-
- return 1;
-#else
- return 0;
-#endif
-}
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/led.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/led.h
deleted file mode 100644
index 9a08a82d..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/led.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-/// \file
-///
-/// \par Purpose
-///
-/// Small set of functions for simple and portable LED usage.
-///
-/// \par Usage
-///
-/// -# Configure one or more LEDs using LED_Configure and
-/// LED_ConfigureAll.
-/// -# Set, clear and toggle LEDs using LED_Set, LED_Clear and
-/// LED_Toggle.
-///
-/// LEDs are numbered starting from 0; the number of LEDs depend on the
-/// board being used. All the functions defined here will compile properly
-/// regardless of whether the LED is defined or not; they will simply
-/// return 0 when a LED which does not exist is given as an argument.
-/// Also, these functions take into account how each LED is connected on to
-/// board; thus, might change the level on the corresponding pin
-/// to 0 or 1, but it will always light the LED on; same thing for the other
-/// methods.
-//------------------------------------------------------------------------------
-
-#ifndef LED_H
-#define LED_H
-
-//------------------------------------------------------------------------------
-// Global Functions
-//------------------------------------------------------------------------------
-
-extern unsigned char LED_Configure(unsigned int led);
-
-extern unsigned char LED_Set(unsigned int led);
-
-extern unsigned char LED_Clear(unsigned int led);
-
-extern unsigned char LED_Toggle(unsigned int led);
-
-#endif //#ifndef LED_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/math.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/math.c
deleted file mode 100644
index 39bed568..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/math.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-
-#include "math.h"
-#include "trace.h"
-
-//------------------------------------------------------------------------------
-// Exported functions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Returns the minimum value between two integers.
-/// \param a First integer to compare.
-/// \param b Second integer to compare.
-//------------------------------------------------------------------------------
-unsigned int min(unsigned int a, unsigned int b)
-{
- if (a < b) {
-
- return a;
- }
- else {
-
- return b;
- }
-}
-
-//------------------------------------------------------------------------------
-/// Returns the absolute value of an integer.
-/// \param value Integer value.
-//------------------------------------------------------------------------------
-// Do not call this function "abs", problem with gcc !
-unsigned int absv(signed int value)
-{
- if (value < 0) {
-
- return -value;
- }
- else {
-
- return value;
- }
-}
-
-//------------------------------------------------------------------------------
-/// Computes and returns x power of y.
-/// \param x Value.
-/// \param y Power.
-//------------------------------------------------------------------------------
-unsigned int power(unsigned int x, unsigned int y)
-{
- unsigned int result = 1;
-
- while (y > 0) {
-
- result *= x;
- y--;
- }
- return result;
-}
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/math.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/math.h
deleted file mode 100644
index 6394f299..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/math.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-#ifndef MATH_H
-#define MATH_H
-
-//------------------------------------------------------------------------------
-// Exported functions
-//------------------------------------------------------------------------------
-
-extern unsigned int min(unsigned int a, unsigned int b);
-extern unsigned int absv(signed int value);
-extern unsigned int power(unsigned int x, unsigned int y);
-#endif //#ifndef MATH_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/rand.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/rand.c
deleted file mode 100644
index 9a0f986d..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/rand.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-#include "rand.h"
-
-//------------------------------------------------------------------------------
-// Global Functions
-//------------------------------------------------------------------------------
-
-static unsigned long int next = 1;
-
-//------------------------------------------------------------------------------
-// Global Functions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Initialize the seed for rand generator.
-/// \param seed rand initiation seed
-//------------------------------------------------------------------------------
-void srand(unsigned int seed)
-{
- next = seed;
-}
-
-//------------------------------------------------------------------------------
-/// Return a random number, maxinum assumed to be 65536
-//------------------------------------------------------------------------------
-
-int rand(void)
-{
- next = next * 1103515245 + 12345;
- return (unsigned int)(next/131072) % 65536;
-}
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/rand.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/rand.h
deleted file mode 100644
index 8a8b21e2..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/rand.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-/// \unit
-///
-/// !!!Purpose
-///
-/// Small function for gererating random number.
-///
-//------------------------------------------------------------------------------
-
-#ifndef RAND_H
-#define RAND_H
-
-//------------------------------------------------------------------------------
-// Global Functions
-//------------------------------------------------------------------------------
-
-extern void srand(unsigned int seed);
-extern int rand(void);
-
-#endif //#ifndef RAND_H
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/retarget.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/retarget.c
deleted file mode 100644
index 1ca875ec..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/retarget.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-/// \unit
-///
-/// !Purpose
-///
-/// This file Configures the target-dependent low level functions for character I/O.
-///
-/// !Contents
-/// The code implement the lower-level functions as follows:
-/// - fputc
-/// - ferror
-/// - _ttywrch
-/// - _sys_exit
-///
-///
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-#include
-#include
-
-// Disable semihosting
-#pragma import(__use_no_semihosting_swi)
-
-struct __FILE { int handle;} ;
-FILE __stdout;
-FILE __stderr;
-
-//------------------------------------------------------------------------------
-/// Outputs a character to a file.
-//------------------------------------------------------------------------------
-int fputc(int ch, FILE *f) {
- if ((f == stdout) || (f == stderr)) {
- DBGU_PutChar(ch);
- return ch;
- }
- else {
- return EOF;
- }
-}
-
-//------------------------------------------------------------------------------
-/// Returns the error status accumulated during file I/O.
-//------------------------------------------------------------------------------
-int ferror(FILE *f) {
- return EOF;
-}
-
-
-void _ttywrch(int ch) {
- DBGU_PutChar((unsigned char)ch);
-}
-
-
-void _sys_exit(int return_code) {
- label: goto label; /* endless loop */
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/stdio.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/stdio.c
deleted file mode 100644
index defbbc08..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/stdio.c
+++ /dev/null
@@ -1,511 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-/// \unit
-///
-/// !Purpose
-///
-/// Implementation of several stdio.h methods, such as printf(), sprintf() and
-/// so on. This reduces the memory footprint of the binary when using those
-/// methods, compared to the libc implementation.
-///
-/// !Usage
-///
-/// Adds stdio.c to the list of file to compile for the project. This will
-/// automatically replace libc methods by the custom ones.
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-
-#include
-#include
-
-//------------------------------------------------------------------------------
-// Local Definitions
-//------------------------------------------------------------------------------
-
-// Maximum string size allowed (in bytes).
-#define MAX_STRING_SIZE 100
-
-//------------------------------------------------------------------------------
-// Global Variables
-//------------------------------------------------------------------------------
-
-// Required for proper compilation.
-struct _reent r = {0, (FILE *) 0, (FILE *) 1, (FILE *) 0};
-struct _reent *_impure_ptr = &r;
-
-//------------------------------------------------------------------------------
-// Local Functions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Writes a character inside the given string. Returns 1.
-// \param pStr Storage string.
-// \param c Character to write.
-//------------------------------------------------------------------------------
-signed int PutChar(char *pStr, char c)
-{
- *pStr = c;
- return 1;
-}
-
-//------------------------------------------------------------------------------
-// Writes a string inside the given string.
-// Returns the size of the written
-// string.
-// \param pStr Storage string.
-// \param pSource Source string.
-//------------------------------------------------------------------------------
-signed int PutString(char *pStr, const char *pSource)
-{
- signed int num = 0;
-
- while (*pSource != 0) {
-
- *pStr++ = *pSource++;
- num++;
- }
-
- return num;
-}
-
-//------------------------------------------------------------------------------
-// Writes an unsigned int inside the given string, using the provided fill &
-// width parameters.
-// Returns the size in characters of the written integer.
-// \param pStr Storage string.
-// \param fill Fill character.
-// \param width Minimum integer width.
-// \param value Integer value.
-//------------------------------------------------------------------------------
-signed int PutUnsignedInt(
- char *pStr,
- char fill,
- signed int width,
- unsigned int value)
-{
- signed int num = 0;
-
- // Take current digit into account when calculating width
- width--;
-
- // Recursively write upper digits
- if ((value / 10) > 0) {
-
- num = PutUnsignedInt(pStr, fill, width, value / 10);
- pStr += num;
- }
- // Write filler characters
- else {
-
- while (width > 0) {
-
- PutChar(pStr, fill);
- pStr++;
- num++;
- width--;
- }
- }
-
- // Write lower digit
- num += PutChar(pStr, (value % 10) + '0');
-
- return num;
-}
-
-//------------------------------------------------------------------------------
-// Writes a signed int inside the given string, using the provided fill & width
-// parameters.
-// Returns the size of the written integer.
-// \param pStr Storage string.
-// \param fill Fill character.
-// \param width Minimum integer width.
-// \param value Signed integer value.
-//------------------------------------------------------------------------------
-signed int PutSignedInt(
- char *pStr,
- char fill,
- signed int width,
- signed int value)
-{
- signed int num = 0;
- unsigned int absolute;
-
- // Compute absolute value
- if (value < 0) {
-
- absolute = -value;
- }
- else {
-
- absolute = value;
- }
-
- // Take current digit into account when calculating width
- width--;
-
- // Recursively write upper digits
- if ((absolute / 10) > 0) {
-
- if (value < 0) {
-
- num = PutSignedInt(pStr, fill, width, -(absolute / 10));
- }
- else {
-
- num = PutSignedInt(pStr, fill, width, absolute / 10);
- }
- pStr += num;
- }
- else {
-
- // Reserve space for sign
- if (value < 0) {
-
- width--;
- }
-
- // Write filler characters
- while (width > 0) {
-
- PutChar(pStr, fill);
- pStr++;
- num++;
- width--;
- }
-
- // Write sign
- if (value < 0) {
-
- num += PutChar(pStr, '-');
- pStr++;
- }
- }
-
- // Write lower digit
- num += PutChar(pStr, (absolute % 10) + '0');
-
- return num;
-}
-
-//------------------------------------------------------------------------------
-// Writes an hexadecimal value into a string, using the given fill, width &
-// capital parameters.
-// Returns the number of char written.
-// \param pStr Storage string.
-// \param fill Fill character.
-// \param width Minimum integer width.
-// \param maj Indicates if the letters must be printed in lower- or upper-case.
-// \param value Hexadecimal value.
-//------------------------------------------------------------------------------
-signed int PutHexa(
- char *pStr,
- char fill,
- signed int width,
- unsigned char maj,
- unsigned int value)
-{
- signed int num = 0;
-
- // Decrement width
- width--;
-
- // Recursively output upper digits
- if ((value >> 4) > 0) {
-
- num += PutHexa(pStr, fill, width, maj, value >> 4);
- pStr += num;
- }
- // Write filler chars
- else {
-
- while (width > 0) {
-
- PutChar(pStr, fill);
- pStr++;
- num++;
- width--;
- }
- }
-
- // Write current digit
- if ((value & 0xF) < 10) {
-
- PutChar(pStr, (value & 0xF) + '0');
- }
- else if (maj) {
-
- PutChar(pStr, (value & 0xF) - 10 + 'A');
- }
- else {
-
- PutChar(pStr, (value & 0xF) - 10 + 'a');
- }
- num++;
-
- return num;
-}
-
-//------------------------------------------------------------------------------
-// Global Functions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Stores the result of a formatted string into another string. Format
-/// arguments are given in a va_list instance.
-/// Return the number of characters written.
-/// \param pStr Destination string.
-/// \param length Length of Destination string.
-/// \param pFormat Format string.
-/// \param ap Argument list.
-//------------------------------------------------------------------------------
-signed int vsnprintf(char *pStr, size_t length, const char *pFormat, va_list ap)
-{
- char fill;
- unsigned char width;
- signed int num = 0;
- signed int size = 0;
-
- // Clear the string
- if (pStr) {
-
- *pStr = 0;
- }
-
- // Phase string
- while (*pFormat != 0 && size < length) {
-
- // Normal character
- if (*pFormat != '%') {
-
- *pStr++ = *pFormat++;
- size++;
- }
- // Escaped '%'
- else if (*(pFormat+1) == '%') {
-
- *pStr++ = '%';
- pFormat += 2;
- size++;
- }
- // Token delimiter
- else {
-
- fill = ' ';
- width = 0;
- pFormat++;
-
- // Parse filler
- if (*pFormat == '0') {
-
- fill = '0';
- pFormat++;
- }
-
- // Parse width
- while ((*pFormat >= '0') && (*pFormat <= '9')) {
-
- width = (width*10) + *pFormat-'0';
- pFormat++;
- }
-
- // Check if there is enough space
- if (size + width > length) {
-
- width = length - size;
- }
-
- // Parse type
- switch (*pFormat) {
- case 'd':
- case 'i': num = PutSignedInt(pStr, fill, width, va_arg(ap, signed int)); break;
- case 'u': num = PutUnsignedInt(pStr, fill, width, va_arg(ap, unsigned int)); break;
- case 'x': num = PutHexa(pStr, fill, width, 0, va_arg(ap, unsigned int)); break;
- case 'X': num = PutHexa(pStr, fill, width, 1, va_arg(ap, unsigned int)); break;
- case 's': num = PutString(pStr, va_arg(ap, char *)); break;
- case 'c': num = PutChar(pStr, va_arg(ap, unsigned int)); break;
- default:
- return EOF;
- }
-
- pFormat++;
- pStr += num;
- size += num;
- }
- }
-
- // NULL-terminated (final \0 is not counted)
- if (size < length) {
-
- *pStr = 0;
- }
- else {
-
- *(--pStr) = 0;
- size--;
- }
-
- return size;
-}
-
-//------------------------------------------------------------------------------
-/// Stores the result of a formatted string into another string. Format
-/// arguments are given in a va_list instance.
-/// Return the number of characters written.
-/// \param pString Destination string.
-/// \param length Length of Destination string.
-/// \param pFormat Format string.
-/// \param ... Other arguments
-//------------------------------------------------------------------------------
-signed int snprintf(char *pString, size_t length, const char *pFormat, ...)
-{
- va_list ap;
- signed int rc;
-
- va_start(ap, pFormat);
- rc = vsnprintf(pString, length, pFormat, ap);
- va_end(ap);
-
- return rc;
-}
-
-//------------------------------------------------------------------------------
-/// Stores the result of a formatted string into another string. Format
-/// arguments are given in a va_list instance.
-/// Return the number of characters written.
-/// \param pString Destination string.
-/// \param pFormat Format string.
-/// \param ap Argument list.
-//------------------------------------------------------------------------------
-signed int vsprintf(char *pString, const char *pFormat, va_list ap)
-{
- return vsnprintf(pString, MAX_STRING_SIZE, pFormat, ap);
-}
-
-//------------------------------------------------------------------------------
-/// Outputs a formatted string on the given stream. Format arguments are given
-/// in a va_list instance.
-/// \param pStream Output stream.
-/// \param pFormat Format string
-/// \param ap Argument list.
-//------------------------------------------------------------------------------
-signed int vfprintf(FILE *pStream, const char *pFormat, va_list ap)
-{
- char pStr[MAX_STRING_SIZE];
- char pError[] = "stdio.c: increase MAX_STRING_SIZE\n\r";
-
- // Write formatted string in buffer
- if (vsprintf(pStr, pFormat, ap) >= MAX_STRING_SIZE) {
-
- fputs(pError, stderr);
- while (1); // Increase MAX_STRING_SIZE
- }
-
- // Display string
- return fputs(pStr, pStream);
-}
-
-//------------------------------------------------------------------------------
-/// Outputs a formatted string on the DBGU stream. Format arguments are given
-/// in a va_list instance.
-/// \param pFormat Format string
-/// \param ap Argument list.
-//------------------------------------------------------------------------------
-signed int vprintf(const char *pFormat, va_list ap)
-{
- return vfprintf(stdout, pFormat, ap);
-}
-
-//------------------------------------------------------------------------------
-/// Outputs a formatted string on the given stream, using a variable number of
-/// arguments.
-/// \param pStream Output stream.
-/// \param pFormat Format string.
-//------------------------------------------------------------------------------
-signed int fprintf(FILE *pStream, const char *pFormat, ...)
-{
- va_list ap;
- signed int result;
-
- // Forward call to vfprintf
- va_start(ap, pFormat);
- result = vfprintf(pStream, pFormat, ap);
- va_end(ap);
-
- return result;
-}
-
-//------------------------------------------------------------------------------
-/// Outputs a formatted string on the DBGU stream, using a variable number of
-/// arguments.
-/// \param pFormat Format string.
-//------------------------------------------------------------------------------
-signed int printf(const char *pFormat, ...)
-{
- va_list ap;
- signed int result;
-
- // Forward call to vprintf
- va_start(ap, pFormat);
- result = vprintf(pFormat, ap);
- va_end(ap);
-
- return result;
-}
-
-//------------------------------------------------------------------------------
-/// Writes a formatted string inside another string.
-/// \param pStr Storage string.
-/// \param pFormat Format string.
-//------------------------------------------------------------------------------
-signed int sprintf(char *pStr, const char *pFormat, ...)
-{
- va_list ap;
- signed int result;
-
- // Forward call to vsprintf
- va_start(ap, pFormat);
- result = vsprintf(pStr, pFormat, ap);
- va_end(ap);
-
- return result;
-}
-
-//------------------------------------------------------------------------------
-/// Outputs a string on stdout.
-/// \param pStr String to output.
-//------------------------------------------------------------------------------
-signed int puts(const char *pStr)
-{
- return fputs(pStr, stdout);
-}
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/string.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/string.c
deleted file mode 100644
index dbbb0e9e..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/string.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-/// \unit
-///
-/// !Purpose
-///
-/// Implementation of several methods defined in string.h, for reducing the
-/// memory footprint when using them (since the whole libc.o file gets included
-/// even when using a single method).
-///
-/// !Usage
-///
-/// Add string.c to the list of files to compile for the project. This will
-/// automatically replace standard libc methods by the custom ones.
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-
-#include
-
-//------------------------------------------------------------------------------
-// Global Functions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Copies data from a source buffer into a destination buffer. The two buffers
-/// must NOT overlap. Returns the destination buffer.
-/// \param pDestination Destination buffer.
-/// \param pSource Source buffer.
-/// \param num Number of bytes to copy.
-//------------------------------------------------------------------------------
-void * memcpy(void *pDestination, const void *pSource, size_t num)
-{
- unsigned char *pByteDestination;
- unsigned char *pByteSource;
- unsigned int *pAlignedSource = (unsigned int *) pSource;
- unsigned int *pAlignedDestination = (unsigned int *) pDestination;
-
- // If num is more than 4 bytes, and both dest. and source are aligned,
- // then copy dwords
- if ((((unsigned int) pAlignedDestination & 0x3) == 0)
- && (((unsigned int) pAlignedSource & 0x3) == 0)
- && (num >= 4)) {
-
- while (num >= 4) {
-
- *pAlignedDestination++ = *pAlignedSource++;
- num -= 4;
- }
- }
-
- // Copy remaining bytes
- pByteDestination = (unsigned char *) pAlignedDestination;
- pByteSource = (unsigned char *) pAlignedSource;
- while (num--) {
-
- *pByteDestination++ = *pByteSource++;
- }
-
- return pDestination;
-}
-
-//------------------------------------------------------------------------------
-/// Fills a memory region with the given value. Returns a pointer to the
-/// memory region.
-/// \param pBuffer Pointer to the start of the memory region to fill
-/// \param value Value to fill the region with
-/// \param num Size to fill in bytes
-//------------------------------------------------------------------------------
-void * memset(void *pBuffer, int value, size_t num)
-{
- unsigned char *pByteDestination;
- unsigned int *pAlignedDestination = (unsigned int *) pBuffer;
- unsigned int alignedValue = (value << 24) | (value << 16) | (value << 8) | value;
-
- // Set words if possible
- if ((((unsigned int) pAlignedDestination & 0x3) == 0) && (num >= 4)) {
- while (num >= 4) {
- *pAlignedDestination++ = alignedValue;
- num -= 4;
- }
- }
- // Set remaining bytes
- pByteDestination = (unsigned char *) pAlignedDestination;
- while (num--) {
- *pByteDestination++ = value;
- }
- return pBuffer;
-}
-
-//-----------------------------------------------------------------------------
-/// Search a character in the given string.
-/// Returns a pointer to the character location.
-/// \param pString Pointer to the start of the string to search.
-/// \param character The character to find.
-//-----------------------------------------------------------------------------
-char * strchr(const char *pString, int character)
-{
- char * p = (char *)pString;
- char c = character & 0xFF;
-
- while(*p != c) {
- if (*p == 0) {
- return 0;
- }
- p++;
- }
- return p;
-}
-
-//-----------------------------------------------------------------------------
-/// Return the length of a given string
-/// \param pString Pointer to the start of the string.
-//-----------------------------------------------------------------------------
-size_t strlen(const char *pString)
-{
- unsigned int length = 0;
-
- while(*pString++ != 0) {
- length++;
- }
- return length;
-}
-
-
-//-----------------------------------------------------------------------------
-/// Search a character backword from the end of given string.
-/// Returns a pointer to the character location.
-/// \param pString Pointer to the start of the string to search.
-/// \param character The character to find.
-//-----------------------------------------------------------------------------
-char * strrchr(const char *pString, int character)
-{
- char *p = 0;
-
- while(*pString != 0) {
- if (*pString++ == character) {
- p = (char*)pString;
- }
- }
- return p;
-}
-
-//-----------------------------------------------------------------------------
-/// Copy from source string to destination string
-/// Return a pointer to the destination string
-/// \param pDestination Pointer to the destination string.
-/// \param pSource Pointer to the source string.
-//-----------------------------------------------------------------------------
-char * strcpy(char *pDestination, const char *pSource)
-{
- char *pSaveDest = pDestination;
-
- for(; (*pDestination = *pSource) != 0; ++pSource, ++pDestination);
- return pSaveDest;
-}
-
-//-----------------------------------------------------------------------------
-/// Compare the first specified bytes of 2 given strings
-/// Return 0 if equals
-/// Return >0 if 1st string > 2nd string
-/// Return <0 if 1st string < 2nd string
-/// \param pString1 Pointer to the start of the 1st string.
-/// \param pString2 Pointer to the start of the 2nd string.
-/// \param count Number of bytes that should be compared.
-//-----------------------------------------------------------------------------
-int strncmp(const char *pString1, const char *pString2, size_t count)
-{
- int r;
-
- while(count) {
- r = *pString1 - *pString2;
- if (r == 0) {
- if (*pString1 == 0) {
- break;
- }
- pString1++;
- pString2++;
- count--;
- continue;
- }
- return r;
- }
- return 0;
-}
-
-//-----------------------------------------------------------------------------
-/// Copy the first number of bytes from source string to destination string
-/// Return the pointer to the destination string.
-/// \param pDestination Pointer to the start of destination string.
-/// \param pSource Pointer to the start of the source string.
-/// \param count Number of bytes that should be copied.
-//-----------------------------------------------------------------------------
-char * strncpy(char *pDestination, const char *pSource, size_t count)
-{
- char *pSaveDest = pDestination;
-
- while (count) {
- *pDestination = *pSource;
- if (*pSource == 0) {
- break;
- }
- pDestination++;
- pSource++;
- count--;
- }
- return pSaveDest;
-}
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/trace.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/trace.c
deleted file mode 100644
index 4073bb9b..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/trace.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-
-#include "trace.h"
-
-//------------------------------------------------------------------------------
-// Internal variables
-//------------------------------------------------------------------------------
-
-/// Trace level can be set at applet initialization
-#if !defined(NOTRACE) && (DYN_TRACES == 1)
- unsigned int traceLevel = TRACE_LEVEL;
-#endif
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/trace.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/trace.h
deleted file mode 100644
index 63e7617a..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/trace.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-/// \file
-///
-/// \par Purpose
-///
-/// Standard output methods for reporting debug information, warnings and
-/// errors, which can be easily be turned on/off.
-///
-/// \par Usage
-/// -# Initialize the DBGU using TRACE_CONFIGURE() if you intend to eventually
-/// disable ALL traces; otherwise use DBGU_Configure().
-/// -# Uses the TRACE_DEBUG(), TRACE_INFO(), TRACE_WARNING(), TRACE_ERROR()
-/// TRACE_FATAL() macros to output traces throughout the program.
-/// -# Each type of trace has a level : Debug 5, Info 4, Warning 3, Error 2
-/// and Fatal 1. Disable a group of traces by changing the value of
-/// TRACE_LEVEL during compilation; traces with a level bigger than TRACE_LEVEL
-/// are not generated. To generate no trace, use the reserved value 0.
-/// -# Trace disabling can be static or dynamic. If dynamic disabling is selected
-/// the trace level can be modified in runtime. If static disabling is selected
-/// the disabled traces are not compiled.
-///
-/// \par traceLevels Trace level description
-/// -# TRACE_DEBUG (5): Traces whose only purpose is for debugging the program,
-/// and which do not produce meaningful information otherwise.
-/// -# TRACE_INFO (4): Informational trace about the program execution. Should
-/// enable the user to see the execution flow.
-/// -# TRACE_WARNING (3): Indicates that a minor error has happened. In most case
-/// it can be discarded safely; it may even be expected.
-/// -# TRACE_ERROR (2): Indicates an error which may not stop the program execution,
-/// but which indicates there is a problem with the code.
-/// -# TRACE_FATAL (1): Indicates a major error which prevents the program from going
-/// any further.
-
-//------------------------------------------------------------------------------
-
-#ifndef TRACE_H
-#define TRACE_H
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-
-#include
-#include
-#include
-
-//------------------------------------------------------------------------------
-// Global Definitions
-//------------------------------------------------------------------------------
-
-/// Softpack Version
-#define SOFTPACK_VERSION "1.0beta1"
-
-#define TRACE_LEVEL_DEBUG 5
-#define TRACE_LEVEL_INFO 4
-#define TRACE_LEVEL_WARNING 3
-#define TRACE_LEVEL_ERROR 2
-#define TRACE_LEVEL_FATAL 1
-#define TRACE_LEVEL_NO_TRACE 0
-
-// By default, all traces are output except the debug one.
-#if !defined(TRACE_LEVEL)
-#define TRACE_LEVEL TRACE_LEVEL_INFO
-#endif
-
-// By default, trace level is static (not dynamic)
-#if !defined(DYN_TRACES)
-#define DYN_TRACES 0
-#endif
-
-#if defined(NOTRACE)
-#error "Error: NOTRACE has to be not defined !"
-#endif
-
-#undef NOTRACE
-#if (DYN_TRACES==0)
- #if (TRACE_LEVEL == TRACE_LEVEL_NO_TRACE)
- #define NOTRACE
- #endif
-#endif
-
-
-
-//------------------------------------------------------------------------------
-// Global Macros
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Initializes the DBGU
-/// \param mode DBGU mode.
-/// \param baudrate DBGU baudrate.
-/// \param mck Master clock frequency.
-//------------------------------------------------------------------------------
-#define TRACE_CONFIGURE(mode, baudrate, mck) { \
- const Pin pinsDbgu[] = {PINS_DBGU}; \
- PIO_Configure(pinsDbgu, PIO_LISTSIZE(pinsDbgu)); \
- DBGU_Configure(mode, baudrate, mck); \
- }
-
-//------------------------------------------------------------------------------
-/// Initializes the DBGU for ISP project
-/// \param mode DBGU mode.
-/// \param baudrate DBGU baudrate.
-/// \param mck Master clock frequency.
-//------------------------------------------------------------------------------
-#ifndef DYNTRACE
-#define DYNTRACE 0
-#endif
-
-#if (TRACE_LEVEL==0) && (DYNTRACE==0)
-#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) {}
-#else
-#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) { \
- const Pin pinsDbgu[] = {PINS_DBGU}; \
- PIO_Configure(pinsDbgu, PIO_LISTSIZE(pinsDbgu)); \
- DBGU_Configure(mode, baudrate, mck); \
- }
-#endif
-
-//------------------------------------------------------------------------------
-/// Outputs a formatted string using if the log level is high
-/// enough. Can be disabled by defining TRACE_LEVEL=0 during compilation.
-/// \param format Formatted string to output.
-/// \param ... Additional parameters depending on formatted string.
-//------------------------------------------------------------------------------
-#if defined(NOTRACE)
-
-// Empty macro
-#define TRACE_DEBUG(...) { }
-#define TRACE_INFO(...) { }
-#define TRACE_WARNING(...) { }
-#define TRACE_ERROR(...) { }
-#define TRACE_FATAL(...) { while(1); }
-
-#define TRACE_DEBUG_WP(...) { }
-#define TRACE_INFO_WP(...) { }
-#define TRACE_WARNING_WP(...) { }
-#define TRACE_ERROR_WP(...) { }
-#define TRACE_FATAL_WP(...) { while(1); }
-
-#elif (DYN_TRACES == 1)
-
-// Trace output depends on traceLevel value
-#define TRACE_DEBUG(...) { if (traceLevel >= TRACE_LEVEL_DEBUG) { printf("-D- " __VA_ARGS__); } }
-#define TRACE_INFO(...) { if (traceLevel >= TRACE_LEVEL_INFO) { printf("-I- " __VA_ARGS__); } }
-#define TRACE_WARNING(...) { if (traceLevel >= TRACE_LEVEL_WARNING) { printf("-W- " __VA_ARGS__); } }
-#define TRACE_ERROR(...) { if (traceLevel >= TRACE_LEVEL_ERROR) { printf("-E- " __VA_ARGS__); } }
-#define TRACE_FATAL(...) { if (traceLevel >= TRACE_LEVEL_FATAL) { printf("-F- " __VA_ARGS__); while(1); } }
-
-#define TRACE_DEBUG_WP(...) { if (traceLevel >= TRACE_LEVEL_DEBUG) { printf(__VA_ARGS__); } }
-#define TRACE_INFO_WP(...) { if (traceLevel >= TRACE_LEVEL_INFO) { printf(__VA_ARGS__); } }
-#define TRACE_WARNING_WP(...) { if (traceLevel >= TRACE_LEVEL_WARNING) { printf(__VA_ARGS__); } }
-#define TRACE_ERROR_WP(...) { if (traceLevel >= TRACE_LEVEL_ERROR) { printf(__VA_ARGS__); } }
-#define TRACE_FATAL_WP(...) { if (traceLevel >= TRACE_LEVEL_FATAL) { printf(__VA_ARGS__); while(1); } }
-
-#else
-
-// Trace compilation depends on TRACE_LEVEL value
-#if (TRACE_LEVEL >= TRACE_LEVEL_DEBUG)
-#define TRACE_DEBUG(...) { printf("-D- " __VA_ARGS__); }
-#define TRACE_DEBUG_WP(...) { printf(__VA_ARGS__); }
-#else
-#define TRACE_DEBUG(...) { }
-#define TRACE_DEBUG_WP(...) { }
-#endif
-
-#if (TRACE_LEVEL >= TRACE_LEVEL_INFO)
-#define TRACE_INFO(...) { printf("-I- " __VA_ARGS__); }
-#define TRACE_INFO_WP(...) { printf(__VA_ARGS__); }
-#else
-#define TRACE_INFO(...) { }
-#define TRACE_INFO_WP(...) { }
-#endif
-
-#if (TRACE_LEVEL >= TRACE_LEVEL_WARNING)
-#define TRACE_WARNING(...) { printf("-W- " __VA_ARGS__); }
-#define TRACE_WARNING_WP(...) { printf(__VA_ARGS__); }
-#else
-#define TRACE_WARNING(...) { }
-#define TRACE_WARNING_WP(...) { }
-#endif
-
-#if (TRACE_LEVEL >= TRACE_LEVEL_ERROR)
-#define TRACE_ERROR(...) { printf("-E- " __VA_ARGS__); }
-#define TRACE_ERROR_WP(...) { printf(__VA_ARGS__); }
-#else
-#define TRACE_ERROR(...) { }
-#define TRACE_ERROR_WP(...) { }
-#endif
-
-#if (TRACE_LEVEL >= TRACE_LEVEL_FATAL)
-#define TRACE_FATAL(...) { printf("-F- " __VA_ARGS__); while(1); }
-#define TRACE_FATAL_WP(...) { printf(__VA_ARGS__); while(1); }
-#else
-#define TRACE_FATAL(...) { while(1); }
-#define TRACE_FATAL_WP(...) { while(1); }
-#endif
-
-#endif
-
-
-//------------------------------------------------------------------------------
-// Exported variables
-//------------------------------------------------------------------------------
-// Depending on DYN_TRACES, traceLevel is a modifable runtime variable
-// or a define
-#if !defined(NOTRACE) && (DYN_TRACES == 1)
- extern unsigned int traceLevel;
-#endif
-
-#endif //#ifndef TRACE_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/util.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/util.c
deleted file mode 100644
index b2bd0dea..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/util.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-#include
-#include
-#include
-
-//------------------------------------------------------------------------------
-// Local Variables
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Print char if printable. If not print a point
-/// \param c char to
-//------------------------------------------------------------------------------
-static void PrintChar(unsigned char c)
-{
- if( (/*c >= 0x00 &&*/ c <= 0x1F) ||
- (c >= 0xB0 && c <= 0xDF) ) {
-
- printf(".");
- }
- else {
-
- printf("%c", c);
- }
-}
-
-//------------------------------------------------------------------------------
-// Global Functions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Displays the content of the given frame on the DBGU.
-/// \param pBuffer Pointer to the frame to dump.
-/// \param size Buffer size in bytes.
-//------------------------------------------------------------------------------
-void UTIL_DbguDumpFrame(unsigned char *pFrame, unsigned int size)
-{
- unsigned int i;
-
- for (i=0; i < size; i++) {
- printf("%02X ", pFrame[i]);
- }
-
- printf("\n\r");
-}
-
-//------------------------------------------------------------------------------
-/// Displays the content of the given buffer on the DBGU.
-/// \param pBuffer Pointer to the buffer to dump.
-/// \param size Buffer size in bytes.
-/// \param address Start address to display
-//------------------------------------------------------------------------------
-void UTIL_DbguDumpMemory(
- unsigned char *pBuffer,
- unsigned int size,
- unsigned int address
- )
-{
- unsigned int i, j;
- unsigned int lastLineStart;
- unsigned char* pTmp;
-
- for (i=0; i < (size / 16); i++) {
-
- printf("0x%08X: ", address + (i*16));
- pTmp = (unsigned char*)&pBuffer[i*16];
- for (j=0; j < 4; j++) {
- printf("%02X%02X%02X%02X ", pTmp[0],pTmp[1],pTmp[2],pTmp[3]);
- pTmp += 4;
- }
-
- pTmp = (unsigned char*)&pBuffer[i*16];
- for (j=0; j < 16; j++) {
- PrintChar(*pTmp++);
- }
-
- printf("\n\r");
- }
-
- if( (size%16) != 0) {
- lastLineStart = size - (size%16);
- printf("0x%08X: ", address + lastLineStart);
-
- for (j= lastLineStart; j < lastLineStart+16; j++) {
-
- if( (j!=lastLineStart) && (j%4 == 0) ) {
- printf(" ");
- }
- if(j= '0' && key <= '9' ) {
- value = (value * 10) + (key - '0');
- nbNb++;
- }
- else if(key == 0x0D || key == ' ') {
- if(nbNb == 0) {
- printf("\n\rWrite a number and press ENTER or SPACE!\n\r");
- return 0;
- } else {
- printf("\n\r");
- *pValue = value;
- return 1;
- }
- } else {
- printf("\n\r'%c' not a number!\n\r", key);
- return 0;
- }
- }
-}
-
-//------------------------------------------------------------------------------
-/// Reads an integer and check the value
-//------------------------------------------------------------------------------
-unsigned char UTIL_DbguGetIntegerMinMax(
- unsigned int *pValue,
- unsigned int min,
- unsigned int max
- )
-{
- unsigned int value = 0;
-
- if( UTIL_DbguGetInteger(&value) == 0) {
- return 0;
- }
-
- if(value < min || value > max) {
- printf("\n\rThe number have to be between %d and %d\n\r", min, max);
- return 0;
- }
-
- printf("\n\r");
- *pValue = value;
- return 1;
-}
-
-//------------------------------------------------------------------------------
-/// Reads an hexadecimal number
-//------------------------------------------------------------------------------
-unsigned char UTIL_DbguGetHexa32(unsigned int *pValue)
-{
- unsigned char key;
- unsigned int i = 0;
- unsigned int value = 0;
- for(i = 0; i < 8; i++) {
- key = DBGU_GetChar();
- DBGU_PutChar(key);
- if(key >= '0' && key <= '9' ) {
- value = (value * 16) + (key - '0');
- }
- else if(key >= 'A' && key <= 'F' ) {
- value = (value * 16) + (key - 'A' + 10) ;
- }
- else if(key >= 'a' && key <= 'f' ) {
- value = (value * 16) + (key - 'a' + 10) ;
- }
- else {
- printf("\n\rIt is not a hexa character!\n\r");
- return 0;
- }
- }
-
- printf("\n\r");
- *pValue = value;
- return 1;
-}
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/util.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/util.h
deleted file mode 100644
index f79ffd3f..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/util.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-#ifndef UTIL_H
-#define UTIL_H
-
-//------------------------------------------------------------------------------
-// Global Functions
-//------------------------------------------------------------------------------
-
-extern void UTIL_DbguDumpFrame(unsigned char *pFrame, unsigned int size);
-
-extern void UTIL_DbguDumpMemory(unsigned char *pBuffer, unsigned int size, unsigned int address);
-
-extern unsigned char UTIL_DbguGetInteger(unsigned int *pValue);
-
-extern unsigned char UTIL_DbguGetIntegerMinMax(unsigned int *pValue, unsigned int min, unsigned int max);
-
-extern unsigned char UTIL_DbguGetHexa32(unsigned int *pValue);
-
-#endif //#ifndef UTIL_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/utility.dir b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/utility.dir
deleted file mode 100644
index 344ef5a6..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/utility.dir
+++ /dev/null
@@ -1,50 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-/// \dir
-///
-/// !!!Purpose
-///
-/// The utility directory contains several very small APIs for performing
-/// specific tasks, such as LED configuration, BMP header decoding, etc.
-///
-/// !!!Contents
-///
-/// Most modules contained here are very small and do not fit in any of the
-/// other at91lib categories. They primarily provide helper functions
-/// (e.g. for handling BMP and WAV files) and re-implementation of libc code for
-/// reducing code size (math, stdio, string).
-///
-/// Two important files are assert.h and trace.h. The first one provides macros
-/// for run-time verifications of parameters & values. Trace.h enables the
-/// programmer to add debug traces to APIs that can be easily turned on or off
-/// depending on the debugging needs.
-//------------------------------------------------------------------------------
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/video.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/video.c
deleted file mode 100644
index 49ec1da2..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/video.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-#include "video.h"
-
-//-----------------------------------------------------------------------------
-/// Conversion YCrCb to RGB:
-/// R = 1.164(Yi – 16) + 1.596(Cr – 128)
-/// G = 1.164(Yi – 16) – 0.813(Cr – 128) – 0.391(Cb – 128)
-/// B = 1.164(Yi – 16) + 2.018(Cb – 128)
-///
-/// Pixel i+1:
-/// YCrCb to RGB:
-/// R = 1.164(Yi+1 – 16) + 1.596(Cr – 128)
-/// G = 1.164(Yi+1 – 16) – 0.813(Cr – 128) – 0.391(Cb – 128)
-/// B = 1.164(Yi+1 – 16) + 2.018(Cb – 128)
-/// \param ycc Source buffer (YCC)
-/// \param rgb Destination buffer (RGB)
-/// \param len Length of buffer
-//-----------------------------------------------------------------------------
-void VIDEO_Ycc2Rgb(unsigned char *ycc, unsigned short *rgb, unsigned int len)
-{
- int r_calc_i;
- int g_calc_i;
- int b_calc_i;
- int r_calc_i_incr;
- int g_calc_i_incr;
- int b_calc_i_incr;
- int cr_i;
- int y_i;
- int cb_i;
- int y_i_incr;
- int val;
- int val1;
- int val2;
- int val3;
- int val4;
- int val5;
- int i;
-
- for(i=0; i 255)
- r_calc_i = 255;
-
- if (g_calc_i < 0)
- g_calc_i = 0;
- else if (g_calc_i > 255)
- g_calc_i = 255;
-
- if (b_calc_i < 0)
- b_calc_i = 0;
- else if (b_calc_i > 255)
- b_calc_i = 255;
-
- if (r_calc_i_incr < 0)
- r_calc_i_incr = 0;
- else if (r_calc_i_incr > 255)
- r_calc_i_incr = 255;
-
- if (g_calc_i_incr < 0)
- g_calc_i_incr = 0;
- else if (g_calc_i_incr > 255)
- g_calc_i_incr = 255;
-
- if (b_calc_i_incr < 0)
- b_calc_i_incr = 0;
- else if (b_calc_i_incr > 255)
- b_calc_i_incr = 255;
-
- *rgb++ = (((unsigned short )r_calc_i & 0xF8) >> 3)
- | ((((unsigned short)g_calc_i & 0xF8) >> 3) << 5)
- | ((((unsigned short)b_calc_i & 0xF8) >> 3) << 10);
-
- *rgb++ = (((unsigned short )r_calc_i_incr & 0xF8) >> 3)
- | ((((unsigned short)g_calc_i_incr & 0xF8) >> 3) << 5)
- | ((((unsigned short)b_calc_i_incr & 0xF8) >> 3) << 10);
- }
-}
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/video.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/video.h
deleted file mode 100644
index c4940e51..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/video.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-/// \unit
-///
-/// !!!Purpose
-///
-/// Video structure, used for LCD and ISI.
-/// Conversion Video from YCC to RGB
-///
-//------------------------------------------------------------------------------
-
-#ifndef _VIDEO_H
-#define _VIDEO_H
-
-//-----------------------------------------------------------------------------
-// Definitions
-//-----------------------------------------------------------------------------
-/// Type of video is YUV
-#define YUV 0
-/// Type of video is RGB
-#define RGB 1
-
-//-----------------------------------------------------------------------------
-/// Video structure
-//-----------------------------------------------------------------------------
-typedef struct _AT91S_VIDEO
-{
- /// LCD Vertical Size
- unsigned int lcd_vsize;
- /// LCD Horizontal Size
- unsigned int lcd_hsize;
- /// LCD Number of Bit Per Pixel
- unsigned int lcd_nbpp;
- /// LCD Frame Buffer Address
- unsigned int lcd_fb_addr;
- /// Base address for the frame buffer descriptors list
- unsigned int Isi_fbd_base;
- /// Start of Line Delay
- unsigned int Hblank;
- /// Start of frame Delay
- unsigned int Vblank;
- /// Vertical size of the Image sensor [0..2047]
- unsigned int codec_vsize;
- /// Horizontal size of the Image sensor [0..2047]
- unsigned int codec_hsize;
- /// Base address for codec DMA
- unsigned int codec_fb_addr;
- /// Buffer index
- unsigned int IsiPrevBuffIndex;
- /// Type of video
- unsigned char rgb_or_yuv;
-}AT91S_VIDEO, *AT91PS_VIDEO;
-
-
-//------------------------------------------------------------------------------
-// Exported functions
-//------------------------------------------------------------------------------
-extern void VIDEO_Ycc2Rgb(unsigned char *ycc, unsigned short *rgb, unsigned int len);
-
-#endif
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/wav.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/wav.c
deleted file mode 100644
index cd75b151..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/wav.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-
-#include "wav.h"
-#include
-
-//------------------------------------------------------------------------------
-// Internal constants
-//------------------------------------------------------------------------------
-
-/// WAV letters "RIFF"
-#define WAV_CHUNKID 0x46464952
-/// WAV letters "WAVE"
-#define WAV_FORMAT 0x45564157
-/// WAV letters "fmt "
-#define WAV_SUBCHUNKID 0x20746D66
-
-//------------------------------------------------------------------------------
-// Exported functions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Returns 1 if the header of a Wav file is valid; otherwise returns 0.
-/// \param file Buffer holding the file to examinate.
-//------------------------------------------------------------------------------
-unsigned char WAV_IsValid(const WavHeader *header)
-{
- return ((header->chunkID == WAV_CHUNKID)
- && (header->format == WAV_FORMAT)
- && (header->subchunk1Size == 0x10));
-}
-
-//------------------------------------------------------------------------------
-/// Display the information of the WAV file (sample rate, stereo/mono and frame
-/// size).
-//------------------------------------------------------------------------------
-void WAV_DisplayInfo(const WavHeader *header)
-{
- printf( "Wave file header information\n\r");
- printf( "--------------------------------\n\r");
- printf( " - Chunk ID = 0x%08X\n\r", header->chunkID);
- printf( " - Chunk Size = %d\n\r", header->chunkSize);
- printf( " - Format = 0x%08X\n\r", header->format);
- printf( " - SubChunk ID = 0x%08X\n\r", header->subchunk1ID);
- printf( " - Subchunk1 Size = %d\n\r", header->subchunk1Size);
- printf( " - Audio Format = 0x%04X\n\r", header->audioFormat);
- printf( " - Num. Channels = %d\n\r", header->numChannels);
- printf( " - Sample Rate = %d\n\r", header->sampleRate);
- printf( " - Byte Rate = %d\n\r", header->byteRate);
- printf( " - Block Align = %d\n\r", header->blockAlign);
- printf( " - Bits Per Sample = %d\n\r", header->bitsPerSample);
- printf( " - Subchunk2 ID = 0x%08X\n\r", header->subchunk2ID);
- printf( " - Subchunk2 Size = %d\n\r", header->subchunk2Size);
-}
\ No newline at end of file
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/wav.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/wav.h
deleted file mode 100644
index 4d26e84c..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/wav.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2008, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-#ifndef WAV_H
-#define WAV_H
-
-//------------------------------------------------------------------------------
-// Exported types
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Standard WAV file header information.
-//------------------------------------------------------------------------------
-typedef struct _WavHeader
-{
- /// Contains the letters "RIFF" in ASCII form.
- unsigned int chunkID;
- /// Size of the rest of the chunk following this number.
- unsigned int chunkSize;
- /// Contains the letters "WAVE".
- unsigned int format;
- /// Contains the letters "fmt ".
- unsigned int subchunk1ID;
- /// 16 for PCM. This is the size of the rest of the Subchunk
- /// which follows this number.
- unsigned int subchunk1Size;
- /// PCM = 1 (i.e. Linear quantization). Values other than 1 indicate some
- /// form of compression.
- unsigned short audioFormat;
- /// Mono = 1, Stereo = 2, etc.
- unsigned short numChannels;
- /// 8000, 44100, etc.
- unsigned int sampleRate;
- /// SampleRate * NumChannels * BitsPerSample/8
- unsigned int byteRate;
- /// NumChannels * BitsPerSample/8
- unsigned short blockAlign;
- /// 8 bits = 8, 16 bits = 16, etc.
- unsigned short bitsPerSample;
- /// Contains the letters "data".
- unsigned int subchunk2ID;
- /// Number of bytes in the data.
- unsigned int subchunk2Size;
-
-} WavHeader;
-
-//------------------------------------------------------------------------------
-// Exported functions
-//------------------------------------------------------------------------------
-
-extern unsigned char WAV_IsValid(const WavHeader *header);
-
-extern void WAV_DisplayInfo(const WavHeader *header);
-
-#endif //#ifndef WAV_H
-
diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/wdt/wdt.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/wdt/wdt.c
deleted file mode 100644
index 6d4f4a3d..00000000
--- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/wdt/wdt.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support
- * ----------------------------------------------------------------------------
- * Copyright (c) 2009, Atmel Corporation
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaimer below.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-/**
- * \file
- *
- * Implementation of Watchdog Timer (WDT) controller.
- *
- */
-
-/** \addtogroup wdt_module Working with WDT
- * The WDT driver provides the interface to configure and use the WDT
- * peripheral.
- *
- * The WDT can be used to prevent system lock-up if the software becomes
- * trapped in a deadlock. It can generate a general reset or a processor
- * reset only. It is clocked by slow clock divided by 128.
- *
- * The WDT is running at reset with 16 seconds watchdog period (slow clock at 32.768 kHz)
- * and external reset generation enabled. The user must either disable it or
- * reprogram it to meet the application requires.
- *
- * To use the WDT, the user could follow these few steps:
- *