Merge pull request #2 from Tencent/master

merge to trunk
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mybays 2019-11-08 16:24:38 +08:00 committed by GitHub
commit 67ce1afba2
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1748 changed files with 581604 additions and 87362 deletions

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@ -69,9 +69,9 @@ TencentOS tiny目前支持STM32、NXP、华大半导体、国民技术、GD32、
# 三、TencentOS tiny 参考文档
## 1、移植指南
- [TencentOS tiny移植指南KEIL版本](./doc/TencentOS-tiny-porting-keil.md)
- [TencentOS tiny移植指南IAR版本](./doc/TencentOS-tiny-porting-iar.md)
- [TencentOS tiny移植指南GCC版本](./doc/TencentOS-tiny-porting-gcc.md)
- [TencentOS tiny移植指南KEIL版本](./doc/TencentOS-tiny-porting-guide-keil.md)
- [TencentOS tiny移植指南IAR版本](./doc/TencentOS-tiny-porting-guide-iar.md)
- [TencentOS tiny移植指南GCC版本](./doc/TencentOS-tiny-porting-guide-gcc.md)
## 2、TencentOS tiny 开发指南
- [TencentOS tiny内核开发指南](./doc/4.TencentOS-tiny开发指南.md)
@ -109,9 +109,13 @@ TencentOS tiny联合合作伙伴(南京厚德物联网)设计了定制开发板
# 九、第三方开发者评测
感谢CSDN博客专家杰杰的贡献
1.基于TencentOS tiny 的环境监测实战项目
[【TencentOS tiny】环境监测实战项目最终完整版](https://www.bilibili.com/video/av73782956?from=search&seid=4421984671929108231)
感谢阿正的贡献
基于野火stm32f103开发板上移植的TencentOS tiny 例程、源码剖析、视频讲解。
2.基于野火stm32f103开发板上移植的TencentOS tiny 例程、源码剖析、视频讲解。
感谢CSDN博客专家杰杰的贡献
## 简单上手:

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@ -86,9 +86,9 @@ TencentOS tiny currently supports mainstream MCUs such as STM32, NXP, Huada Semi
# TencentOS tiny reference documentation
## 1、Porting guide
- [TencentOS tiny Porting guideKEIL version](./doc/TencentOS-tiny-porting-keil.md)
- [TencentOS tiny Porting guideIAR version](./doc/TencentOS-tiny-porting-iar.md)
- [TencentOS tiny Porting guideGCC version](./doc/TencentOS-tiny-porting-gcc.md)
- [TencentOS tiny Porting guideKEIL version](./doc/TencentOS-tiny-porting-guide-keil.md)
- [TencentOS tiny Porting guideIAR version](./doc/TencentOS-tiny-porting-guide-iar.md)
- [TencentOS tiny Porting guideGCC version](./doc/TencentOS-tiny-porting-guide-gcc.md)
## 2、Development guide
- [TencentOS tiny Kernel development guide](./doc/4.TencentOS-tiny开发指南.md)

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@ -0,0 +1,141 @@
/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#ifndef _TOS_CPU_H_
#define _TOS_CPU_H_
typedef struct cpu_context_st {
cpu_data_t _R4;
cpu_data_t _R5;
cpu_data_t _R6;
cpu_data_t _R7;
cpu_data_t _R8;
cpu_data_t _R9;
cpu_data_t _R10;
cpu_data_t _R11;
#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U)
cpu_data_t EXC_RETURN;
#endif
cpu_data_t _R0;
cpu_data_t _R1;
cpu_data_t _R2;
cpu_data_t _R3;
cpu_data_t _R12;
cpu_data_t _R14;
cpu_data_t _PC;
cpu_data_t _xPSR;
} cpu_context_t;
__API__ uint32_t tos_cpu_clz(uint32_t val);
__API__ void tos_cpu_int_disable(void);
__API__ void tos_cpu_int_enable(void);
__API__ cpu_cpsr_t tos_cpu_cpsr_save(void);
__API__ void tos_cpu_cpsr_restore(cpu_cpsr_t cpsr);
#if (TOS_CFG_CPU_HRTIMER_EN > 0u)
__API__ void tos_cpu_hrtimer_init(void);
__API__ cpu_hrtimer_t tos_cpu_hrtimer_read(void);
#endif
__KERNEL__ void cpu_init(void);
__KERNEL__ void cpu_reset(void);
__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick);
__KERNEL__ void cpu_sched_start(void);
__KERNEL__ void cpu_context_switch(void);
__KERNEL__ void cpu_irq_context_switch(void);
#if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u
__KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth);
#endif
__KERNEL__ k_stack_t *cpu_task_stk_init(void *entry,
void *arg,
void *exit,
k_stack_t *stk_base,
size_t stk_size);
#if TOS_CFG_TICKLESS_EN > 0u
__KERNEL__ void cpu_systick_resume(void);
__KERNEL__ void cpu_systick_suspend(void);
__KERNEL__ void cpu_systick_reload_reset(void);
__KERNEL__ void cpu_systick_pending_reset(void);
__KERNEL__ k_time_t cpu_systick_max_delay_millisecond(void);
__KERNEL__ void cpu_systick_expires_set(k_time_t millisecond);
__KERNEL__ void cpu_systick_reset(void);
#endif
#if TOS_CFG_PWR_MGR_EN > 0u
__KERNEL__ void cpu_sleep_mode_enter(void);
__KERNEL__ void cpu_stop_mode_enter(void);
__KERNEL__ void cpu_standby_mode_enter(void);
#endif
#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U)
__KERNEL__ void cpu_flush_fpu(void);
#endif /* TOS_CFG_CPU_ARM_FPU_EN */
__KERNEL__ void cpu_fault_diagnosis(void);
#endif
/* Allocates CPU status register word. */
#define TOS_CPU_CPSR_ALLOC() cpu_cpsr_t cpu_cpsr = (cpu_cpsr_t)0u
/* Save CPU status word & disable interrupts.*/
#define TOS_CPU_INT_DISABLE() \
do { \
cpu_cpsr = tos_cpu_cpsr_save(); \
} while (0)
/* Restore CPU status word. */
#define TOS_CPU_INT_ENABLE() \
do { \
tos_cpu_cpsr_restore(cpu_cpsr); \
} while (0)
#endif /* _TOS_CPU_H_ */

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@ -0,0 +1,34 @@
/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#ifndef _TOS_CPU_DEF_H_
#define _TOS_CPU_DEF_H_
enum CPU_WORD_SIZE {
CPU_WORD_SIZE_08,
CPU_WORD_SIZE_16,
CPU_WORD_SIZE_32,
CPU_WORD_SIZE_64,
};
enum CPU_STK_GROWTH {
CPU_STK_GROWTH_ASCENDING,
CPU_STK_GROWTH_DESCENDING,
};
#endif /* _TOS_CPU_DEF_H_ */

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/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#ifndef _TOS_CPU_TYPES_H_
#define _TOS_CPU_TYPES_H_
/* CPU address type based on address bus size. */
#if (TOS_CFG_CPU_ADDR_SIZE == CPU_WORD_SIZE_32)
typedef uint32_t cpu_addr_t;
#elif (TOS_CFG_CPU_ADDR_SIZE == CPU_WORD_SIZE_16)
typedef uint16_t cpu_addr_t;
#else
typedef uint8_t cpu_addr_t;
#endif
/* CPU data type based on data bus size. */
#if (TOS_CFG_CPU_DATA_SIZE == CPU_WORD_SIZE_32)
typedef uint32_t cpu_data_t;
#elif (TOS_CFG_CPU_DATA_SIZE == CPU_WORD_SIZE_16)
typedef uint16_t cpu_data_t;
#else
typedef uint8_t cpu_data_t;
#endif
#if (TOS_CFG_CPU_HRTIMER_EN > 0)
#if (TOS_CFG_CPU_HRTIMER_SIZE == CPU_WORD_SIZE_08)
typedef uint8_t cpu_hrtimer_t;
#elif (TOS_CFG_CPU_HRTIMER_SIZE == CPU_WORD_SIZE_16)
typedef uint16_t cpu_hrtimer_t;
#elif (TOS_CFG_CPU_HRTIMER_SIZE == CPU_WORD_SIZE_64)
typedef uint64_t cpu_hrtimer_t;
#else
typedef uint32_t cpu_hrtimer_t;
#endif
#else
typedef uint32_t cpu_hrtimer_t;
#endif
//typedef cpu_addr_t size_t;
typedef cpu_addr_t cpu_cpsr_t;
#endif

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/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#ifndef _TOS_FAULT_H_
#define _TOS_FAULT_H_
#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
typedef int (*k_fault_log_writer_t)(const char *format, ...);
#define K_FAULT_STACK_DUMP_DEPTH 10u
#define K_FAULT_CALL_STACK_BACKTRACE_DEPTH 5u
#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U)
typedef struct fault_fpu_frame_st {
cpu_data_t s0;
cpu_data_t s1;
cpu_data_t s2;
cpu_data_t s3;
cpu_data_t s4;
cpu_data_t s5;
cpu_data_t s6;
cpu_data_t s7;
cpu_data_t s8;
cpu_data_t s9;
cpu_data_t s10;
cpu_data_t s11;
cpu_data_t s12;
cpu_data_t s13;
cpu_data_t s14;
cpu_data_t s15;
cpu_data_t fpscr;
} fault_fpu_frame_t;
#endif
typedef struct fault_cpu_frame_st {
cpu_data_t r0;
cpu_data_t r1;
cpu_data_t r2;
cpu_data_t r3;
cpu_data_t r12;
cpu_data_t lr;
cpu_data_t pc;
cpu_data_t spsr;
} fault_cpu_frame_t;
typedef struct fault_exc_frame_st {
fault_cpu_frame_t cpu_frame;
#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U)
fault_fpu_frame_t fpu_frame;
#endif
} fault_exc_frame_t;
/**
* information we need to do fault backtrace
*/
typedef struct fault_information_st {
int is_thumb : 1; /**< whether it is thumb we use when we fall into fault? */
int is_on_task : 1; /**< whether we are on a task when fall into fault? */
int is_stk_ovrf : 1; /**< whether we get a stack overflow */
#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U)
int is_ext_stk_frm : 1; /**< whether it is a extended stack frame?(whether the cpu has pushed fpu registers onto the stack) */
#endif
cpu_addr_t pc; /**< just where fault happens */
cpu_addr_t sp_before_fault; /**< original sp just before the cpu push the fault exception frame */
/**
* we need main_stack_start & main_stack_limit to do call stack backtrace
* when we fall into fault during a task, we should do the call stack backtrace on the task's stack
* but if not, which means we are in kernel, we should do the call stack backtrace on the main stack
* in arm v7-m, this should be the MSP's start and limit
* in arm v7-a, call stack backtrace is another story(much more elegant because we have FP).
*/
cpu_addr_t stack_start; /**< current sp start address we use. if on task, it'll be the task's stack, otherwise it'll be the msp */
cpu_addr_t stack_limit; /**< current sp limit address */
cpu_addr_t code_start; /**< current code start address */
cpu_addr_t code_limit; /**< current code limit address */
} fault_info_t;
#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#define DEFAULT_CODE_SECTION_NAME ER_IROM1
#define DEFAULT_CSTACK_SECTION_NAME STACK
#define SECTION_START(_name_) _name_##$$Base
#define SECTION_END(_name_) _name_##$$Limit
#define IMAGE_SECTION_START(_name_) Image$$##_name_##$$Base
#define IMAGE_SECTION_END(_name_) Image$$##_name_##$$Limit
#define CSTACK_BLOCK_START(_name_) SECTION_START(_name_)
#define CSTACK_BLOCK_END(_name_) SECTION_END(_name_)
#define CODE_SECTION_START(_name_) IMAGE_SECTION_START(_name_)
#define CODE_SECTION_END(_name_) IMAGE_SECTION_END(_name_)
extern const int CSTACK_BLOCK_START(DEFAULT_CSTACK_SECTION_NAME);
extern const int CSTACK_BLOCK_END(DEFAULT_CSTACK_SECTION_NAME);
extern const int CODE_SECTION_START(DEFAULT_CODE_SECTION_NAME);
extern const int CODE_SECTION_END(DEFAULT_CODE_SECTION_NAME);
__STATIC_INLINE__ cpu_addr_t fault_code_start(void)
{
return (cpu_addr_t)&CODE_SECTION_START(DEFAULT_CODE_SECTION_NAME);
}
__STATIC_INLINE__ cpu_addr_t fault_code_limit(void)
{
return (cpu_addr_t)&CODE_SECTION_END(DEFAULT_CODE_SECTION_NAME);
}
__STATIC_INLINE__ cpu_addr_t fault_msp_start(void)
{
return (cpu_addr_t)&CSTACK_BLOCK_START(DEFAULT_CSTACK_SECTION_NAME);
}
__STATIC_INLINE__ cpu_addr_t fault_msp_limit(void)
{
return (cpu_addr_t)&CSTACK_BLOCK_END(DEFAULT_CSTACK_SECTION_NAME);
}
#elif defined(__ICCARM__)
#define DEFAULT_CODE_SECTION_NAME ".text"
#define DEFAULT_CSTACK_SECTION_NAME "CSTACK"
#pragma section=DEFAULT_CSTACK_SECTION_NAME
#pragma section=DEFAULT_CODE_SECTION_NAME
__STATIC_INLINE__ cpu_addr_t fault_code_start(void)
{
return (cpu_addr_t)__section_begin(DEFAULT_CODE_SECTION_NAME);
}
__STATIC_INLINE__ cpu_addr_t fault_code_limit(void)
{
return (cpu_addr_t)__section_end(DEFAULT_CODE_SECTION_NAME);
}
__STATIC_INLINE__ cpu_addr_t fault_msp_start(void)
{
return (cpu_addr_t)__section_begin(DEFAULT_CSTACK_SECTION_NAME);
}
__STATIC_INLINE__ cpu_addr_t fault_msp_limit(void)
{
return (cpu_addr_t)__section_end(DEFAULT_CSTACK_SECTION_NAME);
}
#elif defined(__GNUC__)
/**
* if we are using keil(armcc) or mdk(iccarm), we probably use the defult link script supplied by the IDE.
* the way to locate the text/stack section start and limit is to find them in default link script.
* but if we build our project by makefile(or something like scons, cmake, etc), we probably need to write
* our own link scrpit, if so, we should do like this(just a demo):
*
_stext = .;
.text : {
*(.text.startup)
*(.text)
*(.text.*)
}
_etext = .;
__bss_start = .;
.bss : {
*(.bss)
*(.bss.*)
*(COMMON)
_sstack = .;
*(.cstack)
_estack = .;
}
__bss_end = .;
* by this, we can locate text/stack section start and limit by _stext/_etext and _sstack/_estack
*/
#define DEFAULT_CODE_SECTION_START _stext
#define DEFAULT_CODE_SECTION_END _etext
#define DEFAULT_CSTACK_SECTION_START _sstack
#define DEFAULT_CSTACK_SECTION_END _estack
extern const int DEFAULT_CODE_SECTION_START;
extern const int DEFAULT_CODE_SECTION_END;
extern const int DEFAULT_CSTACK_SECTION_START;
extern const int DEFAULT_CSTACK_SECTION_END;
__STATIC_INLINE__ cpu_addr_t fault_code_start(void)
{
return (cpu_addr_t)(&(DEFAULT_CODE_SECTION_START));
}
__STATIC_INLINE__ cpu_addr_t fault_code_limit(void)
{
return (cpu_addr_t)(&(DEFAULT_CODE_SECTION_END));
}
__STATIC_INLINE__ cpu_addr_t fault_msp_start(void)
{
return (cpu_addr_t)(&(DEFAULT_CSTACK_SECTION_START));
}
__STATIC_INLINE__ cpu_addr_t fault_msp_limit(void)
{
return (cpu_addr_t)(&(DEFAULT_CSTACK_SECTION_END));
}
#endif
__API__ void tos_fault_log_writer_set(k_fault_log_writer_t log_writer);
__KERNEL__ int fault_default_log_writer(const char *format, ...);
__KERNEL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame);
#endif
#endif /* _TOS_FAULT_H_ */

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/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#include <tos.h>
__API__ uint32_t tos_cpu_clz(uint32_t val)
{
#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 0u)
uint32_t nbr_lead_zeros = 0;
if (!(val & 0XFFFF0000)) {
val <<= 16;
nbr_lead_zeros += 16;
}
if (!(val & 0XFF000000)) {
val <<= 8;
nbr_lead_zeros += 8;
}
if (!(val & 0XF0000000)) {
val <<= 4;
nbr_lead_zeros += 4;
}
if (!(val & 0XC0000000)) {
val <<= 2;
nbr_lead_zeros += 2;
}
if (!(val & 0X80000000)) {
nbr_lead_zeros += 1;
}
if (!val) {
nbr_lead_zeros += 1;
}
return (nbr_lead_zeros);
#else
return port_clz(val);
#endif
}
__API__ void tos_cpu_int_disable(void)
{
port_int_disable();
}
__API__ void tos_cpu_int_enable(void)
{
port_int_enable();
}
__API__ cpu_cpsr_t tos_cpu_cpsr_save(void)
{
return port_cpsr_save();
}
__API__ void tos_cpu_cpsr_restore(cpu_cpsr_t cpsr)
{
port_cpsr_restore(cpsr);
}
__KERNEL__ void cpu_init(void)
{
k_cpu_cycle_per_tick = TOS_CFG_CPU_CLOCK / k_cpu_tick_per_second;
cpu_systick_init(k_cpu_cycle_per_tick);
#if (TOS_CFG_CPU_HRTIMER_EN > 0)
tos_cpu_hrtimer_init();
#endif
}
__KERNEL__ void cpu_reset(void)
{
port_cpu_reset();
}
__KERNEL__ void cpu_sched_start(void)
{
port_sched_start();
}
__KERNEL__ void cpu_context_switch(void)
{
port_context_switch();
}
__KERNEL__ void cpu_irq_context_switch(void)
{
port_irq_context_switch();
}
__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick)
{
port_systick_priority_set(TOS_CFG_CPU_SYSTICK_PRIO);
port_systick_config(cycle_per_tick);
}
#if TOS_CFG_TICKLESS_EN > 0u
/**
* @brief Set value to systick reload value register
*
* @param cycles The value set to register
*
* @return None
*/
__STATIC_INLINE__ void cpu_systick_reload(k_cycle_t cycle_per_tick)
{
port_systick_reload(cycle_per_tick);
}
/**
* @brief Enable systick interrupt
*
* @return None
*/
__KERNEL__ void cpu_systick_resume(void)
{
port_systick_resume();
}
/**
* @brief Disable systick interrupt
*
* @return None
*/
__KERNEL__ void cpu_systick_suspend(void)
{
port_systick_suspend();
}
__KERNEL__ k_time_t cpu_systick_max_delay_millisecond(void)
{
return port_systick_max_delay_millisecond();
}
__KERNEL__ void cpu_systick_expires_set(k_time_t millisecond)
{
k_cycle_t cycles;
cycles = (k_cycle_t)((uint64_t)millisecond * TOS_CFG_CPU_CLOCK / K_TIME_MILLISEC_PER_SEC); /* CLOCK means cycle per second */
cpu_systick_reload(cycles - 12); /* interrupt delay */
}
__KERNEL__ void cpu_systick_pending_reset(void)
{
port_systick_pending_reset();
}
__KERNEL__ void cpu_systick_reset(void)
{
cpu_systick_reload(k_cpu_cycle_per_tick);
}
#endif /* TOS_CFG_TICKLESS_EN */
#if TOS_CFG_PWR_MGR_EN > 0u
__KERNEL__ void cpu_sleep_mode_enter(void)
{
port_sleep_mode_enter();
}
__KERNEL__ void cpu_stop_mode_enter(void)
{
port_stop_mode_enter();
}
__KERNEL__ void cpu_standby_mode_enter(void)
{
port_standby_mode_enter();
}
#endif /* TOS_CFG_PWR_MGR_EN */
__KERNEL__ k_stack_t *cpu_task_stk_init(void *entry,
void *arg,
void *exit,
k_stack_t *stk_base,
size_t stk_size)
{
cpu_data_t *sp;
sp = (cpu_data_t *)&stk_base[stk_size];
sp = (cpu_data_t *)((cpu_addr_t)sp & 0xFFFFFFF8);
#if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u
uint8_t *slot = (uint8_t *)&stk_base[0];
for (; slot < (uint8_t *)sp; ++slot) {
*slot = 0xCC;
}
#endif
/* auto-saved on exception(pendSV) by hardware */
*--sp = (cpu_data_t)0x01000000u; /* xPSR */
*--sp = (cpu_data_t)entry; /* entry */
*--sp = (cpu_data_t)exit; /* R14 (LR) */
*--sp = (cpu_data_t)0x12121212u; /* R12 */
*--sp = (cpu_data_t)0x03030303u; /* R3 */
*--sp = (cpu_data_t)0x02020202u; /* R2 */
*--sp = (cpu_data_t)0x01010101u; /* R1 */
*--sp = (cpu_data_t)arg; /* R0: arg */
/* Remaining registers saved on process stack */
/* EXC_RETURN = 0xFFFFFFFDL
Initial state: Thread mode + non-floating-point state + PSP
31 - 28 : EXC_RETURN flag, 0xF
27 - 5 : reserved, 0xFFFFFE
4 : 1, basic stack frame; 0, extended stack frame
3 : 1, return to Thread mode; 0, return to Handler mode
2 : 1, return to PSP; 0, return to MSP
1 : reserved, 0
0 : reserved, 1
*/
#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U)
*--sp = (cpu_data_t)0xFFFFFFFDL;
#endif
*--sp = (cpu_data_t)0x11111111u; /* R11 */
*--sp = (cpu_data_t)0x10101010u; /* R10 */
*--sp = (cpu_data_t)0x09090909u; /* R9 */
*--sp = (cpu_data_t)0x08080808u; /* R8 */
*--sp = (cpu_data_t)0x07070707u; /* R7 */
*--sp = (cpu_data_t)0x06060606u; /* R6 */
*--sp = (cpu_data_t)0x05050505u; /* R5 */
*--sp = (cpu_data_t)0x04040404u; /* R4 */
return (k_stack_t *)sp;
}
#if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u
__KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth)
{
uint8_t *slot;
uint8_t *sp, *bp;
int the_depth = 0;
bp = (uint8_t *)&stk_base[0];
sp = &stk_base[stk_size];
sp = (uint8_t *)((cpu_addr_t)sp & 0xFFFFFFF8);
for (slot = sp - 1; slot >= bp; --slot) {
if (*slot != 0xCC) {
the_depth = sp - slot;
}
}
*depth = the_depth;
if (the_depth == stk_size) {
return K_ERR_TASK_STK_OVERFLOW;
}
return K_ERR_NONE;
}
#endif
#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U)
__KERNEL__ void cpu_flush_fpu(void)
{
(void)__get_FPSCR();
}
#endif
__KERNEL__ void cpu_fault_diagnosis(void)
{
port_fault_diagnosis();
}
#endif /* TOS_CFG_FAULT_BACKTRACE_EN */

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/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#include "tos.h"
#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
__STATIC_INLINE__ void fault_spin(void)
{
tos_knl_sched_lock();
tos_cpu_int_disable();
while (K_TRUE) {
;
}
}
/* EXC_RETURN:
31 - 28 : EXC_RETURN flag
27 - 5 : reserved
4 : 1, basic stack frame; 0, extended stack frame
3 : 1, return to Thread mode; 0, return to Handler mode
2 : 1, return to PSP; 0, return to MSP
1 : reserved, 0
0 : reserved, 1
*/
__STATIC_INLINE__ int fault_is_on_task(cpu_data_t lr)
{
return (lr & (1u << 2)) != 0;
}
__STATIC_INLINE__ int fault_is_thumb(cpu_data_t psr)
{
return (psr & (1u << 24)) != 0;
}
__STATIC_INLINE__ int fault_is_code(fault_info_t *info, cpu_data_t value)
{
return value >= info->code_start && value <= info->code_limit;
}
#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U)
__STATIC_INLINE__ int fault_is_extended_stack_frame(cpu_data_t lr)
{
return (lr & (1u << 4)) == 0;
}
__STATIC__ void fault_dump_fpu_frame(fault_fpu_frame_t *fpu_frame)
{
/*
* As known, v7-m has a feature named "LAZY PUSH", for the reason we do not do any float
* operation in fault_backtrace, cpu will not do the real fpu register push to the stack.
* that means the value we dump in fault_dump_fpu_frame will not be the correct value of
* each FPU register.
* We define a function here which access to FPSCR, if this function involved, cpu will do
* the real FPU register push so we will get the correct dump.
* I know it's ugly, but it works. If you know a better way, please tell me.
*/
cpu_flush_fpu();
k_fault_log_writer("\n\n====================== FPU Registers =======================\n");
k_fault_log_writer(" %s: %08x\n", "FPSCR", fpu_frame->fpscr);
k_fault_log_writer(" %s: %08x %s: %08x %s: %08x %s: %08x\n",
"S0 ", fpu_frame->s0,
"S1 ", fpu_frame->s1,
"S2 ", fpu_frame->s2,
"S3 ", fpu_frame->s3);
k_fault_log_writer(" %s: %08x %s: %08x %s: %08x %s: %08x\n",
"S4 ", fpu_frame->s4,
"S5 ", fpu_frame->s5,
"S6 ", fpu_frame->s6,
"S7 ", fpu_frame->s7);
k_fault_log_writer(" %s: %08x %s: %08x %s: %08x %s: %08x\n",
"S8 ", fpu_frame->s8,
"S9 ", fpu_frame->s9,
"S10", fpu_frame->s10,
"S11", fpu_frame->s11);
k_fault_log_writer(" %s: %08x %s: %08x %s: %08x %s: %08x\n",
"S12", fpu_frame->s12,
"S13", fpu_frame->s13,
"S14", fpu_frame->s14,
"S15", fpu_frame->s15);
}
#endif
__STATIC__ void fault_dump_cpu_frame(fault_cpu_frame_t *cpu_frame)
{
k_fault_log_writer("\n\n====================== CPU Registers =======================\n");
k_fault_log_writer(" %s: %08x %s: %08x %s: %08x %s: %08x\n",
"R0 ", cpu_frame->r0,
"R1 ", cpu_frame->r1,
"R2 ", cpu_frame->r2,
"R3 ", cpu_frame->r3);
k_fault_log_writer(" %s: %08x %s: %08x %s: %08x %s: %08x\n",
"R12", cpu_frame->r12,
"LR ", cpu_frame->lr,
"PC ", cpu_frame->pc,
"PSR", cpu_frame->spsr);
}
__STATIC__ void fault_dump_stack(fault_info_t *info, size_t depth)
{
cpu_addr_t sp = info->sp_before_fault;;
k_fault_log_writer("\nTASK STACK DUMP:\n");
while (sp <= info->stack_limit && depth--) {
k_fault_log_writer(" addr: %08x data: %08x\n", sp, (cpu_data_t)*(cpu_data_t *)sp);
sp += sizeof(cpu_addr_t);
}
}
__STATIC__ void fault_call_stack_backtrace(fault_info_t *info, size_t depth)
{
cpu_data_t value;
cpu_addr_t sp = info->sp_before_fault;
if (info->is_stk_ovrf) {
return;
}
k_fault_log_writer("\n\n====================== Dump Call Stack =====================\n");
k_fault_log_writer(" %x\n", info->pc);
/* walk through the stack, check every content on stack whether is a instruction(code) */
for (; sp < info->stack_limit && depth; sp += sizeof(cpu_addr_t)) {
value = *((cpu_addr_t *)sp) - sizeof(cpu_addr_t);
/* if thumb, a instruction's first bit must be 1 */
if (info->is_thumb && !(value & 1)) {
continue;
}
if (fault_is_code(info, value)) {
k_fault_log_writer(" %x\n", value);
--depth;
}
}
}
__STATIC__ void fault_dump_task(fault_info_t *info)
{
k_task_t *task;
if (!info->is_on_task) {
return;
}
task = k_curr_task;
k_fault_log_writer("\n\n====================== Fault on task =======================\n");
k_fault_log_writer(" TASK NAME: %s\n", task->name);
k_fault_log_writer(" STK BASE: %x\n", info->stack_start);
k_fault_log_writer(" STK SIZE: %x\n", task->stk_size * sizeof(k_stack_t));
k_fault_log_writer(" STK LIMIT: %x\n", info->stack_limit);
if (!info->is_stk_ovrf) {
fault_dump_stack(info, K_FAULT_STACK_DUMP_DEPTH);
}
}
__STATIC__ void fault_dump_information(fault_info_t *info)
{
k_fault_log_writer("\n\n================== Dump Fault Information ==================\n");
k_fault_log_writer(" THUMB: %s\n", info->is_thumb ? "TRUE" : "FALSE");
k_fault_log_writer(" ON TASK: %s\n", info->is_on_task? "TRUE" : "FALSE");
k_fault_log_writer(" STK OVRF: %s\n", info->is_stk_ovrf? "TRUE" : "FALSE");
#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U)
k_fault_log_writer(" EXT STK: %s\n", info->is_ext_stk_frm? "TRUE" : "FALSE");
#endif
k_fault_log_writer(" PC: %08x\n", info->pc);
k_fault_log_writer(" SP: %08x\n", info->sp_before_fault);
k_fault_log_writer(" STK START: %08x\n", info->stack_start);
k_fault_log_writer(" STK LIMIT: %08x\n", info->stack_limit);
k_fault_log_writer(" COD START: %08x\n", info->code_start);
k_fault_log_writer(" COD LIMIT: %08x\n", info->code_limit);
}
__STATIC__ void fault_gather_information(cpu_data_t lr, fault_exc_frame_t *frame, fault_info_t *info)
{
info->is_thumb = fault_is_thumb(frame->cpu_frame.spsr);
info->is_on_task = fault_is_on_task(lr);
info->pc = frame->cpu_frame.pc;
info->sp_before_fault = (cpu_addr_t)frame + sizeof(fault_cpu_frame_t);
#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U)
info->is_ext_stk_frm = fault_is_extended_stack_frame(lr);
if (info->is_ext_stk_frm) {
info->sp_before_fault += sizeof(fault_fpu_frame_t);
}
#endif
info->code_start = fault_code_start();
info->code_limit = fault_code_limit();
if (info->is_on_task) {
info->stack_start = (cpu_addr_t)k_curr_task->stk_base;
info->stack_limit = info->stack_start + k_curr_task->stk_size * sizeof(k_task_t);
} else {
info->stack_start = fault_msp_start();
info->stack_limit = fault_msp_limit();
}
info->is_stk_ovrf = (info->sp_before_fault < info->stack_start || info->sp_before_fault > info->stack_limit);
}
__KERNEL__ int fault_default_log_writer(const char *format, ...)
{
int len;
va_list ap;
va_start(ap, format);
len = vprintf(format, ap);
va_end(ap);
return len;
}
__API__ void tos_fault_log_writer_set(k_fault_log_writer_t log_writer)
{
k_fault_log_writer = log_writer;
}
__KERNEL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame)
{
fault_info_t info;
fault_gather_information(lr, frame, &info);
fault_dump_information(&info);
fault_dump_task(&info);
fault_dump_cpu_frame(&frame->cpu_frame);
#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U)
if (info.is_ext_stk_frm) {
fault_dump_fpu_frame(&frame->fpu_frame);
}
#endif
fault_call_stack_backtrace(&info, K_FAULT_CALL_STACK_BACKTRACE_DEPTH);
cpu_fault_diagnosis();
fault_spin();
}
#endif

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/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#ifndef _PORT_H_
#define _PORT_H_
__PORT__ void port_int_disable(void);
__PORT__ void port_int_enable(void);
__PORT__ cpu_cpsr_t port_cpsr_save(void);
__PORT__ void port_cpsr_restore(cpu_cpsr_t cpsr);
__PORT__ void port_cpu_reset(void);
__PORT__ void port_sched_start(void) __NO_RETURN__;
__PORT__ void port_context_switch(void);
__PORT__ void port_irq_context_switch(void);
__PORT__ void port_systick_config(uint32_t cycle_per_tick);
__PORT__ void port_systick_priority_set(uint32_t prio);
#if TOS_CFG_TICKLESS_EN > 0u
__PORT__ void port_systick_resume(void);
__PORT__ void port_systick_suspend(void);
__PORT__ void port_systick_reload(uint32_t cycle_per_tick);
__PORT__ void port_systick_pending_reset(void);
__PORT__ k_time_t port_systick_max_delay_millisecond(void);
#endif
#if TOS_CFG_PWR_MGR_EN > 0u
__PORT__ void port_sleep_mode_enter(void);
__PORT__ void port_stop_mode_enter(void);
__PORT__ void port_standby_mode_enter(void);
#endif
#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
__PORT__ void HardFault_Handler(void);
__PORT__ void port_fault_diagnosis(void);
#endif
#endif /* _PORT_H_ */

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/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#include "tos.h"
#include "core_cm23.h"
__PORT__ void port_cpu_reset(void)
{
NVIC_SystemReset();
}
__PORT__ void port_systick_config(uint32_t cycle_per_tick)
{
(void)SysTick_Config(cycle_per_tick);
}
__PORT__ void port_systick_priority_set(uint32_t prio)
{
NVIC_SetPriority(SysTick_IRQn, prio);
}
#if TOS_CFG_TICKLESS_EN > 0u
__PORT__ k_time_t port_systick_max_delay_millisecond(void)
{
k_time_t max_millisecond;
uint32_t max_cycle;
max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second
return max_millisecond;
}
__PORT__ void port_systick_resume(void)
{
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
}
__PORT__ void port_systick_suspend(void)
{
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
__PORT__ void port_systick_reload(uint32_t cycle_per_tick)
{
uint32_t max_cycle;
max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
if (max_cycle - SysTick->VAL > cycle_per_tick - 1u) {
SysTick->LOAD = max_cycle;
} else {
SysTick->LOAD = (cycle_per_tick - 1u) + SysTick->VAL;
}
SysTick->VAL = 0;
}
__PORT__ void port_systick_pending_reset(void)
{
SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
}
#endif
#if TOS_CFG_PWR_MGR_EN > 0u
__PORT__ void port_sleep_mode_enter(void)
{
#if 1
HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
#else
HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
#endif
}
__PORT__ void port_stop_mode_enter(void)
{
HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
}
__PORT__ void port_standby_mode_enter(void)
{
HAL_PWR_EnterSTANDBYMode();
}
#endif
#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
__PORT__ void port_fault_diagnosis(void)
{
k_fault_log_writer("fault diagnosis does not supported in CORTEX M0\n");
}
/*------------------ RealView Compiler -----------------*/
/* V5 */
#if defined(__CC_ARM)
__PORT__ __ASM__ void HardFault_Handler(void)
{
IMPORT fault_backtrace
MOV r0, lr
TST lr, #0x04
ITE EQ
MRSEQ r1, MSP
MRSNE r1, PSP
BL fault_backtrace
}
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
__PORT__ void __NAKED__ HardFault_Handler(void)
{
__ASM__ __VOLATILE__ (
"MOV r0, lr\n\t"
"TST lr, #0x04\n\t"
"ITE EQ\n\t"
"MRSEQ r1, MSP\n\t"
"MRSNE r1, PSP\n\t"
"BL fault_backtrace\n\t"
);
}
#endif /* ARMCC VERSION */
#endif /* TOS_CFG_FAULT_BACKTRACE_EN */

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/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#ifndef _PORT_CONFIG_H_
#define _PORT_CONFIG_H_
#define TOS_CFG_CPU_ADDR_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_DATA_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_STK_GROWTH CPU_STK_GROWTH_DESCENDING
// #define TOS_CFG_CPU_HRTIMER_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_HRTIMER_EN 0u
#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT 0u
#endif /* _PORT_CONFIG_H_ */

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EXPORT port_int_disable
EXPORT port_int_enable
EXPORT port_cpsr_save
EXPORT port_cpsr_restore
EXPORT port_sched_start
EXPORT port_context_switch
EXPORT port_irq_context_switch
EXPORT PendSV_Handler
IMPORT k_curr_task
IMPORT k_next_task
NVIC_INT_CTRL EQU 0xE000ED04 ; Interrupt control state register.
NVIC_SYSPRI14 EQU 0xE000ED20 ; System priority register (priority 14).
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest).
NVIC_PENDSVSET EQU 0x10000000 ; Value to trigger PendSV exception.
AREA |.text|, CODE, READONLY, ALIGN=2
THUMB
REQUIRE8
PRESERVE8
GLOBAL port_int_disable
port_int_disable
CPSID I
BX LR
GLOBAL port_int_enable
port_int_enable
CPSIE I
BX LR
GLOBAL port_cpsr_save
port_cpsr_save
MRS R0, PRIMASK
CPSID I
BX LR
GLOBAL port_cpsr_restore
port_cpsr_restore
MSR PRIMASK, R0
BX LR
GLOBAL port_sched_start
port_sched_start
LDR R0, =NVIC_SYSPRI14
LDR R1, =NVIC_PENDSV_PRI
STR R1, [R0]
MOVS R0, #0
MSR PSP, R0
LDR R0, =NVIC_INT_CTRL
LDR R1, =NVIC_PENDSVSET
STR R1, [R0]
CPSIE I
__unreachable
B __unreachable
GLOBAL port_context_switch
port_context_switch
LDR R0, =NVIC_INT_CTRL
LDR R1, =NVIC_PENDSVSET
STR R1, [R0]
BX LR
GLOBAL port_irq_context_switch
port_irq_context_switch
LDR R0, =NVIC_INT_CTRL
LDR R1, =NVIC_PENDSVSET
STR R1, [R0]
BX LR
GLOBAL PendSV_Handler
PendSV_Handler
CPSID I
MRS R0, PSP
CMP R0, #0
BEQ PendSVHandler_nosave
SUBS R0, R0, #0x20
STMIA R0!, {R4 - R7}
MOV R4, R8
MOV R5, R9
MOV R6, R10
MOV R7, R11
STMIA R0!, {R4-R7}
SUBS R0, R0, #0x20
LDR R1, =k_curr_task
LDR R1, [R1]
STR R0, [R1]
PendSVHandler_nosave
LDR R0, =k_curr_task
LDR R1, =k_next_task
LDR R2, [R1]
STR R2, [R0]
LDR R0, [R2]
LDMIA R0!, {R4 - R7}
LDMIA R0!, {R2 - R3}
MOV R8, R2
MOV R9, R3
LDMIA R0!, {R2 - R3}
MOV R10, R2
MOV R11, R3
MSR PSP, R0
MOV R0, R14
MOVS R1, #0x04
ORRS R0, R1
MOV R14, R0
CPSIE I
BX LR
ALIGN
END

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/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#ifndef _PORT_H_
#define _PORT_H_
__PORT__ void port_int_disable(void);
__PORT__ void port_int_enable(void);
__PORT__ cpu_cpsr_t port_cpsr_save(void);
__PORT__ void port_cpsr_restore(cpu_cpsr_t cpsr);
__PORT__ void port_cpu_reset(void);
__PORT__ void port_sched_start(void) __NO_RETURN__;
__PORT__ void port_context_switch(void);
__PORT__ void port_irq_context_switch(void);
__PORT__ void port_systick_config(uint32_t cycle_per_tick);
__PORT__ void port_systick_priority_set(uint32_t prio);
#if TOS_CFG_TICKLESS_EN > 0u
__PORT__ void port_systick_resume(void);
__PORT__ void port_systick_suspend(void);
__PORT__ void port_systick_reload(uint32_t cycle_per_tick);
__PORT__ void port_systick_pending_reset(void);
__PORT__ k_time_t port_systick_max_delay_millisecond(void);
#endif
#if TOS_CFG_PWR_MGR_EN > 0u
__PORT__ void port_sleep_mode_enter(void);
__PORT__ void port_stop_mode_enter(void);
__PORT__ void port_standby_mode_enter(void);
#endif
#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
__PORT__ void HardFault_Handler(void);
__PORT__ void port_fault_diagnosis(void);
#endif
#endif /* _PORT_H_ */

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@ -0,0 +1,145 @@
/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#include "tos.h"
#include "core_cm0plus.h"
__PORT__ void port_cpu_reset(void)
{
NVIC_SystemReset();
}
__PORT__ void port_systick_config(uint32_t cycle_per_tick)
{
(void)SysTick_Config(cycle_per_tick);
}
__PORT__ void port_systick_priority_set(uint32_t prio)
{
NVIC_SetPriority(SysTick_IRQn, prio);
}
#if TOS_CFG_TICKLESS_EN > 0u
__PORT__ k_time_t port_systick_max_delay_millisecond(void)
{
k_time_t max_millisecond;
uint32_t max_cycle;
max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second
return max_millisecond;
}
__PORT__ void port_systick_resume(void)
{
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
}
__PORT__ void port_systick_suspend(void)
{
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
__PORT__ void port_systick_reload(uint32_t cycle_per_tick)
{
uint32_t max_cycle;
max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
if (max_cycle - SysTick->VAL > cycle_per_tick - 1u) {
SysTick->LOAD = max_cycle;
} else {
SysTick->LOAD = (cycle_per_tick - 1u) + SysTick->VAL;
}
SysTick->VAL = 0;
}
__PORT__ void port_systick_pending_reset(void)
{
SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
}
#endif
#if TOS_CFG_PWR_MGR_EN > 0u
__PORT__ void port_sleep_mode_enter(void)
{
#if 1
HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
#else
HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
#endif
}
__PORT__ void port_stop_mode_enter(void)
{
HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
}
__PORT__ void port_standby_mode_enter(void)
{
HAL_PWR_EnterSTANDBYMode();
}
#endif
#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
__PORT__ void port_fault_diagnosis(void)
{
k_fault_log_writer("fault diagnosis does not supported in CORTEX M0\n");
}
/*------------------ RealView Compiler -----------------*/
/* V5 */
#if defined(__CC_ARM)
__PORT__ __ASM__ void HardFault_Handler(void)
{
IMPORT fault_backtrace
MOV r0, lr
TST lr, #0x04
ITE EQ
MRSEQ r1, MSP
MRSNE r1, PSP
BL fault_backtrace
}
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
__PORT__ void __NAKED__ HardFault_Handler(void)
{
__ASM__ __VOLATILE__ (
"MOV r0, lr\n\t"
"TST lr, #0x04\n\t"
"ITE EQ\n\t"
"MRSEQ r1, MSP\n\t"
"MRSNE r1, PSP\n\t"
"BL fault_backtrace\n\t"
);
}
#endif /* ARMCC VERSION */
#endif /* TOS_CFG_FAULT_BACKTRACE_EN */

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@ -0,0 +1,29 @@
/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#ifndef _PORT_CONFIG_H_
#define _PORT_CONFIG_H_
#define TOS_CFG_CPU_ADDR_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_DATA_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_STK_GROWTH CPU_STK_GROWTH_DESCENDING
// #define TOS_CFG_CPU_HRTIMER_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_HRTIMER_EN 0u
#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT 0u
#endif /* _PORT_CONFIG_H_ */

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@ -0,0 +1,143 @@
.global port_int_disable
.global port_int_enable
.global port_cpsr_save
.global port_cpsr_restore
.global port_sched_start
.global port_context_switch
.global port_irq_context_switch
.global PendSV_Handler
.global k_curr_task
.global k_next_task
.equ NVIC_INT_CTRL , 0xE000ED04 @Interrupt control state register.
.equ NVIC_SYSPRI14 , 0xE000ED20 @System priority register (priority 14).
.equ NVIC_PENDSV_PRI , 0x00FF0000 @ PendSV priority value (lowest).
.equ NVIC_PENDSVSET , 0x10000000 @ Value to trigger PendSV exception.
.text
.align 2
.thumb
.syntax unified
.type port_int_disable, %function
port_int_disable:
CPSID I
BX LR
.type port_int_enable, %function
port_int_enable:
CPSIE I
BX LR
.type port_cpsr_save, %function
port_cpsr_save:
MRS R0, PRIMASK
CPSID I
BX LR
.type port_cpsr_restore, %function
port_cpsr_restore:
MSR PRIMASK, R0
BX LR
.thumb_func
.type port_sched_start, %function
port_sched_start:
LDR R0, =NVIC_SYSPRI14
LDR R1, =NVIC_PENDSV_PRI
STR R1, [R0]
MOVS R0, #0
MSR PSP, R0
LDR R0, =NVIC_INT_CTRL
LDR R1, =NVIC_PENDSVSET
STR R1, [R0]
CPSIE I
__unreachable:
B __unreachable
.thumb_func
.type port_context_switch, %function
port_context_switch:
LDR R0, =NVIC_INT_CTRL
LDR R1, =NVIC_PENDSVSET
STR R1, [R0]
BX LR
.thumb_func
.type port_irq_context_switch, %function
port_irq_context_switch:
LDR R0, =NVIC_INT_CTRL
LDR R1, =NVIC_PENDSVSET
STR R1, [R0]
BX LR
.thumb_func
.type PendSV_Handler, %function
PendSV_Handler:
CPSID I
MRS R0, PSP
CMP R0, #0
BEQ PendSVHandler_nosave
SUBS R0, R0, #0x20
STMIA R0!, {R4 - R7}
MOV R4, R8
MOV R5, R9
MOV R6, R10
MOV R7, R11
STMIA R0!, {R4-R7}
SUBS R0, R0, #0x20
LDR R1, =k_curr_task
LDR R1, [R1]
STR R0, [R1]
PendSVHandler_nosave:
LDR R0, =k_curr_task
LDR R1, =k_next_task
LDR R2, [R1]
STR R2, [R0]
LDR R0, [R2]
LDMIA R0!, {R4 - R7}
LDMIA R0!, {R2 - R3}
MOV R8, R2
MOV R9, R3
LDMIA R0!, {R2 - R3}
MOV R10, R2
MOV R11, R3
MSR PSP, R0
MOV R0, R14
MOVS R1, #0x04
ORRS R0, R1
MOV R14, R0
CPSIE I
BX LR
.end

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@ -0,0 +1,73 @@
/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#ifndef _PORT_H_
#define _PORT_H_
__PORT__ void port_int_disable(void);
__PORT__ void port_int_enable(void);
__PORT__ cpu_cpsr_t port_cpsr_save(void);
__PORT__ void port_cpsr_restore(cpu_cpsr_t cpsr);
__PORT__ void port_cpu_reset(void);
__PORT__ void port_sched_start(void) __NO_RETURN__;
__PORT__ void port_context_switch(void);
__PORT__ void port_irq_context_switch(void);
__PORT__ void port_systick_config(uint32_t cycle_per_tick);
__PORT__ void port_systick_priority_set(uint32_t prio);
#if TOS_CFG_TICKLESS_EN > 0u
__PORT__ void port_systick_resume(void);
__PORT__ void port_systick_suspend(void);
__PORT__ void port_systick_reload(uint32_t cycle_per_tick);
__PORT__ void port_systick_pending_reset(void);
__PORT__ k_time_t port_systick_max_delay_millisecond(void);
#endif
#if TOS_CFG_PWR_MGR_EN > 0u
__PORT__ void port_sleep_mode_enter(void);
__PORT__ void port_stop_mode_enter(void);
__PORT__ void port_standby_mode_enter(void);
#endif
#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
__PORT__ void HardFault_Handler(void);
__PORT__ void port_fault_diagnosis(void);
#endif
#endif /* _PORT_H_ */

View File

@ -0,0 +1,145 @@
/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#include "tos.h"
#include "core_cm0plus.h"
__PORT__ void port_cpu_reset(void)
{
NVIC_SystemReset();
}
__PORT__ void port_systick_config(uint32_t cycle_per_tick)
{
(void)SysTick_Config(cycle_per_tick);
}
__PORT__ void port_systick_priority_set(uint32_t prio)
{
NVIC_SetPriority(SysTick_IRQn, prio);
}
#if TOS_CFG_TICKLESS_EN > 0u
__PORT__ k_time_t port_systick_max_delay_millisecond(void)
{
k_time_t max_millisecond;
uint32_t max_cycle;
max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second
return max_millisecond;
}
__PORT__ void port_systick_resume(void)
{
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
}
__PORT__ void port_systick_suspend(void)
{
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
__PORT__ void port_systick_reload(uint32_t cycle_per_tick)
{
uint32_t max_cycle;
max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
if (max_cycle - SysTick->VAL > cycle_per_tick - 1u) {
SysTick->LOAD = max_cycle;
} else {
SysTick->LOAD = (cycle_per_tick - 1u) + SysTick->VAL;
}
SysTick->VAL = 0;
}
__PORT__ void port_systick_pending_reset(void)
{
SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
}
#endif
#if TOS_CFG_PWR_MGR_EN > 0u
__PORT__ void port_sleep_mode_enter(void)
{
#if 1
HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
#else
HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
#endif
}
__PORT__ void port_stop_mode_enter(void)
{
HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
}
__PORT__ void port_standby_mode_enter(void)
{
HAL_PWR_EnterSTANDBYMode();
}
#endif
#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
__PORT__ void port_fault_diagnosis(void)
{
k_fault_log_writer("fault diagnosis does not supported in CORTEX M0\n");
}
/*------------------ RealView Compiler -----------------*/
/* V5 */
#if defined(__CC_ARM)
__PORT__ __ASM__ void HardFault_Handler(void)
{
IMPORT fault_backtrace
MOV r0, lr
TST lr, #0x04
ITE EQ
MRSEQ r1, MSP
MRSNE r1, PSP
BL fault_backtrace
}
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
__PORT__ void __NAKED__ HardFault_Handler(void)
{
__ASM__ __VOLATILE__ (
"MOV r0, lr\n\t"
"TST lr, #0x04\n\t"
"ITE EQ\n\t"
"MRSEQ r1, MSP\n\t"
"MRSNE r1, PSP\n\t"
"BL fault_backtrace\n\t"
);
}
#endif /* ARMCC VERSION */
#endif /* TOS_CFG_FAULT_BACKTRACE_EN */

View File

@ -0,0 +1,29 @@
/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#ifndef _PORT_CONFIG_H_
#define _PORT_CONFIG_H_
#define TOS_CFG_CPU_ADDR_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_DATA_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_STK_GROWTH CPU_STK_GROWTH_DESCENDING
// #define TOS_CFG_CPU_HRTIMER_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_HRTIMER_EN 0u
#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT 0u
#endif /* _PORT_CONFIG_H_ */

View File

@ -0,0 +1,126 @@
PUBLIC port_int_disable
PUBLIC port_int_enable
PUBLIC port_cpsr_save
PUBLIC port_cpsr_restore
PUBLIC port_sched_start
PUBLIC port_context_switch
PUBLIC port_irq_context_switch
PUBLIC PendSV_Handler
EXTERN k_curr_task
EXTERN k_next_task
NVIC_INT_CTRL EQU 0xE000ED04 ; Interrupt control state register.
NVIC_SYSPRI14 EQU 0xE000ED20 ; System priority register (priority 14).
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest).
NVIC_PENDSVSET EQU 0x10000000 ; Value to trigger PendSV exception.
RSEG CODE:CODE:NOROOT(2)
THUMB
port_int_disable
CPSID I
BX LR
port_int_enable
CPSIE I
BX LR
port_cpsr_save
MRS R0, PRIMASK
CPSID I
BX LR
port_cpsr_restore
MSR PRIMASK, R0
BX LR
port_sched_start
LDR R0, =NVIC_SYSPRI14
LDR R1, =NVIC_PENDSV_PRI
STR R1, [R0]
MOVS R0, #0
MSR PSP, R0
LDR R0, =NVIC_INT_CTRL
LDR R1, =NVIC_PENDSVSET
STR R1, [R0]
CPSIE I
__unreachable
B __unreachable
port_context_switch
LDR R0, =NVIC_INT_CTRL
LDR R1, =NVIC_PENDSVSET
STR R1, [R0]
BX LR
port_irq_context_switch
LDR R0, =NVIC_INT_CTRL
LDR R1, =NVIC_PENDSVSET
STR R1, [R0]
BX LR
PendSV_Handler
CPSID I
MRS R0, PSP
CMP R0, #0
BEQ PendSVHandler_nosave
SUBS R0, R0, #0x20
STMIA R0!, {R4 - R7}
MOV R4, R8
MOV R5, R9
MOV R6, R10
MOV R7, R11
STMIA R0!, {R4-R7}
SUBS R0, R0, #0x20
LDR R1, =k_curr_task
LDR R1, [R1]
STR R0, [R1]
PendSVHandler_nosave
LDR R0, =k_curr_task
LDR R1, =k_next_task
LDR R2, [R1]
STR R2, [R0]
LDR R0, [R2]
LDMIA R0!, {R4 - R7}
LDMIA R0!, {R2 - R3}
MOV R8, R2
MOV R9, R3
LDMIA R0!, {R2 - R3}
MOV R10, R2
MOV R11, R3
MSR PSP, R0
MOV R0, R14
MOVS R1, #0x04
ORRS R0, R1
MOV R14, R0
CPSIE I
BX LR
END

View File

@ -78,6 +78,7 @@ __API__ void tos_cpu_cpsr_restore(cpu_cpsr_t cpsr)
__KERNEL__ void cpu_init(void)
{
port_init();
k_cpu_cycle_per_tick = TOS_CFG_CPU_CLOCK / k_cpu_tick_per_second;
cpu_systick_init(k_cpu_cycle_per_tick);
@ -108,7 +109,6 @@ __KERNEL__ void cpu_irq_context_switch(void)
__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick)
{
port_systick_priority_set(TOS_CFG_CPU_SYSTICK_PRIO);
port_systick_config(cycle_per_tick);
}

View File

@ -59,7 +59,6 @@ extern k_task_t *k_next_task;
__PORT__ void _handle_tick_signal();
__PORT__ void _handle_context_switch();
__PORT__ void _delay_ms(uint32_t ms);
__PORT__ void _suspend_thread(pthread_t thread_id);
__PORT__ void _resume_thread(pthread_t thread_id);
__PORT__ void _wait_resume();
@ -70,6 +69,7 @@ __PORT__ void _suspend_task(k_task_t *task);
__PORT__ void _resume_task(k_task_t *task);
__PORT__ void _install_signal(int sig,void (*func)(int));
__PORT__ void _filter_signal(sigset_t *sigset);
__PORT__ uint64_t _get_time_ms(void);
typedef struct {
sigset_t signal_mask;
@ -80,16 +80,24 @@ interrupt_manager _int_manager={
.count = 0
};
static uint64_t tick_ms = 0;
static pthread_t main_thread_id;
static pthread_mutex_t cpsr_mutex;
#define CHECK_IS_MAIN_THREAD(main_thread_id) \
if(main_thread_id != pthread_self()) return
__PORT__ void port_int_disable(void)
{
sigset_t signal_mask,*manager_mask=NULL;
if(_int_manager.count == 0){
pthread_mutex_lock(&cpsr_mutex);
manager_mask = &(_int_manager.signal_mask);
sigfillset(&signal_mask);
_filter_signal(&signal_mask);
pthread_sigmask(SIG_BLOCK,&signal_mask,manager_mask);
}
_int_manager.count ++;
sigfillset(&signal_mask);
_filter_signal(&signal_mask);
pthread_sigmask(SIG_BLOCK,&signal_mask,manager_mask);
}
__PORT__ void port_int_enable(void)
@ -100,6 +108,7 @@ __PORT__ void port_int_enable(void)
if(_int_manager.count == 0){
sigaddset(&(_int_manager.signal_mask),SIG_RESUME); //ensure SIG_RESUME is blocked
_filter_signal(&(_int_manager.signal_mask));
pthread_mutex_unlock(&cpsr_mutex);
pthread_sigmask(SIG_SETMASK,&(_int_manager.signal_mask),NULL);
}
}
@ -124,15 +133,11 @@ __PORT__ pthread_t port_create_thread(void *arg)
__PORT__ void port_sched_start(void)
{
_install_signal(SIG_SUSPEND, _handle_suspend_thread);
_install_signal(SIG_RESUME, _handle_resume_thread);
_install_signal(SIG_CONTEXT_SWITCH, _handle_context_switch);
k_curr_task = k_next_task;
_resume_task(k_curr_task);
while(1){
_delay_ms(1000);
_wait_resume();
}
}
@ -182,8 +187,21 @@ __PORT__ void port_systick_config(uint32_t cycle_per_tick)
}
}
__PORT__ void port_systick_priority_set(uint32_t prio)
__PORT__ void port_init(void)
{
main_thread_id = pthread_self();
pthread_mutex_init(&cpsr_mutex,NULL);
_install_signal(SIG_SUSPEND, _handle_suspend_thread);
_install_signal(SIG_RESUME, _handle_resume_thread);
_install_signal(SIG_CONTEXT_SWITCH, _handle_context_switch);
}
__PORT__ void port_delay_ms(uint32_t ms)
{
uint64_t start_time = _get_time_ms();
do{
usleep(100);
}while((_get_time_ms() - start_time) < ms);
}
__PORT__ void _filter_signal(sigset_t *sigset)
@ -195,18 +213,7 @@ __PORT__ void _filter_signal(sigset_t *sigset)
__PORT__ uint64_t _get_time_ms(void)
{
struct timeval timer;
gettimeofday( &timer, NULL );
return (1000 * timer.tv_sec + timer.tv_usec/1000);
}
__PORT__ void _delay_ms(uint32_t ms)
{
uint64_t start_time = _get_time_ms();
do{
usleep(100);
}while((_get_time_ms() - start_time) < ms);
return (tick_ms);
}
__PORT__ void _install_signal(int sig,void (*func)(int))
@ -225,10 +232,12 @@ __PORT__ void _install_signal(int sig,void (*func)(int))
__PORT__ void _handle_tick_signal()
{
CHECK_IS_MAIN_THREAD(main_thread_id);
tick_ms ++;
if(tos_knl_is_running()) {
tos_knl_irq_enter();
tos_tick_handler();
tos_knl_irq_leave();
tos_knl_irq_enter();
tos_tick_handler();
tos_knl_irq_leave();
}
}

View File

@ -89,10 +89,12 @@ __PORT__ void port_irq_context_switch(void);
__PORT__ void port_systick_config(uint32_t cycle_per_tick);
__PORT__ void port_systick_priority_set(uint32_t prio); //ok
__PORT__ void port_init(void);
__PORT__ pthread_t port_create_thread(void *arg);
__PORT__ void port_delay_ms(uint32_t ms);
#if TOS_CFG_TICKLESS_EN > 0u
__PORT__ void port_systick_resume(void);

View File

@ -46,6 +46,16 @@ __KERNEL__ void cpu_init(void) {
port_cpu_init();
}
__API__ void tos_cpu_int_disable(void)
{
port_int_disable();
}
__API__ void tos_cpu_int_enable(void)
{
port_int_enable();
}
__API__ cpu_cpsr_t tos_cpu_cpsr_save(void)
{
return port_cpsr_save();

View File

@ -77,7 +77,7 @@
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>0</CpuCode>
<CpuCode>18</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
@ -203,7 +203,7 @@
<Group>
<GroupName>Application/User</GroupName>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@ -523,7 +523,7 @@
<Group>
<GroupName>tos/kernel</GroupName>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@ -546,18 +546,6 @@
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<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
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<PathWithFileName>..\..\..\..\kernel\core\tos_global.c</PathWithFileName>
<FilenameWithoutPath>tos_global.c</FilenameWithoutPath>
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@ -565,7 +553,7 @@
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@ -589,19 +577,7 @@
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<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\kernel\core\tos_msg.c</PathWithFileName>
<FilenameWithoutPath>tos_msg.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
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@ -613,7 +589,7 @@
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@ -625,19 +601,7 @@
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<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\kernel\core\tos_queue.c</PathWithFileName>
<FilenameWithoutPath>tos_queue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
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@ -649,7 +613,7 @@
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@ -661,7 +625,7 @@
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@ -673,7 +637,7 @@
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@ -685,7 +649,7 @@
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@ -697,7 +661,7 @@
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@ -709,7 +673,7 @@
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@ -721,7 +685,7 @@
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@ -731,6 +695,126 @@
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<PathWithFileName>..\..\..\..\kernel\core\tos_binary_heap.c</PathWithFileName>
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@ -741,7 +825,7 @@
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@ -761,7 +845,7 @@
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View File

@ -537,11 +537,6 @@
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_event.c</FilePath>
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<File>
<FileName>tos_fifo.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_fifo.c</FilePath>
</File>
<File>
<FileName>tos_global.c</FileName>
<FileType>1</FileType>
@ -557,11 +552,6 @@
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_mmheap.c</FilePath>
</File>
<File>
<FileName>tos_msg.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_msg.c</FilePath>
</File>
<File>
<FileName>tos_mutex.c</FileName>
<FileType>1</FileType>
@ -572,11 +562,6 @@
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<FilePath>..\..\..\..\kernel\core\tos_pend.c</FilePath>
</File>
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<FileName>tos_queue.c</FileName>
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<FilePath>..\..\..\..\kernel\core\tos_queue.c</FilePath>
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<File>
<FileName>tos_robin.c</FileName>
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@ -617,6 +602,56 @@
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<FilePath>..\..\..\..\kernel\core\tos_timer.c</FilePath>
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<FileName>tos_binary_heap.c</FileName>
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<Group>

View File

@ -0,0 +1,109 @@
<html>
<body>
<pre>
<h1>µVision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: ¦ÌVision V5.26.2.0
Copyright (C) 2018 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: sheldon dai, tencent, LIC=AK1CX-H5HPV-SGF7K-ZGDWF-QC6LB-GRJE8
Tool Versions:
Toolchain: MDK-ARM Professional Version: 5.26.2.0
Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
C Compiler: Armcc.exe V5.06 update 6 (build 750)
Assembler: Armasm.exe V5.06 update 6 (build 750)
Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
Library Manager: ArmAr.exe V5.06 update 6 (build 750)
Hex Converter: FromElf.exe V5.06 update 6 (build 750)
CPU DLL: SARMCM3.DLL V5.26.2.0
Dialog DLL: DCM.DLL V1.17.2.0
Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.5.0
Dialog DLL: TCM.DLL V1.36.1.0
<h2>Project:</h2>
D:\github\master\TencentOS-tiny\board\ALIENTEK-MiniSTM32F103RCT6\KEIL\hello_world\ALIENTEK-MiniSTM32F103RCT6.uvprojx
Project File Date: 10/28/2019
<h2>Output:</h2>
*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
Build target 'ALIENTEK-MiniSTM32F103RCT6'
assembling startup_stm32f103xe.s...
compiling main.c...
compiling stm32f1xx_hal_msp.c...
compiling usart.c...
compiling gpio.c...
compiling stm32f1xx_it.c...
compiling stm32f1xx_hal.c...
compiling mcu_init.c...
compiling stm32f1xx_hal_cortex.c...
compiling stm32f1xx_hal_exti.c...
compiling stm32f1xx_hal_dma.c...
compiling stm32f1xx_hal_flash.c...
compiling stm32f1xx_hal_flash_ex.c...
compiling stm32f1xx_hal_gpio_ex.c...
compiling stm32f1xx_hal_gpio.c...
compiling stm32f1xx_hal_pwr.c...
compiling stm32f1xx_hal_rcc.c...
compiling stm32f1xx_hal_rcc_ex.c...
assembling port_s.S...
compiling stm32f1xx_hal_tim.c...
compiling stm32f1xx_hal_tim_ex.c...
compiling system_stm32f1xx.c...
compiling stm32f1xx_hal_uart.c...
compiling tos_cpu.c...
compiling port_c.c...
compiling tos_event.c...
compiling tos_global.c...
compiling tos_mmblk.c...
compiling tos_mutex.c...
compiling tos_pend.c...
compiling tos_robin.c...
compiling tos_mmheap.c...
compiling tos_sched.c...
compiling tos_sys.c...
compiling tos_sem.c...
compiling tos_time.c...
compiling tos_task.c...
compiling tos_tick.c...
compiling tos_timer.c...
compiling tos_binary_heap.c...
compiling tos_char_fifo.c...
compiling tos_countdownlatch.c...
compiling tos_completion.c...
compiling tos_mail_queue.c...
compiling tos_message_queue.c...
compiling tos_priority_mail_queue.c...
compiling tos_priority_message_queue.c...
compiling tos_priority_queue.c...
compiling tos_ring_queue.c...
compiling hello_world.c...
compiling cmsis_os.c...
linking...
Program Size: Code=8492 RO-data=500 RW-data=92 ZI-data=31508
"ALIENTEK-MiniSTM32F103RCT6\ALIENTEK-MiniSTM32F103RCT6.axf" - 0 Error(s), 0 Warning(s).
<h2>Software Packages used:</h2>
Package Vendor: ARM
http://www.keil.com/pack/ARM.CMSIS.5.6.0.pack
ARM.CMSIS.5.6.0
CMSIS (Cortex Microcontroller Software Interface Standard)
* Component: CORE Version: 5.3.0
Package Vendor: Keil
http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack
Keil.STM32F1xx_DFP.2.2.0
STMicroelectronics STM32F1 Series Device Support, Drivers and Examples
<h2>Collection of Component include folders:</h2>
.\RTE\_ALIENTEK-MiniSTM32F103RCT6
C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.6.0\CMSIS\Core\Include
C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include
<h2>Collection of Component Files used:</h2>
* Component: ARM::CMSIS:CORE:5.3.0
Build Time Elapsed: 00:00:08
</pre>
</body>
</html>

View File

@ -0,0 +1,16 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00040000 { ; load region size_region
ER_IROM1 0x08000000 0x00040000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x0000C000 { ; RW data
.ANY (+RW +ZI)
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View File

@ -0,0 +1,97 @@
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU Configuration
// <o0.0> DBG_SLEEP
// <i> Debug Sleep Mode
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
// <o0.1> DBG_STOP
// <i> Debug Stop Mode
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
// <o0.2> DBG_STANDBY
// <i> Debug Standby Mode
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
// <o0.8> DBG_IWDG_STOP
// <i> Debug independent watchdog stopped when core is halted
// <i> 0: The watchdog counter clock continues even if the core is halted
// <i> 1: The watchdog counter clock is stopped when the core is halted
// <o0.9> DBG_WWDG_STOP
// <i> Debug window watchdog stopped when core is halted
// <i> 0: The window watchdog counter clock continues even if the core is halted
// <i> 1: The window watchdog counter clock is stopped when the core is halted
// <o0.10> DBG_TIM1_STOP
// <i> Timer 1 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.11> DBG_TIM2_STOP
// <i> Timer 2 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.12> DBG_TIM3_STOP
// <i> Timer 3 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.13> DBG_TIM4_STOP
// <i> Timer 4 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.14> DBG_CAN1_STOP
// <i> Debug CAN1 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: CAN1 receive registers are frozen
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.17> DBG_TIM8_STOP
// <i> Timer 8 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.18> DBG_TIM5_STOP
// <i> Timer 5 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.19> DBG_TIM6_STOP
// <i> Timer 6 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.20> DBG_TIM7_STOP
// <i> Timer 7 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.21> DBG_CAN2_STOP
// <i> Debug CAN2 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: CAN2 receive registers are frozen
// <o0.25> DBG_TIM12_STOP
// <i> Timer 12 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.26> DBG_TIM13_STOP
// <i> Timer 13 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.27> DBG_TIM14_STOP
// <i> Timer 14 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.28> DBG_TIM9_STOP
// <i> Timer 9 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.29> DBG_TIM10_STOP
// <i> Timer 10 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.30> DBG_TIM11_STOP
// <i> Timer 11 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// </h>
DbgMCU_CR = 0x00000007;
// <<< end of configuration section >>>

View File

@ -0,0 +1,20 @@
/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: 'ALIENTEK-MiniSTM32F103RCT6'
* Target: 'ALIENTEK-MiniSTM32F103RCT6'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "stm32f10x.h"
#endif /* RTE_COMPONENTS_H */

View File

@ -23,20 +23,10 @@
#define TOS_CFG_MUTEX_EN 1u
#define TOS_CFG_QUEUE_EN 1u
#define TOS_CFG_TIMER_EN 1u
#define TOS_CFG_SEM_EN 1u
#if (TOS_CFG_QUEUE_EN > 0u)
#define TOS_CFG_MSG_EN 1u
#else
#define TOS_CFG_MSG_EN 0u
#endif
#define TOS_CFG_MSG_POOL_SIZE 10u
#define TOS_CFG_IDLE_TASK_STK_SIZE 80u
#define TOS_CFG_CPU_TICK_PER_SECOND 1000u

View File

@ -1172,14 +1172,29 @@
</group>
<group>
<name>kernel</name>
<file>
<name>$PROJ_DIR$\..\..\..\..\kernel\core\tos_binary_heap.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\kernel\core\tos_char_fifo.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\kernel\core\tos_completion.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\kernel\core\tos_countdownlatch.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\kernel\core\tos_event.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\kernel\core\tos_fifo.c</name>
<name>$PROJ_DIR$\..\..\..\..\kernel\core\tos_global.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\kernel\core\tos_global.c</name>
<name>$PROJ_DIR$\..\..\..\..\kernel\core\tos_mail_queue.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\kernel\core\tos_message_queue.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\kernel\core\tos_mmblk.c</name>
@ -1187,9 +1202,6 @@
<file>
<name>$PROJ_DIR$\..\..\..\..\kernel\core\tos_mmheap.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\kernel\core\tos_msg.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\kernel\core\tos_mutex.c</name>
</file>
@ -1197,10 +1209,16 @@
<name>$PROJ_DIR$\..\..\..\..\kernel\core\tos_pend.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\kernel\pm\tos_pm.c</name>
<name>$PROJ_DIR$\..\..\..\..\kernel\core\tos_priority_mail_queue.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\kernel\core\tos_queue.c</name>
<name>$PROJ_DIR$\..\..\..\..\kernel\core\tos_priority_message_queue.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\kernel\core\tos_priority_queue.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\kernel\core\tos_ring_queue.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\kernel\core\tos_robin.c</name>
@ -1220,9 +1238,6 @@
<file>
<name>$PROJ_DIR$\..\..\..\..\kernel\core\tos_tick.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\kernel\pm\tos_tickless.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\kernel\core\tos_time.c</name>
</file>

View File

@ -0,0 +1,130 @@
<html>
<body>
<pre>
<h1>µVision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: ¦ÌVision V5.26.2.0
Copyright (C) 2018 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: sheldon dai, tencent, LIC=AK1CX-H5HPV-SGF7K-ZGDWF-QC6LB-GRJE8
Tool Versions:
Toolchain: MDK-ARM Professional Version: 5.26.2.0
Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
C Compiler: Armcc.exe V5.06 update 6 (build 750)
Assembler: Armasm.exe V5.06 update 6 (build 750)
Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
Library Manager: ArmAr.exe V5.06 update 6 (build 750)
Hex Converter: FromElf.exe V5.06 update 6 (build 750)
CPU DLL: SARMCM3.DLL V5.26.2.0
Dialog DLL: DCM.DLL V1.17.2.0
Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.5.0
Dialog DLL: TCM.DLL V1.36.1.0
<h2>Project:</h2>
D:\github\master\TencentOS-tiny\board\ALIENTEK_Apollo_STM32F767\KEIL\fatfs\TencentOS_tiny.uvprojx
Project File Date: 10/28/2019
<h2>Output:</h2>
*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
Build target 'TencentOS_tiny'
assembling startup_stm32f767xx.s...
compiling usart.c...
compiling mcu_init.c...
compiling gpio.c...
compiling stm32f7xx_hal_msp.c...
compiling main.c...
compiling sdmmc.c...
compiling stm32f7xx_it.c...
compiling stm32f7xx_hal_cortex.c...
compiling stm32f7xx_hal.c...
compiling stm32f7xx_hal_flash_ex.c...
compiling stm32f7xx_hal_flash.c...
compiling stm32f7xx_hal_dma.c...
compiling stm32f7xx_hal_gpio.c...
compiling stm32f7xx_hal_dma_ex.c...
compiling stm32f7xx_hal_i2c.c...
compiling stm32f7xx_hal_i2c_ex.c...
compiling stm32f7xx_hal_pwr_ex.c...
compiling stm32f7xx_hal_rcc.c...
compiling stm32f7xx_hal_pwr.c...
compiling stm32f7xx_hal_rcc_ex.c...
compiling stm32f7xx_hal_tim.c...
compiling stm32f7xx_hal_uart.c...
compiling stm32f7xx_hal_tim_ex.c...
compiling stm32f7xx_ll_sdmmc.c...
compiling stm32f7xx_hal_rtc.c...
compiling stm32f7xx_hal_mmc.c...
compiling stm32f7xx_hal_sd.c...
compiling stm32f7xx_hal_rtc_ex.c...
compiling tos_event.c...
compiling system_stm32f7xx.c...
compiling tos_mutex.c...
compiling tos_robin.c...
compiling tos_pend.c...
compiling tos_mmblk.c...
compiling tos_global.c...
compiling tos_mmheap.c...
compiling tos_sched.c...
compiling tos_task.c...
compiling tos_sys.c...
compiling tos_timer.c...
compiling tos_time.c...
compiling tos_sem.c...
compiling tos_tick.c...
compiling tos_binary_heap.c...
compiling tos_char_fifo.c...
compiling tos_message_queue.c...
compiling tos_countdownlatch.c...
compiling tos_mail_queue.c...
compiling tos_priority_mail_queue.c...
compiling tos_completion.c...
assembling port_s.S...
compiling tos_priority_queue.c...
compiling tos_priority_message_queue.c...
compiling port_c.c...
compiling cmsis_os.c...
compiling tos_cpu.c...
compiling tos_ring_queue.c...
compiling tos_fault.c...
compiling tos_hal_sd.c...
compiling fatfs_sample.c...
compiling ffunicode.c...
compiling diskio.c...
compiling fatfs_drv.c...
compiling ffsystem.c...
compiling ff.c...
compiling tos_vfs.c...
compiling tos_vfs_device.c...
compiling tos_vfs_file.c...
compiling tos_vfs_fs.c...
compiling tos_vfs_inode.c...
linking...
Program Size: Code=32028 RO-data=175720 RW-data=100 ZI-data=17972
FromELF: creating hex file...
"ALIENTEK_Aploo_STM32F767\TencentOS_tiny.axf" - 0 Error(s), 0 Warning(s).
<h2>Software Packages used:</h2>
Package Vendor: ARM
http://www.keil.com/pack/ARM.CMSIS.5.6.0.pack
ARM.CMSIS.5.6.0
CMSIS (Cortex Microcontroller Software Interface Standard)
* Component: CORE Version: 5.3.0
Package Vendor: Keil
http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.11.0.pack
Keil.STM32F7xx_DFP.2.11.0
STMicroelectronics STM32F7 Series Device Support, Drivers and Examples
<h2>Collection of Component include folders:</h2>
.\RTE\_TencentOS_tiny
C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.6.0\CMSIS\Core\Include
C:\Keil_v5\ARM\PACK\Keil\STM32F7xx_DFP\2.11.0\Drivers\CMSIS\Device\ST\STM32F7xx\Include
<h2>Collection of Component Files used:</h2>
* Component: ARM::CMSIS:CORE:5.3.0
Build Time Elapsed: 00:00:20
</pre>
</body>
</html>

View File

@ -0,0 +1,16 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00080000 { ; RW data
.ANY (+RW +ZI)
}
}

View File

@ -0,0 +1,77 @@
// File: STM32F76x_77x.dbgconf
// Version: 1.0.0
// Note: refer to STM32F76xxx STM32F77xxx reference manual (RM0410)
// refer to STM32F76xxx STM32F77xxx datasheets
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU configuration register (DBGMCU_CR)
// <o.2> DBG_STANDBY <i> Debug standby mode
// <o.1> DBG_STOP <i> Debug stop mode
// <o.0> DBG_SLEEP <i> Debug sleep mode
// </h>
DbgMCU_CR = 0x00000007;
// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
// <i> Reserved bits must be kept at reset value
// <o.26> DBG_CAN2_STOP <i> Debug CAN2 stopped when core is halted
// <o.25> DBG_CAN1_STOP <i> Debug CAN1 stopped when core is halted
// <o.24> DBG_I2C4_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.13> DBG_CAN3_STOP <i> Debug CAN3 stopped when core is halted
// <o.12> DBG_IWDG_STOP <i> Debug independent watchdog stopped when core is halted
// <o.11> DBG_WWDG_STOP <i> Debug window watchdog stopped when core is halted
// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
// <o.9> DBG_LPTIM1_STOP <i> LPTMI1 counter stopped when core is halted
// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
// <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
// <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
// </h>
DbgMCU_APB1_Fz = 0x00000000;
// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
// <i> Reserved bits must be kept at reset value
// <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
// <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
// <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
// <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
// <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
// </h>
DbgMCU_APB2_Fz = 0x00000000;
// <h> TPIU Pin Routing (TRACECLK fixed on Pin PE2)
// <i> TRACECLK: Pin PE2
// <o1> TRACED0
// <i> ETM Trace Data 0
// <0x00040003=> Pin PE3
// <0x00020001=> Pin PC1
// <0x0006000D=> Pin PG13
// <o2> TRACED1
// <i> ETM Trace Data 1
// <0x00040004=> Pin PE4
// <0x00020008=> Pin PC8
// <0x0006000E=> Pin PG14
// <o3> TRACED2
// <i> ETM Trace Data 2
// <0x00040005=> Pin PE5
// <0x00030002=> Pin PD2
// <o4> TRACED3
// <i> ETM Trace Data 3
// <0x00040006=> Pin PE6
// <0x0002000C=> Pin PC12
// </h>
TraceClk_Pin = 0x00040002;
TraceD0_Pin = 0x00040003;
TraceD1_Pin = 0x00040004;
TraceD2_Pin = 0x00040005;
TraceD3_Pin = 0x00040006;
// <<< end of configuration section >>>

View File

@ -14,7 +14,7 @@
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "stm32l4xx.h"
#define CMSIS_device_header "stm32f7xx.h"
#endif /* RTE_COMPONENTS_H */

View File

@ -663,18 +663,6 @@
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\kernel\core\tos_fifo.c</PathWithFileName>
<FilenameWithoutPath>tos_fifo.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>33</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\kernel\core\tos_global.c</PathWithFileName>
<FilenameWithoutPath>tos_global.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
@ -682,7 +670,7 @@
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>34</FileNumber>
<FileNumber>33</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -694,7 +682,7 @@
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>35</FileNumber>
<FileNumber>34</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -706,19 +694,7 @@
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>36</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\kernel\core\tos_msg.c</PathWithFileName>
<FilenameWithoutPath>tos_msg.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>37</FileNumber>
<FileNumber>35</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -730,7 +706,7 @@
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>38</FileNumber>
<FileNumber>36</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -742,19 +718,7 @@
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>39</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\kernel\core\tos_queue.c</PathWithFileName>
<FilenameWithoutPath>tos_queue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>40</FileNumber>
<FileNumber>37</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -766,7 +730,7 @@
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>41</FileNumber>
<FileNumber>38</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -778,7 +742,7 @@
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>42</FileNumber>
<FileNumber>39</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -790,7 +754,7 @@
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>43</FileNumber>
<FileNumber>40</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -802,7 +766,7 @@
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>44</FileNumber>
<FileNumber>41</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -814,7 +778,7 @@
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>45</FileNumber>
<FileNumber>42</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -826,7 +790,7 @@
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>46</FileNumber>
<FileNumber>43</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -838,7 +802,7 @@
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>47</FileNumber>
<FileNumber>44</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -848,6 +812,126 @@
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>45</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\kernel\core\tos_binary_heap.c</PathWithFileName>
<FilenameWithoutPath>tos_binary_heap.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>46</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\kernel\core\tos_char_fifo.c</PathWithFileName>
<FilenameWithoutPath>tos_char_fifo.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>47</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\kernel\core\tos_completion.c</PathWithFileName>
<FilenameWithoutPath>tos_completion.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>48</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\kernel\core\tos_countdownlatch.c</PathWithFileName>
<FilenameWithoutPath>tos_countdownlatch.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>49</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\kernel\core\tos_mail_queue.c</PathWithFileName>
<FilenameWithoutPath>tos_mail_queue.c</FilenameWithoutPath>
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View File

@ -557,11 +557,6 @@
<FileType>1</FileType>
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<FileName>tos_global.c</FileName>
<FileType>1</FileType>
@ -577,11 +572,6 @@
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<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_msg.c</FilePath>
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@ -592,11 +582,6 @@
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@ -637,6 +622,56 @@
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View File

@ -0,0 +1,131 @@
<html>
<body>
<pre>
<h1>µVision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: ¦ÌVision V5.26.2.0
Copyright (C) 2018 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: sheldon dai, tencent, LIC=AK1CX-H5HPV-SGF7K-ZGDWF-QC6LB-GRJE8
Tool Versions:
Toolchain: MDK-ARM Professional Version: 5.26.2.0
Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
C Compiler: Armcc.exe V5.06 update 6 (build 750)
Assembler: Armasm.exe V5.06 update 6 (build 750)
Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
Library Manager: ArmAr.exe V5.06 update 6 (build 750)
Hex Converter: FromElf.exe V5.06 update 6 (build 750)
CPU DLL: SARMCM3.DLL V5.26.2.0
Dialog DLL: DCM.DLL V1.17.2.0
Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.5.0
Dialog DLL: TCM.DLL V1.36.1.0
<h2>Project:</h2>
D:\github\master\TencentOS-tiny\board\ALIENTEK_Apollo_STM32F767\KEIL\fatfs_through_vfs\TencentOS_tiny.uvprojx
Project File Date: 10/28/2019
<h2>Output:</h2>
*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
Build target 'TencentOS_tiny'
compiling gpio.c...
assembling startup_stm32f767xx.s...
compiling usart.c...
compiling main.c...
compiling mcu_init.c...
compiling stm32f7xx_it.c...
compiling stm32f7xx_hal_msp.c...
compiling sdmmc.c...
compiling stm32f7xx_hal.c...
compiling stm32f7xx_hal_cortex.c...
compiling stm32f7xx_hal_dma.c...
compiling stm32f7xx_hal_flash.c...
compiling stm32f7xx_hal_flash_ex.c...
compiling stm32f7xx_hal_gpio.c...
compiling stm32f7xx_hal_dma_ex.c...
compiling stm32f7xx_hal_i2c_ex.c...
compiling stm32f7xx_hal_i2c.c...
compiling stm32f7xx_hal_pwr.c...
compiling stm32f7xx_hal_pwr_ex.c...
compiling stm32f7xx_hal_rcc_ex.c...
compiling stm32f7xx_hal_rcc.c...
compiling stm32f7xx_hal_tim_ex.c...
compiling stm32f7xx_hal_tim.c...
compiling stm32f7xx_hal_uart.c...
compiling stm32f7xx_hal_rtc.c...
compiling stm32f7xx_hal_rtc_ex.c...
compiling stm32f7xx_hal_mmc.c...
compiling tos_event.c...
compiling tos_global.c...
compiling system_stm32f7xx.c...
compiling stm32f7xx_hal_sd.c...
compiling stm32f7xx_ll_sdmmc.c...
compiling tos_mmheap.c...
compiling tos_mmblk.c...
compiling tos_pend.c...
compiling tos_robin.c...
compiling tos_sem.c...
compiling tos_mutex.c...
compiling tos_sched.c...
compiling tos_task.c...
compiling tos_sys.c...
compiling tos_char_fifo.c...
compiling tos_tick.c...
compiling tos_binary_heap.c...
compiling tos_time.c...
compiling tos_timer.c...
compiling tos_completion.c...
compiling tos_mail_queue.c...
compiling tos_countdownlatch.c...
compiling tos_priority_mail_queue.c...
compiling tos_message_queue.c...
compiling tos_priority_message_queue.c...
assembling port_s.S...
compiling tos_priority_queue.c...
compiling port_c.c...
compiling tos_ring_queue.c...
compiling tos_cpu.c...
compiling tos_fault.c...
compiling cmsis_os.c...
compiling fatfs_through_vfs_sample.c...
compiling tos_hal_sd.c...
compiling tos_vfs_device.c...
compiling tos_vfs.c...
compiling tos_vfs_file.c...
compiling tos_diskio.c...
compiling tos_vfs_fs.c...
compiling tos_vfs_inode.c...
compiling tos_fatfs_drv.c...
compiling tos_fatfs_vfs.c...
compiling tos_ffsystem.c...
compiling tos_ffunicode.c...
compiling tos_ff.c...
linking...
Program Size: Code=37504 RO-data=175704 RW-data=244 ZI-data=18796
FromELF: creating hex file...
"ALIENTEK_Aploo_STM32F767\TencentOS_tiny.axf" - 0 Error(s), 0 Warning(s).
<h2>Software Packages used:</h2>
Package Vendor: ARM
http://www.keil.com/pack/ARM.CMSIS.5.6.0.pack
ARM.CMSIS.5.6.0
CMSIS (Cortex Microcontroller Software Interface Standard)
* Component: CORE Version: 5.3.0
Package Vendor: Keil
http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.11.0.pack
Keil.STM32F7xx_DFP.2.11.0
STMicroelectronics STM32F7 Series Device Support, Drivers and Examples
<h2>Collection of Component include folders:</h2>
.\RTE\_TencentOS_tiny
C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.6.0\CMSIS\Core\Include
C:\Keil_v5\ARM\PACK\Keil\STM32F7xx_DFP\2.11.0\Drivers\CMSIS\Device\ST\STM32F7xx\Include
<h2>Collection of Component Files used:</h2>
* Component: ARM::CMSIS:CORE:5.3.0
Build Time Elapsed: 00:00:14
</pre>
</body>
</html>

View File

@ -0,0 +1,16 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00080000 { ; RW data
.ANY (+RW +ZI)
}
}

View File

@ -0,0 +1,77 @@
// File: STM32F76x_77x.dbgconf
// Version: 1.0.0
// Note: refer to STM32F76xxx STM32F77xxx reference manual (RM0410)
// refer to STM32F76xxx STM32F77xxx datasheets
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU configuration register (DBGMCU_CR)
// <o.2> DBG_STANDBY <i> Debug standby mode
// <o.1> DBG_STOP <i> Debug stop mode
// <o.0> DBG_SLEEP <i> Debug sleep mode
// </h>
DbgMCU_CR = 0x00000007;
// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
// <i> Reserved bits must be kept at reset value
// <o.26> DBG_CAN2_STOP <i> Debug CAN2 stopped when core is halted
// <o.25> DBG_CAN1_STOP <i> Debug CAN1 stopped when core is halted
// <o.24> DBG_I2C4_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.13> DBG_CAN3_STOP <i> Debug CAN3 stopped when core is halted
// <o.12> DBG_IWDG_STOP <i> Debug independent watchdog stopped when core is halted
// <o.11> DBG_WWDG_STOP <i> Debug window watchdog stopped when core is halted
// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
// <o.9> DBG_LPTIM1_STOP <i> LPTMI1 counter stopped when core is halted
// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
// <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
// <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
// </h>
DbgMCU_APB1_Fz = 0x00000000;
// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
// <i> Reserved bits must be kept at reset value
// <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
// <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
// <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
// <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
// <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
// </h>
DbgMCU_APB2_Fz = 0x00000000;
// <h> TPIU Pin Routing (TRACECLK fixed on Pin PE2)
// <i> TRACECLK: Pin PE2
// <o1> TRACED0
// <i> ETM Trace Data 0
// <0x00040003=> Pin PE3
// <0x00020001=> Pin PC1
// <0x0006000D=> Pin PG13
// <o2> TRACED1
// <i> ETM Trace Data 1
// <0x00040004=> Pin PE4
// <0x00020008=> Pin PC8
// <0x0006000E=> Pin PG14
// <o3> TRACED2
// <i> ETM Trace Data 2
// <0x00040005=> Pin PE5
// <0x00030002=> Pin PD2
// <o4> TRACED3
// <i> ETM Trace Data 3
// <0x00040006=> Pin PE6
// <0x0002000C=> Pin PC12
// </h>
TraceClk_Pin = 0x00040002;
TraceD0_Pin = 0x00040003;
TraceD1_Pin = 0x00040004;
TraceD2_Pin = 0x00040005;
TraceD3_Pin = 0x00040006;
// <<< end of configuration section >>>

View File

@ -14,7 +14,7 @@
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "stm32l4xx.h"
#define CMSIS_device_header "stm32f7xx.h"
#endif /* RTE_COMPONENTS_H */

View File

@ -268,7 +268,7 @@
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View File

@ -557,11 +557,6 @@
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View File

@ -0,0 +1,60 @@
<html>
<body>
<pre>
<h1>µVision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: ¦ÌVision V5.26.2.0
Copyright (C) 2018 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: sheldon dai, tencent, LIC=AK1CX-H5HPV-SGF7K-ZGDWF-QC6LB-GRJE8
Tool Versions:
Toolchain: MDK-ARM Professional Version: 5.26.2.0
Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
C Compiler: Armcc.exe V5.06 update 6 (build 750)
Assembler: Armasm.exe V5.06 update 6 (build 750)
Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
Library Manager: ArmAr.exe V5.06 update 6 (build 750)
Hex Converter: FromElf.exe V5.06 update 6 (build 750)
CPU DLL: SARMCM3.DLL V5.26.2.0
Dialog DLL: DCM.DLL V1.17.2.0
Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.5.0
Dialog DLL: TCM.DLL V1.36.1.0
<h2>Project:</h2>
D:\github\master\TencentOS-tiny\board\ALIENTEK_Apollo_STM32F767\KEIL\hello_world\TencentOS_tiny.uvprojx
Project File Date: 10/28/2019
<h2>Output:</h2>
*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
Build target 'TencentOS_tiny'
compiling hello_world.c...
linking...
Program Size: Code=11136 RO-data=700 RW-data=92 ZI-data=14420
FromELF: creating hex file...
"ALIENTEK_Aploo_STM32F767\TencentOS_tiny.axf" - 0 Error(s), 0 Warning(s).
<h2>Software Packages used:</h2>
Package Vendor: ARM
http://www.keil.com/pack/ARM.CMSIS.5.6.0.pack
ARM.CMSIS.5.6.0
CMSIS (Cortex Microcontroller Software Interface Standard)
* Component: CORE Version: 5.3.0
Package Vendor: Keil
http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.11.0.pack
Keil.STM32F7xx_DFP.2.11.0
STMicroelectronics STM32F7 Series Device Support, Drivers and Examples
<h2>Collection of Component include folders:</h2>
.\RTE\_TencentOS_tiny
C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.6.0\CMSIS\Core\Include
C:\Keil_v5\ARM\PACK\Keil\STM32F7xx_DFP\2.11.0\Drivers\CMSIS\Device\ST\STM32F7xx\Include
<h2>Collection of Component Files used:</h2>
* Component: ARM::CMSIS:CORE:5.3.0
Build Time Elapsed: 00:00:02
</pre>
</body>
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View File

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; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00080000 { ; RW data
.ANY (+RW +ZI)
}
}

View File

@ -0,0 +1,77 @@
// File: STM32F76x_77x.dbgconf
// Version: 1.0.0
// Note: refer to STM32F76xxx STM32F77xxx reference manual (RM0410)
// refer to STM32F76xxx STM32F77xxx datasheets
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU configuration register (DBGMCU_CR)
// <o.2> DBG_STANDBY <i> Debug standby mode
// <o.1> DBG_STOP <i> Debug stop mode
// <o.0> DBG_SLEEP <i> Debug sleep mode
// </h>
DbgMCU_CR = 0x00000007;
// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
// <i> Reserved bits must be kept at reset value
// <o.26> DBG_CAN2_STOP <i> Debug CAN2 stopped when core is halted
// <o.25> DBG_CAN1_STOP <i> Debug CAN1 stopped when core is halted
// <o.24> DBG_I2C4_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.13> DBG_CAN3_STOP <i> Debug CAN3 stopped when core is halted
// <o.12> DBG_IWDG_STOP <i> Debug independent watchdog stopped when core is halted
// <o.11> DBG_WWDG_STOP <i> Debug window watchdog stopped when core is halted
// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
// <o.9> DBG_LPTIM1_STOP <i> LPTMI1 counter stopped when core is halted
// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
// <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
// <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
// </h>
DbgMCU_APB1_Fz = 0x00000000;
// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
// <i> Reserved bits must be kept at reset value
// <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
// <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
// <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
// <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
// <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
// </h>
DbgMCU_APB2_Fz = 0x00000000;
// <h> TPIU Pin Routing (TRACECLK fixed on Pin PE2)
// <i> TRACECLK: Pin PE2
// <o1> TRACED0
// <i> ETM Trace Data 0
// <0x00040003=> Pin PE3
// <0x00020001=> Pin PC1
// <0x0006000D=> Pin PG13
// <o2> TRACED1
// <i> ETM Trace Data 1
// <0x00040004=> Pin PE4
// <0x00020008=> Pin PC8
// <0x0006000E=> Pin PG14
// <o3> TRACED2
// <i> ETM Trace Data 2
// <0x00040005=> Pin PE5
// <0x00030002=> Pin PD2
// <o4> TRACED3
// <i> ETM Trace Data 3
// <0x00040006=> Pin PE6
// <0x0002000C=> Pin PC12
// </h>
TraceClk_Pin = 0x00040002;
TraceD0_Pin = 0x00040003;
TraceD1_Pin = 0x00040004;
TraceD2_Pin = 0x00040005;
TraceD3_Pin = 0x00040006;
// <<< end of configuration section >>>

View File

@ -14,7 +14,7 @@
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "stm32l4xx.h"
#define CMSIS_device_header "stm32f7xx.h"
#endif /* RTE_COMPONENTS_H */

View File

@ -203,7 +203,7 @@
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View File

@ -21,8 +21,6 @@
#define TOS_CFG_MUTEX_EN 1u
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#define TOS_CFG_TICKLESS_EN 0u
#define TOS_CFG_VFS_EN 1u
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#define TOS_CFG_MSG_EN 0u
#endif
#define TOS_CFG_MSG_POOL_SIZE 10u
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#define TOS_CFG_IDLE_TASK_STK_SIZE 80u

View File

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<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
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<PathWithFileName>..\..\..\..\kernel\core\tos_priority_mail_queue.c</PathWithFileName>
<FilenameWithoutPath>tos_priority_mail_queue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
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<File>
<GroupNumber>6</GroupNumber>
<FileNumber>49</FileNumber>
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<PathWithFileName>..\..\..\..\kernel\core\tos_priority_message_queue.c</PathWithFileName>
<FilenameWithoutPath>tos_priority_message_queue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
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<File>
<GroupNumber>6</GroupNumber>
<FileNumber>50</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\kernel\core\tos_priority_queue.c</PathWithFileName>
<FilenameWithoutPath>tos_priority_queue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
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<File>
<GroupNumber>6</GroupNumber>
<FileNumber>51</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\kernel\core\tos_ring_queue.c</PathWithFileName>
<FilenameWithoutPath>tos_ring_queue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
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</Group>
<Group>
@ -765,7 +849,7 @@
<RteFlg>0</RteFlg>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>45</FileNumber>
<FileNumber>52</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -785,7 +869,7 @@
<RteFlg>0</RteFlg>
<File>
<GroupNumber>8</GroupNumber>
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View File

@ -547,11 +547,6 @@
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_event.c</FilePath>
</File>
<File>
<FileName>tos_fifo.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_fifo.c</FilePath>
</File>
<File>
<FileName>tos_global.c</FileName>
<FileType>1</FileType>
@ -567,11 +562,6 @@
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_mmheap.c</FilePath>
</File>
<File>
<FileName>tos_msg.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_msg.c</FilePath>
</File>
<File>
<FileName>tos_mutex.c</FileName>
<FileType>1</FileType>
@ -582,11 +572,6 @@
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_pend.c</FilePath>
</File>
<File>
<FileName>tos_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_queue.c</FilePath>
</File>
<File>
<FileName>tos_robin.c</FileName>
<FileType>1</FileType>
@ -627,6 +612,56 @@
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_timer.c</FilePath>
</File>
<File>
<FileName>tos_binary_heap.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_binary_heap.c</FilePath>
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<File>
<FileName>tos_char_fifo.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_char_fifo.c</FilePath>
</File>
<File>
<FileName>tos_completion.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_completion.c</FilePath>
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<File>
<FileName>tos_countdownlatch.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_countdownlatch.c</FilePath>
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<File>
<FileName>tos_mail_queue.c</FileName>
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<FilePath>..\..\..\..\kernel\core\tos_message_queue.c</FilePath>
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<FileName>tos_priority_queue.c</FileName>
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<FilePath>..\..\..\..\kernel\core\tos_priority_queue.c</FilePath>
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<FileName>tos_ring_queue.c</FileName>
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<FilePath>..\..\..\..\kernel\core\tos_ring_queue.c</FilePath>
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</Group>
<Group>

View File

@ -0,0 +1,111 @@
<html>
<body>
<pre>
<h1>µVision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: ¦ÌVision V5.26.2.0
Copyright (C) 2018 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: sheldon dai, tencent, LIC=AK1CX-H5HPV-SGF7K-ZGDWF-QC6LB-GRJE8
Tool Versions:
Toolchain: MDK-ARM Professional Version: 5.26.2.0
Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
C Compiler: Armcc.exe V5.06 update 6 (build 750)
Assembler: Armasm.exe V5.06 update 6 (build 750)
Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
Library Manager: ArmAr.exe V5.06 update 6 (build 750)
Hex Converter: FromElf.exe V5.06 update 6 (build 750)
CPU DLL: SARMCM3.DLL V5.26.2.0
Dialog DLL: DCM.DLL V1.17.2.0
Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.5.0
Dialog DLL: TCM.DLL V1.36.1.0
<h2>Project:</h2>
D:\github\master\TencentOS-tiny\board\ALIENTEK_EXPLORER_STM32F407ZGT6\KEIL\hello_world\ALIENTEK_EXPLORER_STM32F407ZGT6.uvprojx
Project File Date: 10/28/2019
<h2>Output:</h2>
*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
Build target 'ALIENTEK_EXPLORER_STM32F407ZGT6'
assembling startup_stm32f407xx.s...
compiling gpio.c...
compiling stm32f4xx_hal_msp.c...
compiling main.c...
compiling stm32f4xx_it.c...
compiling usart.c...
compiling mcu_init.c...
compiling stm32f4xx_hal.c...
compiling stm32f4xx_hal_cortex.c...
compiling stm32f4xx_hal_dma.c...
compiling stm32f4xx_hal_exti.c...
compiling stm32f4xx_hal_flash.c...
compiling stm32f4xx_hal_dma_ex.c...
compiling stm32f4xx_hal_flash_ex.c...
compiling stm32f4xx_hal_flash_ramfunc.c...
compiling stm32f4xx_hal_gpio.c...
compiling stm32f4xx_hal_rcc.c...
compiling stm32f4xx_hal_pwr.c...
compiling stm32f4xx_hal_rcc_ex.c...
compiling stm32f4xx_hal_pwr_ex.c...
compiling stm32f4xx_hal_tim.c...
compiling stm32f4xx_hal_uart.c...
compiling stm32f4xx_hal_tim_ex.c...
assembling port_s.S...
compiling system_stm32f4xx.c...
compiling tos_cpu.c...
compiling port_c.c...
compiling tos_event.c...
compiling tos_global.c...
compiling tos_mmblk.c...
compiling tos_mutex.c...
compiling tos_mmheap.c...
compiling tos_pend.c...
compiling tos_robin.c...
compiling tos_sched.c...
compiling tos_sys.c...
compiling tos_tick.c...
compiling tos_sem.c...
compiling tos_task.c...
compiling tos_timer.c...
compiling tos_binary_heap.c...
compiling tos_time.c...
compiling tos_completion.c...
compiling tos_countdownlatch.c...
compiling tos_char_fifo.c...
compiling tos_mail_queue.c...
compiling tos_message_queue.c...
compiling tos_priority_message_queue.c...
compiling tos_priority_mail_queue.c...
compiling tos_priority_queue.c...
compiling tos_ring_queue.c...
compiling hello_world.c...
compiling cmsis_os.c...
linking...
Program Size: Code=9716 RO-data=588 RW-data=92 ZI-data=7620
"ALIENTEK_EXPLORER_STM32F407ZGT6\ALIENTEK_EXPLORER_STM32F407ZGT6.axf" - 0 Error(s), 0 Warning(s).
<h2>Software Packages used:</h2>
Package Vendor: ARM
http://www.keil.com/pack/ARM.CMSIS.5.6.0.pack
ARM.CMSIS.5.6.0
CMSIS (Cortex Microcontroller Software Interface Standard)
* Component: CORE Version: 5.3.0
Package Vendor: Keil
http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack
Keil.STM32F4xx_DFP.2.13.0
STMicroelectronics STM32F4 Series Device Support, Drivers and Examples
<h2>Collection of Component include folders:</h2>
.\RTE\_ALIENTEK_EXPLORER_STM32F407ZGT6
C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.6.0\CMSIS\Core\Include
C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.13.0\Drivers\CMSIS\Device\ST\STM32F4xx\Include
<h2>Collection of Component Files used:</h2>
* Component: ARM::CMSIS:CORE:5.3.0
Build Time Elapsed: 00:00:09
</pre>
</body>
</html>

View File

@ -0,0 +1,16 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00020000 { ; RW data
.ANY (+RW +ZI)
}
}

View File

@ -0,0 +1,48 @@
// File: STM32F405_415_407_417_427_437_429_439.dbgconf
// Version: 1.0.0
// Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090)
// refer to STM32F40x STM32F41x datasheets
// refer to STM32F42x STM32F43x datasheets
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU configuration register (DBGMCU_CR)
// <o.2> DBG_STANDBY <i> Debug Standby Mode
// <o.1> DBG_STOP <i> Debug Stop Mode
// <o.0> DBG_SLEEP <i> Debug Sleep Mode
// </h>
DbgMCU_CR = 0x00000007;
// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
// <i> Reserved bits must be kept at reset value
// <o.26> DBG_CAN2_STOP <i> CAN2 stopped when core is halted
// <o.25> DBG_CAN1_STOP <i> CAN2 stopped when core is halted
// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> I2C3 SMBUS timeout mode stopped when core is halted
// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> I2C2 SMBUS timeout mode stopped when core is halted
// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> I2C1 SMBUS timeout mode stopped when core is halted
// <o.12> DBG_IWDG_STOP <i> Independent watchdog stopped when core is halted
// <o.11> DBG_WWDG_STOP <i> Window watchdog stopped when core is halted
// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
// <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
// <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
// </h>
DbgMCU_APB1_Fz = 0x00000000;
// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
// <i> Reserved bits must be kept at reset value
// <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
// <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
// <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
// <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
// <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
// </h>
DbgMCU_APB2_Fz = 0x00000000;
// <<< end of configuration section >>>

View File

@ -0,0 +1,20 @@
/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: 'ALIENTEK_EXPLORER_STM32F407ZGT6'
* Target: 'ALIENTEK_EXPLORER_STM32F407ZGT6'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "stm32f4xx.h"
#endif /* RTE_COMPONENTS_H */

View File

@ -21,8 +21,6 @@
#define TOS_CFG_MUTEX_EN 1u
#define TOS_CFG_QUEUE_EN 1u
#define TOS_CFG_TIMER_EN 1u
#define TOS_CFG_PWR_MGR_EN 0u
@ -33,14 +31,6 @@
#define TOS_CFG_FAULT_BACKTRACE_EN 0u
#if (TOS_CFG_QUEUE_EN > 0u)
#define TOS_CFG_MSG_EN 1u
#else
#define TOS_CFG_MSG_EN 0u
#endif
#define TOS_CFG_MSG_POOL_SIZE 3u
#define TOS_CFG_IDLE_TASK_STK_SIZE 512u
#define TOS_CFG_CPU_TICK_PER_SECOND 1000u

View File

@ -77,7 +77,7 @@
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>0</CpuCode>
<CpuCode>18</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
@ -546,18 +546,6 @@
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\kernel\core\tos_fifo.c</PathWithFileName>
<FilenameWithoutPath>tos_fifo.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
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<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\kernel\core\tos_global.c</PathWithFileName>
<FilenameWithoutPath>tos_global.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
@ -565,7 +553,7 @@
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<File>
<GroupNumber>6</GroupNumber>
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@ -589,19 +577,7 @@
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<tvExpOptDlg>0</tvExpOptDlg>
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<PathWithFileName>..\..\..\..\kernel\core\tos_msg.c</PathWithFileName>
<FilenameWithoutPath>tos_msg.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
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@ -613,7 +589,7 @@
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@ -697,7 +661,7 @@
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@ -709,7 +673,7 @@
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@ -721,7 +685,7 @@
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@ -731,6 +695,126 @@
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<PathWithFileName>..\..\..\..\kernel\core\tos_mail_queue.c</PathWithFileName>
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<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\kernel\core\tos_priority_queue.c</PathWithFileName>
<FilenameWithoutPath>tos_priority_queue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>49</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\kernel\core\tos_ring_queue.c</PathWithFileName>
<FilenameWithoutPath>tos_ring_queue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
@ -741,7 +825,7 @@
<RteFlg>0</RteFlg>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>43</FileNumber>
<FileNumber>50</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -761,7 +845,7 @@
<RteFlg>0</RteFlg>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>44</FileNumber>
<FileNumber>51</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>

View File

@ -537,11 +537,6 @@
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_event.c</FilePath>
</File>
<File>
<FileName>tos_fifo.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_fifo.c</FilePath>
</File>
<File>
<FileName>tos_global.c</FileName>
<FileType>1</FileType>
@ -557,11 +552,6 @@
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_mmheap.c</FilePath>
</File>
<File>
<FileName>tos_msg.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_msg.c</FilePath>
</File>
<File>
<FileName>tos_mutex.c</FileName>
<FileType>1</FileType>
@ -572,11 +562,6 @@
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_pend.c</FilePath>
</File>
<File>
<FileName>tos_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_queue.c</FilePath>
</File>
<File>
<FileName>tos_robin.c</FileName>
<FileType>1</FileType>
@ -617,6 +602,56 @@
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_timer.c</FilePath>
</File>
<File>
<FileName>tos_binary_heap.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_binary_heap.c</FilePath>
</File>
<File>
<FileName>tos_char_fifo.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_char_fifo.c</FilePath>
</File>
<File>
<FileName>tos_completion.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_completion.c</FilePath>
</File>
<File>
<FileName>tos_countdownlatch.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_countdownlatch.c</FilePath>
</File>
<File>
<FileName>tos_mail_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_mail_queue.c</FilePath>
</File>
<File>
<FileName>tos_message_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_message_queue.c</FilePath>
</File>
<File>
<FileName>tos_priority_mail_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_priority_mail_queue.c</FilePath>
</File>
<File>
<FileName>tos_priority_message_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_priority_message_queue.c</FilePath>
</File>
<File>
<FileName>tos_priority_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_priority_queue.c</FilePath>
</File>
<File>
<FileName>tos_ring_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_ring_queue.c</FilePath>
</File>
</Files>
</Group>
<Group>

View File

@ -0,0 +1,109 @@
<html>
<body>
<pre>
<h1>µVision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: ¦ÌVision V5.26.2.0
Copyright (C) 2018 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: sheldon dai, tencent, LIC=AK1CX-H5HPV-SGF7K-ZGDWF-QC6LB-GRJE8
Tool Versions:
Toolchain: MDK-ARM Professional Version: 5.26.2.0
Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
C Compiler: Armcc.exe V5.06 update 6 (build 750)
Assembler: Armasm.exe V5.06 update 6 (build 750)
Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
Library Manager: ArmAr.exe V5.06 update 6 (build 750)
Hex Converter: FromElf.exe V5.06 update 6 (build 750)
CPU DLL: SARMCM3.DLL V5.26.2.0
Dialog DLL: DCM.DLL V1.17.2.0
Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.5.0
Dialog DLL: TCM.DLL V1.36.1.0
<h2>Project:</h2>
D:\github\master\TencentOS-tiny\board\ALIENTEK_Elite_STM32F103ZET6\KEIL\hello_world\ALIENTEK_Elite_STM32F103.uvprojx
Project File Date: 10/28/2019
<h2>Output:</h2>
*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
Build target 'ALIENTEK_Elite_STM32F103'
assembling startup_stm32f103xe.s...
compiling gpio.c...
compiling stm32f1xx_hal_msp.c...
compiling stm32f1xx_it.c...
compiling usart.c...
compiling mcu_init.c...
compiling main.c...
compiling stm32f1xx_hal.c...
compiling stm32f1xx_hal_cortex.c...
compiling stm32f1xx_hal_dma.c...
compiling stm32f1xx_hal_exti.c...
compiling stm32f1xx_hal_flash.c...
compiling stm32f1xx_hal_gpio.c...
compiling stm32f1xx_hal_gpio_ex.c...
compiling stm32f1xx_hal_flash_ex.c...
compiling stm32f1xx_hal_pwr.c...
compiling stm32f1xx_hal_rcc.c...
compiling stm32f1xx_hal_rcc_ex.c...
compiling stm32f1xx_hal_tim.c...
compiling stm32f1xx_hal_tim_ex.c...
compiling system_stm32f1xx.c...
compiling tos_cpu.c...
compiling port_c.c...
compiling stm32f1xx_hal_uart.c...
assembling port_s.S...
compiling tos_event.c...
compiling tos_global.c...
compiling tos_mmblk.c...
compiling tos_mmheap.c...
compiling tos_mutex.c...
compiling tos_robin.c...
compiling tos_pend.c...
compiling tos_sched.c...
compiling tos_sem.c...
compiling tos_sys.c...
compiling tos_task.c...
compiling tos_tick.c...
compiling tos_time.c...
compiling tos_timer.c...
compiling tos_binary_heap.c...
compiling tos_char_fifo.c...
compiling tos_completion.c...
compiling tos_countdownlatch.c...
compiling tos_mail_queue.c...
compiling tos_message_queue.c...
compiling tos_priority_mail_queue.c...
compiling tos_priority_message_queue.c...
compiling tos_priority_queue.c...
compiling tos_ring_queue.c...
compiling cmsis_os.c...
compiling hello_world.c...
linking...
Program Size: Code=9444 RO-data=500 RW-data=92 ZI-data=31508
"ALIENTEK_Elite_STM32F103\ALIENTEK_Elite_STM32F103.axf" - 0 Error(s), 0 Warning(s).
<h2>Software Packages used:</h2>
Package Vendor: ARM
http://www.keil.com/pack/ARM.CMSIS.5.6.0.pack
ARM.CMSIS.5.6.0
CMSIS (Cortex Microcontroller Software Interface Standard)
* Component: CORE Version: 5.3.0
Package Vendor: Keil
http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack
Keil.STM32F1xx_DFP.2.2.0
STMicroelectronics STM32F1 Series Device Support, Drivers and Examples
<h2>Collection of Component include folders:</h2>
.\RTE\_ALIENTEK_Elite_STM32F103
C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.6.0\CMSIS\Core\Include
C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include
<h2>Collection of Component Files used:</h2>
* Component: ARM::CMSIS:CORE:5.3.0
Build Time Elapsed: 00:00:09
</pre>
</body>
</html>

View File

@ -0,0 +1,16 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00080000 { ; load region size_region
ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00010000 { ; RW data
.ANY (+RW +ZI)
}
}

View File

@ -0,0 +1,97 @@
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU Configuration
// <o0.0> DBG_SLEEP
// <i> Debug Sleep Mode
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
// <o0.1> DBG_STOP
// <i> Debug Stop Mode
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
// <o0.2> DBG_STANDBY
// <i> Debug Standby Mode
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
// <o0.8> DBG_IWDG_STOP
// <i> Debug independent watchdog stopped when core is halted
// <i> 0: The watchdog counter clock continues even if the core is halted
// <i> 1: The watchdog counter clock is stopped when the core is halted
// <o0.9> DBG_WWDG_STOP
// <i> Debug window watchdog stopped when core is halted
// <i> 0: The window watchdog counter clock continues even if the core is halted
// <i> 1: The window watchdog counter clock is stopped when the core is halted
// <o0.10> DBG_TIM1_STOP
// <i> Timer 1 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.11> DBG_TIM2_STOP
// <i> Timer 2 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.12> DBG_TIM3_STOP
// <i> Timer 3 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.13> DBG_TIM4_STOP
// <i> Timer 4 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.14> DBG_CAN1_STOP
// <i> Debug CAN1 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: CAN1 receive registers are frozen
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.17> DBG_TIM8_STOP
// <i> Timer 8 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.18> DBG_TIM5_STOP
// <i> Timer 5 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.19> DBG_TIM6_STOP
// <i> Timer 6 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.20> DBG_TIM7_STOP
// <i> Timer 7 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.21> DBG_CAN2_STOP
// <i> Debug CAN2 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: CAN2 receive registers are frozen
// <o0.25> DBG_TIM12_STOP
// <i> Timer 12 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.26> DBG_TIM13_STOP
// <i> Timer 13 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.27> DBG_TIM14_STOP
// <i> Timer 14 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.28> DBG_TIM9_STOP
// <i> Timer 9 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.29> DBG_TIM10_STOP
// <i> Timer 10 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.30> DBG_TIM11_STOP
// <i> Timer 11 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// </h>
DbgMCU_CR = 0x00000007;
// <<< end of configuration section >>>

View File

@ -0,0 +1,20 @@
/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: 'ALIENTEK_Elite_STM32F103'
* Target: 'ALIENTEK_Elite_STM32F103'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "stm32f10x.h"
#endif /* RTE_COMPONENTS_H */

View File

@ -23,20 +23,10 @@
#define TOS_CFG_MUTEX_EN 1u
#define TOS_CFG_QUEUE_EN 1u
#define TOS_CFG_TIMER_EN 1u
#define TOS_CFG_SEM_EN 1u
#if (TOS_CFG_QUEUE_EN > 0u)
#define TOS_CFG_MSG_EN 1u
#else
#define TOS_CFG_MSG_EN 0u
#endif
#define TOS_CFG_MSG_POOL_SIZE 10u
#define TOS_CFG_IDLE_TASK_STK_SIZE 80u
#define TOS_CFG_CPU_TICK_PER_SECOND 1000u

View File

@ -223,7 +223,7 @@
<Group>
<GroupName>Application/User</GroupName>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@ -650,18 +650,6 @@
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\kernel\core\tos_fifo.c</PathWithFileName>
<FilenameWithoutPath>tos_fifo.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>35</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\kernel\core\tos_global.c</PathWithFileName>
<FilenameWithoutPath>tos_global.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
@ -669,7 +657,7 @@
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>36</FileNumber>
<FileNumber>35</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -681,7 +669,7 @@
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<File>
<GroupNumber>6</GroupNumber>
<FileNumber>37</FileNumber>
<FileNumber>36</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -693,19 +681,7 @@
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<File>
<GroupNumber>6</GroupNumber>
<FileNumber>38</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\kernel\core\tos_msg.c</PathWithFileName>
<FilenameWithoutPath>tos_msg.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>39</FileNumber>
<FileNumber>37</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -717,7 +693,7 @@
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<File>
<GroupNumber>6</GroupNumber>
<FileNumber>40</FileNumber>
<FileNumber>38</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -729,19 +705,7 @@
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<File>
<GroupNumber>6</GroupNumber>
<FileNumber>41</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\kernel\core\tos_queue.c</PathWithFileName>
<FilenameWithoutPath>tos_queue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>42</FileNumber>
<FileNumber>39</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -753,7 +717,7 @@
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>43</FileNumber>
<FileNumber>40</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -765,7 +729,7 @@
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>44</FileNumber>
<FileNumber>41</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -777,7 +741,7 @@
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>45</FileNumber>
<FileNumber>42</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -789,7 +753,7 @@
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<File>
<GroupNumber>6</GroupNumber>
<FileNumber>46</FileNumber>
<FileNumber>43</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -801,7 +765,7 @@
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>47</FileNumber>
<FileNumber>44</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -813,7 +777,7 @@
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>48</FileNumber>
<FileNumber>45</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -825,7 +789,7 @@
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>49</FileNumber>
<FileNumber>46</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -835,6 +799,126 @@
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>47</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\kernel\core\tos_binary_heap.c</PathWithFileName>
<FilenameWithoutPath>tos_binary_heap.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>48</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\kernel\core\tos_char_fifo.c</PathWithFileName>
<FilenameWithoutPath>tos_char_fifo.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>49</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\kernel\core\tos_completion.c</PathWithFileName>
<FilenameWithoutPath>tos_completion.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
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<FileNumber>50</FileNumber>
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<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\kernel\core\tos_countdownlatch.c</PathWithFileName>
<FilenameWithoutPath>tos_countdownlatch.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
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<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\kernel\core\tos_mail_queue.c</PathWithFileName>
<FilenameWithoutPath>tos_mail_queue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>52</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\kernel\core\tos_message_queue.c</PathWithFileName>
<FilenameWithoutPath>tos_message_queue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>53</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\kernel\core\tos_priority_mail_queue.c</PathWithFileName>
<FilenameWithoutPath>tos_priority_mail_queue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>54</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\kernel\core\tos_priority_message_queue.c</PathWithFileName>
<FilenameWithoutPath>tos_priority_message_queue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>55</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\kernel\core\tos_priority_queue.c</PathWithFileName>
<FilenameWithoutPath>tos_priority_queue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>56</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\kernel\core\tos_ring_queue.c</PathWithFileName>
<FilenameWithoutPath>tos_ring_queue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
@ -845,7 +929,7 @@
<RteFlg>0</RteFlg>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>50</FileNumber>
<FileNumber>57</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -865,7 +949,7 @@
<RteFlg>0</RteFlg>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>51</FileNumber>
<FileNumber>58</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
@ -885,7 +969,7 @@
<RteFlg>0</RteFlg>
<File>
<GroupNumber>9</GroupNumber>
<FileNumber>52</FileNumber>
<FileNumber>59</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>

View File

@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>STM32L475VETx</Device>
<Vendor>STMicroelectronics</Vendor>
<PackID>Keil.STM32L4xx_DFP.2.1.0</PackID>
<PackID>Keil.STM32L4xx_DFP.2.0.0</PackID>
<PackURL>http://www.keil.com/pack</PackURL>
<Cpu>IRAM(0x20000000-0x20017FFF) IRAM2(0x10000000-0x10007FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4")</Cpu>
<FlashUtilSpec></FlashUtilSpec>
@ -572,11 +572,6 @@
<FileType>1</FileType>
<FilePath>..\..\..\kernel\core\tos_event.c</FilePath>
</File>
<File>
<FileName>tos_fifo.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\kernel\core\tos_fifo.c</FilePath>
</File>
<File>
<FileName>tos_global.c</FileName>
<FileType>1</FileType>
@ -592,11 +587,6 @@
<FileType>1</FileType>
<FilePath>..\..\..\kernel\core\tos_mmheap.c</FilePath>
</File>
<File>
<FileName>tos_msg.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\kernel\core\tos_msg.c</FilePath>
</File>
<File>
<FileName>tos_mutex.c</FileName>
<FileType>1</FileType>
@ -607,11 +597,6 @@
<FileType>1</FileType>
<FilePath>..\..\..\kernel\core\tos_pend.c</FilePath>
</File>
<File>
<FileName>tos_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\kernel\core\tos_queue.c</FilePath>
</File>
<File>
<FileName>tos_robin.c</FileName>
<FileType>1</FileType>
@ -652,6 +637,56 @@
<FileType>1</FileType>
<FilePath>..\..\..\kernel\core\tos_timer.c</FilePath>
</File>
<File>
<FileName>tos_binary_heap.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\kernel\core\tos_binary_heap.c</FilePath>
</File>
<File>
<FileName>tos_char_fifo.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\kernel\core\tos_char_fifo.c</FilePath>
</File>
<File>
<FileName>tos_completion.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\kernel\core\tos_completion.c</FilePath>
</File>
<File>
<FileName>tos_countdownlatch.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\kernel\core\tos_countdownlatch.c</FilePath>
</File>
<File>
<FileName>tos_mail_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\kernel\core\tos_mail_queue.c</FilePath>
</File>
<File>
<FileName>tos_message_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\kernel\core\tos_message_queue.c</FilePath>
</File>
<File>
<FileName>tos_priority_mail_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\kernel\core\tos_priority_mail_queue.c</FilePath>
</File>
<File>
<FileName>tos_priority_message_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\kernel\core\tos_priority_message_queue.c</FilePath>
</File>
<File>
<FileName>tos_priority_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\kernel\core\tos_priority_queue.c</FilePath>
</File>
<File>
<FileName>tos_ring_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\kernel\core\tos_ring_queue.c</FilePath>
</File>
</Files>
</Group>
<Group>

View File

@ -1,7 +1,7 @@
// File: STM32L43x_44x_45x_46x.dbgconf
// File: STM32L4x5_4x6.dbgconf
// Version: 1.0.0
// Note: refer to STM32L43xxx STM32L44xxx STM32L45xxx STM32L46xxx Reference manual (RM0394)
// refer to STM32L431xx, STM32L432xx, STM32L433xx, STM32L442xx, STM32L443xx, STM32L451xx, STM32L452xx, STM32L462xx datasheets
// Note: refer to STM32L4x5 and STM32L4x6 Reference manual (RM0351)
// refer to STM32L475xx, STM32L476xx, STM32L486xx, STM32L496xx and STM32L4A6xx datasheets
// <<< Use Configuration Wizard in Context Menu >>>
@ -26,6 +26,10 @@ DbgMCU_CR = 0x00000007;
// <i> LPTIM1 counter stopped when core is halted
// <i> 0: The counter clock of LPTIM1 is fed even if the core is halted
// <i> 1: The counter clock of LPTIM1 is stopped when the core is halted
// <o0.26> DBG_CAN2_STOP
// <i> bxCAN2 stopped when core is halted (Reserved on STM32L475xx/476xx/486xx devices)
// <i> 0: Same behavior as in normal mode
// <i> 1: The bxCAN2 receive registers are frozen
// <o0.25> DBG_CAN_STOP
// <i> bxCAN1 stopped when core is halted
// <i> 0: Same behavior as in normal mode
@ -62,6 +66,18 @@ DbgMCU_CR = 0x00000007;
// <i> TIM6 counter stopped when core is halted
// <i> 0: The counter clock of TIM6 is fed even if the core is halted
// <i> 1: The counter clock of TIM6 is stopped when the core is halted
// <o0.3> DBG_TIM5_STOP
// <i> TIM5 counter stopped when core is halted
// <i> 0: The counter clock of TIM5 is fed even if the core is halted
// <i> 1: The counter clock of TIM5 is stopped when the core is halted
// <o0.2> DBG_TIM4_STOP
// <i> TIM4 counter stopped when core is halted
// <i> 0: The counter clock of TIM4 is fed even if the core is halted
// <i> 1: The counter clock of TIM4 is stopped when the core is halted
// <o0.1> DBG_TIM3_STOP
// <i> TIM3 counter stopped when core is halted
// <i> 0: The counter clock of TIM3 is fed even if the core is halted
// <i> 1: The counter clock of TIM3 is stopped when the core is halted
// <o0.0> DBG_TIM2_STOP
// <i> TIM2 counter stopped when core is halted
// <i> 0: The counter clock of TIM2 is fed even if the core is halted
@ -74,10 +90,18 @@ DbgMCU_APB1_Fz1 = 0x00000000;
// <i> LPTIM2 counter stopped when core is halted
// <i> 0: The counter clock of LPTIM2 is fed even if the core is halted
// <i> 1: The counter clock of LPTIM2 is stopped when the core is halted
// <o0.1> DBG_I2C4_STOP
// <i> I2C4 SMBUS timeout counter stopped when core is halted (Reserved on STM32L475xx/476xx/486xx devices)
// <i> 0: Same behavior as in normal mode
// <i> 1: The I2C4 SMBus timeout is frozen
// </h>
DbgMCU_APB1_Fz2 = 0x00000000;
// <h> Debug MCU APB2 freeze register (DBGMCU_APB2FZR)
// <o0.18> DBG_TIM17_STOP
// <i> TIM17 counter stopped when core is halted
// <i> 0: The clock of the TIM17 counter is fed even if the core is halted
// <i> 1: The clock of the TIM17 counter is stopped when the core is halted
// <o0.17> DBG_TIM16_STOP
// <i> TIM16 counter stopped when core is halted
// <i> 0: The clock of the TIM16 counter is fed even if the core is halted
@ -86,6 +110,10 @@ DbgMCU_APB1_Fz2 = 0x00000000;
// <i> TIM15 counter stopped when core is halted
// <i> 0: The clock of the TIM15 counter is fed even if the core is halted
// <i> 1: The clock of the TIM15 counter is stopped when the core is halted
// <o0.13> DBG_TIM8_STOP
// <i> TIM8 counter stopped when core is halted
// <i> 0: The clock of the TIM8 counter is fed even if the core is halted
// <i> 1: The clock of the TIM8 counter is stopped when the core is halted
// <o0.11> DBG_TIM1_STOP
// <i> TIM1 counter stopped when core is halted
// <i> 0: The clock of the TIM1 counter is fed even if the core is halted

View File

@ -0,0 +1,118 @@
<html>
<body>
<pre>
<h1>µVision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: ¦ÌVision V5.26.2.0
Copyright (C) 2018 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: sheldon dai, tencent, LIC=AK1CX-H5HPV-SGF7K-ZGDWF-QC6LB-GRJE8
Tool Versions:
Toolchain: MDK-ARM Professional Version: 5.26.2.0
Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
C Compiler: Armcc.exe V5.06 update 6 (build 750)
Assembler: Armasm.exe V5.06 update 6 (build 750)
Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
Library Manager: ArmAr.exe V5.06 update 6 (build 750)
Hex Converter: FromElf.exe V5.06 update 6 (build 750)
CPU DLL: SARMCM3.DLL V5.26.2.0
Dialog DLL: DCM.DLL V1.17.2.0
Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.5.0
Dialog DLL: TCM.DLL V1.36.1.0
<h2>Project:</h2>
D:\github\master\TencentOS-tiny\board\ALIENTEK_Pandora_STM32L475\Keil\ALIENTEK_Pandora_STM32L475.uvprojx
Project File Date: 10/28/2019
<h2>Output:</h2>
*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
Build target 'ALIENTEK_Pandora_STM32L475'
assembling startup_stm32l475xx.s...
compiling usart.c...
compiling stm32l4xx_hal_msp.c...
compiling mcu_init.c...
compiling stm32l4xx_it.c...
compiling gpio.c...
compiling spi.c...
compiling main.c...
compiling stm32l4xx_hal_dma_ex.c...
compiling stm32l4xx_hal_flash_ramfunc.c...
compiling stm32l4xx_hal.c...
compiling stm32l4xx_hal_flash_ex.c...
compiling stm32l4xx_hal_cortex.c...
compiling stm32l4xx_hal_dma.c...
compiling stm32l4xx_hal_flash.c...
compiling stm32l4xx_hal_i2c_ex.c...
compiling stm32l4xx_hal_i2c.c...
compiling stm32l4xx_hal_rcc.c...
compiling stm32l4xx_hal_gpio.c...
compiling stm32l4xx_hal_rcc_ex.c...
compiling stm32l4xx_hal_pwr.c...
compiling stm32l4xx_hal_pwr_ex.c...
compiling stm32l4xx_hal_spi.c...
compiling stm32l4xx_hal_tim.c...
assembling port_s.S...
compiling stm32l4xx_hal_uart.c...
compiling system_stm32l4xx.c...
compiling stm32l4xx_hal_spi_ex.c...
compiling stm32l4xx_hal_tim_ex.c...
compiling stm32l4xx_hal_uart_ex.c...
compiling port_c.c...
compiling tos_global.c...
compiling tos_cpu.c...
compiling tos_mmblk.c...
compiling tos_mutex.c...
compiling tos_mmheap.c...
compiling tos_event.c...
compiling tos_pend.c...
compiling tos_robin.c...
compiling tos_sched.c...
compiling tos_task.c...
compiling tos_sys.c...
compiling tos_tick.c...
compiling tos_sem.c...
compiling tos_timer.c...
compiling tos_binary_heap.c...
compiling tos_countdownlatch.c...
compiling tos_time.c...
compiling tos_char_fifo.c...
compiling tos_completion.c...
compiling tos_mail_queue.c...
compiling tos_priority_mail_queue.c...
compiling tos_message_queue.c...
compiling lcd.c...
compiling tos_ring_queue.c...
compiling tos_priority_message_queue.c...
compiling tos_priority_queue.c...
compiling hello_world.c...
compiling cmsis_os.c...
linking...
Program Size: Code=20228 RO-data=42016 RW-data=144 ZI-data=45312
FromELF: creating hex file...
".\OBJ\TencentOS_tiny.axf" - 0 Error(s), 0 Warning(s).
<h2>Software Packages used:</h2>
Package Vendor: ARM
http://www.keil.com/pack/ARM.CMSIS.5.6.0.pack
ARM.CMSIS.5.6.0
CMSIS (Cortex Microcontroller Software Interface Standard)
* Component: CORE Version: 5.3.0
Package Vendor: Keil
http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack
Keil.STM32L4xx_DFP.2.0.0
STMicroelectronics STM32L4 Series Device Support, Drivers and Examples
<h2>Collection of Component include folders:</h2>
.\RTE\_ALIENTEK_Pandora_STM32L475
C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.6.0\CMSIS\Core\Include
C:\Keil_v5\ARM\PACK\Keil\STM32L4xx_DFP\2.0.0\Drivers\CMSIS\Device\ST\STM32L4xx\Include
<h2>Collection of Component Files used:</h2>
* Component: ARM::CMSIS:CORE:5.3.0
Build Time Elapsed: 00:01:46
</pre>
</body>
</html>

File diff suppressed because it is too large Load Diff

View File

@ -0,0 +1,16 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00080000 { ; load region size_region
ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00018000 { ; RW data
.ANY (+RW +ZI)
}
}

View File

@ -0,0 +1,20 @@
/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: 'ALIENTEK_Pandora_STM32L475'
* Target: 'ALIENTEK_Pandora_STM32L475'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "stm32l4xx.h"
#endif /* RTE_COMPONENTS_H */

View File

@ -21,8 +21,6 @@
#define TOS_CFG_MUTEX_EN 1u
#define TOS_CFG_QUEUE_EN 1u
#define TOS_CFG_TIMER_EN 1u
#define TOS_CFG_PWR_MGR_EN 0u
@ -31,14 +29,6 @@
#define TOS_CFG_SEM_EN 1u
#if (TOS_CFG_QUEUE_EN > 0u)
#define TOS_CFG_MSG_EN 1u
#else
#define TOS_CFG_MSG_EN 0u
#endif
#define TOS_CFG_MSG_POOL_SIZE 3u
#define TOS_CFG_IDLE_TASK_STK_SIZE 80u
#define TOS_CFG_CPU_TICK_PER_SECOND 1000u

View File

@ -0,0 +1,48 @@
// File: STM32F405_415_407_417_427_437_429_439.dbgconf
// Version: 1.0.0
// Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090)
// refer to STM32F40x STM32F41x datasheets
// refer to STM32F42x STM32F43x datasheets
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU configuration register (DBGMCU_CR)
// <o.2> DBG_STANDBY <i> Debug Standby Mode
// <o.1> DBG_STOP <i> Debug Stop Mode
// <o.0> DBG_SLEEP <i> Debug Sleep Mode
// </h>
DbgMCU_CR = 0x00000007;
// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
// <i> Reserved bits must be kept at reset value
// <o.26> DBG_CAN2_STOP <i> CAN2 stopped when core is halted
// <o.25> DBG_CAN1_STOP <i> CAN2 stopped when core is halted
// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> I2C3 SMBUS timeout mode stopped when core is halted
// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> I2C2 SMBUS timeout mode stopped when core is halted
// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> I2C1 SMBUS timeout mode stopped when core is halted
// <o.12> DBG_IWDG_STOP <i> Independent watchdog stopped when core is halted
// <o.11> DBG_WWDG_STOP <i> Window watchdog stopped when core is halted
// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
// <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
// <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
// </h>
DbgMCU_APB1_Fz = 0x00000000;
// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
// <i> Reserved bits must be kept at reset value
// <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
// <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
// <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
// <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
// <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
// </h>
DbgMCU_APB2_Fz = 0x00000000;
// <<< end of configuration section >>>

View File

@ -0,0 +1,135 @@
<html>
<body>
<pre>
<h1>µVision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: ¦ÌVision V5.26.2.0
Copyright (C) 2018 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: sheldon dai, tencent, LIC=AK1CX-H5HPV-SGF7K-ZGDWF-QC6LB-GRJE8
Tool Versions:
Toolchain: MDK-ARM Professional Version: 5.26.2.0
Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
C Compiler: Armcc.exe V5.06 update 6 (build 750)
Assembler: Armasm.exe V5.06 update 6 (build 750)
Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
Library Manager: ArmAr.exe V5.06 update 6 (build 750)
Hex Converter: FromElf.exe V5.06 update 6 (build 750)
CPU DLL: SARMCM3.DLL V5.26.2.0
Dialog DLL: DCM.DLL V1.17.2.0
Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.5.0
Dialog DLL: TCM.DLL V1.36.1.0
<h2>Project:</h2>
D:\github\master\TencentOS-tiny\board\ALIENTEK_STM32F429\KEIL\fatfs\TencentOS_tiny.uvprojx
Project File Date: 10/28/2019
<h2>Output:</h2>
*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
Build target 'TencentOS_tiny'
compiling main.c...
assembling startup_stm32f429xx.s...
compiling gpio.c...
compiling led.c...
compiling spi.c...
compiling stm32f4xx_hal_msp.c...
compiling rng.c...
compiling stm32f4xx_it.c...
compiling usart.c...
compiling mcu_init.c...
compiling sdio.c...
compiling dwt.c...
compiling stm32f4xx_hal.c...
compiling fatfs_sample.c...
compiling stm32f4xx_hal_cortex.c...
compiling stm32f4xx_hal_dma.c...
compiling stm32f4xx_hal_dma_ex.c...
compiling stm32f4xx_hal_flash.c...
compiling stm32f4xx_hal_flash_ramfunc.c...
compiling stm32f4xx_hal_flash_ex.c...
compiling stm32f4xx_hal_gpio.c...
compiling stm32f4xx_hal_pwr.c...
compiling stm32f4xx_hal_pwr_ex.c...
compiling stm32f4xx_hal_rcc.c...
compiling stm32f4xx_hal_rcc_ex.c...
compiling stm32f4xx_hal_tim.c...
compiling stm32f4xx_hal_tim_ex.c...
compiling stm32f4xx_hal_rng.c...
compiling stm32f4xx_hal_uart.c...
compiling stm32f4xx_hal_rtc_ex.c...
compiling stm32f4xx_hal_rtc.c...
compiling stm32f4xx_hal_mmc.c...
compiling stm32f4xx_hal_spi.c...
compiling stm32f4xx_hal_sd.c...
compiling stm32f4xx_ll_sdmmc.c...
compiling system_stm32f4xx.c...
compiling tos_event.c...
compiling tos_global.c...
compiling tos_mmblk.c...
compiling tos_mutex.c...
compiling tos_mmheap.c...
compiling tos_pend.c...
compiling tos_robin.c...
compiling tos_sched.c...
compiling tos_sem.c...
compiling tos_sys.c...
compiling tos_tick.c...
compiling tos_task.c...
compiling tos_time.c...
compiling tos_timer.c...
compiling tos_binary_heap.c...
compiling tos_char_fifo.c...
compiling tos_completion.c...
compiling tos_countdownlatch.c...
compiling tos_mail_queue.c...
compiling tos_message_queue.c...
compiling tos_priority_mail_queue.c...
compiling tos_priority_message_queue.c...
compiling tos_priority_queue.c...
compiling tos_ring_queue.c...
compiling tos_cpu.c...
compiling tos_fault.c...
assembling port_s.S...
compiling port_c.c...
compiling cmsis_os.c...
compiling tos_vfs.c...
compiling tos_vfs_device.c...
compiling tos_vfs_file.c...
compiling tos_vfs_fs.c...
compiling tos_vfs_inode.c...
compiling diskio.c...
compiling ffunicode.c...
compiling ffsystem.c...
compiling ff.c...
compiling tos_hal_sd.c...
compiling fatfs_drv.c...
linking...
Program Size: Code=30568 RO-data=175644 RW-data=108 ZI-data=38148
FromELF: creating hex file...
".\Obj\TencentOS_tiny.axf" - 0 Error(s), 0 Warning(s).
<h2>Software Packages used:</h2>
Package Vendor: ARM
http://www.keil.com/pack/ARM.CMSIS.5.6.0.pack
ARM.CMSIS.5.6.0
CMSIS (Cortex Microcontroller Software Interface Standard)
* Component: CORE Version: 5.3.0
Package Vendor: Keil
http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack
Keil.STM32F4xx_DFP.2.13.0
STMicroelectronics STM32F4 Series Device Support, Drivers and Examples
<h2>Collection of Component include folders:</h2>
.\RTE\_TencentOS_tiny
C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.6.0\CMSIS\Core\Include
C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.13.0\Drivers\CMSIS\Device\ST\STM32F4xx\Include
<h2>Collection of Component Files used:</h2>
* Component: ARM::CMSIS:CORE:5.3.0
Build Time Elapsed: 00:00:14
</pre>
</body>
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; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
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/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: 'TencentOS_tiny'
* Target: 'TencentOS_tiny'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
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#define CMSIS_device_header "stm32f4xx.h"
#endif /* RTE_COMPONENTS_H */

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// File: STM32F405_415_407_417_427_437_429_439.dbgconf
// Version: 1.0.0
// Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090)
// refer to STM32F40x STM32F41x datasheets
// refer to STM32F42x STM32F43x datasheets
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU configuration register (DBGMCU_CR)
// <o.2> DBG_STANDBY <i> Debug Standby Mode
// <o.1> DBG_STOP <i> Debug Stop Mode
// <o.0> DBG_SLEEP <i> Debug Sleep Mode
// </h>
DbgMCU_CR = 0x00000007;
// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
// <i> Reserved bits must be kept at reset value
// <o.26> DBG_CAN2_STOP <i> CAN2 stopped when core is halted
// <o.25> DBG_CAN1_STOP <i> CAN2 stopped when core is halted
// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> I2C3 SMBUS timeout mode stopped when core is halted
// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> I2C2 SMBUS timeout mode stopped when core is halted
// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> I2C1 SMBUS timeout mode stopped when core is halted
// <o.12> DBG_IWDG_STOP <i> Independent watchdog stopped when core is halted
// <o.11> DBG_WWDG_STOP <i> Window watchdog stopped when core is halted
// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
// <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
// <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
// </h>
DbgMCU_APB1_Fz = 0x00000000;
// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
// <i> Reserved bits must be kept at reset value
// <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
// <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
// <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
// <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
// <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
// </h>
DbgMCU_APB2_Fz = 0x00000000;
// <<< end of configuration section >>>

View File

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<h1>µVision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: ¦ÌVision V5.26.2.0
Copyright (C) 2018 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: sheldon dai, tencent, LIC=AK1CX-H5HPV-SGF7K-ZGDWF-QC6LB-GRJE8
Tool Versions:
Toolchain: MDK-ARM Professional Version: 5.26.2.0
Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
C Compiler: Armcc.exe V5.06 update 6 (build 750)
Assembler: Armasm.exe V5.06 update 6 (build 750)
Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
Library Manager: ArmAr.exe V5.06 update 6 (build 750)
Hex Converter: FromElf.exe V5.06 update 6 (build 750)
CPU DLL: SARMCM3.DLL V5.26.2.0
Dialog DLL: DCM.DLL V1.17.2.0
Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.5.0
Dialog DLL: TCM.DLL V1.36.1.0
<h2>Project:</h2>
D:\github\master\TencentOS-tiny\board\ALIENTEK_STM32F429\KEIL\fatfs_through_vfs\TencentOS_tiny.uvprojx
Project File Date: 10/28/2019
<h2>Output:</h2>
*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
Build target 'TencentOS_tiny'
compiling rng.c...
compiling gpio.c...
compiling led.c...
assembling startup_stm32f429xx.s...
compiling main.c...
compiling spi.c...
compiling stm32f4xx_hal_msp.c...
compiling stm32f4xx_it.c...
compiling usart.c...
compiling sdio.c...
compiling mcu_init.c...
compiling dwt.c...
compiling fatfs_through_vfs_sample.c...
compiling stm32f4xx_hal.c...
compiling stm32f4xx_hal_cortex.c...
compiling stm32f4xx_hal_flash.c...
compiling stm32f4xx_hal_dma.c...
compiling stm32f4xx_hal_dma_ex.c...
compiling stm32f4xx_hal_flash_ex.c...
compiling stm32f4xx_hal_flash_ramfunc.c...
compiling stm32f4xx_hal_gpio.c...
compiling stm32f4xx_hal_pwr.c...
compiling stm32f4xx_hal_tim.c...
compiling stm32f4xx_hal_pwr_ex.c...
compiling stm32f4xx_hal_rcc.c...
compiling stm32f4xx_hal_rcc_ex.c...
compiling stm32f4xx_hal_tim_ex.c...
compiling stm32f4xx_hal_uart.c...
compiling stm32f4xx_hal_rng.c...
compiling stm32f4xx_hal_rtc.c...
compiling stm32f4xx_hal_rtc_ex.c...
compiling stm32f4xx_hal_mmc.c...
compiling stm32f4xx_hal_spi.c...
compiling stm32f4xx_hal_sd.c...
compiling stm32f4xx_ll_sdmmc.c...
compiling tos_event.c...
compiling tos_mmblk.c...
compiling tos_global.c...
compiling system_stm32f4xx.c...
compiling tos_pend.c...
compiling tos_mutex.c...
compiling tos_mmheap.c...
compiling tos_robin.c...
compiling tos_sched.c...
compiling tos_sem.c...
compiling tos_sys.c...
compiling tos_task.c...
compiling tos_tick.c...
compiling tos_time.c...
compiling tos_timer.c...
compiling tos_binary_heap.c...
compiling tos_char_fifo.c...
compiling tos_completion.c...
compiling tos_mail_queue.c...
compiling tos_countdownlatch.c...
compiling tos_message_queue.c...
compiling tos_priority_mail_queue.c...
compiling tos_priority_message_queue.c...
compiling tos_priority_queue.c...
compiling tos_ring_queue.c...
compiling tos_cpu.c...
compiling tos_fault.c...
assembling port_s.S...
compiling port_c.c...
compiling cmsis_os.c...
compiling tos_vfs.c...
compiling tos_vfs_device.c...
compiling tos_vfs_file.c...
compiling tos_vfs_fs.c...
compiling tos_vfs_inode.c...
compiling tos_fatfs_vfs.c...
compiling tos_ffsystem.c...
compiling tos_diskio.c...
compiling tos_fatfs_drv.c...
compiling tos_hal_sd.c...
compiling tos_ffunicode.c...
compiling tos_ff.c...
linking...
Program Size: Code=36048 RO-data=175628 RW-data=252 ZI-data=38972
FromELF: creating hex file...
".\Obj\TencentOS_tiny.axf" - 0 Error(s), 0 Warning(s).
<h2>Software Packages used:</h2>
Package Vendor: ARM
http://www.keil.com/pack/ARM.CMSIS.5.6.0.pack
ARM.CMSIS.5.6.0
CMSIS (Cortex Microcontroller Software Interface Standard)
* Component: CORE Version: 5.3.0
Package Vendor: Keil
http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack
Keil.STM32F4xx_DFP.2.13.0
STMicroelectronics STM32F4 Series Device Support, Drivers and Examples
<h2>Collection of Component include folders:</h2>
.\RTE\_TencentOS_tiny
C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.6.0\CMSIS\Core\Include
C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.13.0\Drivers\CMSIS\Device\ST\STM32F4xx\Include
<h2>Collection of Component Files used:</h2>
* Component: ARM::CMSIS:CORE:5.3.0
Build Time Elapsed: 00:00:14
</pre>
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LR_IROM1 0x08000000 0x00100000 { ; load region size_region
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
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/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: 'TencentOS_tiny'
* Target: 'TencentOS_tiny'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "stm32f4xx.h"
#endif /* RTE_COMPONENTS_H */

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<FileName>tos_ring_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_ring_queue.c</FilePath>
</File>
</Files>
</Group>
<Group>

View File

@ -0,0 +1,48 @@
// File: STM32F405_415_407_417_427_437_429_439.dbgconf
// Version: 1.0.0
// Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090)
// refer to STM32F40x STM32F41x datasheets
// refer to STM32F42x STM32F43x datasheets
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU configuration register (DBGMCU_CR)
// <o.2> DBG_STANDBY <i> Debug Standby Mode
// <o.1> DBG_STOP <i> Debug Stop Mode
// <o.0> DBG_SLEEP <i> Debug Sleep Mode
// </h>
DbgMCU_CR = 0x00000007;
// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
// <i> Reserved bits must be kept at reset value
// <o.26> DBG_CAN2_STOP <i> CAN2 stopped when core is halted
// <o.25> DBG_CAN1_STOP <i> CAN2 stopped when core is halted
// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> I2C3 SMBUS timeout mode stopped when core is halted
// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> I2C2 SMBUS timeout mode stopped when core is halted
// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> I2C1 SMBUS timeout mode stopped when core is halted
// <o.12> DBG_IWDG_STOP <i> Independent watchdog stopped when core is halted
// <o.11> DBG_WWDG_STOP <i> Window watchdog stopped when core is halted
// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
// <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
// <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
// </h>
DbgMCU_APB1_Fz = 0x00000000;
// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
// <i> Reserved bits must be kept at reset value
// <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
// <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
// <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
// <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
// <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
// </h>
DbgMCU_APB2_Fz = 0x00000000;
// <<< end of configuration section >>>

View File

@ -0,0 +1,128 @@
<html>
<body>
<pre>
<h1>µVision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: ¦ÌVision V5.26.2.0
Copyright (C) 2018 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: sheldon dai, tencent, LIC=AK1CX-H5HPV-SGF7K-ZGDWF-QC6LB-GRJE8
Tool Versions:
Toolchain: MDK-ARM Professional Version: 5.26.2.0
Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
C Compiler: Armcc.exe V5.06 update 6 (build 750)
Assembler: Armasm.exe V5.06 update 6 (build 750)
Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
Library Manager: ArmAr.exe V5.06 update 6 (build 750)
Hex Converter: FromElf.exe V5.06 update 6 (build 750)
CPU DLL: SARMCM3.DLL V5.26.2.0
Dialog DLL: DCM.DLL V1.17.2.0
Target DLL: Segger\JL2CM3.dll V2.99.31.0
Dialog DLL: TCM.DLL V1.36.1.0
<h2>Project:</h2>
D:\github\master\TencentOS-tiny\board\ALIENTEK_STM32F429\KEIL\hello_world\TencentOS_tiny.uvprojx
Project File Date: 10/28/2019
<h2>Output:</h2>
*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
Build target 'TencentOS_tiny'
compiling stm32f4xx_hal_msp.c...
compiling spi.c...
assembling startup_stm32f429xx.s...
compiling main.c...
compiling led.c...
compiling gpio.c...
compiling rng.c...
compiling stm32f4xx_it.c...
compiling usart.c...
compiling dwt.c...
compiling hello_world.c...
compiling mcu_init.c...
compiling stm32f4xx_hal.c...
compiling stm32f4xx_hal_cortex.c...
compiling stm32f4xx_hal_dma.c...
compiling stm32f4xx_hal_dma_ex.c...
compiling stm32f4xx_hal_flash_ex.c...
compiling stm32f4xx_hal_flash.c...
compiling stm32f4xx_hal_flash_ramfunc.c...
compiling stm32f4xx_hal_pwr.c...
compiling stm32f4xx_hal_gpio.c...
compiling stm32f4xx_hal_pwr_ex.c...
compiling stm32f4xx_hal_rcc.c...
compiling stm32f4xx_hal_rcc_ex.c...
compiling stm32f4xx_hal_tim_ex.c...
compiling stm32f4xx_hal_rtc.c...
compiling stm32f4xx_hal_tim.c...
compiling stm32f4xx_hal_rng.c...
compiling stm32f4xx_hal_uart.c...
compiling stm32f4xx_hal_rtc_ex.c...
compiling system_stm32f4xx.c...
compiling stm32f4xx_hal_spi.c...
compiling tos_event.c...
compiling tos_global.c...
compiling tos_mmblk.c...
compiling tos_mutex.c...
compiling tos_mmheap.c...
compiling tos_pend.c...
compiling tos_robin.c...
compiling tos_sched.c...
compiling tos_sem.c...
compiling tos_sys.c...
compiling tos_task.c...
compiling tos_tick.c...
compiling tos_time.c...
compiling tos_pm.c...
compiling tos_tickless.c...
compiling tos_timer.c...
compiling tos_binary_heap.c...
compiling tos_char_fifo.c...
compiling tos_completion.c...
compiling tos_countdownlatch.c...
compiling tos_mail_queue.c...
compiling tos_message_queue.c...
compiling tos_priority_message_queue.c...
compiling tos_priority_mail_queue.c...
compiling tos_priority_queue.c...
compiling tos_cpu.c...
compiling tos_ring_queue.c...
assembling port_s.S...
compiling cmsis_os.c...
compiling bsp_pwr_mgr.c...
..\..\BSP\Src\tickless\bsp_pwr_mgr.c(24): warning: #940-D: missing return statement at end of non-void function "tos_bsp_tickless_setup"
}
..\..\BSP\Src\tickless\bsp_pwr_mgr.c: 1 warning, 0 errors
compiling bsp_tickless_alarm.c...
compiling bsp_pm_device.c...
compiling port_c.c...
compiling tos_fault.c...
linking...
Program Size: Code=13424 RO-data=624 RW-data=100 ZI-data=34596
FromELF: creating hex file...
".\Obj\TencentOS_tiny.axf" - 0 Error(s), 1 Warning(s).
<h2>Software Packages used:</h2>
Package Vendor: ARM
http://www.keil.com/pack/ARM.CMSIS.5.6.0.pack
ARM.CMSIS.5.6.0
CMSIS (Cortex Microcontroller Software Interface Standard)
* Component: CORE Version: 5.3.0
Package Vendor: Keil
http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack
Keil.STM32F4xx_DFP.2.13.0
STMicroelectronics STM32F4 Series Device Support, Drivers and Examples
<h2>Collection of Component include folders:</h2>
.\RTE\_TencentOS_tiny
C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.6.0\CMSIS\Core\Include
C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.13.0\Drivers\CMSIS\Device\ST\STM32F4xx\Include
<h2>Collection of Component Files used:</h2>
* Component: ARM::CMSIS:CORE:5.3.0
Build Time Elapsed: 00:00:12
</pre>
</body>
</html>

File diff suppressed because it is too large Load Diff

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@ -0,0 +1,16 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00030000 { ; RW data
.ANY (+RW +ZI)
}
}

View File

@ -0,0 +1,20 @@
/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: 'TencentOS_tiny'
* Target: 'TencentOS_tiny'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "stm32f4xx.h"
#endif /* RTE_COMPONENTS_H */

View File

@ -630,18 +630,6 @@
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<FileName>tos_countdownlatch.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_countdownlatch.c</FilePath>
</File>
<File>
<FileName>tos_mail_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_mail_queue.c</FilePath>
</File>
<File>
<FileName>tos_message_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_message_queue.c</FilePath>
</File>
<File>
<FileName>tos_priority_mail_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_priority_mail_queue.c</FilePath>
</File>
<File>
<FileName>tos_priority_message_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_priority_message_queue.c</FilePath>
</File>
<File>
<FileName>tos_priority_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_priority_queue.c</FilePath>
</File>
<File>
<FileName>tos_ring_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\kernel\core\tos_ring_queue.c</FilePath>
</File>
</Files>
</Group>
<Group>

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