98 lines
4.1 KiB
LLVM
98 lines
4.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=i686-pc-win32 -mcpu=corei7-avx | FileCheck %s
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux"
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@e = dso_local global i32 0, align 4
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@f = dso_local local_unnamed_addr global i32 0, align 4
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@d = dso_local global i32 0, align 4
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@c = dso_local global i32 0, align 4
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@b = dso_local global i32 0, align 4
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@a = dso_local local_unnamed_addr global i32 0, align 4
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define dso_local i32 @main() {
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; CHECK-LABEL: @main(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @e, align 4
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; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @f, align 4
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], [[TMP1]]
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; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
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; CHECK: if.then:
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; CHECK-NEXT: [[TMP2:%.*]] = load volatile i32, i32* @d, align 4
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; CHECK-NEXT: [[TMP3:%.*]] = load volatile i32, i32* @c, align 4
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; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP3]], 0
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; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[LOR_RHS:%.*]], label [[LOR_END:%.*]]
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; CHECK: lor.rhs:
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; CHECK-NEXT: [[TMP4:%.*]] = load volatile i32, i32* @d, align 4
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; CHECK-NEXT: [[TOBOOL1:%.*]] = icmp ne i32 [[TMP4]], 0
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; CHECK-NEXT: [[PHI_CAST:%.*]] = zext i1 [[TOBOOL1]] to i32
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; CHECK-NEXT: br label [[LOR_END]]
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; CHECK: lor.end:
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; CHECK-NEXT: [[TMP5:%.*]] = phi i32 [ 1, [[IF_THEN]] ], [ [[PHI_CAST]], [[LOR_RHS]] ]
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; CHECK-NEXT: [[TOBOOL2:%.*]] = icmp ne i32 [[TMP1]], 0
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; CHECK-NEXT: [[LAND_EXT:%.*]] = zext i1 [[TOBOOL2]] to i32
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; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP5]], [[LAND_EXT]]
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; CHECK-NEXT: store volatile i32 [[OR]], i32* @b, align 4
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; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP1]], [[TMP2]]
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; CHECK-NEXT: [[TMP6:%.*]] = load volatile i32, i32* @d, align 4
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; CHECK-NEXT: [[TOBOOL4_NOT:%.*]] = icmp eq i32 [[TMP6]], 0
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; CHECK-NEXT: br i1 [[TOBOOL4_NOT]], label [[LAND_END7:%.*]], label [[LAND_RHS5:%.*]]
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; CHECK: land.rhs5:
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; CHECK-NEXT: [[TMP7:%.*]] = load volatile i32, i32* @c, align 4
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; CHECK-NEXT: [[TOBOOL6:%.*]] = icmp ne i32 [[TMP7]], 0
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; CHECK-NEXT: [[PHI_CAST11:%.*]] = zext i1 [[TOBOOL6]] to i32
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; CHECK-NEXT: br label [[LAND_END7]]
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; CHECK: land.end7:
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; CHECK-NEXT: [[TMP8:%.*]] = phi i32 [ 0, [[LOR_END]] ], [ [[PHI_CAST11]], [[LAND_RHS5]] ]
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; CHECK-NEXT: [[OR9:%.*]] = or i32 [[TMP8]], [[DIV]]
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; CHECK-NEXT: store i32 [[OR9]], i32* @a, align 4
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; CHECK-NEXT: br label [[IF_END]]
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; CHECK: if.end:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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%0 = load volatile i32, i32* @e, align 4
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%1 = load i32, i32* @f, align 4
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%cmp = icmp sgt i32 %0, %1
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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%2 = load volatile i32, i32* @d, align 4
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%3 = load volatile i32, i32* @c, align 4
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%tobool.not = icmp eq i32 %3, 0
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br i1 %tobool.not, label %lor.rhs, label %lor.end
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lor.rhs: ; preds = %if.then
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%4 = load volatile i32, i32* @d, align 4
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%tobool1 = icmp ne i32 %4, 0
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%phi.cast = zext i1 %tobool1 to i32
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br label %lor.end
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lor.end: ; preds = %lor.rhs, %if.then
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%5 = phi i32 [ 1, %if.then ], [ %phi.cast, %lor.rhs ]
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%tobool2 = icmp ne i32 %1, 0
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%land.ext = zext i1 %tobool2 to i32
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%or = or i32 %5, %land.ext
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store volatile i32 %or, i32* @b, align 4
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%div = sdiv i32 %1, %2
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%6 = load volatile i32, i32* @d, align 4
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%tobool4.not = icmp eq i32 %6, 0
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br i1 %tobool4.not, label %land.end7, label %land.rhs5
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land.rhs5: ; preds = %lor.end
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%7 = load volatile i32, i32* @c, align 4
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%tobool6 = icmp ne i32 %7, 0
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%phi.cast11 = zext i1 %tobool6 to i32
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br label %land.end7
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land.end7: ; preds = %land.rhs5, %lor.end
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%8 = phi i32 [ 0, %lor.end ], [ %phi.cast11, %land.rhs5 ]
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%or9 = or i32 %8, %div
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store i32 %or9, i32* @a, align 4
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br label %if.end
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if.end: ; preds = %land.end7, %entry
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ret i32 0
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}
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