67 lines
2.7 KiB
LLVM
67 lines
2.7 KiB
LLVM
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -passes=slp-vectorizer < %s | FileCheck -check-prefixes=GCN,GFX908 %s
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -passes=slp-vectorizer < %s | FileCheck -check-prefixes=GCN,GFX90A %s
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; GCN-LABEL: @fadd_combine
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; GFX908: fadd float
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; GFX908: fadd float
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; GFX90A: fadd <2 x float>
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define amdgpu_kernel void @fadd_combine(float addrspace(1)* %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = zext i32 %tmp to i64
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%tmp2 = getelementptr inbounds float, float addrspace(1)* %arg, i64 %tmp1
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%tmp3 = load float, float addrspace(1)* %tmp2, align 4
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%tmp4 = fadd float %tmp3, 1.000000e+00
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store float %tmp4, float addrspace(1)* %tmp2, align 4
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%tmp5 = add nuw nsw i64 %tmp1, 1
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%tmp6 = getelementptr inbounds float, float addrspace(1)* %arg, i64 %tmp5
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%tmp7 = load float, float addrspace(1)* %tmp6, align 4
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%tmp8 = fadd float %tmp7, 1.000000e+00
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store float %tmp8, float addrspace(1)* %tmp6, align 4
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ret void
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}
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; GCN-LABEL: @fmul_combine
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; GFX908: fmul float
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; GFX908: fmul float
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; GFX90A: fmul <2 x float>
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define amdgpu_kernel void @fmul_combine(float addrspace(1)* %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = zext i32 %tmp to i64
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%tmp2 = getelementptr inbounds float, float addrspace(1)* %arg, i64 %tmp1
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%tmp3 = load float, float addrspace(1)* %tmp2, align 4
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%tmp4 = fmul float %tmp3, 1.000000e+00
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store float %tmp4, float addrspace(1)* %tmp2, align 4
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%tmp5 = add nuw nsw i64 %tmp1, 1
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%tmp6 = getelementptr inbounds float, float addrspace(1)* %arg, i64 %tmp5
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%tmp7 = load float, float addrspace(1)* %tmp6, align 4
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%tmp8 = fmul float %tmp7, 1.000000e+00
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store float %tmp8, float addrspace(1)* %tmp6, align 4
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ret void
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}
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; GCN-LABEL: @fma_combine
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; GFX908: call float @llvm.fma.f32
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; GFX908: call float @llvm.fma.f32
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; GFX90A: call <2 x float> @llvm.fma.v2f32
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define amdgpu_kernel void @fma_combine(float addrspace(1)* %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = zext i32 %tmp to i64
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%tmp2 = getelementptr inbounds float, float addrspace(1)* %arg, i64 %tmp1
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%tmp3 = load float, float addrspace(1)* %tmp2, align 4
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%tmp4 = tail call float @llvm.fma.f32(float %tmp3, float 1.000000e+00, float 1.000000e+00)
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store float %tmp4, float addrspace(1)* %tmp2, align 4
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%tmp5 = add nuw nsw i64 %tmp1, 1
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%tmp6 = getelementptr inbounds float, float addrspace(1)* %arg, i64 %tmp5
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%tmp7 = load float, float addrspace(1)* %tmp6, align 4
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%tmp8 = tail call float @llvm.fma.f32(float %tmp7, float 1.000000e+00, float 1.000000e+00)
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store float %tmp8, float addrspace(1)* %tmp6, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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declare float @llvm.fma.f32(float, float, float)
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