151 lines
5.4 KiB
LLVM
151 lines
5.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -S -passes=instcombine | FileCheck %s
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; PR21929
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define i32 @modulo2(i32 %x) {
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; CHECK-LABEL: @modulo2(
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; CHECK-NEXT: [[RET_I:%.*]] = and i32 [[X:%.*]], 1
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; CHECK-NEXT: ret i32 [[RET_I]]
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;
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%rem.i = srem i32 %x, 2
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%cmp.i = icmp slt i32 %rem.i, 0
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%add.i = select i1 %cmp.i, i32 2, i32 0
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%ret.i = add nsw i32 %add.i, %rem.i
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ret i32 %ret.i
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}
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define <2 x i32> @modulo2_vec(<2 x i32> %x) {
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; CHECK-LABEL: @modulo2_vec(
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; CHECK-NEXT: [[RET_I:%.*]] = and <2 x i32> [[X:%.*]], <i32 1, i32 1>
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; CHECK-NEXT: ret <2 x i32> [[RET_I]]
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;
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%rem.i = srem <2 x i32> %x, <i32 2, i32 2>
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%cmp.i = icmp slt <2 x i32> %rem.i, zeroinitializer
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%add.i = select <2 x i1> %cmp.i, <2 x i32> <i32 2, i32 2>, <2 x i32> zeroinitializer
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%ret.i = add nsw <2 x i32> %add.i, %rem.i
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ret <2 x i32> %ret.i
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}
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define i32 @modulo3(i32 %x) {
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; CHECK-LABEL: @modulo3(
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; CHECK-NEXT: [[REM_I:%.*]] = srem i32 [[X:%.*]], 3
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; CHECK-NEXT: [[CMP_I:%.*]] = icmp slt i32 [[REM_I]], 0
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; CHECK-NEXT: [[ADD_I:%.*]] = select i1 [[CMP_I]], i32 3, i32 0
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; CHECK-NEXT: [[RET_I:%.*]] = add nsw i32 [[ADD_I]], [[REM_I]]
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; CHECK-NEXT: ret i32 [[RET_I]]
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;
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%rem.i = srem i32 %x, 3
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%cmp.i = icmp slt i32 %rem.i, 0
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%add.i = select i1 %cmp.i, i32 3, i32 0
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%ret.i = add nsw i32 %add.i, %rem.i
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ret i32 %ret.i
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}
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define <2 x i32> @modulo3_vec(<2 x i32> %x) {
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; CHECK-LABEL: @modulo3_vec(
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; CHECK-NEXT: [[REM_I:%.*]] = srem <2 x i32> [[X:%.*]], <i32 3, i32 3>
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; CHECK-NEXT: [[CMP_I:%.*]] = icmp slt <2 x i32> [[REM_I]], zeroinitializer
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; CHECK-NEXT: [[ADD_I:%.*]] = select <2 x i1> [[CMP_I]], <2 x i32> <i32 3, i32 3>, <2 x i32> zeroinitializer
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; CHECK-NEXT: [[RET_I:%.*]] = add nsw <2 x i32> [[ADD_I]], [[REM_I]]
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; CHECK-NEXT: ret <2 x i32> [[RET_I]]
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;
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%rem.i = srem <2 x i32> %x, <i32 3, i32 3>
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%cmp.i = icmp slt <2 x i32> %rem.i, zeroinitializer
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%add.i = select <2 x i1> %cmp.i, <2 x i32> <i32 3, i32 3>, <2 x i32> zeroinitializer
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%ret.i = add nsw <2 x i32> %add.i, %rem.i
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ret <2 x i32> %ret.i
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}
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define i32 @modulo4(i32 %x) {
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; CHECK-LABEL: @modulo4(
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; CHECK-NEXT: [[RET_I:%.*]] = and i32 [[X:%.*]], 3
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; CHECK-NEXT: ret i32 [[RET_I]]
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;
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%rem.i = srem i32 %x, 4
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%cmp.i = icmp slt i32 %rem.i, 0
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%add.i = select i1 %cmp.i, i32 4, i32 0
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%ret.i = add nsw i32 %add.i, %rem.i
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ret i32 %ret.i
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}
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define <2 x i32> @modulo4_vec(<2 x i32> %x) {
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; CHECK-LABEL: @modulo4_vec(
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; CHECK-NEXT: [[RET_I:%.*]] = and <2 x i32> [[X:%.*]], <i32 3, i32 3>
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; CHECK-NEXT: ret <2 x i32> [[RET_I]]
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;
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%rem.i = srem <2 x i32> %x, <i32 4, i32 4>
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%cmp.i = icmp slt <2 x i32> %rem.i, zeroinitializer
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%add.i = select <2 x i1> %cmp.i, <2 x i32> <i32 4, i32 4>, <2 x i32> zeroinitializer
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%ret.i = add nsw <2 x i32> %add.i, %rem.i
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ret <2 x i32> %ret.i
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}
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define i32 @modulo7(i32 %x) {
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; CHECK-LABEL: @modulo7(
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; CHECK-NEXT: [[REM_I:%.*]] = srem i32 [[X:%.*]], 7
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; CHECK-NEXT: [[CMP_I:%.*]] = icmp slt i32 [[REM_I]], 0
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; CHECK-NEXT: [[ADD_I:%.*]] = select i1 [[CMP_I]], i32 7, i32 0
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; CHECK-NEXT: [[RET_I:%.*]] = add nsw i32 [[ADD_I]], [[REM_I]]
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; CHECK-NEXT: ret i32 [[RET_I]]
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;
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%rem.i = srem i32 %x, 7
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%cmp.i = icmp slt i32 %rem.i, 0
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%add.i = select i1 %cmp.i, i32 7, i32 0
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%ret.i = add nsw i32 %add.i, %rem.i
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ret i32 %ret.i
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}
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define <2 x i32> @modulo7_vec(<2 x i32> %x) {
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; CHECK-LABEL: @modulo7_vec(
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; CHECK-NEXT: [[REM_I:%.*]] = srem <2 x i32> [[X:%.*]], <i32 7, i32 7>
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; CHECK-NEXT: [[CMP_I:%.*]] = icmp slt <2 x i32> [[REM_I]], zeroinitializer
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; CHECK-NEXT: [[ADD_I:%.*]] = select <2 x i1> [[CMP_I]], <2 x i32> <i32 7, i32 7>, <2 x i32> zeroinitializer
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; CHECK-NEXT: [[RET_I:%.*]] = add nsw <2 x i32> [[ADD_I]], [[REM_I]]
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; CHECK-NEXT: ret <2 x i32> [[RET_I]]
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;
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%rem.i = srem <2 x i32> %x, <i32 7, i32 7>
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%cmp.i = icmp slt <2 x i32> %rem.i, zeroinitializer
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%add.i = select <2 x i1> %cmp.i, <2 x i32> <i32 7, i32 7>, <2 x i32> zeroinitializer
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%ret.i = add nsw <2 x i32> %add.i, %rem.i
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ret <2 x i32> %ret.i
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}
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define i32 @modulo32(i32 %x) {
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; CHECK-LABEL: @modulo32(
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; CHECK-NEXT: [[RET_I:%.*]] = and i32 [[X:%.*]], 31
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; CHECK-NEXT: ret i32 [[RET_I]]
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;
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%rem.i = srem i32 %x, 32
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%cmp.i = icmp slt i32 %rem.i, 0
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%add.i = select i1 %cmp.i, i32 32, i32 0
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%ret.i = add nsw i32 %add.i, %rem.i
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ret i32 %ret.i
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}
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define <2 x i32> @modulo32_vec(<2 x i32> %x) {
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; CHECK-LABEL: @modulo32_vec(
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; CHECK-NEXT: [[RET_I:%.*]] = and <2 x i32> [[X:%.*]], <i32 31, i32 31>
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; CHECK-NEXT: ret <2 x i32> [[RET_I]]
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;
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%rem.i = srem <2 x i32> %x, <i32 32, i32 32>
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%cmp.i = icmp slt <2 x i32> %rem.i, zeroinitializer
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%add.i = select <2 x i1> %cmp.i, <2 x i32> <i32 32, i32 32>, <2 x i32> zeroinitializer
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%ret.i = add nsw <2 x i32> %add.i, %rem.i
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ret <2 x i32> %ret.i
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}
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define <2 x i32> @modulo16_32_vec(<2 x i32> %x) {
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; CHECK-LABEL: @modulo16_32_vec(
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; CHECK-NEXT: [[REM_I:%.*]] = srem <2 x i32> [[X:%.*]], <i32 16, i32 32>
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; CHECK-NEXT: [[CMP_I:%.*]] = icmp slt <2 x i32> [[REM_I]], zeroinitializer
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; CHECK-NEXT: [[ADD_I:%.*]] = select <2 x i1> [[CMP_I]], <2 x i32> <i32 16, i32 32>, <2 x i32> zeroinitializer
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; CHECK-NEXT: [[RET_I:%.*]] = add nsw <2 x i32> [[ADD_I]], [[REM_I]]
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; CHECK-NEXT: ret <2 x i32> [[RET_I]]
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;
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%rem.i = srem <2 x i32> %x, <i32 16, i32 32>
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%cmp.i = icmp slt <2 x i32> %rem.i, zeroinitializer
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%add.i = select <2 x i1> %cmp.i, <2 x i32> <i32 16, i32 32>, <2 x i32> zeroinitializer
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%ret.i = add nsw <2 x i32> %add.i, %rem.i
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ret <2 x i32> %ret.i
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}
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