564 lines
15 KiB
LLVM
564 lines
15 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=instcombine -S | FileCheck %s
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declare void @use(i32)
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declare void @use_vec(<2 x i8>)
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define i1 @test_nuw_and_unsigned_pred(i64 %x) {
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; CHECK-LABEL: @test_nuw_and_unsigned_pred(
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; CHECK-NEXT: [[Z:%.*]] = icmp ugt i64 [[X:%.*]], 7
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; CHECK-NEXT: ret i1 [[Z]]
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;
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%y = sub nuw i64 10, %x
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%z = icmp ult i64 %y, 3
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ret i1 %z
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}
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define i1 @test_nsw_and_signed_pred(i64 %x) {
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; CHECK-LABEL: @test_nsw_and_signed_pred(
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; CHECK-NEXT: [[Z:%.*]] = icmp slt i64 [[X:%.*]], -7
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; CHECK-NEXT: ret i1 [[Z]]
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;
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%y = sub nsw i64 3, %x
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%z = icmp sgt i64 %y, 10
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ret i1 %z
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}
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define i1 @test_nuw_nsw_and_unsigned_pred(i64 %x) {
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; CHECK-LABEL: @test_nuw_nsw_and_unsigned_pred(
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; CHECK-NEXT: [[Z:%.*]] = icmp ugt i64 [[X:%.*]], 6
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; CHECK-NEXT: ret i1 [[Z]]
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;
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%y = sub nuw nsw i64 10, %x
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%z = icmp ule i64 %y, 3
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ret i1 %z
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}
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define i1 @test_nuw_nsw_and_signed_pred(i64 %x) {
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; CHECK-LABEL: @test_nuw_nsw_and_signed_pred(
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; CHECK-NEXT: [[Z:%.*]] = icmp sgt i64 [[X:%.*]], 7
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; CHECK-NEXT: ret i1 [[Z]]
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;
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%y = sub nuw nsw i64 10, %x
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%z = icmp slt i64 %y, 3
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ret i1 %z
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}
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define i1 @test_negative_nuw_and_signed_pred(i64 %x) {
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; CHECK-LABEL: @test_negative_nuw_and_signed_pred(
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; CHECK-NEXT: [[NOTSUB:%.*]] = add nuw i64 [[X:%.*]], -11
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; CHECK-NEXT: [[Z:%.*]] = icmp sgt i64 [[NOTSUB]], -4
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; CHECK-NEXT: ret i1 [[Z]]
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;
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%y = sub nuw i64 10, %x
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%z = icmp slt i64 %y, 3
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ret i1 %z
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}
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define i1 @test_negative_nsw_and_unsigned_pred(i64 %x) {
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; CHECK-LABEL: @test_negative_nsw_and_unsigned_pred(
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; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[X:%.*]], -8
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; CHECK-NEXT: [[Z:%.*]] = icmp ult i64 [[TMP1]], 3
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; CHECK-NEXT: ret i1 [[Z]]
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;
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%y = sub nsw i64 10, %x
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%z = icmp ult i64 %y, 3
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ret i1 %z
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}
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define i1 @test_negative_combined_sub_unsigned_overflow(i64 %x) {
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; CHECK-LABEL: @test_negative_combined_sub_unsigned_overflow(
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; CHECK-NEXT: ret i1 true
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;
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%y = sub nuw i64 10, %x
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%z = icmp ult i64 %y, 11
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ret i1 %z
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}
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define i1 @test_negative_combined_sub_signed_overflow(i8 %x) {
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; CHECK-LABEL: @test_negative_combined_sub_signed_overflow(
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; CHECK-NEXT: ret i1 false
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;
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%y = sub nsw i8 127, %x
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%z = icmp slt i8 %y, -1
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ret i1 %z
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}
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define i1 @test_sub_0_Y_eq_0(i8 %y) {
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; CHECK-LABEL: @test_sub_0_Y_eq_0(
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; CHECK-NEXT: [[Z:%.*]] = icmp eq i8 [[Y:%.*]], 0
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; CHECK-NEXT: ret i1 [[Z]]
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;
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%s = sub i8 0, %y
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%z = icmp eq i8 %s, 0
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ret i1 %z
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}
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define i1 @test_sub_0_Y_ne_0(i8 %y) {
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; CHECK-LABEL: @test_sub_0_Y_ne_0(
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; CHECK-NEXT: [[Z:%.*]] = icmp ne i8 [[Y:%.*]], 0
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; CHECK-NEXT: ret i1 [[Z]]
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;
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%s = sub i8 0, %y
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%z = icmp ne i8 %s, 0
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ret i1 %z
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}
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define i1 @test_sub_4_Y_ne_4(i8 %y) {
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; CHECK-LABEL: @test_sub_4_Y_ne_4(
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; CHECK-NEXT: [[Z:%.*]] = icmp ne i8 [[Y:%.*]], 0
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; CHECK-NEXT: ret i1 [[Z]]
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;
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%s = sub i8 4, %y
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%z = icmp ne i8 %s, 4
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ret i1 %z
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}
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define i1 @test_sub_127_Y_eq_127(i8 %y) {
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; CHECK-LABEL: @test_sub_127_Y_eq_127(
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; CHECK-NEXT: [[Z:%.*]] = icmp eq i8 [[Y:%.*]], 0
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; CHECK-NEXT: ret i1 [[Z]]
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;
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%s = sub i8 127, %y
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%z = icmp eq i8 %s, 127
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ret i1 %z
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}
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define i1 @test_sub_255_Y_eq_255(i8 %y) {
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; CHECK-LABEL: @test_sub_255_Y_eq_255(
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; CHECK-NEXT: [[Z:%.*]] = icmp eq i8 [[Y:%.*]], 0
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; CHECK-NEXT: ret i1 [[Z]]
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;
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%s = sub i8 255, %y
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%z = icmp eq i8 %s, 255
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ret i1 %z
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}
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define <2 x i1> @test_sub_255_Y_eq_255_vec(<2 x i8> %y) {
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; CHECK-LABEL: @test_sub_255_Y_eq_255_vec(
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; CHECK-NEXT: [[Z:%.*]] = icmp eq <2 x i8> [[Y:%.*]], zeroinitializer
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; CHECK-NEXT: ret <2 x i1> [[Z]]
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;
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%s = sub <2 x i8> <i8 255, i8 255>, %y
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%z = icmp eq <2 x i8> %s, <i8 255, i8 255>
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ret <2 x i1> %z
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}
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define <2 x i1> @icmp_eq_sub_undef(<2 x i32> %a) {
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; CHECK-LABEL: @icmp_eq_sub_undef(
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[A:%.*]], <i32 5, i32 undef>
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; CHECK-NEXT: ret <2 x i1> [[CMP]]
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;
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%sub = sub <2 x i32> <i32 15, i32 undef>, %a
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%cmp = icmp eq <2 x i32> %sub, <i32 10, i32 10>
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ret <2 x i1> %cmp
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}
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define <2 x i1> @icmp_eq_sub_non_splat(<2 x i32> %a) {
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; CHECK-LABEL: @icmp_eq_sub_non_splat(
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[A:%.*]], <i32 5, i32 6>
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; CHECK-NEXT: ret <2 x i1> [[CMP]]
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;
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%sub = sub <2 x i32> <i32 15, i32 16>, %a
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%cmp = icmp eq <2 x i32> %sub, <i32 10, i32 10>
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ret <2 x i1> %cmp
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}
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define <2 x i1> @icmp_eq_sub_undef2(<2 x i32> %a) {
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; CHECK-LABEL: @icmp_eq_sub_undef2(
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; CHECK-NEXT: [[SUB:%.*]] = sub <2 x i32> <i32 15, i32 15>, [[A:%.*]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[SUB]], <i32 10, i32 undef>
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; CHECK-NEXT: ret <2 x i1> [[CMP]]
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;
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%sub = sub <2 x i32> <i32 15, i32 15>, %a
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%cmp = icmp eq <2 x i32> %sub, <i32 10, i32 undef>
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ret <2 x i1> %cmp
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}
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define <2 x i1> @icmp_eq_sub_non_splat2(<2 x i32> %a) {
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; CHECK-LABEL: @icmp_eq_sub_non_splat2(
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; CHECK-NEXT: [[SUB:%.*]] = sub <2 x i32> <i32 15, i32 15>, [[A:%.*]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[SUB]], <i32 10, i32 11>
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; CHECK-NEXT: ret <2 x i1> [[CMP]]
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;
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%sub = sub <2 x i32> <i32 15, i32 15>, %a
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%cmp = icmp eq <2 x i32> %sub, <i32 10, i32 11>
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ret <2 x i1> %cmp
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}
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define i1 @neg_sgt_42(i32 %x) {
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; CHECK-LABEL: @neg_sgt_42(
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; CHECK-NEXT: [[NOTSUB:%.*]] = add i32 [[X:%.*]], -1
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; CHECK-NEXT: [[R:%.*]] = icmp slt i32 [[NOTSUB]], -43
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; CHECK-NEXT: ret i1 [[R]]
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;
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%negx = sub i32 0, %x
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%r = icmp sgt i32 %negx, 42
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ret i1 %r
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}
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define i1 @neg_eq_43(i32 %x) {
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; CHECK-LABEL: @neg_eq_43(
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; CHECK-NEXT: [[NEGX:%.*]] = sub i32 0, [[X:%.*]]
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; CHECK-NEXT: call void @use(i32 [[NEGX]])
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; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[X]], -43
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; CHECK-NEXT: ret i1 [[R]]
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;
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%negx = sub i32 0, %x
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call void @use(i32 %negx)
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%r = icmp eq i32 %negx, 43
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ret i1 %r
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}
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define i1 @neg_ne_44(i32 %x) {
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; CHECK-LABEL: @neg_ne_44(
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; CHECK-NEXT: [[NEGX:%.*]] = sub i32 0, [[X:%.*]]
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; CHECK-NEXT: call void @use(i32 [[NEGX]])
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; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[X]], -44
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; CHECK-NEXT: ret i1 [[R]]
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;
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%negx = sub i32 0, %x
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call void @use(i32 %negx)
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%r = icmp ne i32 %negx, 44
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ret i1 %r
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}
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define i1 @neg_nsw_eq_45(i32 %x) {
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; CHECK-LABEL: @neg_nsw_eq_45(
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; CHECK-NEXT: [[NEGX:%.*]] = sub nsw i32 0, [[X:%.*]]
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; CHECK-NEXT: call void @use(i32 [[NEGX]])
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; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[X]], -45
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; CHECK-NEXT: ret i1 [[R]]
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;
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%negx = sub nsw i32 0, %x
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call void @use(i32 %negx)
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%r = icmp eq i32 %negx, 45
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ret i1 %r
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}
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define i1 @neg_nsw_ne_46(i32 %x) {
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; CHECK-LABEL: @neg_nsw_ne_46(
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; CHECK-NEXT: [[NEGX:%.*]] = sub nsw i32 0, [[X:%.*]]
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; CHECK-NEXT: call void @use(i32 [[NEGX]])
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; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[X]], -46
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; CHECK-NEXT: ret i1 [[R]]
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;
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%negx = sub nsw i32 0, %x
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call void @use(i32 %negx)
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%r = icmp ne i32 %negx, 46
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ret i1 %r
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}
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define i1 @subC_eq(i32 %x) {
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; CHECK-LABEL: @subC_eq(
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; CHECK-NEXT: [[SUBX:%.*]] = sub i32 -2147483648, [[X:%.*]]
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; CHECK-NEXT: call void @use(i32 [[SUBX]])
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; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[X]], 2147483605
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; CHECK-NEXT: ret i1 [[R]]
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;
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%subx = sub i32 -2147483648, %x
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call void @use(i32 %subx)
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%r = icmp eq i32 %subx, 43
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ret i1 %r
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}
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define <2 x i1> @subC_ne(<2 x i8> %x) {
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; CHECK-LABEL: @subC_ne(
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; CHECK-NEXT: [[SUBX:%.*]] = sub <2 x i8> <i8 -6, i8 -128>, [[X:%.*]]
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; CHECK-NEXT: call void @use_vec(<2 x i8> [[SUBX]])
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; CHECK-NEXT: [[R:%.*]] = icmp ne <2 x i8> [[X]], <i8 38, i8 -84>
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; CHECK-NEXT: ret <2 x i1> [[R]]
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;
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%subx = sub <2 x i8> <i8 -6, i8 -128>, %x
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call void @use_vec(<2 x i8> %subx)
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%r = icmp ne <2 x i8> %subx, <i8 -44, i8 -44>
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ret <2 x i1> %r
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}
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define i1 @subC_nsw_eq(i32 %x) {
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; CHECK-LABEL: @subC_nsw_eq(
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; CHECK-NEXT: [[SUBX:%.*]] = sub nsw i32 -100, [[X:%.*]]
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; CHECK-NEXT: call void @use(i32 [[SUBX]])
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; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[X]], 2147483548
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; CHECK-NEXT: ret i1 [[R]]
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;
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%subx = sub nsw i32 -100, %x
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call void @use(i32 %subx)
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%r = icmp eq i32 %subx, -2147483648
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ret i1 %r
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}
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define i1 @subC_nsw_ne(i32 %x) {
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; CHECK-LABEL: @subC_nsw_ne(
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; CHECK-NEXT: [[SUBX:%.*]] = sub nsw i32 -2147483647, [[X:%.*]]
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; CHECK-NEXT: call void @use(i32 [[SUBX]])
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; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[X]], 2147483603
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; CHECK-NEXT: ret i1 [[R]]
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;
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%subx = sub nsw i32 -2147483647, %x
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call void @use(i32 %subx)
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%r = icmp ne i32 %subx, 46
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ret i1 %r
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}
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define i1 @neg_slt_42(i128 %x) {
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; CHECK-LABEL: @neg_slt_42(
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; CHECK-NEXT: [[NOTSUB:%.*]] = add i128 [[X:%.*]], -1
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; CHECK-NEXT: [[R:%.*]] = icmp sgt i128 [[NOTSUB]], -43
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; CHECK-NEXT: ret i1 [[R]]
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;
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%negx = sub i128 0, %x
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%r = icmp slt i128 %negx, 42
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ret i1 %r
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}
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define <2 x i1> @neg_ugt_42_splat(<2 x i7> %x) {
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; CHECK-LABEL: @neg_ugt_42_splat(
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; CHECK-NEXT: [[NOTSUB:%.*]] = add <2 x i7> [[X:%.*]], <i7 -1, i7 -1>
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; CHECK-NEXT: [[R:%.*]] = icmp ult <2 x i7> [[NOTSUB]], <i7 -43, i7 -43>
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; CHECK-NEXT: ret <2 x i1> [[R]]
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;
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%negx = sub <2 x i7> zeroinitializer, %x
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%r = icmp ugt <2 x i7> %negx, <i7 42, i7 42>
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ret <2 x i1> %r
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}
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define i1 @neg_sgt_42_use(i32 %x) {
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; CHECK-LABEL: @neg_sgt_42_use(
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; CHECK-NEXT: [[NEGX:%.*]] = sub i32 0, [[X:%.*]]
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; CHECK-NEXT: call void @use(i32 [[NEGX]])
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; CHECK-NEXT: [[R:%.*]] = icmp sgt i32 [[NEGX]], 42
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; CHECK-NEXT: ret i1 [[R]]
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;
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%negx = sub i32 0, %x
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call void @use(i32 %negx)
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%r = icmp sgt i32 %negx, 42
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ret i1 %r
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}
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; Test common/edge cases with signed pred.
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define i1 @neg_slt_n1(i8 %x) {
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; CHECK-LABEL: @neg_slt_n1(
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; CHECK-NEXT: [[NOTSUB:%.*]] = add i8 [[X:%.*]], -1
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; CHECK-NEXT: [[R:%.*]] = icmp sgt i8 [[NOTSUB]], 0
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; CHECK-NEXT: ret i1 [[R]]
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;
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%negx = sub i8 0, %x
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%r = icmp slt i8 %negx, -1
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ret i1 %r
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}
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define i1 @neg_slt_0(i8 %x) {
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; CHECK-LABEL: @neg_slt_0(
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; CHECK-NEXT: [[NOTSUB:%.*]] = add i8 [[X:%.*]], -1
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; CHECK-NEXT: [[ISNEGNEG:%.*]] = icmp sgt i8 [[NOTSUB]], -1
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; CHECK-NEXT: ret i1 [[ISNEGNEG]]
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;
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%negx = sub i8 0, %x
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%isnegneg = icmp slt i8 %negx, 0
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ret i1 %isnegneg
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}
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define i1 @neg_slt_1(i8 %x) {
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; CHECK-LABEL: @neg_slt_1(
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; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[X:%.*]], -127
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; CHECK-NEXT: ret i1 [[R]]
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;
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%negx = sub i8 0, %x
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%r = icmp slt i8 %negx, 1
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ret i1 %r
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}
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define i1 @neg_sgt_n1(i8 %x) {
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; CHECK-LABEL: @neg_sgt_n1(
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; CHECK-NEXT: [[NOTSUB:%.*]] = add i8 [[X:%.*]], -1
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; CHECK-NEXT: [[R:%.*]] = icmp slt i8 [[NOTSUB]], 0
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; CHECK-NEXT: ret i1 [[R]]
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;
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%negx = sub i8 0, %x
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%r = icmp sgt i8 %negx, -1
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ret i1 %r
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}
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define i1 @neg_sgt_0(i8 %x) {
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; CHECK-LABEL: @neg_sgt_0(
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; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[X:%.*]], -128
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; CHECK-NEXT: ret i1 [[R]]
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;
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%negx = sub i8 0, %x
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%r = icmp sgt i8 %negx, 0
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ret i1 %r
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}
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define i1 @neg_sgt_1(i8 %x) {
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; CHECK-LABEL: @neg_sgt_1(
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; CHECK-NEXT: [[NOTSUB:%.*]] = add i8 [[X:%.*]], -1
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; CHECK-NEXT: [[R:%.*]] = icmp slt i8 [[NOTSUB]], -2
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; CHECK-NEXT: ret i1 [[R]]
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;
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%negx = sub i8 0, %x
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%r = icmp sgt i8 %negx, 1
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ret i1 %r
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}
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; Test common/edge cases with signed pred and nsw.
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define i1 @neg_nsw_slt_n1(i8 %x) {
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; CHECK-LABEL: @neg_nsw_slt_n1(
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; CHECK-NEXT: [[R:%.*]] = icmp sgt i8 [[X:%.*]], 1
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; CHECK-NEXT: ret i1 [[R]]
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;
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%negx = sub nsw i8 0, %x
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%r = icmp slt i8 %negx, -1
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ret i1 %r
|
|
}
|
|
|
|
define i1 @neg_nsw_slt_0(i8 %x) {
|
|
; CHECK-LABEL: @neg_nsw_slt_0(
|
|
; CHECK-NEXT: [[ISNEGNEG:%.*]] = icmp sgt i8 [[X:%.*]], 0
|
|
; CHECK-NEXT: ret i1 [[ISNEGNEG]]
|
|
;
|
|
%negx = sub nsw i8 0, %x
|
|
%isnegneg = icmp slt i8 %negx, 0
|
|
ret i1 %isnegneg
|
|
}
|
|
|
|
define i1 @neg_nsw_slt_1(i8 %x) {
|
|
; CHECK-LABEL: @neg_nsw_slt_1(
|
|
; CHECK-NEXT: [[R:%.*]] = icmp sgt i8 [[X:%.*]], -1
|
|
; CHECK-NEXT: ret i1 [[R]]
|
|
;
|
|
%negx = sub nsw i8 0, %x
|
|
%r = icmp slt i8 %negx, 1
|
|
ret i1 %r
|
|
}
|
|
|
|
define i1 @neg_nsw_sgt_n1(i8 %x) {
|
|
; CHECK-LABEL: @neg_nsw_sgt_n1(
|
|
; CHECK-NEXT: [[R:%.*]] = icmp slt i8 [[X:%.*]], 1
|
|
; CHECK-NEXT: ret i1 [[R]]
|
|
;
|
|
%negx = sub nsw i8 0, %x
|
|
%r = icmp sgt i8 %negx, -1
|
|
ret i1 %r
|
|
}
|
|
|
|
define i1 @neg_nsw_sgt_0(i8 %x) {
|
|
; CHECK-LABEL: @neg_nsw_sgt_0(
|
|
; CHECK-NEXT: [[R:%.*]] = icmp slt i8 [[X:%.*]], 0
|
|
; CHECK-NEXT: ret i1 [[R]]
|
|
;
|
|
%negx = sub nsw i8 0, %x
|
|
%r = icmp sgt i8 %negx, 0
|
|
ret i1 %r
|
|
}
|
|
|
|
define i1 @neg_nsw_sgt_1(i8 %x) {
|
|
; CHECK-LABEL: @neg_nsw_sgt_1(
|
|
; CHECK-NEXT: [[R:%.*]] = icmp slt i8 [[X:%.*]], -1
|
|
; CHECK-NEXT: ret i1 [[R]]
|
|
;
|
|
%negx = sub nsw i8 0, %x
|
|
%r = icmp sgt i8 %negx, 1
|
|
ret i1 %r
|
|
}
|
|
|
|
define i1 @sub_eq_zero_use(i32 %x, i32 %y) {
|
|
; CHECK-LABEL: @sub_eq_zero_use(
|
|
; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[X:%.*]], [[Y:%.*]]
|
|
; CHECK-NEXT: call void @use(i32 [[SUB]])
|
|
; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[X]], [[Y]]
|
|
; CHECK-NEXT: ret i1 [[R]]
|
|
;
|
|
%sub = sub i32 %x, %y
|
|
call void @use(i32 %sub)
|
|
%r = icmp eq i32 %sub, 0
|
|
ret i1 %r
|
|
}
|
|
|
|
define <2 x i1> @sub_ne_zero_use(<2 x i8> %x, <2 x i8> %y) {
|
|
; CHECK-LABEL: @sub_ne_zero_use(
|
|
; CHECK-NEXT: [[SUB:%.*]] = sub <2 x i8> [[X:%.*]], [[Y:%.*]]
|
|
; CHECK-NEXT: call void @use_vec(<2 x i8> [[SUB]])
|
|
; CHECK-NEXT: [[R:%.*]] = icmp eq <2 x i8> [[X]], [[Y]]
|
|
; CHECK-NEXT: ret <2 x i1> [[R]]
|
|
;
|
|
%sub = sub <2 x i8> %x, %y
|
|
call void @use_vec(<2 x i8> %sub)
|
|
%r = icmp eq <2 x i8> %sub, zeroinitializer
|
|
ret <2 x i1> %r
|
|
}
|
|
|
|
define i32 @sub_eq_zero_select(i32 %a, i32 %b, ptr %p) {
|
|
; CHECK-LABEL: @sub_eq_zero_select(
|
|
; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[A:%.*]], [[B:%.*]]
|
|
; CHECK-NEXT: store i32 [[SUB]], ptr [[P:%.*]], align 4
|
|
; CHECK-NEXT: ret i32 [[B]]
|
|
;
|
|
%sub = sub i32 %a, %b
|
|
store i32 %sub, ptr %p
|
|
%cmp = icmp eq i32 %sub, 0
|
|
%sel = select i1 %cmp, i32 %a, i32 %b
|
|
ret i32 %sel
|
|
}
|
|
|
|
; Replacing the "SUB == 0" regresses codegen, and it may be hard to recover from that.
|
|
|
|
declare i32 @llvm.umin.i32(i32, i32)
|
|
|
|
define void @PR54558_reduced(i32 %arg) {
|
|
; CHECK-LABEL: @PR54558_reduced(
|
|
; CHECK-NEXT: bb_entry:
|
|
; CHECK-NEXT: br label [[BB_LOOP:%.*]]
|
|
; CHECK: bb_loop:
|
|
; CHECK-NEXT: [[PHI_OUTER:%.*]] = phi i32 [ [[SUB:%.*]], [[BB_LOOP]] ], [ [[ARG:%.*]], [[BB_ENTRY:%.*]] ]
|
|
; CHECK-NEXT: [[MIN:%.*]] = tail call i32 @llvm.umin.i32(i32 [[PHI_OUTER]], i32 43)
|
|
; CHECK-NEXT: call void @use(i32 [[MIN]])
|
|
; CHECK-NEXT: [[SUB]] = sub i32 [[PHI_OUTER]], [[MIN]]
|
|
; CHECK-NEXT: [[COND_OUTER:%.*]] = icmp eq i32 [[SUB]], 0
|
|
; CHECK-NEXT: br i1 [[COND_OUTER]], label [[BB_EXIT:%.*]], label [[BB_LOOP]]
|
|
; CHECK: bb_exit:
|
|
; CHECK-NEXT: ret void
|
|
;
|
|
bb_entry:
|
|
br label %bb_loop
|
|
|
|
bb_loop:
|
|
%phi_outer = phi i32 [ %sub, %bb_loop ], [ %arg, %bb_entry ]
|
|
%min = tail call i32 @llvm.umin.i32(i32 %phi_outer, i32 43)
|
|
call void @use(i32 %min)
|
|
%sub = sub i32 %phi_outer, %min
|
|
%cond_outer = icmp eq i32 %sub, 0
|
|
br i1 %cond_outer, label %bb_exit, label %bb_loop
|
|
|
|
bb_exit:
|
|
ret void
|
|
}
|
|
|
|
; TODO: It might be ok to replace the "SUB == 0" in this example if codegen can invert it.
|
|
|
|
define void @PR54558_reduced_more(i32 %x, i32 %y) {
|
|
; CHECK-LABEL: @PR54558_reduced_more(
|
|
; CHECK-NEXT: bb_entry:
|
|
; CHECK-NEXT: br label [[BB_LOOP:%.*]]
|
|
; CHECK: bb_loop:
|
|
; CHECK-NEXT: [[PHI_OUTER:%.*]] = phi i32 [ [[SUB:%.*]], [[BB_LOOP]] ], [ [[X:%.*]], [[BB_ENTRY:%.*]] ]
|
|
; CHECK-NEXT: [[SUB]] = sub i32 [[PHI_OUTER]], [[Y:%.*]]
|
|
; CHECK-NEXT: [[COND_OUTER:%.*]] = icmp eq i32 [[SUB]], 0
|
|
; CHECK-NEXT: br i1 [[COND_OUTER]], label [[BB_EXIT:%.*]], label [[BB_LOOP]]
|
|
; CHECK: bb_exit:
|
|
; CHECK-NEXT: ret void
|
|
;
|
|
bb_entry:
|
|
br label %bb_loop
|
|
|
|
bb_loop:
|
|
%phi_outer = phi i32 [ %sub, %bb_loop ], [ %x, %bb_entry ]
|
|
%sub = sub i32 %phi_outer, %y
|
|
%cond_outer = icmp eq i32 %sub, 0
|
|
br i1 %cond_outer, label %bb_exit, label %bb_loop
|
|
|
|
bb_exit:
|
|
ret void
|
|
}
|