295 lines
8.8 KiB
LLVM
295 lines
8.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=instcombine -S | FileCheck %s
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declare void @use(i8)
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define i1 @mul_mask_pow2_eq0(i8 %x) {
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; CHECK-LABEL: @mul_mask_pow2_eq0(
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; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], 1
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[TMP1]], 0
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%mul = mul i8 %x, 44
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%and = and i8 %mul, 4
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%cmp = icmp eq i8 %and, 0
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ret i1 %cmp
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}
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; TODO: Demanded bits does not convert the mul to shift,
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; but the 'and' could be of 'x' directly.
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define i1 @mul_mask_pow2_ne0_use1(i8 %x) {
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; CHECK-LABEL: @mul_mask_pow2_ne0_use1(
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; CHECK-NEXT: [[MUL:%.*]] = mul i8 [[X:%.*]], 40
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; CHECK-NEXT: call void @use(i8 [[MUL]])
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; CHECK-NEXT: [[AND:%.*]] = and i8 [[MUL]], 8
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; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[AND]], 0
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%mul = mul i8 %x, 40
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call void @use(i8 %mul)
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%and = and i8 %mul, 8
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%cmp = icmp ne i8 %and, 0
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ret i1 %cmp
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}
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; negative test - extra use of 'and' would require more instructions
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define i1 @mul_mask_pow2_ne0_use2(i8 %x) {
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; CHECK-LABEL: @mul_mask_pow2_ne0_use2(
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; CHECK-NEXT: [[MUL:%.*]] = shl i8 [[X:%.*]], 3
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; CHECK-NEXT: [[AND:%.*]] = and i8 [[MUL]], 8
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; CHECK-NEXT: call void @use(i8 [[AND]])
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; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[AND]], 0
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%mul = mul i8 %x, 40
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%and = and i8 %mul, 8
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call void @use(i8 %and)
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%cmp = icmp ne i8 %and, 0
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ret i1 %cmp
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}
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; non-equality predicates are converted to equality
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define i1 @mul_mask_pow2_sgt0(i8 %x) {
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; CHECK-LABEL: @mul_mask_pow2_sgt0(
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; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], 1
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; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[TMP1]], 0
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%mul = mul i8 %x, 44
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%and = and i8 %mul, 4
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%cmp = icmp sgt i8 %and, 0
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ret i1 %cmp
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}
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; unnecessary mask bits are removed
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define i1 @mul_mask_fakepow2_ne0(i8 %x) {
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; CHECK-LABEL: @mul_mask_fakepow2_ne0(
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; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], 1
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; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[TMP1]], 0
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%mul = mul i8 %x, 44
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%and = and i8 %mul, 5
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%cmp = icmp ne i8 %and, 0
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ret i1 %cmp
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}
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; non-zero cmp constant is converted
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define i1 @mul_mask_pow2_eq4(i8 %x) {
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; CHECK-LABEL: @mul_mask_pow2_eq4(
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; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], 1
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; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[TMP1]], 0
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%mul = mul i8 %x, 44
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%and = and i8 %mul, 4
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%cmp = icmp eq i8 %and, 4
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ret i1 %cmp
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}
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; negative test - must be pow2 mask constant
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define i1 @mul_mask_notpow2_ne(i8 %x) {
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; CHECK-LABEL: @mul_mask_notpow2_ne(
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; CHECK-NEXT: [[MUL:%.*]] = mul i8 [[X:%.*]], 12
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; CHECK-NEXT: [[AND:%.*]] = and i8 [[MUL]], 12
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; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[AND]], 0
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%mul = mul i8 %x, 60
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%and = and i8 %mul, 12
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%cmp = icmp ne i8 %and, 0
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ret i1 %cmp
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}
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define i1 @pr40493(i32 %area) {
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; CHECK-LABEL: @pr40493(
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AREA:%.*]], 1
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 0
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%mul = mul i32 %area, 12
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%rem = and i32 %mul, 4
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%cmp = icmp eq i32 %rem, 0
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ret i1 %cmp
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}
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define i1 @pr40493_neg1(i32 %area) {
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; CHECK-LABEL: @pr40493_neg1(
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; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[AREA:%.*]], 3
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; CHECK-NEXT: [[REM:%.*]] = and i32 [[MUL]], 4
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 0
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%mul = mul i32 %area, 11
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%rem = and i32 %mul, 4
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%cmp = icmp eq i32 %rem, 0
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ret i1 %cmp
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}
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define i1 @pr40493_neg2(i32 %area) {
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; CHECK-LABEL: @pr40493_neg2(
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; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[AREA:%.*]], 12
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; CHECK-NEXT: [[REM:%.*]] = and i32 [[MUL]], 12
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 0
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%mul = mul i32 %area, 12
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%rem = and i32 %mul, 15
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%cmp = icmp eq i32 %rem, 0
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ret i1 %cmp
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}
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define i32 @pr40493_neg3(i32 %area) {
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; CHECK-LABEL: @pr40493_neg3(
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; CHECK-NEXT: [[MUL:%.*]] = shl i32 [[AREA:%.*]], 2
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; CHECK-NEXT: [[REM:%.*]] = and i32 [[MUL]], 4
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; CHECK-NEXT: ret i32 [[REM]]
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;
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%mul = mul i32 %area, 12
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%rem = and i32 %mul, 4
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ret i32 %rem
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}
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define <4 x i1> @pr40493_vec1(<4 x i32> %area) {
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; CHECK-LABEL: @pr40493_vec1(
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; CHECK-NEXT: [[TMP1:%.*]] = and <4 x i32> [[AREA:%.*]], <i32 1, i32 1, i32 1, i32 1>
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[TMP1]], zeroinitializer
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; CHECK-NEXT: ret <4 x i1> [[CMP]]
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;
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%mul = mul <4 x i32> %area, <i32 12, i32 12, i32 12, i32 12>
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%rem = and <4 x i32> %mul, <i32 4, i32 4, i32 4, i32 4>
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%cmp = icmp eq <4 x i32> %rem, zeroinitializer
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ret <4 x i1> %cmp
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}
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define <4 x i1> @pr40493_vec2(<4 x i32> %area) {
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; CHECK-LABEL: @pr40493_vec2(
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; CHECK-NEXT: [[MUL:%.*]] = mul <4 x i32> [[AREA:%.*]], <i32 12, i32 12, i32 12, i32 undef>
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; CHECK-NEXT: [[REM:%.*]] = and <4 x i32> [[MUL]], <i32 4, i32 4, i32 4, i32 4>
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[REM]], zeroinitializer
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; CHECK-NEXT: ret <4 x i1> [[CMP]]
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;
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%mul = mul <4 x i32> %area, <i32 12, i32 12, i32 12, i32 undef>
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%rem = and <4 x i32> %mul, <i32 4, i32 4, i32 4, i32 4>
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%cmp = icmp eq <4 x i32> %rem, zeroinitializer
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ret <4 x i1> %cmp
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}
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define <4 x i1> @pr40493_vec3(<4 x i32> %area) {
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; CHECK-LABEL: @pr40493_vec3(
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; CHECK-NEXT: [[MUL:%.*]] = mul <4 x i32> [[AREA:%.*]], <i32 12, i32 12, i32 12, i32 12>
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; CHECK-NEXT: [[REM:%.*]] = and <4 x i32> [[MUL]], <i32 4, i32 4, i32 4, i32 undef>
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[REM]], zeroinitializer
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; CHECK-NEXT: ret <4 x i1> [[CMP]]
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;
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%mul = mul <4 x i32> %area, <i32 12, i32 12, i32 12, i32 12>
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%rem = and <4 x i32> %mul, <i32 4, i32 4, i32 4, i32 undef>
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%cmp = icmp eq <4 x i32> %rem, zeroinitializer
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ret <4 x i1> %cmp
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}
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define <4 x i1> @pr40493_vec4(<4 x i32> %area) {
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; CHECK-LABEL: @pr40493_vec4(
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; CHECK-NEXT: [[MUL:%.*]] = mul <4 x i32> [[AREA:%.*]], <i32 12, i32 12, i32 12, i32 undef>
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; CHECK-NEXT: [[REM:%.*]] = and <4 x i32> [[MUL]], <i32 4, i32 4, i32 4, i32 undef>
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[REM]], zeroinitializer
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; CHECK-NEXT: ret <4 x i1> [[CMP]]
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;
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%mul = mul <4 x i32> %area, <i32 12, i32 12, i32 12, i32 undef>
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%rem = and <4 x i32> %mul, <i32 4, i32 4, i32 4, i32 undef>
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%cmp = icmp eq <4 x i32> %rem, zeroinitializer
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ret <4 x i1> %cmp
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}
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define <4 x i1> @pr40493_vec5(<4 x i32> %area) {
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; CHECK-LABEL: @pr40493_vec5(
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; CHECK-NEXT: [[MUL:%.*]] = mul <4 x i32> [[AREA:%.*]], <i32 12, i32 12, i32 20, i32 20>
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; CHECK-NEXT: [[REM:%.*]] = and <4 x i32> [[MUL]], <i32 2, i32 4, i32 2, i32 4>
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[REM]], zeroinitializer
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; CHECK-NEXT: ret <4 x i1> [[CMP]]
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;
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%mul = mul <4 x i32> %area, <i32 12, i32 12, i32 20, i32 20>
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%rem = and <4 x i32> %mul, <i32 2, i32 4, i32 2, i32 4>
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%cmp = icmp eq <4 x i32> %rem, zeroinitializer
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ret <4 x i1> %cmp
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}
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define i1 @pr51551(i32 %x, i32 %y) {
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; CHECK-LABEL: @pr51551(
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 3
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%t0 = and i32 %y, -7
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%t1 = or i32 %t0, 1
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%mul = mul nsw i32 %t1, %x
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%and = and i32 %mul, 3
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%cmp = icmp eq i32 %and, 0
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ret i1 %cmp
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}
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define i1 @pr51551_2(i32 %x, i32 %y) {
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; CHECK-LABEL: @pr51551_2(
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%t0 = and i32 %y, -7
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%t1 = or i32 %t0, 1
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%mul = mul nsw i32 %t1, %x
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%and = and i32 %mul, 1
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%cmp = icmp eq i32 %and, 0
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ret i1 %cmp
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}
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define i1 @pr51551_neg1(i32 %x, i32 %y) {
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; CHECK-LABEL: @pr51551_neg1(
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; CHECK-NEXT: [[T0:%.*]] = and i32 [[Y:%.*]], 4
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; CHECK-NEXT: [[T1:%.*]] = or i32 [[T0]], 1
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; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[T1]], [[X:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[MUL]], 7
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%t0 = and i32 %y, -3
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%t1 = or i32 %t0, 1
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%mul = mul nsw i32 %t1, %x
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%and = and i32 %mul, 7
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%cmp = icmp eq i32 %and, 0
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ret i1 %cmp
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}
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define i1 @pr51551_neg2(i32 %x, i32 %y) {
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; CHECK-LABEL: @pr51551_neg2(
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[Y:%.*]], 1
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; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP1]], 0
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; CHECK-NEXT: [[X_OP:%.*]] = and i32 [[X:%.*]], 7
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[X_OP]], 0
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; CHECK-NEXT: [[CMP:%.*]] = select i1 [[DOTNOT]], i1 true, i1 [[CMP1]]
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%t0 = and i32 %y, -7
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%mul = mul nsw i32 %t0, %x
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%and = and i32 %mul, 7
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%cmp = icmp eq i32 %and, 0
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ret i1 %cmp
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}
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define i32 @pr51551_demand3bits(i32 %x, i32 %y) {
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; CHECK-LABEL: @pr51551_demand3bits(
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 7
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; CHECK-NEXT: ret i32 [[AND]]
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;
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%t0 = and i32 %y, -7
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%t1 = or i32 %t0, 1
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%mul = mul nsw i32 %t1, %x
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%and = and i32 %mul, 7
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ret i32 %and
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}
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