llvm-project/llvm/test/MC/LoongArch/Basic/Integer
Weining Lu c98add7a11 [LoongArch] Report error in AsmParser when rd == rk or rd == rj for AM* instructions
Do this check because the ISA manual says (edited from the original translation):

> If the AM* instruction has its rd == rj, an Instruction Non-defined Exception will be triggered when the instruction is executed.
>
> If the AM* instruction has its rd == rk, the execution result is unpredictable. It is software's responsibility to avoid this situation.

Note that binutils does the same check except when rd == r0 but this
is undocumented.

Differential Revision: https://reviews.llvm.org/D136076
2022-10-21 09:56:45 +08:00
..
arith.s
atomic.s
barrier.s
bit-manipu.s
bit-shift.s
bound-check.s
branch.s
crc.s
invalid-dis.s
invalid.s [LoongArch] Add more fixups and relocations 2022-09-05 14:55:18 +08:00
invalid64.s [LoongArch] Report error in AsmParser when rd == rk or rd == rj for AM* instructions 2022-10-21 09:56:45 +08:00
memory.s [LoongArch] Add the missing ld.d instruction definition 2022-06-02 14:57:23 +08:00
misc.s
pseudos.s