126 lines
3.5 KiB
LLVM
126 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=x86-64 < %s | FileCheck %s
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; This file checks the reassociation of ADD instruction.
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; The two ADD instructions add v0,v1,t2 together. t2 has a long dependence
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; chain, v0 and v1 has a short dependence chain, in order to get the shortest
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; latency, v0 and v1 should be added first, and its result is added to t2
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; later.
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define void @add8(i8 %x0, i8 %x1, i8 %x2, i8* %p) {
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; CHECK-LABEL: add8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: orb $16, %dil
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; CHECK-NEXT: orb $32, %sil
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; CHECK-NEXT: addb %dil, %sil
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; CHECK-NEXT: addb $-8, %dl
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; CHECK-NEXT: orb $7, %dl
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; CHECK-NEXT: movzbl %dl, %eax
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; CHECK-NEXT: imull $100, %eax, %eax
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; CHECK-NEXT: addb %sil, %al
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; CHECK-NEXT: movb %al, (%rcx)
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; CHECK-NEXT: retq
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%v0 = or i8 %x0, 16
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%v1 = or i8 %x1, 32
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%t0 = sub i8 %x2, 8
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%t1 = or i8 %t0, 7
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%t2 = mul i8 %t1, 100
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%t3 = add i8 %t2, %v1
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%t4 = add i8 %t3, %v0
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store i8 %t4, i8* %p, align 4
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ret void
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}
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define void @add16(i16 %x0, i16 %x1, i16 %x2, i16* %p) {
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; CHECK-LABEL: add16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: orl $16, %edi
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; CHECK-NEXT: orl $32, %esi
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; CHECK-NEXT: addl %edi, %esi
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; CHECK-NEXT: addl $-8, %edx
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; CHECK-NEXT: orl $7, %edx
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; CHECK-NEXT: imull $100, %edx, %eax
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; CHECK-NEXT: addl %esi, %eax
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; CHECK-NEXT: movw %ax, (%rcx)
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; CHECK-NEXT: retq
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%v0 = or i16 %x0, 16
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%v1 = or i16 %x1, 32
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%t0 = sub i16 %x2, 8
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%t1 = or i16 %t0, 7
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%t2 = mul i16 %t1, 100
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%t3 = add i16 %t2, %v1
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%t4 = add i16 %t3, %v0
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store i16 %t4, i16* %p, align 4
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ret void
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}
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define void @add32(i32 %x0, i32 %x1, i32 %x2, i32* %p) {
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; CHECK-LABEL: add32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: orl $16, %edi
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; CHECK-NEXT: orl $32, %esi
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; CHECK-NEXT: addl %edi, %esi
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; CHECK-NEXT: addl $-8, %edx
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; CHECK-NEXT: orl $7, %edx
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; CHECK-NEXT: imull $100, %edx, %eax
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; CHECK-NEXT: addl %esi, %eax
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; CHECK-NEXT: movl %eax, (%rcx)
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; CHECK-NEXT: retq
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%v0 = or i32 %x0, 16
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%v1 = or i32 %x1, 32
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%t0 = sub i32 %x2, 8
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%t1 = or i32 %t0, 7
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%t2 = mul i32 %t1, 100
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%t3 = add i32 %t2, %v1
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%t4 = add i32 %t3, %v0
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store i32 %t4, i32* %p, align 4
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ret void
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}
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define void @add64(i64 %x0, i64 %x1, i64 %x2, i64* %p) {
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; CHECK-LABEL: add64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: orq $16, %rdi
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; CHECK-NEXT: orq $32, %rsi
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; CHECK-NEXT: addq %rdi, %rsi
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; CHECK-NEXT: addq $-8, %rdx
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; CHECK-NEXT: orq $7, %rdx
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; CHECK-NEXT: imulq $100, %rdx, %rax
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; CHECK-NEXT: addq %rsi, %rax
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; CHECK-NEXT: movq %rax, (%rcx)
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; CHECK-NEXT: retq
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%v0 = or i64 %x0, 16
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%v1 = or i64 %x1, 32
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%t0 = sub i64 %x2, 8
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%t1 = or i64 %t0, 7
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%t2 = mul i64 %t1, 100
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%t3 = add i64 %t2, %v1
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%t4 = add i64 %t3, %v0
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store i64 %t4, i64* %p, align 4
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ret void
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}
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; Negative test. Original sequence has shorter latency, don't transform it.
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define void @add64_negative(i64 %x0, i64 %x1, i64 %x2, i64* %p) {
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; CHECK-LABEL: add64_negative:
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; CHECK: # %bb.0:
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; CHECK-NEXT: orq $16, %rdi
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; CHECK-NEXT: orq $32, %rsi
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; CHECK-NEXT: addq %rdi, %rsi
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; CHECK-NEXT: addq $-8, %rdx
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; CHECK-NEXT: orq $7, %rdx
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; CHECK-NEXT: imulq $100, %rdx, %rax
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; CHECK-NEXT: addq %rsi, %rax
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; CHECK-NEXT: movq %rax, (%rcx)
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; CHECK-NEXT: retq
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%v0 = or i64 %x0, 16
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%v1 = or i64 %x1, 32
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%t0 = sub i64 %x2, 8
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%t1 = or i64 %t0, 7
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%t2 = mul i64 %t1, 100
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%t3 = add i64 %v0, %v1
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%t4 = add i64 %t3, %t2
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store i64 %t4, i64* %p, align 4
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ret void
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}
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