142 lines
4.0 KiB
LLVM
142 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-DSP
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; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NO-DSP
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; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefixes=CHECK,CHECK-DSP
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; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s -check-prefixes=CHECK,CHECK-NO-DSP
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; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefixes=CHECK,CHECK-DSP
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; rdar://11318438
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define zeroext i8 @test1(i32 %A.u) {
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; CHECK-LABEL: test1:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtb r0, r0
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; CHECK-NEXT: bx lr
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%B.u = trunc i32 %A.u to i8
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ret i8 %B.u
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}
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define zeroext i32 @test2(i32 %A.u, i32 %B.u) {
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; CHECK-DSP-LABEL: test2:
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; CHECK-DSP: @ %bb.0:
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; CHECK-DSP-NEXT: uxtab r0, r0, r1
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; CHECK-DSP-NEXT: bx lr
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;
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; CHECK-NO-DSP-LABEL: test2:
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; CHECK-NO-DSP: @ %bb.0:
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; CHECK-NO-DSP-NEXT: uxtb r1, r1
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; CHECK-NO-DSP-NEXT: add r0, r1
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; CHECK-NO-DSP-NEXT: bx lr
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%C.u = trunc i32 %B.u to i8
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%D.u = zext i8 %C.u to i32
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%E.u = add i32 %A.u, %D.u
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ret i32 %E.u
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}
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define zeroext i32 @test3(i32 %A.u) {
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; CHECK-LABEL: test3:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: ubfx r0, r0, #8, #16
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; CHECK-NEXT: bx lr
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%B.u = lshr i32 %A.u, 8
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%C.u = shl i32 %A.u, 24
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%D.u = or i32 %B.u, %C.u
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%E.u = trunc i32 %D.u to i16
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%F.u = zext i16 %E.u to i32
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ret i32 %F.u
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}
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define i32 @test4(i32 %A, i32 %X) {
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; CHECK-DSP-LABEL: test4:
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; CHECK-DSP: @ %bb.0:
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; CHECK-DSP-NEXT: uxtab r0, r0, r1, ror #16
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; CHECK-DSP-NEXT: bx lr
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;
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; CHECK-NO-DSP-LABEL: test4:
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; CHECK-NO-DSP: @ %bb.0:
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; CHECK-NO-DSP-NEXT: ubfx r1, r1, #16, #8
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; CHECK-NO-DSP-NEXT: add r0, r1
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; CHECK-NO-DSP-NEXT: bx lr
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%X.hi = lshr i32 %X, 16
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%X.trunc = trunc i32 %X.hi to i8
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%addend = zext i8 %X.trunc to i32
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%sum = add i32 %A, %addend
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ret i32 %sum
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}
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define i32 @test5(i32 %A, i32 %X) {
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; CHECK-DSP-LABEL: test5:
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; CHECK-DSP: @ %bb.0:
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; CHECK-DSP-NEXT: uxtah r0, r0, r1, ror #8
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; CHECK-DSP-NEXT: bx lr
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;
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; CHECK-NO-DSP-LABEL: test5:
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; CHECK-NO-DSP: @ %bb.0:
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; CHECK-NO-DSP-NEXT: ubfx r1, r1, #8, #16
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; CHECK-NO-DSP-NEXT: add r0, r1
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; CHECK-NO-DSP-NEXT: bx lr
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%X.hi = lshr i32 %X, 8
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%X.trunc = trunc i32 %X.hi to i16
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%addend = zext i16 %X.trunc to i32
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%sum = add i32 %A, %addend
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ret i32 %sum
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}
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define i32 @test6(i32 %A, i32 %X) {
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; CHECK-DSP-LABEL: test6:
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; CHECK-DSP: @ %bb.0:
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; CHECK-DSP-NEXT: uxtab r0, r0, r1, ror #8
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; CHECK-DSP-NEXT: bx lr
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;
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; CHECK-NO-DSP-LABEL: test6:
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; CHECK-NO-DSP: @ %bb.0:
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; CHECK-NO-DSP-NEXT: ubfx r1, r1, #8, #8
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; CHECK-NO-DSP-NEXT: add r0, r1
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; CHECK-NO-DSP-NEXT: bx lr
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%X.hi = lshr i32 %X, 8
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%X.trunc = trunc i32 %X.hi to i8
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%addend = zext i8 %X.trunc to i32
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%sum = add i32 %A, %addend
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ret i32 %sum
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}
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define i32 @test7(i32 %A, i32 %X) {
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; CHECK-DSP-LABEL: test7:
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; CHECK-DSP: @ %bb.0:
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; CHECK-DSP-NEXT: uxtah r0, r0, r1, ror #24
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; CHECK-DSP-NEXT: bx lr
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;
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; CHECK-NO-DSP-LABEL: test7:
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; CHECK-NO-DSP: @ %bb.0:
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; CHECK-NO-DSP-NEXT: ror.w r1, r1, #24
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; CHECK-NO-DSP-NEXT: uxth r1, r1
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; CHECK-NO-DSP-NEXT: add r0, r1
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; CHECK-NO-DSP-NEXT: bx lr
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%lshr = lshr i32 %X, 24
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%shl = shl i32 %X, 8
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%or = or i32 %lshr, %shl
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%trunc = trunc i32 %or to i16
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%zext = zext i16 %trunc to i32
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%add = add i32 %A, %zext
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ret i32 %add
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}
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define i32 @test8(i32 %A, i32 %X) {
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; CHECK-DSP-LABEL: test8:
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; CHECK-DSP: @ %bb.0:
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; CHECK-DSP-NEXT: uxtah r0, r0, r1, ror #24
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; CHECK-DSP-NEXT: bx lr
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;
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; CHECK-NO-DSP-LABEL: test8:
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; CHECK-NO-DSP: @ %bb.0:
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; CHECK-NO-DSP-NEXT: ror.w r1, r1, #24
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; CHECK-NO-DSP-NEXT: uxth r1, r1
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; CHECK-NO-DSP-NEXT: add r0, r1
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; CHECK-NO-DSP-NEXT: bx lr
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%lshr = lshr i32 %X, 24
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%shl = shl i32 %X, 8
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%or = or i32 %lshr, %shl
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%and = and i32 %or, 65535
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%add = add i32 %A, %and
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ret i32 %add
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}
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