322 lines
10 KiB
LLVM
322 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+zbb -riscv-v-vector-bits-min=128 -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s
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define i64 @reduce_add(i64 %x, <4 x i64> %v) {
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; CHECK-LABEL: reduce_add:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; CHECK-NEXT: vmv.s.x v10, a0
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; CHECK-NEXT: vredsum.vs v8, v8, v10
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%rdx = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %v)
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%res = add i64 %rdx, %x
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ret i64 %res
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}
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define i64 @reduce_add2(<4 x i64> %v) {
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; CHECK-LABEL: reduce_add2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; CHECK-NEXT: vmv.v.i v10, 8
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; CHECK-NEXT: vredsum.vs v8, v8, v10
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%rdx = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %v)
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%res = add i64 %rdx, 8
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ret i64 %res
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}
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define i64 @reduce_and(i64 %x, <4 x i64> %v) {
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; CHECK-LABEL: reduce_and:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; CHECK-NEXT: vmv.s.x v10, a0
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; CHECK-NEXT: vredand.vs v8, v8, v10
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%rdx = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %v)
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%res = and i64 %rdx, %x
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ret i64 %res
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}
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define i64 @reduce_and2(<4 x i64> %v) {
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; CHECK-LABEL: reduce_and2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; CHECK-NEXT: vmv.v.i v10, 8
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; CHECK-NEXT: vredand.vs v8, v8, v10
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%rdx = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %v)
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%res = and i64 %rdx, 8
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ret i64 %res
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}
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define i64 @reduce_or(i64 %x, <4 x i64> %v) {
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; CHECK-LABEL: reduce_or:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; CHECK-NEXT: vmv.s.x v10, a0
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; CHECK-NEXT: vredor.vs v8, v8, v10
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%rdx = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %v)
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%res = or i64 %rdx, %x
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ret i64 %res
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}
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define i64 @reduce_or2(<4 x i64> %v) {
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; CHECK-LABEL: reduce_or2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; CHECK-NEXT: vmv.v.i v10, 8
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; CHECK-NEXT: vredor.vs v8, v8, v10
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%rdx = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %v)
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%res = or i64 %rdx, 8
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ret i64 %res
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}
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define i64 @reduce_xor(i64 %x, <4 x i64> %v) {
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; CHECK-LABEL: reduce_xor:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; CHECK-NEXT: vmv.s.x v10, a0
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; CHECK-NEXT: vredxor.vs v8, v8, v10
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%rdx = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %v)
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%res = xor i64 %rdx, %x
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ret i64 %res
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}
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define i64 @reduce_xor2(<4 x i64> %v) {
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; CHECK-LABEL: reduce_xor2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; CHECK-NEXT: vmv.s.x v10, zero
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; CHECK-NEXT: vredxor.vs v8, v8, v10
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: andi a0, a0, 8
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; CHECK-NEXT: ret
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entry:
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%rdx = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %v)
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%res = and i64 %rdx, 8
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ret i64 %res
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}
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define i64 @reduce_umax(i64 %x, <4 x i64> %v) {
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; CHECK-LABEL: reduce_umax:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; CHECK-NEXT: vmv.s.x v10, a0
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; CHECK-NEXT: vredmaxu.vs v8, v8, v10
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%rdx = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> %v)
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%res = call i64 @llvm.umax.i64(i64 %rdx, i64 %x)
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ret i64 %res
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}
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define i64 @reduce_umax2(<4 x i64> %v) {
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; CHECK-LABEL: reduce_umax2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; CHECK-NEXT: vmv.v.i v10, 8
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; CHECK-NEXT: vredmaxu.vs v8, v8, v10
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%rdx = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> %v)
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%res = call i64 @llvm.umax.i64(i64 %rdx, i64 8)
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ret i64 %res
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}
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define i64 @reduce_umin(i64 %x, <4 x i64> %v) {
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; CHECK-LABEL: reduce_umin:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; CHECK-NEXT: vmv.s.x v10, a0
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; CHECK-NEXT: vredminu.vs v8, v8, v10
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%rdx = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> %v)
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%res = call i64 @llvm.umin.i64(i64 %rdx, i64 %x)
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ret i64 %res
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}
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define i64 @reduce_umin2(<4 x i64> %v) {
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; CHECK-LABEL: reduce_umin2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; CHECK-NEXT: vmv.v.i v10, 8
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; CHECK-NEXT: vredminu.vs v8, v8, v10
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%rdx = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> %v)
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%res = call i64 @llvm.umin.i64(i64 %rdx, i64 8)
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ret i64 %res
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}
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define i64 @reduce_smax(i64 %x, <4 x i64> %v) {
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; CHECK-LABEL: reduce_smax:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; CHECK-NEXT: vmv.s.x v10, a0
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; CHECK-NEXT: vredmax.vs v8, v8, v10
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%rdx = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> %v)
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%res = call i64 @llvm.smax.i64(i64 %rdx, i64 %x)
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ret i64 %res
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}
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define i64 @reduce_smax2(<4 x i64> %v) {
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; CHECK-LABEL: reduce_smax2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; CHECK-NEXT: vmv.v.i v10, 8
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; CHECK-NEXT: vredmax.vs v8, v8, v10
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%rdx = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> %v)
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%res = call i64 @llvm.smax.i64(i64 %rdx, i64 8)
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ret i64 %res
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}
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define i64 @reduce_smin(i64 %x, <4 x i64> %v) {
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; CHECK-LABEL: reduce_smin:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; CHECK-NEXT: vmv.s.x v10, a0
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; CHECK-NEXT: vredmin.vs v8, v8, v10
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%rdx = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> %v)
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%res = call i64 @llvm.smin.i64(i64 %rdx, i64 %x)
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ret i64 %res
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}
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define i64 @reduce_smin2(<4 x i64> %v) {
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; CHECK-LABEL: reduce_smin2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; CHECK-NEXT: vmv.v.i v10, 8
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; CHECK-NEXT: vredmin.vs v8, v8, v10
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%rdx = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> %v)
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%res = call i64 @llvm.smin.i64(i64 %rdx, i64 8)
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ret i64 %res
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}
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define float @reduce_fadd(float %x, <4 x float> %v) {
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; CHECK-LABEL: reduce_fadd:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
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; CHECK-NEXT: vfmv.s.f v9, fa0
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vfredusum.vs v8, v8, v9
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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entry:
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%rdx = call fast float @llvm.vector.reduce.fadd.v4f32(float %x, <4 x float> %v)
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ret float %rdx
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}
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define float @reduce_fadd2(float %x, <4 x float> %v) {
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; CHECK-LABEL: reduce_fadd2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
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; CHECK-NEXT: vfmv.s.f v9, fa0
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vfredusum.vs v8, v8, v9
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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entry:
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%rdx = call fast float @llvm.vector.reduce.fadd.v4f32(float 0.0, <4 x float> %v)
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%res = fadd fast float %rdx, %x
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ret float %res
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}
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define float @reduce_fmax(float %x, <4 x float> %v) {
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; CHECK-LABEL: reduce_fmax:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
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; CHECK-NEXT: vfmv.s.f v9, fa0
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vfredmax.vs v8, v8, v9
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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entry:
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%rdx = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v)
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%res = call float @llvm.maxnum.f32(float %x, float %rdx)
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ret float %res
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}
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define float @reduce_fmin(float %x, <4 x float> %v) {
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; CHECK-LABEL: reduce_fmin:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
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; CHECK-NEXT: vfmv.s.f v9, fa0
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vfredmin.vs v8, v8, v9
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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entry:
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%rdx = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v)
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%res = call float @llvm.minnum.f32(float %x, float %rdx)
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ret float %res
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}
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; Function Attrs: nofree nosync nounwind readnone willreturn
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declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)
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declare i64 @llvm.vector.reduce.and.v4i64(<4 x i64>)
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declare i64 @llvm.vector.reduce.or.v4i64(<4 x i64>)
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declare i64 @llvm.vector.reduce.xor.v4i64(<4 x i64>)
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declare i64 @llvm.vector.reduce.umax.v4i64(<4 x i64>)
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declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)
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declare i64 @llvm.vector.reduce.smax.v4i64(<4 x i64>)
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declare i64 @llvm.vector.reduce.smin.v4i64(<4 x i64>)
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declare float @llvm.vector.reduce.fadd.v4f32(float, <4 x float>)
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declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>)
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declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
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declare i64 @llvm.umax.i64(i64, i64)
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declare i64 @llvm.umin.i64(i64, i64)
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declare i64 @llvm.smax.i64(i64, i64)
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declare i64 @llvm.smin.i64(i64, i64)
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declare float @llvm.maxnum.f32(float ,float)
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declare float @llvm.minnum.f32(float ,float)
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