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llvm-project/llvm/test/CodeGen/RISCV/rv64zbs.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I
; RUN: llc -mtriple=riscv64 -mattr=+zbs -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64ZBS
define signext i32 @bclr_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: bclr_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: not a1, a1
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclr_i32:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: andi a1, a1, 31
; RV64ZBS-NEXT: bclr a0, a0, a1
; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%and = and i32 %b, 31
%shl = shl nuw i32 1, %and
%neg = xor i32 %shl, -1
%and1 = and i32 %neg, %a
ret i32 %and1
}
define signext i32 @bclr_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: bclr_i32_no_mask:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: not a1, a1
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclr_i32_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclr a0, a0, a1
; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%shl = shl i32 1, %b
%neg = xor i32 %shl, -1
%and1 = and i32 %neg, %a
ret i32 %and1
}
define signext i32 @bclr_i32_load(i32* %p, i32 signext %b) nounwind {
; RV64I-LABEL: bclr_i32_load:
; RV64I: # %bb.0:
; RV64I-NEXT: lw a0, 0(a0)
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: not a1, a1
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclr_i32_load:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lw a0, 0(a0)
; RV64ZBS-NEXT: bclr a0, a0, a1
; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%a = load i32, i32* %p
%shl = shl i32 1, %b
%neg = xor i32 %shl, -1
%and1 = and i32 %neg, %a
ret i32 %and1
}
define i64 @bclr_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: bclr_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sll a1, a2, a1
; RV64I-NEXT: not a1, a1
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclr_i64:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclr a0, a0, a1
; RV64ZBS-NEXT: ret
%and = and i64 %b, 63
%shl = shl nuw i64 1, %and
%neg = xor i64 %shl, -1
%and1 = and i64 %neg, %a
ret i64 %and1
}
define i64 @bclr_i64_no_mask(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: bclr_i64_no_mask:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sll a1, a2, a1
; RV64I-NEXT: not a1, a1
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclr_i64_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclr a0, a0, a1
; RV64ZBS-NEXT: ret
%shl = shl i64 1, %b
%neg = xor i64 %shl, -1
%and1 = and i64 %neg, %a
ret i64 %and1
}
define signext i32 @bset_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: bset_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bset_i32:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: andi a1, a1, 31
; RV64ZBS-NEXT: bset a0, a0, a1
; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%and = and i32 %b, 31
%shl = shl nuw i32 1, %and
%or = or i32 %shl, %a
ret i32 %or
}
define signext i32 @bset_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: bset_i32_no_mask:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bset_i32_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bset a0, a0, a1
; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%shl = shl i32 1, %b
%or = or i32 %shl, %a
ret i32 %or
}
define signext i32 @bset_i32_load(i32* %p, i32 signext %b) nounwind {
; RV64I-LABEL: bset_i32_load:
; RV64I: # %bb.0:
; RV64I-NEXT: lw a0, 0(a0)
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bset_i32_load:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lw a0, 0(a0)
; RV64ZBS-NEXT: bset a0, a0, a1
; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%a = load i32, i32* %p
%shl = shl i32 1, %b
%or = or i32 %shl, %a
ret i32 %or
}
; We can use bsetw for 1 << x by setting the first source to zero.
define signext i32 @bset_i32_zero(i32 signext %a) nounwind {
; RV64I-LABEL: bset_i32_zero:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: sllw a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bset_i32_zero:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bset a0, zero, a0
; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%shl = shl i32 1, %a
ret i32 %shl
}
define i64 @bset_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: bset_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sll a1, a2, a1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bset_i64:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bset a0, a0, a1
; RV64ZBS-NEXT: ret
%conv = and i64 %b, 63
%shl = shl nuw i64 1, %conv
%or = or i64 %shl, %a
ret i64 %or
}
define i64 @bset_i64_no_mask(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: bset_i64_no_mask:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sll a1, a2, a1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bset_i64_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bset a0, a0, a1
; RV64ZBS-NEXT: ret
%shl = shl i64 1, %b
%or = or i64 %shl, %a
ret i64 %or
}
; We can use bsetw for 1 << x by setting the first source to zero.
define signext i64 @bset_i64_zero(i64 signext %a) nounwind {
; RV64I-LABEL: bset_i64_zero:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: sll a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bset_i64_zero:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bset a0, zero, a0
; RV64ZBS-NEXT: ret
%shl = shl i64 1, %a
ret i64 %shl
}
define signext i32 @binv_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: binv_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: xor a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binv_i32:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: andi a1, a1, 31
; RV64ZBS-NEXT: binv a0, a0, a1
; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%and = and i32 %b, 31
%shl = shl nuw i32 1, %and
%xor = xor i32 %shl, %a
ret i32 %xor
}
define signext i32 @binv_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: binv_i32_no_mask:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: xor a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binv_i32_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binv a0, a0, a1
; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%shl = shl i32 1, %b
%xor = xor i32 %shl, %a
ret i32 %xor
}
define signext i32 @binv_i32_load(i32* %p, i32 signext %b) nounwind {
; RV64I-LABEL: binv_i32_load:
; RV64I: # %bb.0:
; RV64I-NEXT: lw a0, 0(a0)
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: xor a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binv_i32_load:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lw a0, 0(a0)
; RV64ZBS-NEXT: binv a0, a0, a1
; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%a = load i32, i32* %p
%shl = shl i32 1, %b
%xor = xor i32 %shl, %a
ret i32 %xor
}
define i64 @binv_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: binv_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sll a1, a2, a1
; RV64I-NEXT: xor a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binv_i64:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binv a0, a0, a1
; RV64ZBS-NEXT: ret
%conv = and i64 %b, 63
%shl = shl nuw i64 1, %conv
%xor = xor i64 %shl, %a
ret i64 %xor
}
define i64 @binv_i64_no_mask(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: binv_i64_no_mask:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sll a1, a2, a1
; RV64I-NEXT: xor a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binv_i64_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binv a0, a0, a1
; RV64ZBS-NEXT: ret
%shl = shl nuw i64 1, %b
%xor = xor i64 %shl, %a
ret i64 %xor
}
define signext i32 @bext_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: bext_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bext_i32:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: andi a1, a1, 31
; RV64ZBS-NEXT: bext a0, a0, a1
; RV64ZBS-NEXT: ret
%and = and i32 %b, 31
%shr = lshr i32 %a, %and
%and1 = and i32 %shr, 1
ret i32 %and1
}
define signext i32 @bext_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: bext_i32_no_mask:
; RV64I: # %bb.0:
; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bext_i32_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bext a0, a0, a1
; RV64ZBS-NEXT: ret
%shr = lshr i32 %a, %b
%and1 = and i32 %shr, 1
ret i32 %and1
}
; This gets previous converted to (i1 (truncate (srl X, Y)). Make sure we are
; able to use bext.
define void @bext_i32_trunc(i32 signext %0, i32 signext %1) {
; RV64I-LABEL: bext_i32_trunc:
; RV64I: # %bb.0:
; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: beqz a0, .LBB19_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB19_2:
; RV64I-NEXT: tail bar@plt
;
; RV64ZBS-LABEL: bext_i32_trunc:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bext a0, a0, a1
; RV64ZBS-NEXT: beqz a0, .LBB19_2
; RV64ZBS-NEXT: # %bb.1:
; RV64ZBS-NEXT: ret
; RV64ZBS-NEXT: .LBB19_2:
; RV64ZBS-NEXT: tail bar@plt
%3 = shl i32 1, %1
%4 = and i32 %3, %0
%5 = icmp eq i32 %4, 0
br i1 %5, label %6, label %7
6: ; preds = %2
tail call void @bar()
br label %7
7: ; preds = %6, %2
ret void
}
declare void @bar()
define i64 @bext_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: bext_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: srl a0, a0, a1
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bext_i64:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bext a0, a0, a1
; RV64ZBS-NEXT: ret
%conv = and i64 %b, 63
%shr = lshr i64 %a, %conv
%and1 = and i64 %shr, 1
ret i64 %and1
}
define i64 @bext_i64_no_mask(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: bext_i64_no_mask:
; RV64I: # %bb.0:
; RV64I-NEXT: srl a0, a0, a1
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bext_i64_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bext a0, a0, a1
; RV64ZBS-NEXT: ret
%shr = lshr i64 %a, %b
%and1 = and i64 %shr, 1
ret i64 %and1
}
define signext i32 @bexti_i32(i32 signext %a) nounwind {
; RV64I-LABEL: bexti_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 58
; RV64I-NEXT: srli a0, a0, 63
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bexti_i32:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bexti a0, a0, 5
; RV64ZBS-NEXT: ret
%shr = lshr i32 %a, 5
%and = and i32 %shr, 1
ret i32 %and
}
define i64 @bexti_i64(i64 %a) nounwind {
; RV64I-LABEL: bexti_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 58
; RV64I-NEXT: srli a0, a0, 63
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bexti_i64:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bexti a0, a0, 5
; RV64ZBS-NEXT: ret
%shr = lshr i64 %a, 5
%and = and i64 %shr, 1
ret i64 %and
}
define signext i32 @bexti_i32_cmp(i32 signext %a) nounwind {
; RV64I-LABEL: bexti_i32_cmp:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 58
; RV64I-NEXT: srli a0, a0, 63
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bexti_i32_cmp:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bexti a0, a0, 5
; RV64ZBS-NEXT: ret
%and = and i32 %a, 32
%cmp = icmp ne i32 %and, 0
%zext = zext i1 %cmp to i32
ret i32 %zext
}
define i64 @bexti_i64_cmp(i64 %a) nounwind {
; RV64I-LABEL: bexti_i64_cmp:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 58
; RV64I-NEXT: srli a0, a0, 63
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bexti_i64_cmp:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bexti a0, a0, 5
; RV64ZBS-NEXT: ret
%and = and i64 %a, 32
%cmp = icmp ne i64 %and, 0
%zext = zext i1 %cmp to i64
ret i64 %zext
}
define signext i32 @bclri_i32_10(i32 signext %a) nounwind {
; CHECK-LABEL: bclri_i32_10:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, -1025
; CHECK-NEXT: ret
%and = and i32 %a, -1025
ret i32 %and
}
define signext i32 @bclri_i32_11(i32 signext %a) nounwind {
; RV64I-LABEL: bclri_i32_11:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: addiw a1, a1, 2047
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclri_i32_11:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 11
; RV64ZBS-NEXT: ret
%and = and i32 %a, -2049
ret i32 %and
}
define signext i32 @bclri_i32_30(i32 signext %a) nounwind {
; RV64I-LABEL: bclri_i32_30:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 786432
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclri_i32_30:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 30
; RV64ZBS-NEXT: ret
%and = and i32 %a, -1073741825
ret i32 %and
}
define signext i32 @bclri_i32_31(i32 signext %a) nounwind {
; CHECK-LABEL: bclri_i32_31:
; CHECK: # %bb.0:
; CHECK-NEXT: slli a0, a0, 33
; CHECK-NEXT: srli a0, a0, 33
; CHECK-NEXT: ret
%and = and i32 %a, -2147483649
ret i32 %and
}
define i64 @bclri_i64_10(i64 %a) nounwind {
; CHECK-LABEL: bclri_i64_10:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, -1025
; CHECK-NEXT: ret
%and = and i64 %a, -1025
ret i64 %and
}
define i64 @bclri_i64_11(i64 %a) nounwind {
; RV64I-LABEL: bclri_i64_11:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: addiw a1, a1, 2047
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclri_i64_11:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 11
; RV64ZBS-NEXT: ret
%and = and i64 %a, -2049
ret i64 %and
}
define i64 @bclri_i64_30(i64 %a) nounwind {
; RV64I-LABEL: bclri_i64_30:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 786432
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclri_i64_30:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 30
; RV64ZBS-NEXT: ret
%and = and i64 %a, -1073741825
ret i64 %and
}
define i64 @bclri_i64_31(i64 %a) nounwind {
; RV64I-LABEL: bclri_i64_31:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclri_i64_31:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 31
; RV64ZBS-NEXT: ret
%and = and i64 %a, -2147483649
ret i64 %and
}
define i64 @bclri_i64_62(i64 %a) nounwind {
; RV64I-LABEL: bclri_i64_62:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: slli a1, a1, 62
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclri_i64_62:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 62
; RV64ZBS-NEXT: ret
%and = and i64 %a, -4611686018427387905
ret i64 %and
}
define i64 @bclri_i64_63(i64 %a) nounwind {
; RV64I-LABEL: bclri_i64_63:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclri_i64_63:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 63
; RV64ZBS-NEXT: ret
%and = and i64 %a, -9223372036854775809
ret i64 %and
}
define i64 @bclri_i64_large0(i64 %a) nounwind {
; RV64I-LABEL: bclri_i64_large0:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1044480
; RV64I-NEXT: addiw a1, a1, -256
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclri_i64_large0:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: andi a0, a0, -256
; RV64ZBS-NEXT: bclri a0, a0, 24
; RV64ZBS-NEXT: ret
%and = and i64 %a, -16777472
ret i64 %and
}
define i64 @bclri_i64_large1(i64 %a) nounwind {
; RV64I-LABEL: bclri_i64_large1:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1044464
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclri_i64_large1:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 16
; RV64ZBS-NEXT: bclri a0, a0, 24
; RV64ZBS-NEXT: ret
%and = and i64 %a, -16842753
ret i64 %and
}
define signext i32 @bseti_i32_10(i32 signext %a) nounwind {
; CHECK-LABEL: bseti_i32_10:
; CHECK: # %bb.0:
; CHECK-NEXT: ori a0, a0, 1024
; CHECK-NEXT: ret
%or = or i32 %a, 1024
ret i32 %or
}
define signext i32 @bseti_i32_11(i32 signext %a) nounwind {
; RV64I-LABEL: bseti_i32_11:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, -2048
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bseti_i32_11:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 11
; RV64ZBS-NEXT: ret
%or = or i32 %a, 2048
ret i32 %or
}
define signext i32 @bseti_i32_30(i32 signext %a) nounwind {
; RV64I-LABEL: bseti_i32_30:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 262144
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bseti_i32_30:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 30
; RV64ZBS-NEXT: ret
%or = or i32 %a, 1073741824
ret i32 %or
}
define signext i32 @bseti_i32_31(i32 signext %a) nounwind {
; CHECK-LABEL: bseti_i32_31:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, 524288
; CHECK-NEXT: or a0, a0, a1
; CHECK-NEXT: ret
%or = or i32 %a, 2147483648
ret i32 %or
}
define i64 @bseti_i64_10(i64 %a) nounwind {
; CHECK-LABEL: bseti_i64_10:
; CHECK: # %bb.0:
; CHECK-NEXT: ori a0, a0, 1024
; CHECK-NEXT: ret
%or = or i64 %a, 1024
ret i64 %or
}
define i64 @bseti_i64_11(i64 %a) nounwind {
; RV64I-LABEL: bseti_i64_11:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, -2048
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bseti_i64_11:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 11
; RV64ZBS-NEXT: ret
%or = or i64 %a, 2048
ret i64 %or
}
define i64 @bseti_i64_30(i64 %a) nounwind {
; RV64I-LABEL: bseti_i64_30:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 262144
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bseti_i64_30:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 30
; RV64ZBS-NEXT: ret
%or = or i64 %a, 1073741824
ret i64 %or
}
define i64 @bseti_i64_31(i64 %a) nounwind {
; RV64I-LABEL: bseti_i64_31:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: slli a1, a1, 31
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bseti_i64_31:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 31
; RV64ZBS-NEXT: ret
%or = or i64 %a, 2147483648
ret i64 %or
}
define i64 @bseti_i64_62(i64 %a) nounwind {
; RV64I-LABEL: bseti_i64_62:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: slli a1, a1, 62
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bseti_i64_62:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 62
; RV64ZBS-NEXT: ret
%or = or i64 %a, 4611686018427387904
ret i64 %or
}
define i64 @bseti_i64_63(i64 %a) nounwind {
; RV64I-LABEL: bseti_i64_63:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: slli a1, a1, 63
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bseti_i64_63:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 63
; RV64ZBS-NEXT: ret
%or = or i64 %a, 9223372036854775808
ret i64 %or
}
define signext i32 @binvi_i32_10(i32 signext %a) nounwind {
; CHECK-LABEL: binvi_i32_10:
; CHECK: # %bb.0:
; CHECK-NEXT: xori a0, a0, 1024
; CHECK-NEXT: ret
%xor = xor i32 %a, 1024
ret i32 %xor
}
define signext i32 @binvi_i32_11(i32 signext %a) nounwind {
; RV64I-LABEL: binvi_i32_11:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, -2048
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binvi_i32_11:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 11
; RV64ZBS-NEXT: ret
%xor = xor i32 %a, 2048
ret i32 %xor
}
define signext i32 @binvi_i32_30(i32 signext %a) nounwind {
; RV64I-LABEL: binvi_i32_30:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 262144
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binvi_i32_30:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 30
; RV64ZBS-NEXT: ret
%xor = xor i32 %a, 1073741824
ret i32 %xor
}
define signext i32 @binvi_i32_31(i32 signext %a) nounwind {
; CHECK-LABEL: binvi_i32_31:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, 524288
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: ret
%xor = xor i32 %a, 2147483648
ret i32 %xor
}
define i64 @binvi_i64_10(i64 %a) nounwind {
; CHECK-LABEL: binvi_i64_10:
; CHECK: # %bb.0:
; CHECK-NEXT: xori a0, a0, 1024
; CHECK-NEXT: ret
%xor = xor i64 %a, 1024
ret i64 %xor
}
define i64 @binvi_i64_11(i64 %a) nounwind {
; RV64I-LABEL: binvi_i64_11:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, -2048
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binvi_i64_11:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 11
; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 2048
ret i64 %xor
}
define i64 @binvi_i64_30(i64 %a) nounwind {
; RV64I-LABEL: binvi_i64_30:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 262144
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binvi_i64_30:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 30
; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 1073741824
ret i64 %xor
}
define i64 @binvi_i64_31(i64 %a) nounwind {
; RV64I-LABEL: binvi_i64_31:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: slli a1, a1, 31
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binvi_i64_31:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 31
; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 2147483648
ret i64 %xor
}
define i64 @binvi_i64_62(i64 %a) nounwind {
; RV64I-LABEL: binvi_i64_62:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: slli a1, a1, 62
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binvi_i64_62:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 62
; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 4611686018427387904
ret i64 %xor
}
define i64 @binvi_i64_63(i64 %a) nounwind {
; RV64I-LABEL: binvi_i64_63:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: slli a1, a1, 63
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binvi_i64_63:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 63
; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 9223372036854775808
ret i64 %xor
}
define i64 @xor_i64_large(i64 %a) nounwind {
; RV64I-LABEL: xor_i64_large:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: addi a1, a1, 1
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: xor_i64_large:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 0
; RV64ZBS-NEXT: binvi a0, a0, 32
; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 4294967297
ret i64 %xor
}
define i64 @xor_i64_4099(i64 %a) nounwind {
; RV64I-LABEL: xor_i64_4099:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, 3
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: xor_i64_4099:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: xori a0, a0, 3
; RV64ZBS-NEXT: binvi a0, a0, 12
; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 4099
ret i64 %xor
}
define i64 @xor_i64_96(i64 %a) nounwind {
; CHECK-LABEL: xor_i64_96:
; CHECK: # %bb.0:
; CHECK-NEXT: xori a0, a0, 96
; CHECK-NEXT: ret
%xor = xor i64 %a, 96
ret i64 %xor
}
define i64 @or_i64_large(i64 %a) nounwind {
; RV64I-LABEL: or_i64_large:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: addi a1, a1, 1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: or_i64_large:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 0
; RV64ZBS-NEXT: bseti a0, a0, 32
; RV64ZBS-NEXT: ret
%or = or i64 %a, 4294967297
ret i64 %or
}
define i64 @xor_i64_66901(i64 %a) nounwind {
; RV64I-LABEL: xor_i64_66901:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, 1365
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: xor_i64_66901:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: xori a0, a0, 1365
; RV64ZBS-NEXT: binvi a0, a0, 16
; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 66901
ret i64 %xor
}
define i64 @or_i64_4099(i64 %a) nounwind {
; RV64I-LABEL: or_i64_4099:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, 3
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: or_i64_4099:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: ori a0, a0, 3
; RV64ZBS-NEXT: bseti a0, a0, 12
; RV64ZBS-NEXT: ret
%or = or i64 %a, 4099
ret i64 %or
}
define i64 @or_i64_96(i64 %a) nounwind {
; CHECK-LABEL: or_i64_96:
; CHECK: # %bb.0:
; CHECK-NEXT: ori a0, a0, 96
; CHECK-NEXT: ret
%or = or i64 %a, 96
ret i64 %or
}
define i64 @or_i64_66901(i64 %a) nounwind {
; RV64I-LABEL: or_i64_66901:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, 1365
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: or_i64_66901:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: ori a0, a0, 1365
; RV64ZBS-NEXT: bseti a0, a0, 16
; RV64ZBS-NEXT: ret
%or = or i64 %a, 66901
ret i64 %or
}
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