445 lines
12 KiB
LLVM
445 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I
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; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=CHECK,RV32ZBB-ZBKB
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; RUN: llc -mtriple=riscv32 -mattr=+zbkb -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=CHECK,RV32ZBB-ZBKB
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define i32 @andn_i32(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: andn_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: not a1, a1
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; RV32I-NEXT: and a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBB-ZBKB-LABEL: andn_i32:
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; RV32ZBB-ZBKB: # %bb.0:
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; RV32ZBB-ZBKB-NEXT: andn a0, a0, a1
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; RV32ZBB-ZBKB-NEXT: ret
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%neg = xor i32 %b, -1
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%and = and i32 %neg, %a
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ret i32 %and
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}
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define i64 @andn_i64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: andn_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: not a3, a3
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; RV32I-NEXT: not a2, a2
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; RV32I-NEXT: and a0, a2, a0
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; RV32I-NEXT: and a1, a3, a1
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; RV32I-NEXT: ret
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;
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; RV32ZBB-ZBKB-LABEL: andn_i64:
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; RV32ZBB-ZBKB: # %bb.0:
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; RV32ZBB-ZBKB-NEXT: andn a0, a0, a2
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; RV32ZBB-ZBKB-NEXT: andn a1, a1, a3
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; RV32ZBB-ZBKB-NEXT: ret
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%neg = xor i64 %b, -1
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%and = and i64 %neg, %a
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ret i64 %and
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}
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define i32 @orn_i32(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: orn_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: not a1, a1
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; RV32I-NEXT: or a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBB-ZBKB-LABEL: orn_i32:
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; RV32ZBB-ZBKB: # %bb.0:
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; RV32ZBB-ZBKB-NEXT: orn a0, a0, a1
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; RV32ZBB-ZBKB-NEXT: ret
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%neg = xor i32 %b, -1
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%or = or i32 %neg, %a
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ret i32 %or
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}
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define i64 @orn_i64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: orn_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: not a3, a3
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; RV32I-NEXT: not a2, a2
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; RV32I-NEXT: or a0, a2, a0
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; RV32I-NEXT: or a1, a3, a1
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; RV32I-NEXT: ret
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;
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; RV32ZBB-ZBKB-LABEL: orn_i64:
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; RV32ZBB-ZBKB: # %bb.0:
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; RV32ZBB-ZBKB-NEXT: orn a0, a0, a2
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; RV32ZBB-ZBKB-NEXT: orn a1, a1, a3
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; RV32ZBB-ZBKB-NEXT: ret
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%neg = xor i64 %b, -1
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%or = or i64 %neg, %a
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ret i64 %or
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}
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define i32 @xnor_i32(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: xnor_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: not a0, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBB-ZBKB-LABEL: xnor_i32:
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; RV32ZBB-ZBKB: # %bb.0:
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; RV32ZBB-ZBKB-NEXT: xnor a0, a0, a1
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; RV32ZBB-ZBKB-NEXT: ret
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%neg = xor i32 %a, -1
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%xor = xor i32 %neg, %b
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ret i32 %xor
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}
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define i64 @xnor_i64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: xnor_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: xor a1, a1, a3
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; RV32I-NEXT: xor a0, a0, a2
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; RV32I-NEXT: not a0, a0
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; RV32I-NEXT: not a1, a1
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; RV32I-NEXT: ret
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;
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; RV32ZBB-ZBKB-LABEL: xnor_i64:
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; RV32ZBB-ZBKB: # %bb.0:
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; RV32ZBB-ZBKB-NEXT: xnor a0, a0, a2
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; RV32ZBB-ZBKB-NEXT: xnor a1, a1, a3
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; RV32ZBB-ZBKB-NEXT: ret
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%neg = xor i64 %a, -1
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%xor = xor i64 %neg, %b
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ret i64 %xor
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}
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declare i32 @llvm.fshl.i32(i32, i32, i32)
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define i32 @rol_i32(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: rol_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sll a2, a0, a1
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; RV32I-NEXT: neg a1, a1
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; RV32I-NEXT: srl a0, a0, a1
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; RV32I-NEXT: or a0, a2, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBB-ZBKB-LABEL: rol_i32:
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; RV32ZBB-ZBKB: # %bb.0:
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; RV32ZBB-ZBKB-NEXT: rol a0, a0, a1
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; RV32ZBB-ZBKB-NEXT: ret
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%or = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %b)
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ret i32 %or
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}
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; This test is presented here in case future expansions of the Bitmanip
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; extensions introduce instructions suitable for this pattern.
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declare i64 @llvm.fshl.i64(i64, i64, i64)
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define i64 @rol_i64(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: rol_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: slli a5, a2, 26
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; CHECK-NEXT: srli a5, a5, 31
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; CHECK-NEXT: mv a4, a1
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; CHECK-NEXT: bnez a5, .LBB7_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: mv a4, a0
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; CHECK-NEXT: .LBB7_2:
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; CHECK-NEXT: sll a3, a4, a2
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; CHECK-NEXT: bnez a5, .LBB7_4
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; CHECK-NEXT: # %bb.3:
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; CHECK-NEXT: mv a0, a1
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; CHECK-NEXT: .LBB7_4:
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; CHECK-NEXT: srli a1, a0, 1
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; CHECK-NEXT: not a5, a2
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; CHECK-NEXT: srl a1, a1, a5
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; CHECK-NEXT: or a3, a3, a1
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; CHECK-NEXT: sll a0, a0, a2
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; CHECK-NEXT: srli a4, a4, 1
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; CHECK-NEXT: srl a1, a4, a5
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; CHECK-NEXT: or a1, a0, a1
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; CHECK-NEXT: mv a0, a3
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; CHECK-NEXT: ret
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%or = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %b)
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ret i64 %or
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}
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declare i32 @llvm.fshr.i32(i32, i32, i32)
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define i32 @ror_i32(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: ror_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srl a2, a0, a1
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; RV32I-NEXT: neg a1, a1
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; RV32I-NEXT: sll a0, a0, a1
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; RV32I-NEXT: or a0, a2, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBB-ZBKB-LABEL: ror_i32:
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; RV32ZBB-ZBKB: # %bb.0:
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; RV32ZBB-ZBKB-NEXT: ror a0, a0, a1
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; RV32ZBB-ZBKB-NEXT: ret
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%or = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %b)
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ret i32 %or
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}
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; This test is presented here in case future expansions of the Bitmanip
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; extensions introduce instructions suitable for this pattern.
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declare i64 @llvm.fshr.i64(i64, i64, i64)
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define i64 @ror_i64(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: ror_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi a5, a2, 32
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; CHECK-NEXT: mv a3, a0
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; CHECK-NEXT: beqz a5, .LBB9_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: mv a3, a1
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; CHECK-NEXT: .LBB9_2:
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; CHECK-NEXT: srl a4, a3, a2
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; CHECK-NEXT: beqz a5, .LBB9_4
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; CHECK-NEXT: # %bb.3:
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; CHECK-NEXT: mv a1, a0
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; CHECK-NEXT: .LBB9_4:
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; CHECK-NEXT: slli a0, a1, 1
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; CHECK-NEXT: not a5, a2
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; CHECK-NEXT: sll a0, a0, a5
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; CHECK-NEXT: or a0, a0, a4
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; CHECK-NEXT: srl a1, a1, a2
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; CHECK-NEXT: slli a3, a3, 1
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; CHECK-NEXT: sll a2, a3, a5
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; CHECK-NEXT: or a1, a2, a1
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; CHECK-NEXT: ret
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%or = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %b)
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ret i64 %or
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}
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define i32 @rori_i32_fshl(i32 %a) nounwind {
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; RV32I-LABEL: rori_i32_fshl:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srli a1, a0, 1
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; RV32I-NEXT: slli a0, a0, 31
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV32ZBB-ZBKB-LABEL: rori_i32_fshl:
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; RV32ZBB-ZBKB: # %bb.0:
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; RV32ZBB-ZBKB-NEXT: rori a0, a0, 1
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; RV32ZBB-ZBKB-NEXT: ret
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%1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 31)
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ret i32 %1
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}
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define i32 @rori_i32_fshr(i32 %a) nounwind {
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; RV32I-LABEL: rori_i32_fshr:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a1, a0, 1
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; RV32I-NEXT: srli a0, a0, 31
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV32ZBB-ZBKB-LABEL: rori_i32_fshr:
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; RV32ZBB-ZBKB: # %bb.0:
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; RV32ZBB-ZBKB-NEXT: rori a0, a0, 31
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; RV32ZBB-ZBKB-NEXT: ret
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%1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 31)
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ret i32 %1
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}
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define i64 @rori_i64(i64 %a) nounwind {
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; CHECK-LABEL: rori_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srli a2, a0, 1
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; CHECK-NEXT: slli a3, a1, 31
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; CHECK-NEXT: or a2, a3, a2
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; CHECK-NEXT: srli a1, a1, 1
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; CHECK-NEXT: slli a0, a0, 31
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; CHECK-NEXT: or a1, a0, a1
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; CHECK-NEXT: mv a0, a2
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; CHECK-NEXT: ret
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%1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 63)
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ret i64 %1
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}
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define i64 @rori_i64_fshr(i64 %a) nounwind {
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; CHECK-LABEL: rori_i64_fshr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srli a2, a1, 31
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; CHECK-NEXT: slli a3, a0, 1
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; CHECK-NEXT: or a2, a3, a2
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; CHECK-NEXT: srli a0, a0, 31
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; CHECK-NEXT: slli a1, a1, 1
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; CHECK-NEXT: or a1, a1, a0
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; CHECK-NEXT: mv a0, a2
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; CHECK-NEXT: ret
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%1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 63)
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ret i64 %1
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}
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define i32 @not_shl_one_i32(i32 %x) {
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; RV32I-LABEL: not_shl_one_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: li a1, 1
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; RV32I-NEXT: sll a0, a1, a0
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; RV32I-NEXT: not a0, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBB-ZBKB-LABEL: not_shl_one_i32:
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; RV32ZBB-ZBKB: # %bb.0:
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; RV32ZBB-ZBKB-NEXT: li a1, -2
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; RV32ZBB-ZBKB-NEXT: rol a0, a1, a0
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; RV32ZBB-ZBKB-NEXT: ret
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%1 = shl i32 1, %x
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%2 = xor i32 %1, -1
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ret i32 %2
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}
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define i64 @not_shl_one_i64(i64 %x) {
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; CHECK-LABEL: not_shl_one_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a1, 1
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; CHECK-NEXT: sll a2, a1, a0
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; CHECK-NEXT: addi a0, a0, -32
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; CHECK-NEXT: slti a3, a0, 0
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; CHECK-NEXT: neg a4, a3
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; CHECK-NEXT: and a2, a4, a2
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; CHECK-NEXT: sll a0, a1, a0
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; CHECK-NEXT: addi a3, a3, -1
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; CHECK-NEXT: and a3, a3, a0
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; CHECK-NEXT: not a0, a2
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; CHECK-NEXT: not a1, a3
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; CHECK-NEXT: ret
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%1 = shl i64 1, %x
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%2 = xor i64 %1, -1
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ret i64 %2
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}
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define i8 @srli_i8(i8 %a) nounwind {
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; CHECK-LABEL: srli_i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: slli a0, a0, 24
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; CHECK-NEXT: srli a0, a0, 30
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; CHECK-NEXT: ret
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%1 = lshr i8 %a, 6
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ret i8 %1
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}
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; We could use sext.b+srai, but slli+srai offers more opportunities for
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; comppressed instructions.
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define i8 @srai_i8(i8 %a) nounwind {
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; CHECK-LABEL: srai_i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: slli a0, a0, 24
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; CHECK-NEXT: srai a0, a0, 29
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; CHECK-NEXT: ret
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%1 = ashr i8 %a, 5
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ret i8 %1
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}
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; We could use zext.h+srli, but slli+srli offers more opportunities for
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; comppressed instructions.
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define i16 @srli_i16(i16 %a) nounwind {
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; CHECK-LABEL: srli_i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: slli a0, a0, 16
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; CHECK-NEXT: srli a0, a0, 22
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; CHECK-NEXT: ret
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%1 = lshr i16 %a, 6
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ret i16 %1
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}
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; We could use sext.h+srai, but slli+srai offers more opportunities for
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; comppressed instructions.
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define i16 @srai_i16(i16 %a) nounwind {
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; CHECK-LABEL: srai_i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: slli a0, a0, 16
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; CHECK-NEXT: srai a0, a0, 25
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; CHECK-NEXT: ret
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%1 = ashr i16 %a, 9
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ret i16 %1
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}
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define i1 @andn_seqz_i32(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: andn_seqz_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: seqz a0, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBB-ZBKB-LABEL: andn_seqz_i32:
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; RV32ZBB-ZBKB: # %bb.0:
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; RV32ZBB-ZBKB-NEXT: andn a0, a1, a0
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; RV32ZBB-ZBKB-NEXT: seqz a0, a0
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; RV32ZBB-ZBKB-NEXT: ret
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%and = and i32 %a, %b
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%cmpeq = icmp eq i32 %and, %b
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ret i1 %cmpeq
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}
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define i1 @andn_seqz_i64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: andn_seqz_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: not a0, a0
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; RV32I-NEXT: not a1, a1
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; RV32I-NEXT: and a1, a1, a3
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; RV32I-NEXT: and a0, a0, a2
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: seqz a0, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBB-ZBKB-LABEL: andn_seqz_i64:
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; RV32ZBB-ZBKB: # %bb.0:
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; RV32ZBB-ZBKB-NEXT: andn a1, a3, a1
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; RV32ZBB-ZBKB-NEXT: andn a0, a2, a0
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; RV32ZBB-ZBKB-NEXT: or a0, a0, a1
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; RV32ZBB-ZBKB-NEXT: seqz a0, a0
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; RV32ZBB-ZBKB-NEXT: ret
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%and = and i64 %a, %b
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%cmpeq = icmp eq i64 %and, %b
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ret i1 %cmpeq
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}
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define i1 @andn_snez_i32(i32 %a, i32 %b) nounwind {
|
|
; RV32I-LABEL: andn_snez_i32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: and a0, a0, a1
|
|
; RV32I-NEXT: xor a0, a0, a1
|
|
; RV32I-NEXT: snez a0, a0
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32ZBB-ZBKB-LABEL: andn_snez_i32:
|
|
; RV32ZBB-ZBKB: # %bb.0:
|
|
; RV32ZBB-ZBKB-NEXT: andn a0, a1, a0
|
|
; RV32ZBB-ZBKB-NEXT: snez a0, a0
|
|
; RV32ZBB-ZBKB-NEXT: ret
|
|
%and = and i32 %a, %b
|
|
%cmpeq = icmp ne i32 %and, %b
|
|
ret i1 %cmpeq
|
|
}
|
|
|
|
define i1 @andn_snez_i64(i64 %a, i64 %b) nounwind {
|
|
; RV32I-LABEL: andn_snez_i64:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: not a0, a0
|
|
; RV32I-NEXT: not a1, a1
|
|
; RV32I-NEXT: and a1, a1, a3
|
|
; RV32I-NEXT: and a0, a0, a2
|
|
; RV32I-NEXT: or a0, a0, a1
|
|
; RV32I-NEXT: snez a0, a0
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32ZBB-ZBKB-LABEL: andn_snez_i64:
|
|
; RV32ZBB-ZBKB: # %bb.0:
|
|
; RV32ZBB-ZBKB-NEXT: andn a1, a3, a1
|
|
; RV32ZBB-ZBKB-NEXT: andn a0, a2, a0
|
|
; RV32ZBB-ZBKB-NEXT: or a0, a0, a1
|
|
; RV32ZBB-ZBKB-NEXT: snez a0, a0
|
|
; RV32ZBB-ZBKB-NEXT: ret
|
|
%and = and i64 %a, %b
|
|
%cmpeq = icmp ne i64 %and, %b
|
|
ret i1 %cmpeq
|
|
}
|