34 lines
1.1 KiB
LLVM
34 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32ZBB
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declare i32 @llvm.riscv.orc.b.i32(i32)
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define i32 @orcb(i32 %a) nounwind {
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; RV32ZBB-LABEL: orcb:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: orc.b a0, a0
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; RV32ZBB-NEXT: ret
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%tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
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ret i32 %tmp
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}
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; Second and+or are redundant with the first, make sure we remove it.
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define i32 @orcb_knownbits(i32 %a) nounwind {
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; RV32ZBB-LABEL: orcb_knownbits:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: lui a1, 1044480
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; RV32ZBB-NEXT: and a0, a0, a1
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; RV32ZBB-NEXT: lui a1, 2048
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; RV32ZBB-NEXT: addi a1, a1, 1
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; RV32ZBB-NEXT: or a0, a0, a1
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; RV32ZBB-NEXT: orc.b a0, a0
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; RV32ZBB-NEXT: ret
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%tmp = and i32 %a, 4278190080 ; 0xFF000000
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%tmp2 = or i32 %tmp, 8388609 ; 0x800001
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%tmp3 = call i32 @llvm.riscv.orc.b.i32(i32 %tmp2)
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%tmp4 = and i32 %tmp3, 4278190080 ; 0xFF000000
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%tmp5 = or i32 %tmp4, 16711935 ; 0xFF00FF
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ret i32 %tmp5
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}
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