136 lines
3.8 KiB
LLVM
136 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
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; RUN: -target-abi ilp32f < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
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; RUN: -target-abi lp64f < %s | FileCheck %s
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define half @select_icmp_eq(i32 signext %a, i32 signext %b, half %c, half %d) {
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; CHECK-LABEL: select_icmp_eq:
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; CHECK: # %bb.0:
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; CHECK-NEXT: beq a0, a1, .LBB0_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: fmv.h fa0, fa1
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: ret
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%1 = icmp eq i32 %a, %b
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%2 = select i1 %1, half %c, half %d
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ret half %2
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}
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define half @select_icmp_ne(i32 signext %a, i32 signext %b, half %c, half %d) {
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; CHECK-LABEL: select_icmp_ne:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bne a0, a1, .LBB1_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: fmv.h fa0, fa1
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; CHECK-NEXT: .LBB1_2:
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; CHECK-NEXT: ret
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%1 = icmp ne i32 %a, %b
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%2 = select i1 %1, half %c, half %d
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ret half %2
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}
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define half @select_icmp_ugt(i32 signext %a, i32 signext %b, half %c, half %d) {
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; CHECK-LABEL: select_icmp_ugt:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bltu a1, a0, .LBB2_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: fmv.h fa0, fa1
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; CHECK-NEXT: .LBB2_2:
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; CHECK-NEXT: ret
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%1 = icmp ugt i32 %a, %b
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%2 = select i1 %1, half %c, half %d
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ret half %2
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}
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define half @select_icmp_uge(i32 signext %a, i32 signext %b, half %c, half %d) {
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; CHECK-LABEL: select_icmp_uge:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bgeu a0, a1, .LBB3_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: fmv.h fa0, fa1
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; CHECK-NEXT: .LBB3_2:
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; CHECK-NEXT: ret
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%1 = icmp uge i32 %a, %b
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%2 = select i1 %1, half %c, half %d
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ret half %2
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}
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define half @select_icmp_ult(i32 signext %a, i32 signext %b, half %c, half %d) {
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; CHECK-LABEL: select_icmp_ult:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bltu a0, a1, .LBB4_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: fmv.h fa0, fa1
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; CHECK-NEXT: .LBB4_2:
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; CHECK-NEXT: ret
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%1 = icmp ult i32 %a, %b
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%2 = select i1 %1, half %c, half %d
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ret half %2
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}
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define half @select_icmp_ule(i32 signext %a, i32 signext %b, half %c, half %d) {
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; CHECK-LABEL: select_icmp_ule:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bgeu a1, a0, .LBB5_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: fmv.h fa0, fa1
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; CHECK-NEXT: .LBB5_2:
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; CHECK-NEXT: ret
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%1 = icmp ule i32 %a, %b
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%2 = select i1 %1, half %c, half %d
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ret half %2
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}
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define half @select_icmp_sgt(i32 signext %a, i32 signext %b, half %c, half %d) {
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; CHECK-LABEL: select_icmp_sgt:
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; CHECK: # %bb.0:
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; CHECK-NEXT: blt a1, a0, .LBB6_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: fmv.h fa0, fa1
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; CHECK-NEXT: .LBB6_2:
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; CHECK-NEXT: ret
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%1 = icmp sgt i32 %a, %b
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%2 = select i1 %1, half %c, half %d
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ret half %2
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}
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define half @select_icmp_sge(i32 signext %a, i32 signext %b, half %c, half %d) {
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; CHECK-LABEL: select_icmp_sge:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bge a0, a1, .LBB7_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: fmv.h fa0, fa1
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; CHECK-NEXT: .LBB7_2:
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; CHECK-NEXT: ret
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%1 = icmp sge i32 %a, %b
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%2 = select i1 %1, half %c, half %d
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ret half %2
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}
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define half @select_icmp_slt(i32 signext %a, i32 signext %b, half %c, half %d) {
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; CHECK-LABEL: select_icmp_slt:
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; CHECK: # %bb.0:
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; CHECK-NEXT: blt a0, a1, .LBB8_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: fmv.h fa0, fa1
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; CHECK-NEXT: .LBB8_2:
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; CHECK-NEXT: ret
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%1 = icmp slt i32 %a, %b
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%2 = select i1 %1, half %c, half %d
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ret half %2
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}
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define half @select_icmp_sle(i32 signext %a, i32 signext %b, half %c, half %d) {
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; CHECK-LABEL: select_icmp_sle:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bge a1, a0, .LBB9_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: fmv.h fa0, fa1
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; CHECK-NEXT: .LBB9_2:
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; CHECK-NEXT: ret
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%1 = icmp sle i32 %a, %b
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%2 = select i1 %1, half %c, half %d
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ret half %2
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}
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