102 lines
3.0 KiB
LLVM
102 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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; Make sure we don't generate an addi in the loop in
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; addition to the addiw. Previously we type legalize the
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; setcc use using signext and the phi use using anyext.
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; We now detect when it would be beneficial to replace
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; anyext with signext.
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define void @quux(i32 signext %arg, i32 signext %arg1) nounwind {
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; RV64I-LABEL: quux:
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; RV64I: # %bb.0: # %bb
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
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; RV64I-NEXT: beq a0, a1, .LBB0_3
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; RV64I-NEXT: # %bb.1: # %bb2.preheader
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; RV64I-NEXT: subw s0, a1, a0
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; RV64I-NEXT: .LBB0_2: # %bb2
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; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
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; RV64I-NEXT: call hoge@plt
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; RV64I-NEXT: addiw s0, s0, -1
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; RV64I-NEXT: bnez s0, .LBB0_2
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; RV64I-NEXT: .LBB0_3: # %bb6
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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bb:
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%tmp = icmp eq i32 %arg, %arg1
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br i1 %tmp, label %bb6, label %bb2
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bb2: ; preds = %bb2, %bb
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%tmp3 = phi i32 [ %tmp4, %bb2 ], [ %arg, %bb ]
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tail call void @hoge()
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%tmp4 = add nsw i32 %tmp3, 1
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%tmp5 = icmp eq i32 %tmp4, %arg1
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br i1 %tmp5, label %bb6, label %bb2
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bb6: ; preds = %bb2, %bb
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ret void
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}
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declare void @hoge()
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; This ends up creating a shl with a i64 result type, but an i32 shift amount.
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; Because custom type legalization for i32 is enabled, this resulted in
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; LowerOperation being called for the amount. This was not expected and
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; triggered an assert.
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define i32 @crash(i32 signext %x, i32 signext %y, i32 signext %z) {
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; RV64I-LABEL: crash:
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; RV64I: # %bb.0:
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; RV64I-NEXT: seqz a3, a0
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; RV64I-NEXT: addw a0, a1, a2
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; RV64I-NEXT: slli a1, a3, 3
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; RV64I-NEXT: .LBB1_1: # %bb
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; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
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; RV64I-NEXT: beq a0, a1, .LBB1_1
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; RV64I-NEXT: # %bb.2: # %bar
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; RV64I-NEXT: ret
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br label %bb
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bb:
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%a = icmp eq i32 %x, 0
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%b = add i32 %y, %z
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%c = select i1 %a, i32 8, i32 0
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%d = icmp eq i32 %b, %c
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br i1 %d, label %bb, label %bar
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bar:
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ret i32 %b
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}
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; We prefer to sign extend i32 constants for phis. The default behavior in
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; SelectionDAGBuilder is zero extend. We have a target hook to override it.
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define i64 @sext_phi_constants(i32 signext %c) {
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; RV64I-LABEL: sext_phi_constants:
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; RV64I: # %bb.0:
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; RV64I-NEXT: li a1, -1
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; RV64I-NEXT: bnez a0, .LBB2_2
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; RV64I-NEXT: # %bb.1: # %iffalse
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; RV64I-NEXT: li a1, -2
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; RV64I-NEXT: .LBB2_2: # %merge
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; RV64I-NEXT: slli a0, a1, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: ret
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%a = icmp ne i32 %c, 0
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br i1 %a, label %iftrue, label %iffalse
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iftrue:
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br label %merge
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iffalse:
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br label %merge
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merge:
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%b = phi i32 [-1, %iftrue], [-2, %iffalse]
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%d = zext i32 %b to i64
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ret i64 %d
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}
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