287 lines
7.5 KiB
LLVM
287 lines
7.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
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; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
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define i8 @alsl_i8(i8 signext %a, i8 signext %b) nounwind {
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; LA32-LABEL: alsl_i8:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: alsl.w $a0, $a0, $a1, 1
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; LA32-NEXT: ret
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;
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; LA64-LABEL: alsl_i8:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: alsl.d $a0, $a0, $a1, 1
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; LA64-NEXT: ret
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entry:
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%mul = mul nsw i8 %a, 2
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%add = add nsw i8 %b, %mul
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ret i8 %add
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}
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define i16 @alsl_i16(i16 signext %a, i16 signext %b) nounwind {
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; LA32-LABEL: alsl_i16:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: alsl.w $a0, $a0, $a1, 2
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; LA32-NEXT: ret
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;
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; LA64-LABEL: alsl_i16:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: alsl.d $a0, $a0, $a1, 2
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; LA64-NEXT: ret
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entry:
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%mul = mul nsw i16 %a, 4
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%add = add nsw i16 %b, %mul
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ret i16 %add
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}
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define i32 @alsl_i32(i32 signext %a, i32 signext %b) nounwind {
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; LA32-LABEL: alsl_i32:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: alsl.w $a0, $a0, $a1, 3
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; LA32-NEXT: ret
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;
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; LA64-LABEL: alsl_i32:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: alsl.d $a0, $a0, $a1, 3
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; LA64-NEXT: ret
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entry:
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%mul = mul nsw i32 %a, 8
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%add = add nsw i32 %b, %mul
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ret i32 %add
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}
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define i64 @alsl_i64(i64 signext %a, i64 signext %b) nounwind {
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; LA32-LABEL: alsl_i64:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: slli.w $a1, $a1, 4
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; LA32-NEXT: srli.w $a4, $a0, 28
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; LA32-NEXT: or $a1, $a1, $a4
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; LA32-NEXT: add.w $a1, $a3, $a1
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; LA32-NEXT: alsl.w $a0, $a0, $a2, 4
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; LA32-NEXT: sltu $a2, $a0, $a2
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; LA32-NEXT: add.w $a1, $a1, $a2
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; LA32-NEXT: ret
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;
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; LA64-LABEL: alsl_i64:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: alsl.d $a0, $a0, $a1, 4
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; LA64-NEXT: ret
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entry:
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%mul = mul nsw i64 %a, 16
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%add = add nsw i64 %b, %mul
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ret i64 %add
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}
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define i32 @alsl_zext_i8(i8 signext %a, i8 signext %b) nounwind {
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; LA32-LABEL: alsl_zext_i8:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: alsl.w $a0, $a0, $a1, 1
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; LA32-NEXT: andi $a0, $a0, 255
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; LA32-NEXT: ret
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;
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; LA64-LABEL: alsl_zext_i8:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: alsl.d $a0, $a0, $a1, 1
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; LA64-NEXT: andi $a0, $a0, 255
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; LA64-NEXT: ret
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entry:
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%mul = mul nsw i8 %a, 2
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%add = add nsw i8 %b, %mul
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%zext = zext i8 %add to i32
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ret i32 %zext
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}
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define i32 @alsl_zext_i16(i16 signext %a, i16 signext %b) nounwind {
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; LA32-LABEL: alsl_zext_i16:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: alsl.w $a0, $a0, $a1, 2
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; LA32-NEXT: bstrpick.w $a0, $a0, 15, 0
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; LA32-NEXT: ret
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;
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; LA64-LABEL: alsl_zext_i16:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: alsl.d $a0, $a0, $a1, 2
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; LA64-NEXT: bstrpick.d $a0, $a0, 15, 0
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; LA64-NEXT: ret
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entry:
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%mul = mul nsw i16 %a, 4
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%add = add nsw i16 %b, %mul
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%zext = zext i16 %add to i32
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ret i32 %zext
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}
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define i64 @alsl_zext_i32(i32 signext %a, i32 signext %b) nounwind {
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; LA32-LABEL: alsl_zext_i32:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: alsl.w $a0, $a0, $a1, 3
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; LA32-NEXT: move $a1, $zero
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; LA32-NEXT: ret
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;
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; LA64-LABEL: alsl_zext_i32:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: alsl.wu $a0, $a0, $a1, 3
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; LA64-NEXT: ret
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entry:
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%mul = mul nsw i32 %a, 8
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%add = add nsw i32 %b, %mul
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%zext = zext i32 %add to i64
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ret i64 %zext
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}
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;; Check that alsl.w or alsl.d is not emitted.
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define i8 @mul_add_i8(i8 signext %a, i8 signext %b) nounwind {
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; LA32-LABEL: mul_add_i8:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: ori $a2, $zero, 3
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; LA32-NEXT: mul.w $a0, $a0, $a2
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; LA32-NEXT: add.w $a0, $a1, $a0
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; LA32-NEXT: ret
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;
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; LA64-LABEL: mul_add_i8:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: ori $a2, $zero, 3
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; LA64-NEXT: mul.d $a0, $a0, $a2
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; LA64-NEXT: add.d $a0, $a1, $a0
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; LA64-NEXT: ret
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entry:
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%mul = mul nsw i8 %a, 3
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%add = add nsw i8 %b, %mul
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ret i8 %add
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}
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define i16 @mul_add_i16(i16 signext %a, i16 signext %b) nounwind {
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; LA32-LABEL: mul_add_i16:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: ori $a2, $zero, 10
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; LA32-NEXT: mul.w $a0, $a0, $a2
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; LA32-NEXT: add.w $a0, $a1, $a0
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; LA32-NEXT: ret
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;
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; LA64-LABEL: mul_add_i16:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: ori $a2, $zero, 10
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; LA64-NEXT: mul.d $a0, $a0, $a2
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; LA64-NEXT: add.d $a0, $a1, $a0
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; LA64-NEXT: ret
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entry:
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%mul = mul nsw i16 %a, 10
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%add = add nsw i16 %b, %mul
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ret i16 %add
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}
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define i32 @mul_add_i32(i32 signext %a, i32 signext %b) nounwind {
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; LA32-LABEL: mul_add_i32:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: ori $a2, $zero, 12
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; LA32-NEXT: mul.w $a0, $a0, $a2
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; LA32-NEXT: add.w $a0, $a1, $a0
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; LA32-NEXT: ret
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;
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; LA64-LABEL: mul_add_i32:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: ori $a2, $zero, 12
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; LA64-NEXT: mul.d $a0, $a0, $a2
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; LA64-NEXT: add.d $a0, $a1, $a0
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; LA64-NEXT: ret
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entry:
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%mul = mul nsw i32 %a, 12
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%add = add nsw i32 %b, %mul
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ret i32 %add
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}
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define i64 @mul_add_i64(i64 signext %a, i64 signext %b) nounwind {
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; LA32-LABEL: mul_add_i64:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: ori $a4, $zero, 15
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; LA32-NEXT: mul.w $a1, $a1, $a4
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; LA32-NEXT: mulh.wu $a5, $a0, $a4
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; LA32-NEXT: add.w $a1, $a5, $a1
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; LA32-NEXT: add.w $a1, $a3, $a1
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; LA32-NEXT: mul.w $a0, $a0, $a4
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; LA32-NEXT: add.w $a0, $a2, $a0
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; LA32-NEXT: sltu $a2, $a0, $a2
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; LA32-NEXT: add.w $a1, $a1, $a2
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; LA32-NEXT: ret
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;
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; LA64-LABEL: mul_add_i64:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: ori $a2, $zero, 15
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; LA64-NEXT: mul.d $a0, $a0, $a2
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; LA64-NEXT: add.d $a0, $a1, $a0
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; LA64-NEXT: ret
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entry:
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%mul = mul nsw i64 %a, 15
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%add = add nsw i64 %b, %mul
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ret i64 %add
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}
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define i32 @mul_add_zext_i8(i8 signext %a, i8 signext %b) nounwind {
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; LA32-LABEL: mul_add_zext_i8:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: ori $a2, $zero, 5
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; LA32-NEXT: mul.w $a0, $a0, $a2
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; LA32-NEXT: add.w $a0, $a1, $a0
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; LA32-NEXT: andi $a0, $a0, 255
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; LA32-NEXT: ret
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;
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; LA64-LABEL: mul_add_zext_i8:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: ori $a2, $zero, 5
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; LA64-NEXT: mul.d $a0, $a0, $a2
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; LA64-NEXT: add.d $a0, $a1, $a0
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; LA64-NEXT: andi $a0, $a0, 255
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; LA64-NEXT: ret
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entry:
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%mul = mul nsw i8 %a, 5
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%add = add nsw i8 %b, %mul
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%zext = zext i8 %add to i32
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ret i32 %zext
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}
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define i32 @mul_add_zext_i16(i16 signext %a, i16 signext %b) nounwind {
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; LA32-LABEL: mul_add_zext_i16:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: ori $a2, $zero, 15
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; LA32-NEXT: mul.w $a0, $a0, $a2
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; LA32-NEXT: add.w $a0, $a1, $a0
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; LA32-NEXT: bstrpick.w $a0, $a0, 15, 0
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; LA32-NEXT: ret
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;
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; LA64-LABEL: mul_add_zext_i16:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: ori $a2, $zero, 15
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; LA64-NEXT: mul.d $a0, $a0, $a2
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; LA64-NEXT: add.d $a0, $a1, $a0
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; LA64-NEXT: bstrpick.d $a0, $a0, 15, 0
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; LA64-NEXT: ret
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entry:
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%mul = mul nsw i16 %a, 15
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%add = add nsw i16 %b, %mul
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%zext = zext i16 %add to i32
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ret i32 %zext
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}
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;; Check that alsl.wu is not emitted.
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define i64 @mul_add_zext_i32(i32 signext %a, i32 signext %b) nounwind {
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; LA32-LABEL: mul_add_zext_i32:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: ori $a2, $zero, 5
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; LA32-NEXT: mul.w $a0, $a0, $a2
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; LA32-NEXT: add.w $a0, $a1, $a0
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; LA32-NEXT: move $a1, $zero
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; LA32-NEXT: ret
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;
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; LA64-LABEL: mul_add_zext_i32:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: ori $a2, $zero, 5
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; LA64-NEXT: mul.d $a0, $a0, $a2
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; LA64-NEXT: add.d $a0, $a1, $a0
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; LA64-NEXT: bstrpick.d $a0, $a0, 31, 0
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; LA64-NEXT: ret
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entry:
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%mul = mul nsw i32 %a, 5
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%add = add nsw i32 %b, %mul
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%zext = zext i32 %add to i64
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ret i64 %zext
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}
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