77 lines
2.9 KiB
LLVM
77 lines
2.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=hexagon < %s | FileCheck %s
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define <32 x i32> @fred(i32 %a0) #0 {
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; CHECK-LABEL: fred:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: r3:2 = combine(#20,#9)
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; CHECK-NEXT: v0 = vxor(v0,v0)
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; CHECK-NEXT: r1 = #24
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; CHECK-NEXT: r4 = #12
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v1 = vror(v0,r1)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v1.w = vinsert(r2)
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; CHECK-NEXT: r4 = #7
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; CHECK-NEXT: r2 = #116
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; CHECK-NEXT: v0 = vror(v0,r4)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.w = vinsert(r4)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v1 = vror(v1,r3)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v1.w = vinsert(r0)
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; CHECK-NEXT: v0 = vror(v0,r2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v1 = vror(v1,r3)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vor(v0,v1)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = insertelement <32 x i32> undef, i32 undef, i32 0
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%v1 = insertelement <32 x i32> %v0, i32 undef, i32 1
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%v2 = insertelement <32 x i32> %v1, i32 undef, i32 2
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%v3 = insertelement <32 x i32> %v2, i32 7, i32 3
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%v4 = insertelement <32 x i32> %v3, i32 undef, i32 4
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%v5 = insertelement <32 x i32> %v4, i32 undef, i32 5
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%v6 = insertelement <32 x i32> %v5, i32 undef, i32 6
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%v7 = insertelement <32 x i32> %v6, i32 undef, i32 7
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%v8 = insertelement <32 x i32> %v7, i32 undef, i32 8
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%v9 = insertelement <32 x i32> %v8, i32 undef, i32 9
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%v10 = insertelement <32 x i32> %v9, i32 undef, i32 10
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%v11 = insertelement <32 x i32> %v10, i32 undef, i32 11
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%v12 = insertelement <32 x i32> %v11, i32 undef, i32 12
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%v13 = insertelement <32 x i32> %v12, i32 undef, i32 13
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%v14 = insertelement <32 x i32> %v13, i32 undef, i32 14
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%v15 = insertelement <32 x i32> %v14, i32 undef, i32 15
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%v16 = insertelement <32 x i32> %v15, i32 undef, i32 16
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%v17 = insertelement <32 x i32> %v16, i32 undef, i32 17
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%v18 = insertelement <32 x i32> %v17, i32 undef, i32 18
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%v19 = insertelement <32 x i32> %v18, i32 undef, i32 19
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%v20 = insertelement <32 x i32> %v19, i32 undef, i32 20
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%v21 = insertelement <32 x i32> %v20, i32 undef, i32 21
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%v22 = insertelement <32 x i32> %v21, i32 9, i32 22
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%v23 = insertelement <32 x i32> %v22, i32 undef, i32 23
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%v24 = insertelement <32 x i32> %v23, i32 undef, i32 24
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%v25 = insertelement <32 x i32> %v24, i32 undef, i32 25
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%v26 = insertelement <32 x i32> %v25, i32 undef, i32 26
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%v27 = insertelement <32 x i32> %v26, i32 %a0, i32 27
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%v28 = insertelement <32 x i32> %v27, i32 undef, i32 28
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%v29 = insertelement <32 x i32> %v28, i32 undef, i32 29
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%v30 = insertelement <32 x i32> %v29, i32 undef, i32 30
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%v31 = insertelement <32 x i32> %v30, i32 undef, i32 31
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ret <32 x i32> %v31
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}
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attributes #0 = { "target-cpu"="hexagonv66" "target-features"="+hvx,+hvx-length128b" }
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