35 lines
1.4 KiB
LLVM
35 lines
1.4 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; Check that vector is produced with vxor
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; CHECK: v{{[0-9]*}} = vxor
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define <16 x i32> @f0(i32 %x) #0 {
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%vect = insertelement <16 x i32> <i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, i32 %x, i32 0
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ret <16 x i32> %vect
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}
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; Check that vector is produced with vsplat
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; CHECK: v{{[0-9]*}} = vsplat
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define <16 x i32> @f1(i32 %x) #0 {
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%vect = insertelement <16 x i32> <i32 undef, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, i32 %x, i32 0
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ret <16 x i32> %vect
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}
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; Check that the correct vror is generated
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; CHECK: [[REG0:r([0-9]+)]] = #56
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; CHECK: vror(v{{[0-9]+}},[[REG0]])
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define <16 x i32> @f2(i32 %x) #0 {
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%vect = insertelement <16 x i32> <i32 1, i32 1, i32 undef, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, i32 %x, i32 2
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ret <16 x i32> %vect
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}
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; Check that the correct vror is generated
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; CHECK: [[REG0:r([0-9]+)]] = #12
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; CHECK: vror(v{{[0-9]+}},[[REG0]])
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define <16 x i32> @f3(i32 %x) #0 {
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%vect = insertelement <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 undef, i32 1, i32 1>, i32 %x, i32 13
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ret <16 x i32> %vect
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}
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attributes #0 = { readnone nounwind "target-cpu"="hexagonv62" "target-features"="+hvx,+hvx-length64b" }
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