5527b21516
This patch makes sure the compiler uses R16/R17 on avrtiny (attiny10
etc) instead of R0/R1.
Some notes:
* For the NEGW and ROLB instructions, it adds an explicit zero
register. This is necessary because the zero register is different
on avrtiny (and InstrInfo Uses lines need a fixed register).
* Not entirely sure about putting all tests in features/avr-tiny.ll,
but it doesn't seem like the "target-cpu"="attiny10" attribute
works.
Updates: https://github.com/llvm/llvm-project/issues/53459
Differential Revision: https://reviews.llvm.org/D138582
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| .. | ||
| ADCWRdRr.mir | ||
| ADDWRdRr.mir | ||
| ANDIWRdK.mir | ||
| ANDWRdRr.mir | ||
| ASRBNRd.mir | ||
| ASRWNRd.mir | ||
| ASRWRd.mir | ||
| COMWRd.mir | ||
| COPY.mir | ||
| CPCWRdRr.mir | ||
| CPWRdRr.mir | ||
| ELPMWRdZ.mir | ||
| EORWRdRr.mir | ||
| FRMIDX.mir | ||
| INWRdA.mir | ||
| LDDWRdPtrQ.mir | ||
| LDDWRdYQ.mir | ||
| LDIWRdK.mir | ||
| LDSWRdK.mir | ||
| LDWRdPtr.mir | ||
| LDWRdPtrPd.mir | ||
| LDWRdPtrPi.mir | ||
| LSLBNRd.mir | ||
| LSLWNRd.mir | ||
| LSLWRd.mir | ||
| LSRBNRd.mir | ||
| LSRWNRd.mir | ||
| LSRWRd.mir | ||
| NEGWRd.mir | ||
| ORIWRdK.mir | ||
| ORWRdRr.mir | ||
| OUTWARr.mir | ||
| POPWRd.mir | ||
| PUSHWRr.mir | ||
| ROLBrd.mir | ||
| SBCIWRdK.mir | ||
| SBCWRdRr.mir | ||
| SEXT.mir | ||
| STDWPtrQRr.mir | ||
| STSWKRr.mir | ||
| STWPtrPdRr.mir | ||
| STWPtrPiRr.mir | ||
| STWPtrRr.mir | ||
| SUBIWRdK.mir | ||
| SUBWRdRr.mir | ||
| ZEXT.mir | ||