114 lines
5.0 KiB
LLVM
114 lines
5.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,SI
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,CI
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@local_memory.local_mem = internal unnamed_addr addrspace(3) global [128 x i32] undef, align 4
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define amdgpu_kernel void @local_memory(i32 addrspace(1)* %out) #0 {
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; GCN-LABEL: local_memory:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: v_lshlrev_b32_e32 v1, 2, v0
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; GCN-NEXT: s_mov_b32 m0, -1
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; GCN-NEXT: ds_write_b32 v1, v0
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; GCN-NEXT: v_add_i32_e32 v0, vcc, 1, v0
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; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 16, v0
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; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
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; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_barrier
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; GCN-NEXT: ds_read_b32 v0, v0
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; GCN-NEXT: s_mov_b32 s2, 0
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: v_mov_b32_e32 v2, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: buffer_store_dword v0, v[1:2], s[0:3], 0 addr64
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; GCN-NEXT: s_endpgm
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entry:
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%y.i = call i32 @llvm.amdgcn.workitem.id.x() #1
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%arrayidx = getelementptr inbounds [128 x i32], [128 x i32] addrspace(3)* @local_memory.local_mem, i32 0, i32 %y.i
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store i32 %y.i, i32 addrspace(3)* %arrayidx, align 4
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%add = add nsw i32 %y.i, 1
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%cmp = icmp eq i32 %add, 16
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%.add = select i1 %cmp, i32 0, i32 %add
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call void @llvm.amdgcn.s.barrier()
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%arrayidx1 = getelementptr inbounds [128 x i32], [128 x i32] addrspace(3)* @local_memory.local_mem, i32 0, i32 %.add
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%tmp = load i32, i32 addrspace(3)* %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %y.i
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store i32 %tmp, i32 addrspace(1)* %arrayidx2, align 4
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ret void
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}
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@local_memory_two_objects.local_mem0 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4
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@local_memory_two_objects.local_mem1 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4
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; Check that the LDS size emitted correctly
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define amdgpu_kernel void @local_memory_two_objects(i32 addrspace(1)* %out) #0 {
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; SI-LABEL: local_memory_two_objects:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
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; SI-NEXT: v_lshlrev_b32_e32 v2, 1, v0
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; SI-NEXT: s_mov_b32 m0, -1
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; SI-NEXT: ds_write2_b32 v1, v0, v2 offset1:4
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; SI-NEXT: v_sub_i32_e32 v0, vcc, 12, v1
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; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_barrier
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; SI-NEXT: v_sub_i32_e32 v2, vcc, 28, v1
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; SI-NEXT: ds_read_b32 v0, v0
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; SI-NEXT: ds_read_b32 v3, v2
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, 0
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; SI-NEXT: v_mov_b32_e32 v2, 0
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; SI-NEXT: s_waitcnt lgkmcnt(1)
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; SI-NEXT: buffer_store_dword v0, v[1:2], s[0:3], 0 addr64
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: buffer_store_dword v3, v[1:2], s[0:3], 0 addr64 offset:16
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; SI-NEXT: s_endpgm
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;
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; CI-LABEL: local_memory_two_objects:
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; CI: ; %bb.0: ; %entry
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; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
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; CI-NEXT: v_lshlrev_b32_e32 v2, 1, v0
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; CI-NEXT: s_mov_b32 m0, -1
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; CI-NEXT: ds_write2_b32 v1, v0, v2 offset1:4
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; CI-NEXT: v_sub_i32_e32 v0, vcc, 0, v1
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; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; CI-NEXT: s_waitcnt lgkmcnt(0)
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; CI-NEXT: s_barrier
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; CI-NEXT: ds_read2_b32 v[3:4], v0 offset0:3 offset1:7
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; CI-NEXT: s_mov_b32 s3, 0xf000
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; CI-NEXT: s_mov_b32 s2, 0
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; CI-NEXT: v_mov_b32_e32 v2, 0
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; CI-NEXT: s_waitcnt lgkmcnt(0)
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; CI-NEXT: buffer_store_dword v3, v[1:2], s[0:3], 0 addr64
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; CI-NEXT: buffer_store_dword v4, v[1:2], s[0:3], 0 addr64 offset:16
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; CI-NEXT: s_endpgm
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entry:
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%x.i = call i32 @llvm.amdgcn.workitem.id.x()
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%arrayidx = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %x.i
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store i32 %x.i, i32 addrspace(3)* %arrayidx, align 4
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%mul = shl nsw i32 %x.i, 1
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%arrayidx1 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %x.i
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store i32 %mul, i32 addrspace(3)* %arrayidx1, align 4
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%sub = sub nsw i32 3, %x.i
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call void @llvm.amdgcn.s.barrier()
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%arrayidx2 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %sub
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%tmp = load i32, i32 addrspace(3)* %arrayidx2, align 4
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%arrayidx3 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %x.i
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store i32 %tmp, i32 addrspace(1)* %arrayidx3, align 4
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%arrayidx4 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %sub
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%tmp1 = load i32, i32 addrspace(3)* %arrayidx4, align 4
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%add = add nsw i32 %x.i, 4
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%arrayidx5 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %add
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store i32 %tmp1, i32 addrspace(1)* %arrayidx5, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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declare void @llvm.amdgcn.s.barrier() #2
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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attributes #2 = { convergent nounwind }
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