286 lines
13 KiB
LLVM
286 lines
13 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefix=ATTRIB %s
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; RUN: llc -march=amdgcn -mcpu=gfx1100 -amdgpu-nsa-threshold=2 -verify-machineinstrs < %s | FileCheck -check-prefix=FORCE-2 %s
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; RUN: llc -march=amdgcn -mcpu=gfx1100 -amdgpu-nsa-threshold=3 -verify-machineinstrs < %s | FileCheck -check-prefix=FORCE-3 %s
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; RUN: llc -march=amdgcn -mcpu=gfx1100 -amdgpu-nsa-threshold=4 -verify-machineinstrs < %s | FileCheck -check-prefix=FORCE-4 %s
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; Note: command line argument should override function attribute.
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define amdgpu_ps <4 x float> @sample_2d_nsa2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %t, float %s) #2 {
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; ATTRIB-LABEL: sample_2d_nsa2:
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; ATTRIB: ; %bb.0: ; %main_body
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; ATTRIB-NEXT: s_mov_b32 s12, exec_lo
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; ATTRIB-NEXT: s_wqm_b32 exec_lo, exec_lo
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; ATTRIB-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; ATTRIB-NEXT: s_and_b32 exec_lo, exec_lo, s12
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; ATTRIB-NEXT: image_sample v[0:3], [v1, v0], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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; ATTRIB-NEXT: s_waitcnt vmcnt(0)
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; ATTRIB-NEXT: ; return to shader part epilog
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;
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; FORCE-2-LABEL: sample_2d_nsa2:
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; FORCE-2: ; %bb.0: ; %main_body
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; FORCE-2-NEXT: s_mov_b32 s12, exec_lo
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; FORCE-2-NEXT: s_wqm_b32 exec_lo, exec_lo
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; FORCE-2-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; FORCE-2-NEXT: s_and_b32 exec_lo, exec_lo, s12
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; FORCE-2-NEXT: image_sample v[0:3], [v1, v0], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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; FORCE-2-NEXT: s_waitcnt vmcnt(0)
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; FORCE-2-NEXT: ; return to shader part epilog
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;
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; FORCE-3-LABEL: sample_2d_nsa2:
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; FORCE-3: ; %bb.0: ; %main_body
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; FORCE-3-NEXT: s_mov_b32 s12, exec_lo
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; FORCE-3-NEXT: s_wqm_b32 exec_lo, exec_lo
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; FORCE-3-NEXT: v_mov_b32_e32 v2, v0
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; FORCE-3-NEXT: s_and_b32 exec_lo, exec_lo, s12
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; FORCE-3-NEXT: image_sample v[0:3], v[1:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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; FORCE-3-NEXT: s_waitcnt vmcnt(0)
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; FORCE-3-NEXT: ; return to shader part epilog
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;
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; FORCE-4-LABEL: sample_2d_nsa2:
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; FORCE-4: ; %bb.0: ; %main_body
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; FORCE-4-NEXT: s_mov_b32 s12, exec_lo
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; FORCE-4-NEXT: s_wqm_b32 exec_lo, exec_lo
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; FORCE-4-NEXT: v_mov_b32_e32 v2, v0
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; FORCE-4-NEXT: s_and_b32 exec_lo, exec_lo, s12
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; FORCE-4-NEXT: image_sample v[0:3], v[1:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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; FORCE-4-NEXT: s_waitcnt vmcnt(0)
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; FORCE-4-NEXT: ; return to shader part epilog
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret <4 x float> %v
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}
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define amdgpu_ps <4 x float> @sample_3d_nsa2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %r, float %s, float %t) #2 {
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; ATTRIB-LABEL: sample_3d_nsa2:
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; ATTRIB: ; %bb.0: ; %main_body
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; ATTRIB-NEXT: s_mov_b32 s12, exec_lo
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; ATTRIB-NEXT: s_wqm_b32 exec_lo, exec_lo
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; ATTRIB-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; ATTRIB-NEXT: s_and_b32 exec_lo, exec_lo, s12
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; ATTRIB-NEXT: image_sample v[0:3], [v1, v2, v0], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
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; ATTRIB-NEXT: s_waitcnt vmcnt(0)
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; ATTRIB-NEXT: ; return to shader part epilog
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;
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; FORCE-2-LABEL: sample_3d_nsa2:
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; FORCE-2: ; %bb.0: ; %main_body
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; FORCE-2-NEXT: s_mov_b32 s12, exec_lo
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; FORCE-2-NEXT: s_wqm_b32 exec_lo, exec_lo
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; FORCE-2-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; FORCE-2-NEXT: s_and_b32 exec_lo, exec_lo, s12
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; FORCE-2-NEXT: image_sample v[0:3], [v1, v2, v0], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
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; FORCE-2-NEXT: s_waitcnt vmcnt(0)
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; FORCE-2-NEXT: ; return to shader part epilog
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;
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; FORCE-3-LABEL: sample_3d_nsa2:
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; FORCE-3: ; %bb.0: ; %main_body
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; FORCE-3-NEXT: s_mov_b32 s12, exec_lo
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; FORCE-3-NEXT: s_wqm_b32 exec_lo, exec_lo
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; FORCE-3-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; FORCE-3-NEXT: s_and_b32 exec_lo, exec_lo, s12
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; FORCE-3-NEXT: image_sample v[0:3], [v1, v2, v0], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
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; FORCE-3-NEXT: s_waitcnt vmcnt(0)
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; FORCE-3-NEXT: ; return to shader part epilog
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;
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; FORCE-4-LABEL: sample_3d_nsa2:
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; FORCE-4: ; %bb.0: ; %main_body
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; FORCE-4-NEXT: s_mov_b32 s12, exec_lo
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; FORCE-4-NEXT: s_wqm_b32 exec_lo, exec_lo
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; FORCE-4-NEXT: v_mov_b32_e32 v3, v0
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; FORCE-4-NEXT: s_and_b32 exec_lo, exec_lo, s12
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; FORCE-4-NEXT: image_sample v[0:3], v[1:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
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; FORCE-4-NEXT: s_waitcnt vmcnt(0)
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; FORCE-4-NEXT: ; return to shader part epilog
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32(i32 15, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret <4 x float> %v
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}
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define amdgpu_ps <4 x float> @sample_2d_nsa3(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %t, float %s) #3 {
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; ATTRIB-LABEL: sample_2d_nsa3:
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; ATTRIB: ; %bb.0: ; %main_body
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; ATTRIB-NEXT: s_mov_b32 s12, exec_lo
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; ATTRIB-NEXT: s_wqm_b32 exec_lo, exec_lo
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; ATTRIB-NEXT: v_mov_b32_e32 v2, v0
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; ATTRIB-NEXT: s_and_b32 exec_lo, exec_lo, s12
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; ATTRIB-NEXT: image_sample v[0:3], v[1:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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; ATTRIB-NEXT: s_waitcnt vmcnt(0)
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; ATTRIB-NEXT: ; return to shader part epilog
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;
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; FORCE-2-LABEL: sample_2d_nsa3:
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; FORCE-2: ; %bb.0: ; %main_body
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; FORCE-2-NEXT: s_mov_b32 s12, exec_lo
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; FORCE-2-NEXT: s_wqm_b32 exec_lo, exec_lo
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; FORCE-2-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; FORCE-2-NEXT: s_and_b32 exec_lo, exec_lo, s12
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; FORCE-2-NEXT: image_sample v[0:3], [v1, v0], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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; FORCE-2-NEXT: s_waitcnt vmcnt(0)
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; FORCE-2-NEXT: ; return to shader part epilog
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;
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; FORCE-3-LABEL: sample_2d_nsa3:
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; FORCE-3: ; %bb.0: ; %main_body
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; FORCE-3-NEXT: s_mov_b32 s12, exec_lo
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; FORCE-3-NEXT: s_wqm_b32 exec_lo, exec_lo
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; FORCE-3-NEXT: v_mov_b32_e32 v2, v0
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; FORCE-3-NEXT: s_and_b32 exec_lo, exec_lo, s12
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; FORCE-3-NEXT: image_sample v[0:3], v[1:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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; FORCE-3-NEXT: s_waitcnt vmcnt(0)
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; FORCE-3-NEXT: ; return to shader part epilog
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;
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; FORCE-4-LABEL: sample_2d_nsa3:
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; FORCE-4: ; %bb.0: ; %main_body
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; FORCE-4-NEXT: s_mov_b32 s12, exec_lo
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; FORCE-4-NEXT: s_wqm_b32 exec_lo, exec_lo
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; FORCE-4-NEXT: v_mov_b32_e32 v2, v0
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; FORCE-4-NEXT: s_and_b32 exec_lo, exec_lo, s12
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; FORCE-4-NEXT: image_sample v[0:3], v[1:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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; FORCE-4-NEXT: s_waitcnt vmcnt(0)
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; FORCE-4-NEXT: ; return to shader part epilog
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret <4 x float> %v
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}
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define amdgpu_ps <4 x float> @sample_3d_nsa3(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %r, float %s, float %t) #3 {
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; ATTRIB-LABEL: sample_3d_nsa3:
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; ATTRIB: ; %bb.0: ; %main_body
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; ATTRIB-NEXT: s_mov_b32 s12, exec_lo
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; ATTRIB-NEXT: s_wqm_b32 exec_lo, exec_lo
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; ATTRIB-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; ATTRIB-NEXT: s_and_b32 exec_lo, exec_lo, s12
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; ATTRIB-NEXT: image_sample v[0:3], [v1, v2, v0], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
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; ATTRIB-NEXT: s_waitcnt vmcnt(0)
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; ATTRIB-NEXT: ; return to shader part epilog
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;
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; FORCE-2-LABEL: sample_3d_nsa3:
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; FORCE-2: ; %bb.0: ; %main_body
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; FORCE-2-NEXT: s_mov_b32 s12, exec_lo
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; FORCE-2-NEXT: s_wqm_b32 exec_lo, exec_lo
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; FORCE-2-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; FORCE-2-NEXT: s_and_b32 exec_lo, exec_lo, s12
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; FORCE-2-NEXT: image_sample v[0:3], [v1, v2, v0], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
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; FORCE-2-NEXT: s_waitcnt vmcnt(0)
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; FORCE-2-NEXT: ; return to shader part epilog
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;
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; FORCE-3-LABEL: sample_3d_nsa3:
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; FORCE-3: ; %bb.0: ; %main_body
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; FORCE-3-NEXT: s_mov_b32 s12, exec_lo
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; FORCE-3-NEXT: s_wqm_b32 exec_lo, exec_lo
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; FORCE-3-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; FORCE-3-NEXT: s_and_b32 exec_lo, exec_lo, s12
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; FORCE-3-NEXT: image_sample v[0:3], [v1, v2, v0], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
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; FORCE-3-NEXT: s_waitcnt vmcnt(0)
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; FORCE-3-NEXT: ; return to shader part epilog
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;
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; FORCE-4-LABEL: sample_3d_nsa3:
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; FORCE-4: ; %bb.0: ; %main_body
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; FORCE-4-NEXT: s_mov_b32 s12, exec_lo
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; FORCE-4-NEXT: s_wqm_b32 exec_lo, exec_lo
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; FORCE-4-NEXT: v_mov_b32_e32 v3, v0
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; FORCE-4-NEXT: s_and_b32 exec_lo, exec_lo, s12
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; FORCE-4-NEXT: image_sample v[0:3], v[1:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
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; FORCE-4-NEXT: s_waitcnt vmcnt(0)
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; FORCE-4-NEXT: ; return to shader part epilog
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32(i32 15, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret <4 x float> %v
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}
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define amdgpu_ps <4 x float> @sample_2d_nsa4(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %t, float %s) #4 {
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; ATTRIB-LABEL: sample_2d_nsa4:
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; ATTRIB: ; %bb.0: ; %main_body
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; ATTRIB-NEXT: s_mov_b32 s12, exec_lo
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; ATTRIB-NEXT: s_wqm_b32 exec_lo, exec_lo
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; ATTRIB-NEXT: v_mov_b32_e32 v2, v0
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; ATTRIB-NEXT: s_and_b32 exec_lo, exec_lo, s12
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; ATTRIB-NEXT: image_sample v[0:3], v[1:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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; ATTRIB-NEXT: s_waitcnt vmcnt(0)
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; ATTRIB-NEXT: ; return to shader part epilog
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;
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; FORCE-2-LABEL: sample_2d_nsa4:
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; FORCE-2: ; %bb.0: ; %main_body
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; FORCE-2-NEXT: s_mov_b32 s12, exec_lo
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; FORCE-2-NEXT: s_wqm_b32 exec_lo, exec_lo
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; FORCE-2-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; FORCE-2-NEXT: s_and_b32 exec_lo, exec_lo, s12
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; FORCE-2-NEXT: image_sample v[0:3], [v1, v0], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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; FORCE-2-NEXT: s_waitcnt vmcnt(0)
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; FORCE-2-NEXT: ; return to shader part epilog
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;
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; FORCE-3-LABEL: sample_2d_nsa4:
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; FORCE-3: ; %bb.0: ; %main_body
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; FORCE-3-NEXT: s_mov_b32 s12, exec_lo
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; FORCE-3-NEXT: s_wqm_b32 exec_lo, exec_lo
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; FORCE-3-NEXT: v_mov_b32_e32 v2, v0
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; FORCE-3-NEXT: s_and_b32 exec_lo, exec_lo, s12
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; FORCE-3-NEXT: image_sample v[0:3], v[1:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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; FORCE-3-NEXT: s_waitcnt vmcnt(0)
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; FORCE-3-NEXT: ; return to shader part epilog
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;
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; FORCE-4-LABEL: sample_2d_nsa4:
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; FORCE-4: ; %bb.0: ; %main_body
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; FORCE-4-NEXT: s_mov_b32 s12, exec_lo
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; FORCE-4-NEXT: s_wqm_b32 exec_lo, exec_lo
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; FORCE-4-NEXT: v_mov_b32_e32 v2, v0
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; FORCE-4-NEXT: s_and_b32 exec_lo, exec_lo, s12
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; FORCE-4-NEXT: image_sample v[0:3], v[1:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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; FORCE-4-NEXT: s_waitcnt vmcnt(0)
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; FORCE-4-NEXT: ; return to shader part epilog
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret <4 x float> %v
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}
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define amdgpu_ps <4 x float> @sample_3d_nsa4(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %r, float %s, float %t) #4 {
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; ATTRIB-LABEL: sample_3d_nsa4:
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; ATTRIB: ; %bb.0: ; %main_body
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; ATTRIB-NEXT: s_mov_b32 s12, exec_lo
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; ATTRIB-NEXT: s_wqm_b32 exec_lo, exec_lo
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; ATTRIB-NEXT: v_mov_b32_e32 v3, v0
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; ATTRIB-NEXT: s_and_b32 exec_lo, exec_lo, s12
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; ATTRIB-NEXT: image_sample v[0:3], v[1:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
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; ATTRIB-NEXT: s_waitcnt vmcnt(0)
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; ATTRIB-NEXT: ; return to shader part epilog
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;
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; FORCE-2-LABEL: sample_3d_nsa4:
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; FORCE-2: ; %bb.0: ; %main_body
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; FORCE-2-NEXT: s_mov_b32 s12, exec_lo
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; FORCE-2-NEXT: s_wqm_b32 exec_lo, exec_lo
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; FORCE-2-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; FORCE-2-NEXT: s_and_b32 exec_lo, exec_lo, s12
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; FORCE-2-NEXT: image_sample v[0:3], [v1, v2, v0], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
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; FORCE-2-NEXT: s_waitcnt vmcnt(0)
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; FORCE-2-NEXT: ; return to shader part epilog
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;
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; FORCE-3-LABEL: sample_3d_nsa4:
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; FORCE-3: ; %bb.0: ; %main_body
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; FORCE-3-NEXT: s_mov_b32 s12, exec_lo
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; FORCE-3-NEXT: s_wqm_b32 exec_lo, exec_lo
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; FORCE-3-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; FORCE-3-NEXT: s_and_b32 exec_lo, exec_lo, s12
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; FORCE-3-NEXT: image_sample v[0:3], [v1, v2, v0], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
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; FORCE-3-NEXT: s_waitcnt vmcnt(0)
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; FORCE-3-NEXT: ; return to shader part epilog
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;
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; FORCE-4-LABEL: sample_3d_nsa4:
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; FORCE-4: ; %bb.0: ; %main_body
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; FORCE-4-NEXT: s_mov_b32 s12, exec_lo
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; FORCE-4-NEXT: s_wqm_b32 exec_lo, exec_lo
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; FORCE-4-NEXT: v_mov_b32_e32 v3, v0
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; FORCE-4-NEXT: s_and_b32 exec_lo, exec_lo, s12
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; FORCE-4-NEXT: image_sample v[0:3], v[1:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
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; FORCE-4-NEXT: s_waitcnt vmcnt(0)
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; FORCE-4-NEXT: ; return to shader part epilog
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32(i32 15, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret <4 x float> %v
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}
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declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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declare <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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attributes #1 = { nounwind readonly }
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attributes #2 = { nounwind readonly "amdgpu-nsa-threshold"="2" }
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attributes #3 = { nounwind readonly "amdgpu-nsa-threshold"="3" }
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attributes #4 = { nounwind readonly "amdgpu-nsa-threshold"="4" }
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