196 lines
7.4 KiB
LLVM
196 lines
7.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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define <4 x i8> @sdiv_v4i8(<4 x i8> %op1) #0 {
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; CHECK-LABEL: sdiv_v4i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI0_0
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.h, vl4
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; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI0_0]
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; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z1.h
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; CHECK-NEXT: asr z0.h, p0/m, z0.h, z1.h
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; CHECK-NEXT: asrd z0.h, p0/m, z0.h, #5
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = sdiv <4 x i8> %op1, shufflevector (<4 x i8> insertelement (<4 x i8> poison, i8 32, i32 0), <4 x i8> poison, <4 x i32> zeroinitializer)
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ret <4 x i8> %res
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}
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define <8 x i8> @sdiv_v8i8(<8 x i8> %op1) #0 {
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; CHECK-LABEL: sdiv_v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.b, vl8
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; CHECK-NEXT: asrd z0.b, p0/m, z0.b, #5
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = sdiv <8 x i8> %op1, shufflevector (<8 x i8> insertelement (<8 x i8> poison, i8 32, i32 0), <8 x i8> poison, <8 x i32> zeroinitializer)
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ret <8 x i8> %res
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}
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define <16 x i8> @sdiv_v16i8(<16 x i8> %op1) #0 {
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; CHECK-LABEL: sdiv_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.b, vl16
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; CHECK-NEXT: asrd z0.b, p0/m, z0.b, #5
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%res = sdiv <16 x i8> %op1, shufflevector (<16 x i8> insertelement (<16 x i8> poison, i8 32, i32 0), <16 x i8> poison, <16 x i32> zeroinitializer)
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ret <16 x i8> %res
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}
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define void @sdiv_v32i8(<32 x i8>* %a) #0 {
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; CHECK-LABEL: sdiv_v32i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.b, vl16
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; CHECK-NEXT: asrd z0.b, p0/m, z0.b, #5
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; CHECK-NEXT: asrd z1.b, p0/m, z1.b, #5
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op1 = load <32 x i8>, <32 x i8>* %a
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%res = sdiv <32 x i8> %op1, shufflevector (<32 x i8> insertelement (<32 x i8> poison, i8 32, i32 0), <32 x i8> poison, <32 x i32> zeroinitializer)
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store <32 x i8> %res, <32 x i8>* %a
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ret void
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}
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define <2 x i16> @sdiv_v2i16(<2 x i16> %op1) #0 {
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; CHECK-LABEL: sdiv_v2i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI4_0
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl2
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; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI4_0]
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; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: asr z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #5
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = sdiv <2 x i16> %op1, shufflevector (<2 x i16> insertelement (<2 x i16> poison, i16 32, i32 0), <2 x i16> poison, <2 x i32> zeroinitializer)
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ret <2 x i16> %res
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}
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define <4 x i16> @sdiv_v4i16(<4 x i16> %op1) #0 {
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; CHECK-LABEL: sdiv_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.h, vl4
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; CHECK-NEXT: asrd z0.h, p0/m, z0.h, #5
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = sdiv <4 x i16> %op1, shufflevector (<4 x i16> insertelement (<4 x i16> poison, i16 32, i32 0), <4 x i16> poison, <4 x i32> zeroinitializer)
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ret <4 x i16> %res
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}
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define <8 x i16> @sdiv_v8i16(<8 x i16> %op1) #0 {
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; CHECK-LABEL: sdiv_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.h, vl8
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; CHECK-NEXT: asrd z0.h, p0/m, z0.h, #5
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%res = sdiv <8 x i16> %op1, shufflevector (<8 x i16> insertelement (<8 x i16> poison, i16 32, i32 0), <8 x i16> poison, <8 x i32> zeroinitializer)
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ret <8 x i16> %res
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}
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define void @sdiv_v16i16(<16 x i16>* %a) #0 {
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; CHECK-LABEL: sdiv_v16i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.h, vl8
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; CHECK-NEXT: asrd z0.h, p0/m, z0.h, #5
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; CHECK-NEXT: asrd z1.h, p0/m, z1.h, #5
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op1 = load <16 x i16>, <16 x i16>* %a
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%res = sdiv <16 x i16> %op1, shufflevector (<16 x i16> insertelement (<16 x i16> poison, i16 32, i32 0), <16 x i16> poison, <16 x i32> zeroinitializer)
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store <16 x i16> %res, <16 x i16>* %a
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ret void
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}
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define <2 x i32> @sdiv_v2i32(<2 x i32> %op1) #0 {
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; CHECK-LABEL: sdiv_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl2
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; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #5
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = sdiv <2 x i32> %op1, shufflevector (<2 x i32> insertelement (<2 x i32> poison, i32 32, i32 0), <2 x i32> poison, <2 x i32> zeroinitializer)
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ret <2 x i32> %res
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}
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define <4 x i32> @sdiv_v4i32(<4 x i32> %op1) #0 {
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; CHECK-LABEL: sdiv_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #5
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%res = sdiv <4 x i32> %op1, shufflevector (<4 x i32> insertelement (<4 x i32> poison, i32 32, i32 0), <4 x i32> poison, <4 x i32> zeroinitializer)
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ret <4 x i32> %res
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}
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define void @sdiv_v8i32(<8 x i32>* %a) #0 {
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; CHECK-LABEL: sdiv_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #5
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; CHECK-NEXT: asrd z1.s, p0/m, z1.s, #5
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op1 = load <8 x i32>, <8 x i32>* %a
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%res = sdiv <8 x i32> %op1, shufflevector (<8 x i32> insertelement (<8 x i32> poison, i32 32, i32 0), <8 x i32> poison, <8 x i32> zeroinitializer)
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store <8 x i32> %res, <8 x i32>* %a
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ret void
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}
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define <1 x i64> @sdiv_v1i64(<1 x i64> %op1) #0 {
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; CHECK-LABEL: sdiv_v1i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.d, vl1
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; CHECK-NEXT: asrd z0.d, p0/m, z0.d, #5
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = sdiv <1 x i64> %op1, shufflevector (<1 x i64> insertelement (<1 x i64> poison, i64 32, i32 0), <1 x i64> poison, <1 x i32> zeroinitializer)
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ret <1 x i64> %res
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}
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; Vector i64 sdiv are not legal for NEON so use SVE when available.
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define <2 x i64> @sdiv_v2i64(<2 x i64> %op1) #0 {
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; CHECK-LABEL: sdiv_v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.d, vl2
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; CHECK-NEXT: asrd z0.d, p0/m, z0.d, #5
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%res = sdiv <2 x i64> %op1, shufflevector (<2 x i64> insertelement (<2 x i64> poison, i64 32, i32 0), <2 x i64> poison, <2 x i32> zeroinitializer)
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ret <2 x i64> %res
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}
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define void @sdiv_v4i64(<4 x i64>* %a) #0 {
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; CHECK-LABEL: sdiv_v4i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.d, vl2
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; CHECK-NEXT: asrd z0.d, p0/m, z0.d, #5
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; CHECK-NEXT: asrd z1.d, p0/m, z1.d, #5
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op1 = load <4 x i64>, <4 x i64>* %a
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%res = sdiv <4 x i64> %op1, shufflevector (<4 x i64> insertelement (<4 x i64> poison, i64 32, i32 0), <4 x i64> poison, <4 x i32> zeroinitializer)
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store <4 x i64> %res, <4 x i64>* %a
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ret void
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}
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attributes #0 = { "target-features"="+sve" }
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