596 lines
21 KiB
LLVM
596 lines
21 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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;
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; RBIT
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;
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define <4 x i8> @bitreverse_v4i8(<4 x i8> %op) #0 {
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; CHECK-LABEL: bitreverse_v4i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI0_0
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.h, vl4
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; CHECK-NEXT: rbit z0.h, p0/m, z0.h
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; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI0_0]
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; CHECK-NEXT: lsr z0.h, p0/m, z0.h, z1.h
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = call <4 x i8> @llvm.bitreverse.v4i8(<4 x i8> %op)
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ret <4 x i8> %res
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}
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define <8 x i8> @bitreverse_v8i8(<8 x i8> %op) #0 {
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; CHECK-LABEL: bitreverse_v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.b, vl8
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; CHECK-NEXT: rbit z0.b, p0/m, z0.b
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = call <8 x i8> @llvm.bitreverse.v8i8(<8 x i8> %op)
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ret <8 x i8> %res
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}
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define <16 x i8> @bitreverse_v16i8(<16 x i8> %op) #0 {
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; CHECK-LABEL: bitreverse_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.b, vl16
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; CHECK-NEXT: rbit z0.b, p0/m, z0.b
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%res = call <16 x i8> @llvm.bitreverse.v16i8(<16 x i8> %op)
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ret <16 x i8> %res
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}
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define void @bitreverse_v32i8(<32 x i8>* %a) #0 {
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; CHECK-LABEL: bitreverse_v32i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.b, vl16
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; CHECK-NEXT: rbit z0.b, p0/m, z0.b
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; CHECK-NEXT: rbit z1.b, p0/m, z1.b
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op = load <32 x i8>, <32 x i8>* %a
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%res = call <32 x i8> @llvm.bitreverse.v32i8(<32 x i8> %op)
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store <32 x i8> %res, <32 x i8>* %a
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ret void
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}
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define <2 x i16> @bitreverse_v2i16(<2 x i16> %op) #0 {
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; CHECK-LABEL: bitreverse_v2i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI4_0
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl2
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; CHECK-NEXT: rbit z0.s, p0/m, z0.s
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; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI4_0]
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; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %op)
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ret <2 x i16> %res
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}
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define <4 x i16> @bitreverse_v4i16(<4 x i16> %op) #0 {
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; CHECK-LABEL: bitreverse_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.h, vl4
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; CHECK-NEXT: rbit z0.h, p0/m, z0.h
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = call <4 x i16> @llvm.bitreverse.v4i16(<4 x i16> %op)
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ret <4 x i16> %res
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}
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define <8 x i16> @bitreverse_v8i16(<8 x i16> %op) #0 {
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; CHECK-LABEL: bitreverse_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.h, vl8
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; CHECK-NEXT: rbit z0.h, p0/m, z0.h
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%res = call <8 x i16> @llvm.bitreverse.v8i16(<8 x i16> %op)
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ret <8 x i16> %res
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}
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define void @bitreverse_v16i16(<16 x i16>* %a) #0 {
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; CHECK-LABEL: bitreverse_v16i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.h, vl8
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; CHECK-NEXT: rbit z0.h, p0/m, z0.h
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; CHECK-NEXT: rbit z1.h, p0/m, z1.h
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op = load <16 x i16>, <16 x i16>* %a
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%res = call <16 x i16> @llvm.bitreverse.v16i16(<16 x i16> %op)
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store <16 x i16> %res, <16 x i16>* %a
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ret void
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}
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define <2 x i32> @bitreverse_v2i32(<2 x i32> %op) #0 {
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; CHECK-LABEL: bitreverse_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl2
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; CHECK-NEXT: rbit z0.s, p0/m, z0.s
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %op)
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ret <2 x i32> %res
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}
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define <4 x i32> @bitreverse_v4i32(<4 x i32> %op) #0 {
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; CHECK-LABEL: bitreverse_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: rbit z0.s, p0/m, z0.s
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%res = call <4 x i32> @llvm.bitreverse.v4i32(<4 x i32> %op)
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ret <4 x i32> %res
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}
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define void @bitreverse_v8i32(<8 x i32>* %a) #0 {
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; CHECK-LABEL: bitreverse_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: rbit z0.s, p0/m, z0.s
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; CHECK-NEXT: rbit z1.s, p0/m, z1.s
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op = load <8 x i32>, <8 x i32>* %a
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%res = call <8 x i32> @llvm.bitreverse.v8i32(<8 x i32> %op)
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store <8 x i32> %res, <8 x i32>* %a
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ret void
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}
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define <1 x i64> @bitreverse_v1i64(<1 x i64> %op) #0 {
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; CHECK-LABEL: bitreverse_v1i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.d, vl1
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; CHECK-NEXT: rbit z0.d, p0/m, z0.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = call <1 x i64> @llvm.bitreverse.v1i64(<1 x i64> %op)
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ret <1 x i64> %res
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}
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define <2 x i64> @bitreverse_v2i64(<2 x i64> %op) #0 {
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; CHECK-LABEL: bitreverse_v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.d, vl2
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; CHECK-NEXT: rbit z0.d, p0/m, z0.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%res = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %op)
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ret <2 x i64> %res
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}
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define void @bitreverse_v4i64(<4 x i64>* %a) #0 {
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; CHECK-LABEL: bitreverse_v4i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.d, vl2
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; CHECK-NEXT: rbit z0.d, p0/m, z0.d
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; CHECK-NEXT: rbit z1.d, p0/m, z1.d
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%op = load <4 x i64>, <4 x i64>* %a
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%res = call <4 x i64> @llvm.bitreverse.v4i64(<4 x i64> %op)
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store <4 x i64> %res, <4 x i64>* %a
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ret void
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}
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;
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; REVB
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;
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define <2 x i16> @bswap_v2i16(<2 x i16> %op) #0 {
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; CHECK-LABEL: bswap_v2i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI14_0
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; CHECK-NEXT: adrp x10, .LCPI14_2
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; CHECK-NEXT: adrp x9, .LCPI14_1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl2
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; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI14_0]
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; CHECK-NEXT: adrp x8, .LCPI14_3
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; CHECK-NEXT: ldr d3, [x10, :lo12:.LCPI14_2]
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; CHECK-NEXT: movprfx z4, z0
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; CHECK-NEXT: lsr z4.s, p0/m, z4.s, z1.s
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; CHECK-NEXT: ldr d2, [x9, :lo12:.LCPI14_1]
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; CHECK-NEXT: movprfx z5, z0
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; CHECK-NEXT: lsr z5.s, p0/m, z5.s, z2.s
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; CHECK-NEXT: lslr z1.s, p0/m, z1.s, z0.s
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; CHECK-NEXT: and z0.d, z0.d, z3.d
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; CHECK-NEXT: and z3.d, z5.d, z3.d
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; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z2.s
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; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI14_3]
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; CHECK-NEXT: orr z3.d, z3.d, z4.d
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; CHECK-NEXT: orr z0.d, z1.d, z0.d
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; CHECK-NEXT: orr z0.d, z0.d, z3.d
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; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z2.s
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %op)
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ret <2 x i16> %res
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}
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define <4 x i16> @bswap_v4i16(<4 x i16> %op) #0 {
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; CHECK-LABEL: bswap_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI15_0
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.h, vl4
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; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI15_0]
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; CHECK-NEXT: movprfx z2, z0
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; CHECK-NEXT: lsr z2.h, p0/m, z2.h, z1.h
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; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z1.h
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; CHECK-NEXT: orr z0.d, z0.d, z2.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = call <4 x i16> @llvm.bswap.v4i16(<4 x i16> %op)
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ret <4 x i16> %res
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}
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define <8 x i16> @bswap_v8i16(<8 x i16> %op) #0 {
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; CHECK-LABEL: bswap_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI16_0
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.h, vl8
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_0]
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; CHECK-NEXT: movprfx z2, z0
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; CHECK-NEXT: lsr z2.h, p0/m, z2.h, z1.h
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; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z1.h
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; CHECK-NEXT: orr z0.d, z0.d, z2.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%res = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %op)
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ret <8 x i16> %res
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}
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define void @bswap_v16i16(<16 x i16>* %a) #0 {
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; CHECK-LABEL: bswap_v16i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI17_0
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; CHECK-NEXT: ptrue p0.h, vl8
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; CHECK-NEXT: ldp q2, q0, [x0]
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_0]
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; CHECK-NEXT: movprfx z3, z0
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; CHECK-NEXT: lsr z3.h, p0/m, z3.h, z1.h
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; CHECK-NEXT: movprfx z4, z2
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; CHECK-NEXT: lsr z4.h, p0/m, z4.h, z1.h
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; CHECK-NEXT: lsl z2.h, p0/m, z2.h, z1.h
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; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z1.h
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; CHECK-NEXT: orr z1.d, z2.d, z4.d
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; CHECK-NEXT: orr z0.d, z0.d, z3.d
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; CHECK-NEXT: stp q1, q0, [x0]
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; CHECK-NEXT: ret
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%op = load <16 x i16>, <16 x i16>* %a
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%res = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %op)
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store <16 x i16> %res, <16 x i16>* %a
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ret void
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}
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define <2 x i32> @bswap_v2i32(<2 x i32> %op) #0 {
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; CHECK-LABEL: bswap_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI18_0
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; CHECK-NEXT: adrp x10, .LCPI18_2
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; CHECK-NEXT: adrp x9, .LCPI18_1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl2
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; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI18_0]
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; CHECK-NEXT: movprfx z4, z0
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; CHECK-NEXT: lsr z4.s, p0/m, z4.s, z1.s
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; CHECK-NEXT: ldr d3, [x10, :lo12:.LCPI18_2]
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; CHECK-NEXT: ldr d2, [x9, :lo12:.LCPI18_1]
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; CHECK-NEXT: movprfx z5, z0
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; CHECK-NEXT: lsr z5.s, p0/m, z5.s, z2.s
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; CHECK-NEXT: and z5.d, z5.d, z3.d
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; CHECK-NEXT: and z3.d, z0.d, z3.d
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; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: movprfx z1, z3
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; CHECK-NEXT: lsl z1.s, p0/m, z1.s, z2.s
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; CHECK-NEXT: orr z2.d, z5.d, z4.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: orr z0.d, z0.d, z2.d
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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%res = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %op)
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ret <2 x i32> %res
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}
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define <4 x i32> @bswap_v4i32(<4 x i32> %op) #0 {
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; CHECK-LABEL: bswap_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI19_0
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; CHECK-NEXT: adrp x10, .LCPI19_2
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; CHECK-NEXT: adrp x9, .LCPI19_1
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI19_0]
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; CHECK-NEXT: movprfx z4, z0
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; CHECK-NEXT: lsr z4.s, p0/m, z4.s, z1.s
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; CHECK-NEXT: ldr q3, [x10, :lo12:.LCPI19_2]
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; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI19_1]
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; CHECK-NEXT: movprfx z5, z0
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; CHECK-NEXT: lsr z5.s, p0/m, z5.s, z2.s
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; CHECK-NEXT: and z5.d, z5.d, z3.d
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; CHECK-NEXT: and z3.d, z0.d, z3.d
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; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: movprfx z1, z3
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; CHECK-NEXT: lsl z1.s, p0/m, z1.s, z2.s
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; CHECK-NEXT: orr z2.d, z5.d, z4.d
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; CHECK-NEXT: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: orr z0.d, z0.d, z2.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%res = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %op)
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ret <4 x i32> %res
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}
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define void @bswap_v8i32(<8 x i32>* %a) #0 {
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; CHECK-LABEL: bswap_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI20_0
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; CHECK-NEXT: adrp x9, .LCPI20_1
|
|
; CHECK-NEXT: ldp q4, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI20_0]
|
|
; CHECK-NEXT: adrp x8, .LCPI20_2
|
|
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI20_1]
|
|
; CHECK-NEXT: movprfx z5, z1
|
|
; CHECK-NEXT: lsr z5.s, p0/m, z5.s, z0.s
|
|
; CHECK-NEXT: movprfx z6, z1
|
|
; CHECK-NEXT: lsr z6.s, p0/m, z6.s, z2.s
|
|
; CHECK-NEXT: movprfx z7, z1
|
|
; CHECK-NEXT: lsl z7.s, p0/m, z7.s, z0.s
|
|
; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI20_2]
|
|
; CHECK-NEXT: movprfx z16, z4
|
|
; CHECK-NEXT: lsr z16.s, p0/m, z16.s, z2.s
|
|
; CHECK-NEXT: and z1.d, z1.d, z3.d
|
|
; CHECK-NEXT: and z6.d, z6.d, z3.d
|
|
; CHECK-NEXT: and z16.d, z16.d, z3.d
|
|
; CHECK-NEXT: and z3.d, z4.d, z3.d
|
|
; CHECK-NEXT: orr z5.d, z6.d, z5.d
|
|
; CHECK-NEXT: movprfx z6, z4
|
|
; CHECK-NEXT: lsr z6.s, p0/m, z6.s, z0.s
|
|
; CHECK-NEXT: lslr z0.s, p0/m, z0.s, z4.s
|
|
; CHECK-NEXT: lsl z1.s, p0/m, z1.s, z2.s
|
|
; CHECK-NEXT: lslr z2.s, p0/m, z2.s, z3.s
|
|
; CHECK-NEXT: orr z3.d, z16.d, z6.d
|
|
; CHECK-NEXT: orr z0.d, z0.d, z2.d
|
|
; CHECK-NEXT: orr z1.d, z7.d, z1.d
|
|
; CHECK-NEXT: orr z0.d, z0.d, z3.d
|
|
; CHECK-NEXT: orr z1.d, z1.d, z5.d
|
|
; CHECK-NEXT: stp q0, q1, [x0]
|
|
; CHECK-NEXT: ret
|
|
%op = load <8 x i32>, <8 x i32>* %a
|
|
%res = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %op)
|
|
store <8 x i32> %res, <8 x i32>* %a
|
|
ret void
|
|
}
|
|
|
|
define <1 x i64> @bswap_v1i64(<1 x i64> %op) #0 {
|
|
; CHECK-LABEL: bswap_v1i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov w8, #56
|
|
; CHECK-NEXT: mov w9, #40
|
|
; CHECK-NEXT: mov w10, #65280
|
|
; CHECK-NEXT: mov w11, #24
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.d, vl1
|
|
; CHECK-NEXT: fmov d1, x8
|
|
; CHECK-NEXT: mov w8, #16711680
|
|
; CHECK-NEXT: fmov d2, x9
|
|
; CHECK-NEXT: mov w9, #8
|
|
; CHECK-NEXT: fmov d3, x10
|
|
; CHECK-NEXT: movprfx z7, z0
|
|
; CHECK-NEXT: lsr z7.d, p0/m, z7.d, z1.d
|
|
; CHECK-NEXT: fmov d5, x8
|
|
; CHECK-NEXT: mov w8, #-16777216
|
|
; CHECK-NEXT: movprfx z16, z0
|
|
; CHECK-NEXT: lsr z16.d, p0/m, z16.d, z2.d
|
|
; CHECK-NEXT: fmov d4, x11
|
|
; CHECK-NEXT: fmov d6, x9
|
|
; CHECK-NEXT: and z16.d, z16.d, z3.d
|
|
; CHECK-NEXT: fmov d17, x8
|
|
; CHECK-NEXT: orr z7.d, z16.d, z7.d
|
|
; CHECK-NEXT: movprfx z16, z0
|
|
; CHECK-NEXT: lsr z16.d, p0/m, z16.d, z4.d
|
|
; CHECK-NEXT: movprfx z18, z0
|
|
; CHECK-NEXT: lsr z18.d, p0/m, z18.d, z6.d
|
|
; CHECK-NEXT: and z16.d, z16.d, z5.d
|
|
; CHECK-NEXT: and z5.d, z0.d, z5.d
|
|
; CHECK-NEXT: and z18.d, z18.d, z17.d
|
|
; CHECK-NEXT: and z17.d, z0.d, z17.d
|
|
; CHECK-NEXT: lslr z6.d, p0/m, z6.d, z17.d
|
|
; CHECK-NEXT: lslr z4.d, p0/m, z4.d, z5.d
|
|
; CHECK-NEXT: and z3.d, z0.d, z3.d
|
|
; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d
|
|
; CHECK-NEXT: orr z16.d, z18.d, z16.d
|
|
; CHECK-NEXT: movprfx z1, z3
|
|
; CHECK-NEXT: lsl z1.d, p0/m, z1.d, z2.d
|
|
; CHECK-NEXT: orr z2.d, z4.d, z6.d
|
|
; CHECK-NEXT: orr z0.d, z0.d, z1.d
|
|
; CHECK-NEXT: orr z1.d, z16.d, z7.d
|
|
; CHECK-NEXT: orr z0.d, z0.d, z2.d
|
|
; CHECK-NEXT: orr z0.d, z0.d, z1.d
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = call <1 x i64> @llvm.bswap.v1i64(<1 x i64> %op)
|
|
ret <1 x i64> %res
|
|
}
|
|
|
|
define <2 x i64> @bswap_v2i64(<2 x i64> %op) #0 {
|
|
; CHECK-LABEL: bswap_v2i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: adrp x8, .LCPI22_0
|
|
; CHECK-NEXT: adrp x9, .LCPI22_1
|
|
; CHECK-NEXT: adrp x10, .LCPI22_2
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI22_0]
|
|
; CHECK-NEXT: adrp x8, .LCPI22_3
|
|
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI22_1]
|
|
; CHECK-NEXT: adrp x9, .LCPI22_4
|
|
; CHECK-NEXT: ldr q3, [x10, :lo12:.LCPI22_2]
|
|
; CHECK-NEXT: adrp x10, .LCPI22_5
|
|
; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI22_3]
|
|
; CHECK-NEXT: adrp x8, .LCPI22_6
|
|
; CHECK-NEXT: ldr q5, [x9, :lo12:.LCPI22_4]
|
|
; CHECK-NEXT: movprfx z7, z0
|
|
; CHECK-NEXT: lsr z7.d, p0/m, z7.d, z1.d
|
|
; CHECK-NEXT: movprfx z16, z0
|
|
; CHECK-NEXT: lsr z16.d, p0/m, z16.d, z2.d
|
|
; CHECK-NEXT: ldr q6, [x10, :lo12:.LCPI22_5]
|
|
; CHECK-NEXT: ldr q17, [x8, :lo12:.LCPI22_6]
|
|
; CHECK-NEXT: and z16.d, z16.d, z3.d
|
|
; CHECK-NEXT: orr z7.d, z16.d, z7.d
|
|
; CHECK-NEXT: movprfx z16, z0
|
|
; CHECK-NEXT: lsr z16.d, p0/m, z16.d, z4.d
|
|
; CHECK-NEXT: movprfx z18, z0
|
|
; CHECK-NEXT: lsr z18.d, p0/m, z18.d, z6.d
|
|
; CHECK-NEXT: and z16.d, z16.d, z5.d
|
|
; CHECK-NEXT: and z18.d, z18.d, z17.d
|
|
; CHECK-NEXT: and z17.d, z0.d, z17.d
|
|
; CHECK-NEXT: and z5.d, z0.d, z5.d
|
|
; CHECK-NEXT: lslr z6.d, p0/m, z6.d, z17.d
|
|
; CHECK-NEXT: lslr z4.d, p0/m, z4.d, z5.d
|
|
; CHECK-NEXT: and z3.d, z0.d, z3.d
|
|
; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d
|
|
; CHECK-NEXT: orr z16.d, z18.d, z16.d
|
|
; CHECK-NEXT: movprfx z1, z3
|
|
; CHECK-NEXT: lsl z1.d, p0/m, z1.d, z2.d
|
|
; CHECK-NEXT: orr z2.d, z4.d, z6.d
|
|
; CHECK-NEXT: orr z0.d, z0.d, z1.d
|
|
; CHECK-NEXT: orr z1.d, z16.d, z7.d
|
|
; CHECK-NEXT: orr z0.d, z0.d, z2.d
|
|
; CHECK-NEXT: orr z0.d, z0.d, z1.d
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%res = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %op)
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
define void @bswap_v4i64(<4 x i64>* %a) #0 {
|
|
; CHECK-LABEL: bswap_v4i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: adrp x8, .LCPI23_0
|
|
; CHECK-NEXT: adrp x9, .LCPI23_1
|
|
; CHECK-NEXT: adrp x10, .LCPI23_3
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: ldp q1, q2, [x0]
|
|
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI23_0]
|
|
; CHECK-NEXT: adrp x8, .LCPI23_2
|
|
; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI23_1]
|
|
; CHECK-NEXT: adrp x9, .LCPI23_4
|
|
; CHECK-NEXT: ldr q5, [x10, :lo12:.LCPI23_3]
|
|
; CHECK-NEXT: adrp x10, .LCPI23_6
|
|
; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI23_2]
|
|
; CHECK-NEXT: adrp x8, .LCPI23_5
|
|
; CHECK-NEXT: ldr q6, [x9, :lo12:.LCPI23_4]
|
|
; CHECK-NEXT: movprfx z16, z2
|
|
; CHECK-NEXT: lsr z16.d, p0/m, z16.d, z3.d
|
|
; CHECK-NEXT: ldr q17, [x10, :lo12:.LCPI23_6]
|
|
; CHECK-NEXT: movprfx z18, z2
|
|
; CHECK-NEXT: lsr z18.d, p0/m, z18.d, z0.d
|
|
; CHECK-NEXT: ldr q7, [x8, :lo12:.LCPI23_5]
|
|
; CHECK-NEXT: movprfx z19, z2
|
|
; CHECK-NEXT: lsr z19.d, p0/m, z19.d, z5.d
|
|
; CHECK-NEXT: movprfx z20, z2
|
|
; CHECK-NEXT: lsr z20.d, p0/m, z20.d, z7.d
|
|
; CHECK-NEXT: and z16.d, z16.d, z4.d
|
|
; CHECK-NEXT: and z19.d, z19.d, z6.d
|
|
; CHECK-NEXT: and z20.d, z20.d, z17.d
|
|
; CHECK-NEXT: orr z16.d, z16.d, z18.d
|
|
; CHECK-NEXT: orr z18.d, z20.d, z19.d
|
|
; CHECK-NEXT: and z19.d, z2.d, z17.d
|
|
; CHECK-NEXT: and z20.d, z2.d, z6.d
|
|
; CHECK-NEXT: lsl z19.d, p0/m, z19.d, z7.d
|
|
; CHECK-NEXT: lsl z20.d, p0/m, z20.d, z5.d
|
|
; CHECK-NEXT: orr z16.d, z18.d, z16.d
|
|
; CHECK-NEXT: orr z18.d, z20.d, z19.d
|
|
; CHECK-NEXT: movprfx z19, z2
|
|
; CHECK-NEXT: lsl z19.d, p0/m, z19.d, z0.d
|
|
; CHECK-NEXT: and z2.d, z2.d, z4.d
|
|
; CHECK-NEXT: movprfx z20, z1
|
|
; CHECK-NEXT: lsr z20.d, p0/m, z20.d, z3.d
|
|
; CHECK-NEXT: lsl z2.d, p0/m, z2.d, z3.d
|
|
; CHECK-NEXT: movprfx z21, z1
|
|
; CHECK-NEXT: lsr z21.d, p0/m, z21.d, z0.d
|
|
; CHECK-NEXT: and z20.d, z20.d, z4.d
|
|
; CHECK-NEXT: orr z2.d, z19.d, z2.d
|
|
; CHECK-NEXT: orr z19.d, z20.d, z21.d
|
|
; CHECK-NEXT: movprfx z20, z1
|
|
; CHECK-NEXT: lsr z20.d, p0/m, z20.d, z5.d
|
|
; CHECK-NEXT: movprfx z21, z1
|
|
; CHECK-NEXT: lsr z21.d, p0/m, z21.d, z7.d
|
|
; CHECK-NEXT: and z20.d, z20.d, z6.d
|
|
; CHECK-NEXT: and z21.d, z21.d, z17.d
|
|
; CHECK-NEXT: and z17.d, z1.d, z17.d
|
|
; CHECK-NEXT: and z6.d, z1.d, z6.d
|
|
; CHECK-NEXT: lslr z7.d, p0/m, z7.d, z17.d
|
|
; CHECK-NEXT: lslr z5.d, p0/m, z5.d, z6.d
|
|
; CHECK-NEXT: lslr z0.d, p0/m, z0.d, z1.d
|
|
; CHECK-NEXT: orr z20.d, z21.d, z20.d
|
|
; CHECK-NEXT: and z4.d, z1.d, z4.d
|
|
; CHECK-NEXT: movprfx z1, z4
|
|
; CHECK-NEXT: lsl z1.d, p0/m, z1.d, z3.d
|
|
; CHECK-NEXT: orr z3.d, z5.d, z7.d
|
|
; CHECK-NEXT: orr z0.d, z0.d, z1.d
|
|
; CHECK-NEXT: orr z1.d, z20.d, z19.d
|
|
; CHECK-NEXT: orr z0.d, z0.d, z3.d
|
|
; CHECK-NEXT: orr z2.d, z2.d, z18.d
|
|
; CHECK-NEXT: orr z0.d, z0.d, z1.d
|
|
; CHECK-NEXT: orr z1.d, z2.d, z16.d
|
|
; CHECK-NEXT: stp q0, q1, [x0]
|
|
; CHECK-NEXT: ret
|
|
%op = load <4 x i64>, <4 x i64>* %a
|
|
%res = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %op)
|
|
store <4 x i64> %res, <4 x i64>* %a
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { "target-features"="+sve" }
|
|
|
|
declare <4 x i8> @llvm.bitreverse.v4i8(<4 x i8>)
|
|
declare <8 x i8> @llvm.bitreverse.v8i8(<8 x i8>)
|
|
declare <16 x i8> @llvm.bitreverse.v16i8(<16 x i8>)
|
|
declare <32 x i8> @llvm.bitreverse.v32i8(<32 x i8>)
|
|
declare <2 x i16> @llvm.bitreverse.v2i16(<2 x i16>)
|
|
declare <4 x i16> @llvm.bitreverse.v4i16(<4 x i16>)
|
|
declare <8 x i16> @llvm.bitreverse.v8i16(<8 x i16>)
|
|
declare <16 x i16> @llvm.bitreverse.v16i16(<16 x i16>)
|
|
declare <2 x i32> @llvm.bitreverse.v2i32(<2 x i32>)
|
|
declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>)
|
|
declare <8 x i32> @llvm.bitreverse.v8i32(<8 x i32>)
|
|
declare <1 x i64> @llvm.bitreverse.v1i64(<1 x i64>)
|
|
declare <2 x i64> @llvm.bitreverse.v2i64(<2 x i64>)
|
|
declare <4 x i64> @llvm.bitreverse.v4i64(<4 x i64>)
|
|
|
|
declare <2 x i16> @llvm.bswap.v2i16(<2 x i16>)
|
|
declare <4 x i16> @llvm.bswap.v4i16(<4 x i16>)
|
|
declare <8 x i16> @llvm.bswap.v8i16(<8 x i16>)
|
|
declare <16 x i16> @llvm.bswap.v16i16(<16 x i16>)
|
|
declare <2 x i32> @llvm.bswap.v2i32(<2 x i32>)
|
|
declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)
|
|
declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>)
|
|
declare <1 x i64> @llvm.bswap.v1i64(<1 x i64>)
|
|
declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>)
|
|
declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>)
|