562 lines
16 KiB
LLVM
562 lines
16 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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;
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; ANDV
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;
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define i8 @andv_v4i8(<4 x i8> %a) #0 {
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; CHECK-LABEL: andv_v4i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.h, vl4
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; CHECK-NEXT: andv h0, p0, z0.h
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> %a)
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ret i8 %res
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}
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define i8 @andv_v8i8(<8 x i8> %a) #0 {
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; CHECK-LABEL: andv_v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.b, vl8
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; CHECK-NEXT: andv b0, p0, z0.b
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> %a)
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ret i8 %res
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}
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define i8 @andv_v16i8(<16 x i8> %a) #0 {
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; CHECK-LABEL: andv_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.b, vl16
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; CHECK-NEXT: andv b0, p0, z0.b
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i8 @llvm.vector.reduce.and.v16i8(<16 x i8> %a)
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ret i8 %res
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}
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define i8 @andv_v32i8(ptr %a) #0 {
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; CHECK-LABEL: andv_v32i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q1, q0, [x0]
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; CHECK-NEXT: ptrue p0.b, vl16
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; CHECK-NEXT: and z0.d, z1.d, z0.d
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; CHECK-NEXT: andv b0, p0, z0.b
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%op = load <32 x i8>, ptr %a
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%res = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> %op)
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ret i8 %res
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}
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define i16 @andv_v2i16(<2 x i16> %a) #0 {
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; CHECK-LABEL: andv_v2i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl2
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; CHECK-NEXT: andv s0, p0, z0.s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i16 @llvm.vector.reduce.and.v2i16(<2 x i16> %a)
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ret i16 %res
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}
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define i16 @andv_v4i16(<4 x i16> %a) #0 {
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; CHECK-LABEL: andv_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.h, vl4
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; CHECK-NEXT: andv h0, p0, z0.h
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> %a)
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ret i16 %res
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}
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define i16 @andv_v8i16(<8 x i16> %a) #0 {
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; CHECK-LABEL: andv_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.h, vl8
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; CHECK-NEXT: andv h0, p0, z0.h
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> %a)
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ret i16 %res
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}
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define i16 @andv_v16i16(ptr %a) #0 {
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; CHECK-LABEL: andv_v16i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q1, q0, [x0]
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; CHECK-NEXT: ptrue p0.h, vl8
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; CHECK-NEXT: and z0.d, z1.d, z0.d
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; CHECK-NEXT: andv h0, p0, z0.h
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%op = load <16 x i16>, ptr %a
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%res = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %op)
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ret i16 %res
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}
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define i32 @andv_v2i32(<2 x i32> %a) #0 {
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; CHECK-LABEL: andv_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl2
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; CHECK-NEXT: andv s0, p0, z0.s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> %a)
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ret i32 %res
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}
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define i32 @andv_v4i32(<4 x i32> %a) #0 {
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; CHECK-LABEL: andv_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: andv s0, p0, z0.s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %a)
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ret i32 %res
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}
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define i32 @andv_v8i32(ptr %a) #0 {
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; CHECK-LABEL: andv_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q1, q0, [x0]
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: and z0.d, z1.d, z0.d
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; CHECK-NEXT: andv s0, p0, z0.s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%op = load <8 x i32>, ptr %a
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%res = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %op)
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ret i32 %res
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}
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define i64 @andv_v2i64(<2 x i64> %a) #0 {
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; CHECK-LABEL: andv_v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.d, vl2
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; CHECK-NEXT: andv d0, p0, z0.d
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: ret
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%res = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> %a)
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ret i64 %res
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}
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define i64 @andv_v4i64(ptr %a) #0 {
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; CHECK-LABEL: andv_v4i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q1, q0, [x0]
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; CHECK-NEXT: ptrue p0.d, vl2
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; CHECK-NEXT: and z0.d, z1.d, z0.d
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; CHECK-NEXT: andv d0, p0, z0.d
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: ret
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%op = load <4 x i64>, ptr %a
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%res = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %op)
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ret i64 %res
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}
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;
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; EORV
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;
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define i8 @eorv_v4i8(<4 x i8> %a) #0 {
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; CHECK-LABEL: eorv_v4i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.h, vl4
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; CHECK-NEXT: eorv h0, p0, z0.h
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i8 @llvm.vector.reduce.xor.v4i8(<4 x i8> %a)
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ret i8 %res
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}
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define i8 @eorv_v8i8(<8 x i8> %a) #0 {
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; CHECK-LABEL: eorv_v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.b, vl8
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; CHECK-NEXT: eorv b0, p0, z0.b
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i8 @llvm.vector.reduce.xor.v8i8(<8 x i8> %a)
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ret i8 %res
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}
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define i8 @eorv_v16i8(<16 x i8> %a) #0 {
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; CHECK-LABEL: eorv_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.b, vl16
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; CHECK-NEXT: eorv b0, p0, z0.b
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i8 @llvm.vector.reduce.xor.v16i8(<16 x i8> %a)
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ret i8 %res
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}
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define i8 @eorv_v32i8(ptr %a) #0 {
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; CHECK-LABEL: eorv_v32i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q1, q0, [x0]
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; CHECK-NEXT: ptrue p0.b, vl16
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; CHECK-NEXT: eor z0.d, z1.d, z0.d
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; CHECK-NEXT: eorv b0, p0, z0.b
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%op = load <32 x i8>, ptr %a
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%res = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> %op)
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ret i8 %res
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}
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define i16 @eorv_v2i16(<2 x i16> %a) #0 {
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; CHECK-LABEL: eorv_v2i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl2
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; CHECK-NEXT: eorv s0, p0, z0.s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i16 @llvm.vector.reduce.xor.v2i16(<2 x i16> %a)
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ret i16 %res
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}
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define i16 @eorv_v4i16(<4 x i16> %a) #0 {
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; CHECK-LABEL: eorv_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.h, vl4
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; CHECK-NEXT: eorv h0, p0, z0.h
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i16 @llvm.vector.reduce.xor.v4i16(<4 x i16> %a)
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ret i16 %res
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}
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define i16 @eorv_v8i16(<8 x i16> %a) #0 {
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; CHECK-LABEL: eorv_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.h, vl8
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; CHECK-NEXT: eorv h0, p0, z0.h
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i16 @llvm.vector.reduce.xor.v8i16(<8 x i16> %a)
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ret i16 %res
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}
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define i16 @eorv_v16i16(ptr %a) #0 {
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; CHECK-LABEL: eorv_v16i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q1, q0, [x0]
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; CHECK-NEXT: ptrue p0.h, vl8
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; CHECK-NEXT: eor z0.d, z1.d, z0.d
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; CHECK-NEXT: eorv h0, p0, z0.h
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%op = load <16 x i16>, ptr %a
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%res = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %op)
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ret i16 %res
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}
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define i32 @eorv_v2i32(<2 x i32> %a) #0 {
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; CHECK-LABEL: eorv_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl2
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; CHECK-NEXT: eorv s0, p0, z0.s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> %a)
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ret i32 %res
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}
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define i32 @eorv_v4i32(<4 x i32> %a) #0 {
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; CHECK-LABEL: eorv_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: eorv s0, p0, z0.s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %a)
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ret i32 %res
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}
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define i32 @eorv_v8i32(ptr %a) #0 {
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; CHECK-LABEL: eorv_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q1, q0, [x0]
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: eor z0.d, z1.d, z0.d
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; CHECK-NEXT: eorv s0, p0, z0.s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%op = load <8 x i32>, ptr %a
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%res = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %op)
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ret i32 %res
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}
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define i64 @eorv_v2i64(<2 x i64> %a) #0 {
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; CHECK-LABEL: eorv_v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.d, vl2
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; CHECK-NEXT: eorv d0, p0, z0.d
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: ret
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%res = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> %a)
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ret i64 %res
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}
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define i64 @eorv_v4i64(ptr %a) #0 {
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; CHECK-LABEL: eorv_v4i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q1, q0, [x0]
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; CHECK-NEXT: ptrue p0.d, vl2
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; CHECK-NEXT: eor z0.d, z1.d, z0.d
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; CHECK-NEXT: eorv d0, p0, z0.d
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: ret
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%op = load <4 x i64>, ptr %a
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%res = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %op)
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ret i64 %res
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}
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;
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; ORV
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;
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define i8 @orv_v4i8(<4 x i8> %a) #0 {
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; CHECK-LABEL: orv_v4i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.h, vl4
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; CHECK-NEXT: orv h0, p0, z0.h
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> %a)
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ret i8 %res
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}
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define i8 @orv_v8i8(<8 x i8> %a) #0 {
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; CHECK-LABEL: orv_v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.b, vl8
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; CHECK-NEXT: orv b0, p0, z0.b
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> %a)
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ret i8 %res
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}
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define i8 @orv_v16i8(<16 x i8> %a) #0 {
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; CHECK-LABEL: orv_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: ptrue p0.b, vl16
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; CHECK-NEXT: orv b0, p0, z0.b
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> %a)
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ret i8 %res
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}
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define i8 @orv_v32i8(ptr %a) #0 {
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; CHECK-LABEL: orv_v32i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q1, q0, [x0]
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; CHECK-NEXT: ptrue p0.b, vl16
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; CHECK-NEXT: orr z0.d, z1.d, z0.d
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; CHECK-NEXT: orv b0, p0, z0.b
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%op = load <32 x i8>, ptr %a
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%res = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> %op)
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ret i8 %res
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}
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define i16 @orv_v2i16(<2 x i16> %a) #0 {
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; CHECK-LABEL: orv_v2i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl2
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; CHECK-NEXT: orv s0, p0, z0.s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%res = call i16 @llvm.vector.reduce.or.v2i16(<2 x i16> %a)
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ret i16 %res
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}
|
|
|
|
define i16 @orv_v4i16(<4 x i16> %a) #0 {
|
|
; CHECK-LABEL: orv_v4i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.h, vl4
|
|
; CHECK-NEXT: orv h0, p0, z0.h
|
|
; CHECK-NEXT: fmov w0, s0
|
|
; CHECK-NEXT: ret
|
|
%res = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> %a)
|
|
ret i16 %res
|
|
}
|
|
|
|
define i16 @orv_v8i16(<8 x i16> %a) #0 {
|
|
; CHECK-LABEL: orv_v8i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: ptrue p0.h, vl8
|
|
; CHECK-NEXT: orv h0, p0, z0.h
|
|
; CHECK-NEXT: fmov w0, s0
|
|
; CHECK-NEXT: ret
|
|
%res = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> %a)
|
|
ret i16 %res
|
|
}
|
|
|
|
define i16 @orv_v16i16(ptr %a) #0 {
|
|
; CHECK-LABEL: orv_v16i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q1, q0, [x0]
|
|
; CHECK-NEXT: ptrue p0.h, vl8
|
|
; CHECK-NEXT: orr z0.d, z1.d, z0.d
|
|
; CHECK-NEXT: orv h0, p0, z0.h
|
|
; CHECK-NEXT: fmov w0, s0
|
|
; CHECK-NEXT: ret
|
|
%op = load <16 x i16>, ptr %a
|
|
%res = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %op)
|
|
ret i16 %res
|
|
}
|
|
|
|
define i32 @orv_v2i32(<2 x i32> %a) #0 {
|
|
; CHECK-LABEL: orv_v2i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.s, vl2
|
|
; CHECK-NEXT: orv s0, p0, z0.s
|
|
; CHECK-NEXT: fmov w0, s0
|
|
; CHECK-NEXT: ret
|
|
%res = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> %a)
|
|
ret i32 %res
|
|
}
|
|
|
|
define i32 @orv_v4i32(<4 x i32> %a) #0 {
|
|
; CHECK-LABEL: orv_v4i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: orv s0, p0, z0.s
|
|
; CHECK-NEXT: fmov w0, s0
|
|
; CHECK-NEXT: ret
|
|
%res = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %a)
|
|
ret i32 %res
|
|
}
|
|
|
|
define i32 @orv_v8i32(ptr %a) #0 {
|
|
; CHECK-LABEL: orv_v8i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q1, q0, [x0]
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: orr z0.d, z1.d, z0.d
|
|
; CHECK-NEXT: orv s0, p0, z0.s
|
|
; CHECK-NEXT: fmov w0, s0
|
|
; CHECK-NEXT: ret
|
|
%op = load <8 x i32>, ptr %a
|
|
%res = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %op)
|
|
ret i32 %res
|
|
}
|
|
|
|
define i64 @orv_v2i64(<2 x i64> %a) #0 {
|
|
; CHECK-LABEL: orv_v2i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: orv d0, p0, z0.d
|
|
; CHECK-NEXT: fmov x0, d0
|
|
; CHECK-NEXT: ret
|
|
%res = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %a)
|
|
ret i64 %res
|
|
}
|
|
|
|
define i64 @orv_v4i64(ptr %a) #0 {
|
|
; CHECK-LABEL: orv_v4i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q1, q0, [x0]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: orr z0.d, z1.d, z0.d
|
|
; CHECK-NEXT: orv d0, p0, z0.d
|
|
; CHECK-NEXT: fmov x0, d0
|
|
; CHECK-NEXT: ret
|
|
%op = load <4 x i64>, ptr %a
|
|
%res = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %op)
|
|
ret i64 %res
|
|
}
|
|
|
|
attributes #0 = { "target-features"="+sve" }
|
|
|
|
declare i8 @llvm.vector.reduce.and.v4i8(<4 x i8>)
|
|
declare i8 @llvm.vector.reduce.and.v8i8(<8 x i8>)
|
|
declare i8 @llvm.vector.reduce.and.v16i8(<16 x i8>)
|
|
declare i8 @llvm.vector.reduce.and.v32i8(<32 x i8>)
|
|
|
|
declare i16 @llvm.vector.reduce.and.v2i16(<2 x i16>)
|
|
declare i16 @llvm.vector.reduce.and.v4i16(<4 x i16>)
|
|
declare i16 @llvm.vector.reduce.and.v8i16(<8 x i16>)
|
|
declare i16 @llvm.vector.reduce.and.v16i16(<16 x i16>)
|
|
|
|
declare i32 @llvm.vector.reduce.and.v2i32(<2 x i32>)
|
|
declare i32 @llvm.vector.reduce.and.v4i32(<4 x i32>)
|
|
declare i32 @llvm.vector.reduce.and.v8i32(<8 x i32>)
|
|
|
|
declare i64 @llvm.vector.reduce.and.v2i64(<2 x i64>)
|
|
declare i64 @llvm.vector.reduce.and.v4i64(<4 x i64>)
|
|
|
|
declare i8 @llvm.vector.reduce.or.v4i8(<4 x i8>)
|
|
declare i8 @llvm.vector.reduce.or.v8i8(<8 x i8>)
|
|
declare i8 @llvm.vector.reduce.or.v16i8(<16 x i8>)
|
|
declare i8 @llvm.vector.reduce.or.v32i8(<32 x i8>)
|
|
|
|
declare i16 @llvm.vector.reduce.or.v2i16(<2 x i16>)
|
|
declare i16 @llvm.vector.reduce.or.v4i16(<4 x i16>)
|
|
declare i16 @llvm.vector.reduce.or.v8i16(<8 x i16>)
|
|
declare i16 @llvm.vector.reduce.or.v16i16(<16 x i16>)
|
|
|
|
declare i32 @llvm.vector.reduce.or.v2i32(<2 x i32>)
|
|
declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32>)
|
|
declare i32 @llvm.vector.reduce.or.v8i32(<8 x i32>)
|
|
|
|
declare i64 @llvm.vector.reduce.or.v2i64(<2 x i64>)
|
|
declare i64 @llvm.vector.reduce.or.v4i64(<4 x i64>)
|
|
|
|
declare i8 @llvm.vector.reduce.xor.v4i8(<4 x i8>)
|
|
declare i8 @llvm.vector.reduce.xor.v8i8(<8 x i8>)
|
|
declare i8 @llvm.vector.reduce.xor.v16i8(<16 x i8>)
|
|
declare i8 @llvm.vector.reduce.xor.v32i8(<32 x i8>)
|
|
|
|
declare i16 @llvm.vector.reduce.xor.v2i16(<2 x i16>)
|
|
declare i16 @llvm.vector.reduce.xor.v4i16(<4 x i16>)
|
|
declare i16 @llvm.vector.reduce.xor.v8i16(<8 x i16>)
|
|
declare i16 @llvm.vector.reduce.xor.v16i16(<16 x i16>)
|
|
|
|
declare i32 @llvm.vector.reduce.xor.v2i32(<2 x i32>)
|
|
declare i32 @llvm.vector.reduce.xor.v4i32(<4 x i32>)
|
|
declare i32 @llvm.vector.reduce.xor.v8i32(<8 x i32>)
|
|
|
|
declare i64 @llvm.vector.reduce.xor.v2i64(<2 x i64>)
|
|
declare i64 @llvm.vector.reduce.xor.v4i64(<4 x i64>)
|