llvm-project/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-loads.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s

target triple = "aarch64-unknown-linux-gnu"

define <4 x i8> @load_v4i8(<4 x i8>* %a) #0 {
; CHECK-LABEL: load_v4i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr s0, [x0]
; CHECK-NEXT:    uunpklo z0.h, z0.b
; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT:    ret
  %load = load <4 x i8>, <4 x i8>* %a
  ret <4 x i8> %load
}

define <8 x i8> @load_v8i8(<8 x i8>* %a) #0 {
; CHECK-LABEL: load_v8i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ret
  %load = load <8 x i8>, <8 x i8>* %a
  ret <8 x i8> %load
}

define <16 x i8> @load_v16i8(<16 x i8>* %a) #0 {
; CHECK-LABEL: load_v16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    ret
  %load = load <16 x i8>, <16 x i8>* %a
  ret <16 x i8> %load
}

define <32 x i8> @load_v32i8(<32 x i8>* %a) #0 {
; CHECK-LABEL: load_v32i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldp q0, q1, [x0]
; CHECK-NEXT:    ret
  %load = load <32 x i8>, <32 x i8>* %a
  ret <32 x i8> %load
}

define <2 x i16> @load_v2i16(<2 x i16>* %a) #0 {
; CHECK-LABEL: load_v2i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    sub sp, sp, #16
; CHECK-NEXT:    .cfi_def_cfa_offset 16
; CHECK-NEXT:    ldrh w8, [x0, #2]
; CHECK-NEXT:    str w8, [sp, #12]
; CHECK-NEXT:    ldrh w8, [x0]
; CHECK-NEXT:    str w8, [sp, #8]
; CHECK-NEXT:    ldr d0, [sp, #8]
; CHECK-NEXT:    add sp, sp, #16
; CHECK-NEXT:    ret
  %load = load <2 x i16>, <2 x i16>* %a
  ret <2 x i16> %load
}

define <2 x half> @load_v2f16(<2 x half>* %a) #0 {
; CHECK-LABEL: load_v2f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr s0, [x0]
; CHECK-NEXT:    ret
  %load = load <2 x half>, <2 x half>* %a
  ret <2 x half> %load
}

define <4 x i16> @load_v4i16(<4 x i16>* %a) #0 {
; CHECK-LABEL: load_v4i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ret
  %load = load <4 x i16>, <4 x i16>* %a
  ret <4 x i16> %load
}

define <4 x half> @load_v4f16(<4 x half>* %a) #0 {
; CHECK-LABEL: load_v4f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ret
  %load = load <4 x half>, <4 x half>* %a
  ret <4 x half> %load
}

define <8 x i16> @load_v8i16(<8 x i16>* %a) #0 {
; CHECK-LABEL: load_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    ret
  %load = load <8 x i16>, <8 x i16>* %a
  ret <8 x i16> %load
}

define <8 x half> @load_v8f16(<8 x half>* %a) #0 {
; CHECK-LABEL: load_v8f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    ret
  %load = load <8 x half>, <8 x half>* %a
  ret <8 x half> %load
}

define <16 x i16> @load_v16i16(<16 x i16>* %a) #0 {
; CHECK-LABEL: load_v16i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldp q0, q1, [x0]
; CHECK-NEXT:    ret
  %load = load <16 x i16>, <16 x i16>* %a
  ret <16 x i16> %load
}

define <16 x half> @load_v16f16(<16 x half>* %a) #0 {
; CHECK-LABEL: load_v16f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldp q0, q1, [x0]
; CHECK-NEXT:    ret
  %load = load <16 x half>, <16 x half>* %a
  ret <16 x half> %load
}

define <2 x i32> @load_v2i32(<2 x i32>* %a) #0 {
; CHECK-LABEL: load_v2i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ret
  %load = load <2 x i32>, <2 x i32>* %a
  ret <2 x i32> %load
}

define <2 x float> @load_v2f32(<2 x float>* %a) #0 {
; CHECK-LABEL: load_v2f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ret
  %load = load <2 x float>, <2 x float>* %a
  ret <2 x float> %load
}

define <4 x i32> @load_v4i32(<4 x i32>* %a) #0 {
; CHECK-LABEL: load_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    ret
  %load = load <4 x i32>, <4 x i32>* %a
  ret <4 x i32> %load
}

define <4 x float> @load_v4f32(<4 x float>* %a) #0 {
; CHECK-LABEL: load_v4f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    ret
  %load = load <4 x float>, <4 x float>* %a
  ret <4 x float> %load
}

define <8 x i32> @load_v8i32(<8 x i32>* %a) #0 {
; CHECK-LABEL: load_v8i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldp q0, q1, [x0]
; CHECK-NEXT:    ret
  %load = load <8 x i32>, <8 x i32>* %a
  ret <8 x i32> %load
}

define <8 x float> @load_v8f32(<8 x float>* %a) #0 {
; CHECK-LABEL: load_v8f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldp q0, q1, [x0]
; CHECK-NEXT:    ret
  %load = load <8 x float>, <8 x float>* %a
  ret <8 x float> %load
}

define <1 x i64> @load_v1i64(<1 x i64>* %a) #0 {
; CHECK-LABEL: load_v1i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ret
  %load = load <1 x i64>, <1 x i64>* %a
  ret <1 x i64> %load
}

define <1 x double> @load_v1f64(<1 x double>* %a) #0 {
; CHECK-LABEL: load_v1f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ret
  %load = load <1 x double>, <1 x double>* %a
  ret <1 x double> %load
}

define <2 x i64> @load_v2i64(<2 x i64>* %a) #0 {
; CHECK-LABEL: load_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    ret
  %load = load <2 x i64>, <2 x i64>* %a
  ret <2 x i64> %load
}

define <2 x double> @load_v2f64(<2 x double>* %a) #0 {
; CHECK-LABEL: load_v2f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0]
; CHECK-NEXT:    ret
  %load = load <2 x double>, <2 x double>* %a
  ret <2 x double> %load
}

define <4 x i64> @load_v4i64(<4 x i64>* %a) #0 {
; CHECK-LABEL: load_v4i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldp q0, q1, [x0]
; CHECK-NEXT:    ret
  %load = load <4 x i64>, <4 x i64>* %a
  ret <4 x i64> %load
}

define <4 x double> @load_v4f64(<4 x double>* %a) #0 {
; CHECK-LABEL: load_v4f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldp q0, q1, [x0]
; CHECK-NEXT:    ret
  %load = load <4 x double>, <4 x double>* %a
  ret <4 x double> %load
}


attributes #0 = { "target-features"="+sve" }