THU-DSP-LAB
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
2
0
Fork 1
Code Issues Packages Projects Releases Wiki Activity
llvm-project/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-le...

267 lines
9.8 KiB
LLVM
Raw Permalink Blame History

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
target triple = "aarch64-unknown-linux-gnu"
define <2 x half> @select_v2f16(<2 x half> %op1, <2 x half> %op2, <2 x i1> %mask) #0 {
; CHECK-LABEL: select_v2f16:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2
; CHECK-NEXT: mov z3.s, z2.s[1]
; CHECK-NEXT: adrp x8, .LCPI0_0
; CHECK-NEXT: fmov w9, s2
; CHECK-NEXT: fmov w10, s3
; CHECK-NEXT: ptrue p0.h, vl4
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI0_0]
; CHECK-NEXT: adrp x8, .LCPI0_1
; CHECK-NEXT: strh w9, [sp, #8]
; CHECK-NEXT: strh w10, [sp, #10]
; CHECK-NEXT: ldr d3, [sp, #8]
; CHECK-NEXT: ldr d4, [x8, :lo12:.LCPI0_1]
; CHECK-NEXT: lsl z3.h, p0/m, z3.h, z2.h
; CHECK-NEXT: asrr z2.h, p0/m, z2.h, z3.h
; CHECK-NEXT: eor z3.d, z2.d, z4.d
; CHECK-NEXT: and z0.d, z0.d, z2.d
; CHECK-NEXT: and z1.d, z1.d, z3.d
; CHECK-NEXT: orr z0.d, z0.d, z1.d
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: add sp, sp, #16
; CHECK-NEXT: ret
%sel = select <2 x i1> %mask, <2 x half> %op1, <2 x half> %op2
ret <2 x half> %sel
}
define <4 x half> @select_v4f16(<4 x half> %op1, <4 x half> %op2, <4 x i1> %mask) #0 {
; CHECK-LABEL: select_v4f16:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI1_0
; CHECK-NEXT: adrp x9, .LCPI1_1
; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2
; CHECK-NEXT: ptrue p0.h, vl4
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI1_0]
; CHECK-NEXT: ldr d4, [x9, :lo12:.LCPI1_1]
; CHECK-NEXT: lsl z2.h, p0/m, z2.h, z3.h
; CHECK-NEXT: asr z2.h, p0/m, z2.h, z3.h
; CHECK-NEXT: eor z3.d, z2.d, z4.d
; CHECK-NEXT: and z0.d, z0.d, z2.d
; CHECK-NEXT: and z1.d, z1.d, z3.d
; CHECK-NEXT: orr z0.d, z0.d, z1.d
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
%sel = select <4 x i1> %mask, <4 x half> %op1, <4 x half> %op2
ret <4 x half> %sel
}
define <8 x half> @select_v8f16(<8 x half> %op1, <8 x half> %op2, <8 x i1> %mask) #0 {
; CHECK-LABEL: select_v8f16:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI2_0
; CHECK-NEXT: adrp x9, .LCPI2_1
; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2
; CHECK-NEXT: ptrue p0.h, vl8
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: uunpklo z2.h, z2.b
; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI2_0]
; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI2_1]
; CHECK-NEXT: lsl z2.h, p0/m, z2.h, z3.h
; CHECK-NEXT: asr z2.h, p0/m, z2.h, z3.h
; CHECK-NEXT: eor z3.d, z2.d, z4.d
; CHECK-NEXT: and z0.d, z0.d, z2.d
; CHECK-NEXT: and z1.d, z1.d, z3.d
; CHECK-NEXT: orr z0.d, z0.d, z1.d
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
%sel = select <8 x i1> %mask, <8 x half> %op1, <8 x half> %op2
ret <8 x half> %sel
}
define void @select_v16f16(ptr %a, ptr %b) #0 {
; CHECK-LABEL: select_v16f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x1]
; CHECK-NEXT: adrp x8, .LCPI3_0
; CHECK-NEXT: ptrue p0.h, vl8
; CHECK-NEXT: ldp q3, q2, [x0]
; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI3_0]
; CHECK-NEXT: fcmeq p1.h, p0/z, z2.h, z1.h
; CHECK-NEXT: fcmeq p0.h, p0/z, z3.h, z0.h
; CHECK-NEXT: mov z5.h, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: mov z6.h, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: and z2.d, z2.d, z5.d
; CHECK-NEXT: eor z5.d, z5.d, z4.d
; CHECK-NEXT: eor z4.d, z6.d, z4.d
; CHECK-NEXT: and z3.d, z3.d, z6.d
; CHECK-NEXT: and z0.d, z0.d, z4.d
; CHECK-NEXT: and z1.d, z1.d, z5.d
; CHECK-NEXT: orr z0.d, z3.d, z0.d
; CHECK-NEXT: orr z1.d, z2.d, z1.d
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
%op1 = load <16 x half>, ptr %a
%op2 = load <16 x half>, ptr %b
%mask = fcmp oeq <16 x half> %op1, %op2
%sel = select <16 x i1> %mask, <16 x half> %op1, <16 x half> %op2
store <16 x half> %sel, ptr %a
ret void
}
define <2 x float> @select_v2f32(<2 x float> %op1, <2 x float> %op2, <2 x i1> %mask) #0 {
; CHECK-LABEL: select_v2f32:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI4_0
; CHECK-NEXT: adrp x9, .LCPI4_1
; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2
; CHECK-NEXT: ptrue p0.s, vl2
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI4_0]
; CHECK-NEXT: ldr d4, [x9, :lo12:.LCPI4_1]
; CHECK-NEXT: lsl z2.s, p0/m, z2.s, z3.s
; CHECK-NEXT: asr z2.s, p0/m, z2.s, z3.s
; CHECK-NEXT: eor z3.d, z2.d, z4.d
; CHECK-NEXT: and z0.d, z0.d, z2.d
; CHECK-NEXT: and z1.d, z1.d, z3.d
; CHECK-NEXT: orr z0.d, z0.d, z1.d
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
%sel = select <2 x i1> %mask, <2 x float> %op1, <2 x float> %op2
ret <2 x float> %sel
}
define <4 x float> @select_v4f32(<4 x float> %op1, <4 x float> %op2, <4 x i1> %mask) #0 {
; CHECK-LABEL: select_v4f32:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI5_0
; CHECK-NEXT: adrp x9, .LCPI5_1
; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2
; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: uunpklo z2.s, z2.h
; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI5_0]
; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI5_1]
; CHECK-NEXT: lsl z2.s, p0/m, z2.s, z3.s
; CHECK-NEXT: asr z2.s, p0/m, z2.s, z3.s
; CHECK-NEXT: eor z3.d, z2.d, z4.d
; CHECK-NEXT: and z0.d, z0.d, z2.d
; CHECK-NEXT: and z1.d, z1.d, z3.d
; CHECK-NEXT: orr z0.d, z0.d, z1.d
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
%sel = select <4 x i1> %mask, <4 x float> %op1, <4 x float> %op2
ret <4 x float> %sel
}
define void @select_v8f32(ptr %a, ptr %b) #0 {
; CHECK-LABEL: select_v8f32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x1]
; CHECK-NEXT: adrp x8, .LCPI6_0
; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: ldp q3, q2, [x0]
; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI6_0]
; CHECK-NEXT: fcmeq p1.s, p0/z, z2.s, z1.s
; CHECK-NEXT: fcmeq p0.s, p0/z, z3.s, z0.s
; CHECK-NEXT: mov z5.s, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: mov z6.s, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: and z2.d, z2.d, z5.d
; CHECK-NEXT: eor z5.d, z5.d, z4.d
; CHECK-NEXT: eor z4.d, z6.d, z4.d
; CHECK-NEXT: and z3.d, z3.d, z6.d
; CHECK-NEXT: and z0.d, z0.d, z4.d
; CHECK-NEXT: and z1.d, z1.d, z5.d
; CHECK-NEXT: orr z0.d, z3.d, z0.d
; CHECK-NEXT: orr z1.d, z2.d, z1.d
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
%op1 = load <8 x float>, ptr %a
%op2 = load <8 x float>, ptr %b
%mask = fcmp oeq <8 x float> %op1, %op2
%sel = select <8 x i1> %mask, <8 x float> %op1, <8 x float> %op2
store <8 x float> %sel, ptr %a
ret void
}
define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, <1 x i1> %mask) #0 {
; CHECK-LABEL: select_v1f64:
; CHECK: // %bb.0:
; CHECK-NEXT: tst w0, #0x1
; CHECK-NEXT: mov x9, #-1
; CHECK-NEXT: csetm x8, ne
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
; CHECK-NEXT: fmov d3, x9
; CHECK-NEXT: fmov d2, x8
; CHECK-NEXT: eor z3.d, z2.d, z3.d
; CHECK-NEXT: and z0.d, z0.d, z2.d
; CHECK-NEXT: and z1.d, z1.d, z3.d
; CHECK-NEXT: orr z0.d, z0.d, z1.d
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
%sel = select <1 x i1> %mask, <1 x double> %op1, <1 x double> %op2
ret <1 x double> %sel
}
define <2 x double> @select_v2f64(<2 x double> %op1, <2 x double> %op2, <2 x i1> %mask) #0 {
; CHECK-LABEL: select_v2f64:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI8_0
; CHECK-NEXT: adrp x9, .LCPI8_1
; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2
; CHECK-NEXT: ptrue p0.d, vl2
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: uunpklo z2.d, z2.s
; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI8_0]
; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI8_1]
; CHECK-NEXT: lsl z2.d, p0/m, z2.d, z3.d
; CHECK-NEXT: asr z2.d, p0/m, z2.d, z3.d
; CHECK-NEXT: eor z3.d, z2.d, z4.d
; CHECK-NEXT: and z0.d, z0.d, z2.d
; CHECK-NEXT: and z1.d, z1.d, z3.d
; CHECK-NEXT: orr z0.d, z0.d, z1.d
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
%sel = select <2 x i1> %mask, <2 x double> %op1, <2 x double> %op2
ret <2 x double> %sel
}
define void @select_v4f64(ptr %a, ptr %b) #0 {
; CHECK-LABEL: select_v4f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x1]
; CHECK-NEXT: adrp x8, .LCPI9_0
; CHECK-NEXT: ptrue p0.d, vl2
; CHECK-NEXT: ldp q3, q2, [x0]
; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI9_0]
; CHECK-NEXT: fcmeq p1.d, p0/z, z2.d, z1.d
; CHECK-NEXT: fcmeq p0.d, p0/z, z3.d, z0.d
; CHECK-NEXT: mov z5.d, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: mov z6.d, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: and z2.d, z2.d, z5.d
; CHECK-NEXT: eor z5.d, z5.d, z4.d
; CHECK-NEXT: eor z4.d, z6.d, z4.d
; CHECK-NEXT: and z3.d, z3.d, z6.d
; CHECK-NEXT: and z0.d, z0.d, z4.d
; CHECK-NEXT: and z1.d, z1.d, z5.d
; CHECK-NEXT: orr z0.d, z3.d, z0.d
; CHECK-NEXT: orr z1.d, z2.d, z1.d
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
%op1 = load <4 x double>, ptr %a
%op2 = load <4 x double>, ptr %b
%mask = fcmp oeq <4 x double> %op1, %op2
%sel = select <4 x i1> %mask, <4 x double> %op1, <4 x double> %op2
store <4 x double> %sel, ptr %a
ret void
}
attributes #0 = { "target-features"="+sve" }
Reference in New Issue View Git Blame Copy Permalink