48 lines
1.8 KiB
LLVM
48 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64"
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;
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; NOTE: SVE lowering for the BSP pseudoinst is not currently implemented, so we
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; don't currently expect the code below to lower to BSL/BIT/BIF. Once
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; this is implemented, this test will be fleshed out.
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;
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define <8 x i32> @fixed_bitselect_v8i32(ptr %pre_cond_ptr, ptr %left_ptr, ptr %right_ptr) #0 {
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; CHECK-LABEL: fixed_bitselect_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI0_0
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; CHECK-NEXT: ldp q1, q0, [x0]
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; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI0_0]
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; CHECK-NEXT: adrp x8, .LCPI0_1
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; CHECK-NEXT: ldp q3, q4, [x1]
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; CHECK-NEXT: sub z6.s, z2.s, z1.s
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; CHECK-NEXT: sub z2.s, z2.s, z0.s
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; CHECK-NEXT: and z3.d, z6.d, z3.d
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; CHECK-NEXT: ldp q7, q16, [x2]
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; CHECK-NEXT: and z2.d, z2.d, z4.d
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; CHECK-NEXT: ldr q5, [x8, :lo12:.LCPI0_1]
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; CHECK-NEXT: add z1.s, z1.s, z5.s
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; CHECK-NEXT: add z0.s, z0.s, z5.s
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; CHECK-NEXT: and z4.d, z0.d, z16.d
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; CHECK-NEXT: and z0.d, z1.d, z7.d
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; CHECK-NEXT: orr z0.d, z0.d, z3.d
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; CHECK-NEXT: orr z1.d, z4.d, z2.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
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; CHECK-NEXT: ret
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%pre_cond = load <8 x i32>, ptr %pre_cond_ptr
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%left = load <8 x i32>, ptr %left_ptr
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%right = load <8 x i32>, ptr %right_ptr
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%neg_cond = sub <8 x i32> zeroinitializer, %pre_cond
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%min_cond = add <8 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
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%left_bits_0 = and <8 x i32> %neg_cond, %left
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%right_bits_0 = and <8 x i32> %min_cond, %right
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%bsl0000 = or <8 x i32> %right_bits_0, %left_bits_0
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ret <8 x i32> %bsl0000
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}
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attributes #0 = { "target-features"="+sve" }
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