39 lines
1.6 KiB
LLVM
39 lines
1.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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; Ensure that a no-op 'and' after an extending load gets removed when the and is
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; constructed via a splat_vector node.
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define <vscale x 2 x i64> @fold_loadext_and(ptr %ptr, i32 %needle, <vscale x 2 x i64> %b) #0 {
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; CHECK-LABEL: fold_loadext_and:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]
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; CHECK-NEXT: ret
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%load = load <vscale x 2 x i32>, ptr %ptr, align 4
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%ext = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>
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%splatinsert = insertelement <vscale x 2 x i64> poison, i64 4294967295, i64 0
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%splat = shufflevector <vscale x 2 x i64> %splatinsert, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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%and = and <vscale x 2 x i64> %ext, %splat
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ret <vscale x 2 x i64> %and
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}
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; Same as above but testing the case we care about. Here the vscale x 2 x i32
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; types get legalized into vscale x 2 x i64 types which introduces the extending
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; load and 'and' nodes similar to the above case.
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define <vscale x 2 x i1> @fold_loadext_and_legalize(ptr %ptr, <vscale x 2 x i32> %a) #0 {
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; CHECK-LABEL: fold_loadext_and_legalize:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: and z0.d, z0.d, #0xffffffff
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; CHECK-NEXT: ld1w { z1.d }, p0/z, [x0]
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; CHECK-NEXT: cmpeq p0.d, p0/z, z1.d, z0.d
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; CHECK-NEXT: ret
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%load = load <vscale x 2 x i32>, ptr %ptr
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%cmp = icmp eq <vscale x 2 x i32> %load, %a
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ret <vscale x 2 x i1> %cmp
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}
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attributes #0 = { "target-features"="+sve" }
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