161 lines
3.9 KiB
LLVM
161 lines
3.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
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;; Check the transformation
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;; CSEL 0, cttz, cc -> AND cttz numbits-1
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;; for cttz in the case of i32 and i64 respectively
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;; Cases for which the optimzation takes place
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define i32 @cttzi32(i32 %x) {
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; CHECK-LABEL: cttzi32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: rbit w8, w0
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; CHECK-NEXT: clz w8, w8
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; CHECK-NEXT: and w0, w8, #0x1f
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; CHECK-NEXT: ret
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entry:
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%0 = call i32 @llvm.cttz.i32(i32 %x, i1 true)
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%1 = icmp eq i32 %x, 0
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%2 = select i1 %1, i32 0, i32 %0
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ret i32 %2
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}
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define i64 @cttzi64(i64 %x) {
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; CHECK-LABEL: cttzi64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: rbit x8, x0
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; CHECK-NEXT: clz x8, x8
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; CHECK-NEXT: and x0, x8, #0x3f
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; CHECK-NEXT: ret
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entry:
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%0 = call i64 @llvm.cttz.i64(i64 %x, i1 true)
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%1 = icmp eq i64 %x, 0
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%2 = select i1 %1, i64 0, i64 %0
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ret i64 %2
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}
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define i32 @cttzi32ne(i32 %x) {
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; CHECK-LABEL: cttzi32ne:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: rbit w8, w0
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; CHECK-NEXT: clz w8, w8
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; CHECK-NEXT: and w0, w8, #0x1f
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; CHECK-NEXT: ret
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entry:
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%0 = call i32 @llvm.cttz.i32(i32 %x, i1 true)
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%1 = icmp ne i32 %x, 0
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%2 = select i1 %1, i32 %0, i32 0
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ret i32 %2
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}
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define i64 @cttzi64ne(i64 %x) {
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; CHECK-LABEL: cttzi64ne:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: rbit x8, x0
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; CHECK-NEXT: clz x8, x8
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; CHECK-NEXT: and x0, x8, #0x3f
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; CHECK-NEXT: ret
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entry:
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%0 = call i64 @llvm.cttz.i64(i64 %x, i1 true)
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%1 = icmp ne i64 %x, 0
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%2 = select i1 %1, i64 %0, i64 0
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ret i64 %2
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}
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define i32 @cttztrunc(i64 %x) {
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; CHECK-LABEL: cttztrunc:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: rbit x8, x0
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; CHECK-NEXT: clz x8, x8
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; CHECK-NEXT: and w0, w8, #0x3f
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; CHECK-NEXT: ret
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entry:
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%0 = call i64 @llvm.cttz.i64(i64 %x, i1 true)
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%1 = icmp eq i64 %x, 0
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%2 = select i1 %1, i64 0, i64 %0
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%3 = trunc i64 %2 to i32
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ret i32 %3
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}
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;; Cases for which the optimization does not take place
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define i32 @cttzne(i32 %x) {
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; CHECK-LABEL: cttzne:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: rbit w8, w0
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; CHECK-NEXT: cmp w0, #0
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; CHECK-NEXT: clz w8, w8
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; CHECK-NEXT: csel w0, wzr, w8, ne
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; CHECK-NEXT: ret
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entry:
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%0 = call i32 @llvm.cttz.i32(i32 %x, i1 true)
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%1 = icmp ne i32 %x, 0
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%2 = select i1 %1, i32 0, i32 %0
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ret i32 %2
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}
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define i32 @cttzxnot0(i32 %x) {
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; CHECK-LABEL: cttzxnot0:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: rbit w8, w0
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; CHECK-NEXT: cmp w0, #10
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; CHECK-NEXT: clz w8, w8
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; CHECK-NEXT: csel w0, wzr, w8, eq
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; CHECK-NEXT: ret
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entry:
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%0 = call i32 @llvm.cttz.i32(i32 %x, i1 true)
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%1 = icmp eq i32 %x, 10
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%2 = select i1 %1, i32 0, i32 %0
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ret i32 %2
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}
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define i32 @cttzlhsnot0(i32 %x) {
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; CHECK-LABEL: cttzlhsnot0:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: rbit w9, w0
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; CHECK-NEXT: mov w8, #10
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; CHECK-NEXT: clz w9, w9
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; CHECK-NEXT: cmp w0, #0
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; CHECK-NEXT: csel w0, w8, w9, eq
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; CHECK-NEXT: ret
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entry:
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%0 = call i32 @llvm.cttz.i32(i32 %x, i1 true)
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%1 = icmp eq i32 %x, 0
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%2 = select i1 %1, i32 10, i32 %0
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ret i32 %2
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}
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define i32 @notcttz(i32 %x) {
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; CHECK-LABEL: notcttz:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: clz w8, w0
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; CHECK-NEXT: cmp w0, #0
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; CHECK-NEXT: csel w0, wzr, w8, eq
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; CHECK-NEXT: ret
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entry:
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%0 = call i32 @llvm.ctlz.i32(i32 %x, i1 true)
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%1 = icmp eq i32 %x, 0
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%2 = select i1 %1, i32 0, i32 %0
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ret i32 %2
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}
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define i32 @cttzlhsnotx(i32 %x, i32 %y) {
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; CHECK-LABEL: cttzlhsnotx:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: rbit w8, w0
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; CHECK-NEXT: cmp w1, #0
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; CHECK-NEXT: clz w8, w8
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; CHECK-NEXT: csel w0, wzr, w8, eq
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; CHECK-NEXT: ret
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entry:
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%0 = call i32 @llvm.cttz.i32(i32 %x, i1 true)
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%1 = icmp eq i32 %y, 0
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%2 = select i1 %1, i32 0, i32 %0
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ret i32 %2
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}
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declare i32 @llvm.cttz.i32(i32, i1)
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declare i64 @llvm.cttz.i64(i64, i1)
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declare i32 @llvm.ctlz.i32(i32, i1)
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