101 lines
5.7 KiB
LLVM
101 lines
5.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s
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target triple = "aarch64-arm-none-eabi"
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; Expected to not transform
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define <2 x half> @complex_add_v2f16(<2 x half> %a, <2 x half> %b) {
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; CHECK-LABEL: complex_add_v2f16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: mov h2, v0.h[1]
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; CHECK-NEXT: mov h3, v1.h[1]
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; CHECK-NEXT: fsub h1, h1, h2
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; CHECK-NEXT: fadd h0, h3, h0
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; CHECK-NEXT: mov v1.h[1], v0.h[0]
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; CHECK-NEXT: fmov d0, d1
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; CHECK-NEXT: ret
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entry:
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%a.real = shufflevector <2 x half> %a, <2 x half> zeroinitializer, <1 x i32> <i32 0>
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%a.imag = shufflevector <2 x half> %a, <2 x half> zeroinitializer, <1 x i32> <i32 1>
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%b.real = shufflevector <2 x half> %b, <2 x half> zeroinitializer, <1 x i32> <i32 0>
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%b.imag = shufflevector <2 x half> %b, <2 x half> zeroinitializer, <1 x i32> <i32 1>
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%0 = fsub fast <1 x half> %b.real, %a.imag
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%1 = fadd fast <1 x half> %b.imag, %a.real
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%interleaved.vec = shufflevector <1 x half> %0, <1 x half> %1, <2 x i32> <i32 0, i32 1>
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ret <2 x half> %interleaved.vec
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}
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; Expected to transform
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define <4 x half> @complex_add_v4f16(<4 x half> %a, <4 x half> %b) {
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; CHECK-LABEL: complex_add_v4f16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcadd v0.4h, v1.4h, v0.4h, #90
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; CHECK-NEXT: ret
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entry:
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%a.real = shufflevector <4 x half> %a, <4 x half> zeroinitializer, <2 x i32> <i32 0, i32 2>
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%a.imag = shufflevector <4 x half> %a, <4 x half> zeroinitializer, <2 x i32> <i32 1, i32 3>
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%b.real = shufflevector <4 x half> %b, <4 x half> zeroinitializer, <2 x i32> <i32 0, i32 2>
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%b.imag = shufflevector <4 x half> %b, <4 x half> zeroinitializer, <2 x i32> <i32 1, i32 3>
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%0 = fsub fast <2 x half> %b.real, %a.imag
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%1 = fadd fast <2 x half> %b.imag, %a.real
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%interleaved.vec = shufflevector <2 x half> %0, <2 x half> %1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
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ret <4 x half> %interleaved.vec
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}
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; Expected to transform
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define <8 x half> @complex_add_v8f16(<8 x half> %a, <8 x half> %b) {
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; CHECK-LABEL: complex_add_v8f16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcadd v0.8h, v1.8h, v0.8h, #90
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; CHECK-NEXT: ret
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entry:
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%a.real = shufflevector <8 x half> %a, <8 x half> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%a.imag = shufflevector <8 x half> %a, <8 x half> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%b.real = shufflevector <8 x half> %b, <8 x half> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%b.imag = shufflevector <8 x half> %b, <8 x half> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%0 = fsub fast <4 x half> %b.real, %a.imag
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%1 = fadd fast <4 x half> %b.imag, %a.real
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%interleaved.vec = shufflevector <4 x half> %0, <4 x half> %1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
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ret <8 x half> %interleaved.vec
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}
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; Expected to transform
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define <16 x half> @complex_add_v16f16(<16 x half> %a, <16 x half> %b) {
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; CHECK-LABEL: complex_add_v16f16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcadd v0.8h, v2.8h, v0.8h, #90
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; CHECK-NEXT: fcadd v1.8h, v3.8h, v1.8h, #90
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; CHECK-NEXT: ret
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entry:
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%a.real = shufflevector <16 x half> %a, <16 x half> zeroinitializer, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%a.imag = shufflevector <16 x half> %a, <16 x half> zeroinitializer, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%b.real = shufflevector <16 x half> %b, <16 x half> zeroinitializer, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%b.imag = shufflevector <16 x half> %b, <16 x half> zeroinitializer, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%0 = fsub fast <8 x half> %b.real, %a.imag
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%1 = fadd fast <8 x half> %b.imag, %a.real
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%interleaved.vec = shufflevector <8 x half> %0, <8 x half> %1, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
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ret <16 x half> %interleaved.vec
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}
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; Expected to transform
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define <32 x half> @complex_add_v32f16(<32 x half> %a, <32 x half> %b) {
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; CHECK-LABEL: complex_add_v32f16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcadd v2.8h, v6.8h, v2.8h, #90
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; CHECK-NEXT: fcadd v0.8h, v4.8h, v0.8h, #90
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; CHECK-NEXT: fcadd v1.8h, v5.8h, v1.8h, #90
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; CHECK-NEXT: fcadd v3.8h, v7.8h, v3.8h, #90
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; CHECK-NEXT: ret
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entry:
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%a.real = shufflevector <32 x half> %a, <32 x half> zeroinitializer, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
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%a.imag = shufflevector <32 x half> %a, <32 x half> zeroinitializer, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
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%b.real = shufflevector <32 x half> %b, <32 x half> zeroinitializer, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
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%b.imag = shufflevector <32 x half> %b, <32 x half> zeroinitializer, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
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%0 = fsub fast <16 x half> %b.real, %a.imag
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%1 = fadd fast <16 x half> %b.imag, %a.real
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%interleaved.vec = shufflevector <16 x half> %0, <16 x half> %1, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
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ret <32 x half> %interleaved.vec
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}
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