128 lines
10 KiB
LLVM
128 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
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; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s
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; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefixes=SIZE %s
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; END.
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define amdgpu_kernel void @fneg_f32() {
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; CHECK-LABEL: 'fneg_f32'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f32 = fneg float undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v2f32 = fneg <2 x float> undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v3f32 = fneg <3 x float> undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v4f32 = fneg <4 x float> undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v5f32 = fneg <5 x float> undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v8f32 = fneg <8 x float> undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v9f32 = fneg <9 x float> undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
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;
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; SIZE-LABEL: 'fneg_f32'
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; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f32 = fneg float undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v2f32 = fneg <2 x float> undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v3f32 = fneg <3 x float> undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v4f32 = fneg <4 x float> undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v5f32 = fneg <5 x float> undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v8f32 = fneg <8 x float> undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v9f32 = fneg <9 x float> undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
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;
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%f32 = fneg float undef
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%v2f32 = fneg <2 x float> undef
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%v3f32 = fneg <3 x float> undef
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%v4f32 = fneg <4 x float> undef
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%v5f32 = fneg <5 x float> undef
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%v8f32 = fneg <8 x float> undef
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%v9f32 = fneg <9 x float> undef
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ret void
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}
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define amdgpu_kernel void @fneg_f64() {
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; CHECK-LABEL: 'fneg_f64'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f64 = fneg double undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v2f64 = fneg <2 x double> undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v3f64 = fneg <3 x double> undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v4f64 = fneg <4 x double> undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v5f64 = fneg <5 x double> undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
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;
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; SIZE-LABEL: 'fneg_f64'
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; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f64 = fneg double undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v2f64 = fneg <2 x double> undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v3f64 = fneg <3 x double> undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v4f64 = fneg <4 x double> undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v5f64 = fneg <5 x double> undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
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;
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%f64 = fneg double undef
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%v2f64 = fneg <2 x double> undef
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%v3f64 = fneg <3 x double> undef
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%v4f64 = fneg <4 x double> undef
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%v5f64 = fneg <5 x double> undef
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ret void
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}
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define amdgpu_kernel void @fneg_f16() {
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; CHECK-LABEL: 'fneg_f16'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f16 = fneg half undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v2f16 = fneg <2 x half> undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v3f16 = fneg <3 x half> undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v4f16 = fneg <4 x half> undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v5f16 = fneg <5 x half> undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v16f16 = fneg <16 x half> undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v17f16 = fneg <17 x half> undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
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;
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; SIZE-LABEL: 'fneg_f16'
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; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f16 = fneg half undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v2f16 = fneg <2 x half> undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v3f16 = fneg <3 x half> undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v4f16 = fneg <4 x half> undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v5f16 = fneg <5 x half> undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v16f16 = fneg <16 x half> undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v17f16 = fneg <17 x half> undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
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;
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%f16 = fneg half undef
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%v2f16 = fneg <2 x half> undef
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%v3f16 = fneg <3 x half> undef
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%v4f16 = fneg <4 x half> undef
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%v5f16 = fneg <5 x half> undef
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%v16f16 = fneg <16 x half> undef
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%v17f16 = fneg <17 x half> undef
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ret void
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}
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define i32 @fneg_idiom(i32 %arg) {
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; CHECK-LABEL: 'fneg_idiom'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float -0.000000e+00, undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F32 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8F32 = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V16F32 = fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F64 = fsub double -0.000000e+00, undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F64 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V4F64 = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V8F64 = fsub <8 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret i32 undef
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;
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; SIZE-LABEL: 'fneg_idiom'
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; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float -0.000000e+00, undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F32 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8F32 = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V16F32 = fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F64 = fsub double -0.000000e+00, undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F64 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4F64 = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V8F64 = fsub <8 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
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;
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%F32 = fsub float -0.0, undef
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%V4F32 = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, undef
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%V8F32 = fsub <8 x float> <float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0>, undef
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%V16F32 = fsub <16 x float> <float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0>, undef
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%F64 = fsub double -0.0, undef
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%V2F64 = fsub <2 x double> <double -0.0, double -0.0>, undef
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%V4F64 = fsub <4 x double> <double -0.0, double -0.0, double -0.0, double -0.0>, undef
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%V8F64 = fsub <8 x double> <double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0>, undef
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ret i32 undef
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}
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