64 lines
2.1 KiB
C++
64 lines
2.1 KiB
C++
//===-- SPIRVAsmBackend.cpp - SPIR-V Assembler Backend ---------*- C++ -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/SPIRVMCTargetDesc.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/Support/EndianStream.h"
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using namespace llvm;
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namespace {
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class SPIRVAsmBackend : public MCAsmBackend {
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public:
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SPIRVAsmBackend(support::endianness Endian) : MCAsmBackend(Endian) {}
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void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
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const MCValue &Target, MutableArrayRef<char> Data,
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uint64_t Value, bool IsResolved,
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const MCSubtargetInfo *STI) const override {}
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std::unique_ptr<MCObjectTargetWriter>
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createObjectTargetWriter() const override {
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return createSPIRVObjectTargetWriter();
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}
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// No instruction requires relaxation.
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bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout) const override {
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return false;
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}
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unsigned getNumFixupKinds() const override { return 1; }
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bool mayNeedRelaxation(const MCInst &Inst,
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const MCSubtargetInfo &STI) const override {
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return false;
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}
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void relaxInstruction(MCInst &Inst,
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const MCSubtargetInfo &STI) const override {}
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bool writeNopData(raw_ostream &OS, uint64_t Count,
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const MCSubtargetInfo *STI) const override {
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return false;
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}
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};
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} // end anonymous namespace
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MCAsmBackend *llvm::createSPIRVAsmBackend(const Target &T,
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const MCSubtargetInfo &STI,
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const MCRegisterInfo &MRI,
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const MCTargetOptions &) {
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return new SPIRVAsmBackend(support::little);
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}
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