657 lines
28 KiB
TableGen
657 lines
28 KiB
TableGen
//===-- RISCVInstrInfoF.td - RISC-V 'F' instructions -------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instructions from the standard 'F',
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// Single-Precision Floating-Point instruction set extension.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// RISC-V specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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def SDT_RISCVFMV_W_X_RV64
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: SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i64>]>;
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def SDT_RISCVFMV_X_ANYEXTW_RV64
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: SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, f32>]>;
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def SDT_RISCVFCVT_W_RV64
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: SDTypeProfile<1, 2, [SDTCisVT<0, i64>, SDTCisFP<1>,
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SDTCisVT<2, i64>]>;
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def SDT_RISCVFCVT_X
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: SDTypeProfile<1, 2, [SDTCisVT<0, XLenVT>, SDTCisFP<1>,
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SDTCisVT<2, XLenVT>]>;
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def SDT_RISCVFROUND
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: SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
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SDTCisVT<3, XLenVT>]>;
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def riscv_fround
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: SDNode<"RISCVISD::FROUND", SDT_RISCVFROUND>;
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def riscv_fmv_w_x_rv64
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: SDNode<"RISCVISD::FMV_W_X_RV64", SDT_RISCVFMV_W_X_RV64>;
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def riscv_fmv_x_anyextw_rv64
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: SDNode<"RISCVISD::FMV_X_ANYEXTW_RV64", SDT_RISCVFMV_X_ANYEXTW_RV64>;
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def riscv_fcvt_w_rv64
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: SDNode<"RISCVISD::FCVT_W_RV64", SDT_RISCVFCVT_W_RV64>;
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def riscv_fcvt_wu_rv64
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: SDNode<"RISCVISD::FCVT_WU_RV64", SDT_RISCVFCVT_W_RV64>;
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def riscv_fcvt_x
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: SDNode<"RISCVISD::FCVT_X", SDT_RISCVFCVT_X>;
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def riscv_fcvt_xu
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: SDNode<"RISCVISD::FCVT_XU", SDT_RISCVFCVT_X>;
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def riscv_strict_fcvt_w_rv64
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: SDNode<"RISCVISD::STRICT_FCVT_W_RV64", SDT_RISCVFCVT_W_RV64,
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[SDNPHasChain]>;
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def riscv_strict_fcvt_wu_rv64
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: SDNode<"RISCVISD::STRICT_FCVT_WU_RV64", SDT_RISCVFCVT_W_RV64,
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[SDNPHasChain]>;
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def riscv_any_fcvt_w_rv64 : PatFrags<(ops node:$src, node:$frm),
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[(riscv_strict_fcvt_w_rv64 node:$src, node:$frm),
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(riscv_fcvt_w_rv64 node:$src, node:$frm)]>;
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def riscv_any_fcvt_wu_rv64 : PatFrags<(ops node:$src, node:$frm),
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[(riscv_strict_fcvt_wu_rv64 node:$src, node:$frm),
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(riscv_fcvt_wu_rv64 node:$src, node:$frm)]>;
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def any_fma_nsz : PatFrag<(ops node:$rs1, node:$rs2, node:$rs3),
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(any_fma node:$rs1, node:$rs2, node:$rs3), [{
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return N->getFlags().hasNoSignedZeros();
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}]>;
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//===----------------------------------------------------------------------===//
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// Operand and SDNode transformation definitions.
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//===----------------------------------------------------------------------===//
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// Zfinx
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def GPRAsFPR : AsmOperandClass {
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let Name = "GPRAsFPR";
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let ParserMethod = "parseGPRAsFPR";
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let RenderMethod = "addRegOperands";
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}
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def FPR32INX : RegisterOperand<GPRF32> {
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let ParserMatchClass = GPRAsFPR;
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let DecoderMethod = "DecodeGPRRegisterClass";
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}
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// inx = 0 : f, d, zfh, zfhmin
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// = 1 : zfinx, zdinx, zhinx, zhinxmin
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// = 2 : zdinx_rv32
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class ExtInfo<bits<2> inx, list<Predicate> pres> {
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string Suffix = !cond(!eq(inx, 0): "",
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!eq(inx, 1): "_INX",
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!eq(inx, 2): "_IN32X");
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list<Predicate> Predicates = pres;
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string Space = !cond(!eq(inx, 0): "",
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!eq(inx, 1): "RVZfinx",
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!eq(inx, 2): "RV32Zdinx");
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}
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class ExtInfo_r<ExtInfo ext, DAGOperand reg> {
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string Suffix = ext.Suffix;
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list<Predicate> Predicates = ext.Predicates;
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string Space = ext.Space;
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DAGOperand Reg = reg;
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}
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class ExtInfo_rr<ExtInfo ext, DAGOperand rdty, DAGOperand rs1ty> {
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string Suffix = ext.Suffix;
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list<Predicate> Predicates = ext.Predicates;
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string Space = ext.Space;
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DAGOperand RdTy = rdty;
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DAGOperand Rs1Ty = rs1ty;
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}
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def FExt : ExtInfo<0, [HasStdExtF]>;
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def F64Ext : ExtInfo<0, [HasStdExtF, IsRV64]>;
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def ZfinxExt : ExtInfo<1, [HasStdExtZfinx]>;
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def Zfinx64Ext : ExtInfo<1, [HasStdExtZfinx, IsRV64]>;
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def F : ExtInfo_r<FExt, FPR32>;
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def F_INX : ExtInfo_r<ZfinxExt, FPR32INX>;
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def FF : ExtInfo_rr<FExt, FPR32, FPR32>;
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def FF_INX : ExtInfo_rr<ZfinxExt, FPR32INX, FPR32INX>;
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def FX : ExtInfo_rr<FExt, FPR32, GPR>;
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def FX_INX : ExtInfo_rr<ZfinxExt, FPR32INX, GPR>;
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def FX_64 : ExtInfo_rr<F64Ext, FPR32, GPR>;
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def FX_INX_64 : ExtInfo_rr<Zfinx64Ext, FPR32INX, GPR>;
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def XF : ExtInfo_rr<FExt, GPR, FPR32>;
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def XF_64 : ExtInfo_rr<F64Ext, GPR, FPR32>;
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def XF_INX : ExtInfo_rr<ZfinxExt, GPR, FPR32INX>;
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def XF_INX_64 : ExtInfo_rr<Zfinx64Ext, GPR, FPR32INX>;
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defvar FINX = [F, F_INX];
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defvar FFINX = [FF, FF_INX];
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defvar FXINX = [FX, FX_INX];
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defvar XFINX = [XF, XF_INX];
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defvar XFIN64X = [XF_64, XF_INX_64];
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defvar FXIN64X = [FX_64, FX_INX_64];
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// Floating-point rounding mode
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def FRMArg : AsmOperandClass {
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let Name = "FRMArg";
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let RenderMethod = "addFRMArgOperands";
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let DiagnosticType = "InvalidFRMArg";
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}
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def frmarg : Operand<XLenVT> {
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let ParserMatchClass = FRMArg;
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let PrintMethod = "printFRMArg";
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let DecoderMethod = "decodeFRMArg";
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}
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//===----------------------------------------------------------------------===//
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// Instruction class templates
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
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class FPLoad_r<bits<3> funct3, string opcodestr, RegisterClass rty,
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SchedWrite sw>
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: RVInstI<funct3, OPC_LOAD_FP, (outs rty:$rd),
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(ins GPRMem:$rs1, simm12:$imm12),
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opcodestr, "$rd, ${imm12}(${rs1})">,
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Sched<[sw, ReadFMemBase]>;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
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class FPStore_r<bits<3> funct3, string opcodestr, RegisterClass rty,
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SchedWrite sw>
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: RVInstS<funct3, OPC_STORE_FP, (outs),
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(ins rty:$rs2, GPRMem:$rs1, simm12:$imm12),
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opcodestr, "$rs2, ${imm12}(${rs1})">,
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Sched<[sw, ReadFStoreData, ReadFMemBase]>;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1,
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UseNamedOperandTable = 1, hasPostISelHook = 1, isCommutable = 1 in
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class FPFMA_rrr_frm<RISCVOpcode opcode, bits<2> funct2, string opcodestr,
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DAGOperand rty>
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: RVInstR4Frm<funct2, opcode, (outs rty:$rd),
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(ins rty:$rs1, rty:$rs2, rty:$rs3, frmarg:$frm),
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opcodestr, "$rd, $rs1, $rs2, $rs3, $frm">;
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multiclass FPFMA_rrr_frm_m<RISCVOpcode opcode, bits<2> funct2,
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string opcodestr, list<ExtInfo_r> Exts> {
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foreach Ext = Exts in
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let Predicates = Ext.Predicates, DecoderNamespace = Ext.Space in
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def Ext.Suffix : FPFMA_rrr_frm<opcode, funct2, opcodestr, Ext.Reg>;
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}
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class FPFMADynFrmAlias<FPFMA_rrr_frm Inst, string OpcodeStr,
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DAGOperand rty>
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: InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
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(Inst rty:$rd, rty:$rs1, rty:$rs2, rty:$rs3, 0b111)>;
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multiclass FPFMADynFrmAlias_m<FPFMA_rrr_frm Inst, string OpcodeStr,
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list<ExtInfo_r> Exts> {
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foreach Ext = Exts in
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let Predicates = Ext.Predicates in
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def : FPFMADynFrmAlias<!cast<FPFMA_rrr_frm>(Inst#Ext.Suffix), OpcodeStr,
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Ext.Reg>;
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1 in
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class FPALU_rr<bits<7> funct7, bits<3> funct3, string opcodestr,
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DAGOperand rty, bit Commutable>
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: RVInstR<funct7, funct3, OPC_OP_FP, (outs rty:$rd),
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(ins rty:$rs1, rty:$rs2), opcodestr, "$rd, $rs1, $rs2"> {
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let isCommutable = Commutable;
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}
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multiclass FPALU_rr_m<bits<7> funct7, bits<3> funct3, string opcodestr,
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list<ExtInfo_r> Exts, bit Commutable = 0> {
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foreach Ext = Exts in
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let Predicates = Ext.Predicates, DecoderNamespace = Ext.Space in
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def Ext.Suffix : FPALU_rr<funct7, funct3, opcodestr, Ext.Reg, Commutable>;
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1,
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UseNamedOperandTable = 1, hasPostISelHook = 1 in
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class FPALU_rr_frm<bits<7> funct7, string opcodestr, DAGOperand rty,
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bit Commutable>
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: RVInstRFrm<funct7, OPC_OP_FP, (outs rty:$rd),
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(ins rty:$rs1, rty:$rs2, frmarg:$frm), opcodestr,
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"$rd, $rs1, $rs2, $frm"> {
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let isCommutable = Commutable;
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}
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multiclass FPALU_rr_frm_m<bits<7> funct7, string opcodestr,
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list<ExtInfo_r> Exts, bit Commutable = 0> {
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foreach Ext = Exts in
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let Predicates = Ext.Predicates, DecoderNamespace = Ext.Space in
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def Ext.Suffix : FPALU_rr_frm<funct7, opcodestr, Ext.Reg, Commutable>;
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}
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class FPALUDynFrmAlias<FPALU_rr_frm Inst, string OpcodeStr,
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DAGOperand rty>
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: InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
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(Inst rty:$rd, rty:$rs1, rty:$rs2, 0b111)>;
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multiclass FPALUDynFrmAlias_m<FPALU_rr_frm Inst, string OpcodeStr,
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list<ExtInfo_r> Exts> {
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foreach Ext = Exts in
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let Predicates = Ext.Predicates in
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def : FPALUDynFrmAlias<!cast<FPALU_rr_frm>(Inst#Ext.Suffix), OpcodeStr,
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Ext.Reg>;
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1 in
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class FPUnaryOp_r<bits<7> funct7, bits<5> rs2val, bits<3> funct3,
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DAGOperand rdty, DAGOperand rs1ty, string opcodestr>
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: RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd), (ins rs1ty:$rs1),
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opcodestr, "$rd, $rs1"> {
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let rs2 = rs2val;
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}
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multiclass FPUnaryOp_r_m<bits<7> funct7, bits<5> rs2val, bits<3> funct3,
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list<ExtInfo_rr> Exts, string opcodestr> {
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foreach Ext = Exts in
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let Predicates = Ext.Predicates, DecoderNamespace = Ext.Space in
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def Ext.Suffix : FPUnaryOp_r<funct7, rs2val, funct3, Ext.RdTy, Ext.Rs1Ty,
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opcodestr>;
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1,
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UseNamedOperandTable = 1, hasPostISelHook = 1 in
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class FPUnaryOp_r_frm<bits<7> funct7, bits<5> rs2val, DAGOperand rdty,
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DAGOperand rs1ty, string opcodestr>
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: RVInstRFrm<funct7, OPC_OP_FP, (outs rdty:$rd),
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(ins rs1ty:$rs1, frmarg:$frm), opcodestr,
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"$rd, $rs1, $frm"> {
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let rs2 = rs2val;
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}
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multiclass FPUnaryOp_r_frm_m<bits<7> funct7, bits<5> rs2val,
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list<ExtInfo_rr> Exts, string opcodestr> {
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foreach Ext = Exts in
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let Predicates = Ext.Predicates, DecoderNamespace = Ext.Space in
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def Ext.Suffix : FPUnaryOp_r_frm<funct7, rs2val, Ext.RdTy, Ext.Rs1Ty,
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opcodestr>;
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}
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class FPUnaryOpDynFrmAlias<FPUnaryOp_r_frm Inst, string OpcodeStr,
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DAGOperand rdty, DAGOperand rs1ty>
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: InstAlias<OpcodeStr#" $rd, $rs1",
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(Inst rdty:$rd, rs1ty:$rs1, 0b111)>;
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multiclass FPUnaryOpDynFrmAlias_m<FPUnaryOp_r_frm Inst, string OpcodeStr,
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list<ExtInfo_rr> Exts> {
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foreach Ext = Exts in
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let Predicates = Ext.Predicates in
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def : FPUnaryOpDynFrmAlias<!cast<FPUnaryOp_r_frm>(Inst#Ext.Suffix),
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OpcodeStr, Ext.RdTy, Ext.Rs1Ty>;
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1 in
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class FPCmp_rr<bits<7> funct7, bits<3> funct3, string opcodestr,
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DAGOperand rty, bit Commutable>
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: RVInstR<funct7, funct3, OPC_OP_FP, (outs GPR:$rd),
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(ins rty:$rs1, rty:$rs2), opcodestr, "$rd, $rs1, $rs2"> {
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let isCommutable = Commutable;
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}
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multiclass FPCmp_rr_m<bits<7> funct7, bits<3> funct3, string opcodestr,
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list<ExtInfo_r> Exts, bit Commutable = 0> {
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foreach Ext = Exts in
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let Predicates = Ext.Predicates, DecoderNamespace = Ext.Space in
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def Ext.Suffix : FPCmp_rr<funct7, funct3, opcodestr, Ext.Reg, Commutable>;
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}
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class PseudoFROUND<RegisterClass Ty>
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: Pseudo<(outs Ty:$rd), (ins Ty:$rs1, Ty:$rs2, ixlenimm:$rm),
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[(set Ty:$rd, (riscv_fround Ty:$rs1, Ty:$rs2, timm:$rm))]> {
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let hasSideEffects = 0;
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let mayLoad = 0;
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let mayStore = 0;
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let usesCustomInserter = 1;
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let mayRaiseFPException = 1;
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtF] in {
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def FLW : FPLoad_r<0b010, "flw", FPR32, WriteFLD32>;
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// Operands for stores are in the order srcreg, base, offset rather than
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// reflecting the order these fields are specified in the instruction
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// encoding.
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def FSW : FPStore_r<0b010, "fsw", FPR32, WriteFST32>;
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} // Predicates = [HasStdExtF]
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let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in {
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defm FMADD_S : FPFMA_rrr_frm_m<OPC_MADD, 0b00, "fmadd.s", FINX>;
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defm FMSUB_S : FPFMA_rrr_frm_m<OPC_MSUB, 0b00, "fmsub.s", FINX>;
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defm FNMSUB_S : FPFMA_rrr_frm_m<OPC_NMSUB, 0b00, "fnmsub.s", FINX>;
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defm FNMADD_S : FPFMA_rrr_frm_m<OPC_NMADD, 0b00, "fnmadd.s", FINX>;
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}
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defm : FPFMADynFrmAlias_m<FMADD_S, "fmadd.s", FINX>;
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defm : FPFMADynFrmAlias_m<FMSUB_S, "fmsub.s", FINX>;
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defm : FPFMADynFrmAlias_m<FNMSUB_S, "fnmsub.s", FINX>;
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defm : FPFMADynFrmAlias_m<FNMADD_S, "fnmadd.s", FINX>;
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let SchedRW = [WriteFAdd32, ReadFAdd32, ReadFAdd32] in {
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defm FADD_S : FPALU_rr_frm_m<0b0000000, "fadd.s", FINX, /*Commutable*/1>;
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defm FSUB_S : FPALU_rr_frm_m<0b0000100, "fsub.s", FINX>;
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}
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let SchedRW = [WriteFMul32, ReadFMul32, ReadFMul32] in
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defm FMUL_S : FPALU_rr_frm_m<0b0001000, "fmul.s", FINX, /*Commutable*/1>;
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let SchedRW = [WriteFDiv32, ReadFDiv32, ReadFDiv32] in
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defm FDIV_S : FPALU_rr_frm_m<0b0001100, "fdiv.s", FINX>;
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defm : FPALUDynFrmAlias_m<FADD_S, "fadd.s", FINX>;
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defm : FPALUDynFrmAlias_m<FSUB_S, "fsub.s", FINX>;
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defm : FPALUDynFrmAlias_m<FMUL_S, "fmul.s", FINX>;
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defm : FPALUDynFrmAlias_m<FDIV_S, "fdiv.s", FINX>;
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defm FSQRT_S : FPUnaryOp_r_frm_m<0b0101100, 0b00000, FFINX, "fsqrt.s">,
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Sched<[WriteFSqrt32, ReadFSqrt32]>;
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defm : FPUnaryOpDynFrmAlias_m<FSQRT_S, "fsqrt.s", FFINX>;
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let SchedRW = [WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32],
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mayRaiseFPException = 0 in {
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defm FSGNJ_S : FPALU_rr_m<0b0010000, 0b000, "fsgnj.s", FINX>;
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defm FSGNJN_S : FPALU_rr_m<0b0010000, 0b001, "fsgnjn.s", FINX>;
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defm FSGNJX_S : FPALU_rr_m<0b0010000, 0b010, "fsgnjx.s", FINX>;
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}
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let SchedRW = [WriteFMinMax32, ReadFMinMax32, ReadFMinMax32] in {
|
|
defm FMIN_S : FPALU_rr_m<0b0010100, 0b000, "fmin.s", FINX, /*Commutable*/1>;
|
|
defm FMAX_S : FPALU_rr_m<0b0010100, 0b001, "fmax.s", FINX, /*Commutable*/1>;
|
|
}
|
|
|
|
defm FCVT_W_S : FPUnaryOp_r_frm_m<0b1100000, 0b00000, XFINX, "fcvt.w.s">,
|
|
Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]>;
|
|
defm : FPUnaryOpDynFrmAlias_m<FCVT_W_S, "fcvt.w.s", XFINX>;
|
|
|
|
defm FCVT_WU_S : FPUnaryOp_r_frm_m<0b1100000, 0b00001, XFINX, "fcvt.wu.s">,
|
|
Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]>;
|
|
defm : FPUnaryOpDynFrmAlias_m<FCVT_WU_S, "fcvt.wu.s", XFINX>;
|
|
|
|
let Predicates = [HasStdExtF], mayRaiseFPException = 0 in
|
|
def FMV_X_W : FPUnaryOp_r<0b1110000, 0b00000, 0b000, GPR, FPR32, "fmv.x.w">,
|
|
Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]>;
|
|
|
|
let SchedRW = [WriteFCmp32, ReadFCmp32, ReadFCmp32] in {
|
|
defm FEQ_S : FPCmp_rr_m<0b1010000, 0b010, "feq.s", FINX, /*Commutable*/1>;
|
|
defm FLT_S : FPCmp_rr_m<0b1010000, 0b001, "flt.s", FINX>;
|
|
defm FLE_S : FPCmp_rr_m<0b1010000, 0b000, "fle.s", FINX>;
|
|
}
|
|
|
|
let mayRaiseFPException = 0 in
|
|
defm FCLASS_S : FPUnaryOp_r_m<0b1110000, 0b00000, 0b001, XFINX, "fclass.s">,
|
|
Sched<[WriteFClass32, ReadFClass32]>;
|
|
|
|
defm FCVT_S_W : FPUnaryOp_r_frm_m<0b1101000, 0b00000, FXINX, "fcvt.s.w">,
|
|
Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]>;
|
|
defm : FPUnaryOpDynFrmAlias_m<FCVT_S_W, "fcvt.s.w", FXINX>;
|
|
|
|
defm FCVT_S_WU : FPUnaryOp_r_frm_m<0b1101000, 0b00001, FXINX, "fcvt.s.wu">,
|
|
Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]>;
|
|
defm : FPUnaryOpDynFrmAlias_m<FCVT_S_WU, "fcvt.s.wu", FXINX>;
|
|
|
|
let Predicates = [HasStdExtF], mayRaiseFPException = 0 in
|
|
def FMV_W_X : FPUnaryOp_r<0b1111000, 0b00000, 0b000, FPR32, GPR, "fmv.w.x">,
|
|
Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]>;
|
|
|
|
defm FCVT_L_S : FPUnaryOp_r_frm_m<0b1100000, 0b00010, XFIN64X, "fcvt.l.s">,
|
|
Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]>;
|
|
defm : FPUnaryOpDynFrmAlias_m<FCVT_L_S, "fcvt.l.s", XFIN64X>;
|
|
|
|
defm FCVT_LU_S : FPUnaryOp_r_frm_m<0b1100000, 0b00011, XFIN64X, "fcvt.lu.s">,
|
|
Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]>;
|
|
defm : FPUnaryOpDynFrmAlias_m<FCVT_LU_S, "fcvt.lu.s", XFIN64X>;
|
|
|
|
defm FCVT_S_L : FPUnaryOp_r_frm_m<0b1101000, 0b00010, FXIN64X, "fcvt.s.l">,
|
|
Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]>;
|
|
defm : FPUnaryOpDynFrmAlias_m<FCVT_S_L, "fcvt.s.l", FXIN64X>;
|
|
|
|
defm FCVT_S_LU : FPUnaryOp_r_frm_m<0b1101000, 0b00011, FXIN64X, "fcvt.s.lu">,
|
|
Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]>;
|
|
defm : FPUnaryOpDynFrmAlias_m<FCVT_S_LU, "fcvt.s.lu", FXIN64X>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
let Predicates = [HasStdExtF] in {
|
|
def : InstAlias<"flw $rd, (${rs1})", (FLW FPR32:$rd, GPR:$rs1, 0), 0>;
|
|
def : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>;
|
|
|
|
def : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
|
|
def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
|
|
def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
|
|
|
|
// fgt.s/fge.s are recognised by the GNU assembler but the canonical
|
|
// flt.s/fle.s forms will always be printed. Therefore, set a zero weight.
|
|
def : InstAlias<"fgt.s $rd, $rs, $rt",
|
|
(FLT_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
|
|
def : InstAlias<"fge.s $rd, $rs, $rt",
|
|
(FLE_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
|
|
|
|
// The following csr instructions actually alias instructions from the base ISA.
|
|
// However, it only makes sense to support them when the F extension is enabled.
|
|
// NOTE: "frcsr", "frrm", and "frflags" are more specialized version of "csrr".
|
|
def : InstAlias<"frcsr $rd", (CSRRS GPR:$rd, SysRegFCSR.Encoding, X0), 2>;
|
|
def : InstAlias<"fscsr $rd, $rs", (CSRRW GPR:$rd, SysRegFCSR.Encoding, GPR:$rs)>;
|
|
def : InstAlias<"fscsr $rs", (CSRRW X0, SysRegFCSR.Encoding, GPR:$rs), 2>;
|
|
|
|
// frsr, fssr are obsolete aliases replaced by frcsr, fscsr, so give them
|
|
// zero weight.
|
|
def : InstAlias<"frsr $rd", (CSRRS GPR:$rd, SysRegFCSR.Encoding, X0), 0>;
|
|
def : InstAlias<"fssr $rd, $rs", (CSRRW GPR:$rd, SysRegFCSR.Encoding, GPR:$rs), 0>;
|
|
def : InstAlias<"fssr $rs", (CSRRW X0, SysRegFCSR.Encoding, GPR:$rs), 0>;
|
|
|
|
def : InstAlias<"frrm $rd", (CSRRS GPR:$rd, SysRegFRM.Encoding, X0), 2>;
|
|
def : InstAlias<"fsrm $rd, $rs", (CSRRW GPR:$rd, SysRegFRM.Encoding, GPR:$rs)>;
|
|
def : InstAlias<"fsrm $rs", (CSRRW X0, SysRegFRM.Encoding, GPR:$rs), 2>;
|
|
def : InstAlias<"fsrmi $rd, $imm", (CSRRWI GPR:$rd, SysRegFRM.Encoding, uimm5:$imm)>;
|
|
def : InstAlias<"fsrmi $imm", (CSRRWI X0, SysRegFRM.Encoding, uimm5:$imm), 2>;
|
|
|
|
def : InstAlias<"frflags $rd", (CSRRS GPR:$rd, SysRegFFLAGS.Encoding, X0), 2>;
|
|
def : InstAlias<"fsflags $rd, $rs", (CSRRW GPR:$rd, SysRegFFLAGS.Encoding, GPR:$rs)>;
|
|
def : InstAlias<"fsflags $rs", (CSRRW X0, SysRegFFLAGS.Encoding, GPR:$rs), 2>;
|
|
def : InstAlias<"fsflagsi $rd, $imm", (CSRRWI GPR:$rd, SysRegFFLAGS.Encoding, uimm5:$imm)>;
|
|
def : InstAlias<"fsflagsi $imm", (CSRRWI X0, SysRegFFLAGS.Encoding, uimm5:$imm), 2>;
|
|
|
|
// fmv.w.x and fmv.x.w were previously known as fmv.s.x and fmv.x.s. Both
|
|
// spellings should be supported by standard tools.
|
|
def : MnemonicAlias<"fmv.s.x", "fmv.w.x">;
|
|
def : MnemonicAlias<"fmv.x.s", "fmv.x.w">;
|
|
|
|
def PseudoFLW : PseudoFloatLoad<"flw", FPR32>;
|
|
def PseudoFSW : PseudoStore<"fsw", FPR32>;
|
|
let usesCustomInserter = 1 in {
|
|
def PseudoQuietFLE_S : PseudoQuietFCMP<FPR32>;
|
|
def PseudoQuietFLT_S : PseudoQuietFCMP<FPR32>;
|
|
}
|
|
} // Predicates = [HasStdExtF]
|
|
|
|
let Predicates = [HasStdExtZfinx] in {
|
|
def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S_INX FPR32INX:$rd, FPR32INX:$rs, FPR32INX:$rs)>;
|
|
def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S_INX FPR32INX:$rd, FPR32INX:$rs, FPR32INX:$rs)>;
|
|
|
|
def : InstAlias<"fgt.s $rd, $rs, $rt",
|
|
(FLT_S_INX GPR:$rd, FPR32INX:$rt, FPR32INX:$rs), 0>;
|
|
def : InstAlias<"fge.s $rd, $rs, $rt",
|
|
(FLE_S_INX GPR:$rd, FPR32INX:$rt, FPR32INX:$rs), 0>;
|
|
} // Predicates = [HasStdExtZfinx]
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Pseudo-instructions and codegen patterns
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// Floating point constants
|
|
def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
|
|
def fpimmneg0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-0.0); }]>;
|
|
|
|
/// Generic pattern classes
|
|
class PatSetCC<RegisterClass Ty, SDPatternOperator OpNode, CondCode Cond, RVInst Inst>
|
|
: Pat<(OpNode Ty:$rs1, Ty:$rs2, Cond), (Inst $rs1, $rs2)>;
|
|
|
|
class PatFprFpr<SDPatternOperator OpNode, RVInstR Inst,
|
|
RegisterClass RegTy>
|
|
: Pat<(OpNode RegTy:$rs1, RegTy:$rs2), (Inst $rs1, $rs2)>;
|
|
|
|
class PatFprFprDynFrm<SDPatternOperator OpNode, RVInstRFrm Inst,
|
|
RegisterClass RegTy>
|
|
: Pat<(OpNode RegTy:$rs1, RegTy:$rs2), (Inst $rs1, $rs2, 0b111)>;
|
|
|
|
let Predicates = [HasStdExtF] in {
|
|
|
|
/// Float constants
|
|
def : Pat<(f32 (fpimm0)), (FMV_W_X X0)>;
|
|
def : Pat<(f32 (fpimmneg0)), (FSGNJN_S (FMV_W_X X0), (FMV_W_X X0))>;
|
|
|
|
/// Float conversion operations
|
|
|
|
// [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
|
|
// are defined later.
|
|
|
|
/// Float arithmetic operations
|
|
|
|
def : PatFprFprDynFrm<any_fadd, FADD_S, FPR32>;
|
|
def : PatFprFprDynFrm<any_fsub, FSUB_S, FPR32>;
|
|
def : PatFprFprDynFrm<any_fmul, FMUL_S, FPR32>;
|
|
def : PatFprFprDynFrm<any_fdiv, FDIV_S, FPR32>;
|
|
|
|
def : Pat<(any_fsqrt FPR32:$rs1), (FSQRT_S FPR32:$rs1, 0b111)>;
|
|
|
|
def : Pat<(fneg FPR32:$rs1), (FSGNJN_S $rs1, $rs1)>;
|
|
def : Pat<(fabs FPR32:$rs1), (FSGNJX_S $rs1, $rs1)>;
|
|
|
|
def : PatFprFpr<fcopysign, FSGNJ_S, FPR32>;
|
|
def : Pat<(fcopysign FPR32:$rs1, (fneg FPR32:$rs2)), (FSGNJN_S $rs1, $rs2)>;
|
|
|
|
// fmadd: rs1 * rs2 + rs3
|
|
def : Pat<(any_fma FPR32:$rs1, FPR32:$rs2, FPR32:$rs3),
|
|
(FMADD_S $rs1, $rs2, $rs3, 0b111)>;
|
|
|
|
// fmsub: rs1 * rs2 - rs3
|
|
def : Pat<(any_fma FPR32:$rs1, FPR32:$rs2, (fneg FPR32:$rs3)),
|
|
(FMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
|
|
|
|
// fnmsub: -rs1 * rs2 + rs3
|
|
def : Pat<(any_fma (fneg FPR32:$rs1), FPR32:$rs2, FPR32:$rs3),
|
|
(FNMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
|
|
|
|
// fnmadd: -rs1 * rs2 - rs3
|
|
def : Pat<(any_fma (fneg FPR32:$rs1), FPR32:$rs2, (fneg FPR32:$rs3)),
|
|
(FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
|
|
|
|
// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA)
|
|
def : Pat<(fneg (any_fma_nsz FPR32:$rs1, FPR32:$rs2, FPR32:$rs3)),
|
|
(FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
|
|
|
|
// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches
|
|
// LLVM's fminnum and fmaxnum
|
|
// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
|
|
def : PatFprFpr<fminnum, FMIN_S, FPR32>;
|
|
def : PatFprFpr<fmaxnum, FMAX_S, FPR32>;
|
|
|
|
/// Setcc
|
|
// FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
|
|
// strict versions of those.
|
|
|
|
// Match non-signaling FEQ_S
|
|
def : PatSetCC<FPR32, any_fsetcc, SETEQ, FEQ_S>;
|
|
def : PatSetCC<FPR32, any_fsetcc, SETOEQ, FEQ_S>;
|
|
def : PatSetCC<FPR32, strict_fsetcc, SETLT, PseudoQuietFLT_S>;
|
|
def : PatSetCC<FPR32, strict_fsetcc, SETOLT, PseudoQuietFLT_S>;
|
|
def : PatSetCC<FPR32, strict_fsetcc, SETLE, PseudoQuietFLE_S>;
|
|
def : PatSetCC<FPR32, strict_fsetcc, SETOLE, PseudoQuietFLE_S>;
|
|
|
|
// Match signaling FEQ_S
|
|
def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETEQ),
|
|
(AND (FLE_S $rs1, $rs2),
|
|
(FLE_S $rs2, $rs1))>;
|
|
def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETOEQ),
|
|
(AND (FLE_S $rs1, $rs2),
|
|
(FLE_S $rs2, $rs1))>;
|
|
// If both operands are the same, use a single FLE.
|
|
def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs1, SETEQ),
|
|
(FLE_S $rs1, $rs1)>;
|
|
def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs1, SETOEQ),
|
|
(FLE_S $rs1, $rs1)>;
|
|
|
|
def : PatSetCC<FPR32, any_fsetccs, SETLT, FLT_S>;
|
|
def : PatSetCC<FPR32, any_fsetccs, SETOLT, FLT_S>;
|
|
def : PatSetCC<FPR32, any_fsetccs, SETLE, FLE_S>;
|
|
def : PatSetCC<FPR32, any_fsetccs, SETOLE, FLE_S>;
|
|
|
|
defm Select_FPR32 : SelectCC_GPR_rrirr<FPR32>;
|
|
|
|
def PseudoFROUND_S : PseudoFROUND<FPR32>;
|
|
|
|
/// Loads
|
|
|
|
defm : UniformLdPat<load, FLW, f32>;
|
|
|
|
/// Stores
|
|
|
|
defm : UniformStPat<store, FSW, FPR32, f32>;
|
|
|
|
} // Predicates = [HasStdExtF]
|
|
|
|
let Predicates = [HasStdExtF, IsRV32] in {
|
|
// Moves (no conversion)
|
|
def : Pat<(bitconvert (i32 GPR:$rs1)), (FMV_W_X GPR:$rs1)>;
|
|
def : Pat<(i32 (bitconvert FPR32:$rs1)), (FMV_X_W FPR32:$rs1)>;
|
|
|
|
// float->[u]int. Round-to-zero must be used.
|
|
def : Pat<(i32 (any_fp_to_sint FPR32:$rs1)), (FCVT_W_S $rs1, 0b001)>;
|
|
def : Pat<(i32 (any_fp_to_uint FPR32:$rs1)), (FCVT_WU_S $rs1, 0b001)>;
|
|
|
|
// Saturating float->[u]int32.
|
|
def : Pat<(i32 (riscv_fcvt_x FPR32:$rs1, timm:$frm)), (FCVT_W_S $rs1, timm:$frm)>;
|
|
def : Pat<(i32 (riscv_fcvt_xu FPR32:$rs1, timm:$frm)), (FCVT_WU_S $rs1, timm:$frm)>;
|
|
|
|
// float->int32 with current rounding mode.
|
|
def : Pat<(i32 (any_lrint FPR32:$rs1)), (FCVT_W_S $rs1, 0b111)>;
|
|
|
|
// float->int32 rounded to nearest with ties rounded away from zero.
|
|
def : Pat<(i32 (any_lround FPR32:$rs1)), (FCVT_W_S $rs1, 0b100)>;
|
|
|
|
// [u]int->float. Match GCC and default to using dynamic rounding mode.
|
|
def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_S_W $rs1, 0b111)>;
|
|
def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_S_WU $rs1, 0b111)>;
|
|
} // Predicates = [HasStdExtF, IsRV32]
|
|
|
|
let Predicates = [HasStdExtF, IsRV64] in {
|
|
// Moves (no conversion)
|
|
def : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (FMV_W_X GPR:$src)>;
|
|
def : Pat<(riscv_fmv_x_anyextw_rv64 FPR32:$src), (FMV_X_W FPR32:$src)>;
|
|
def : Pat<(sext_inreg (riscv_fmv_x_anyextw_rv64 FPR32:$src), i32),
|
|
(FMV_X_W FPR32:$src)>;
|
|
|
|
// Use target specific isd nodes to help us remember the result is sign
|
|
// extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be
|
|
// duplicated if it has another user that didn't need the sign_extend.
|
|
def : Pat<(riscv_any_fcvt_w_rv64 FPR32:$rs1, timm:$frm), (FCVT_W_S $rs1, timm:$frm)>;
|
|
def : Pat<(riscv_any_fcvt_wu_rv64 FPR32:$rs1, timm:$frm), (FCVT_WU_S $rs1, timm:$frm)>;
|
|
|
|
// float->[u]int64. Round-to-zero must be used.
|
|
def : Pat<(i64 (any_fp_to_sint FPR32:$rs1)), (FCVT_L_S $rs1, 0b001)>;
|
|
def : Pat<(i64 (any_fp_to_uint FPR32:$rs1)), (FCVT_LU_S $rs1, 0b001)>;
|
|
|
|
// Saturating float->[u]int64.
|
|
def : Pat<(i64 (riscv_fcvt_x FPR32:$rs1, timm:$frm)), (FCVT_L_S $rs1, timm:$frm)>;
|
|
def : Pat<(i64 (riscv_fcvt_xu FPR32:$rs1, timm:$frm)), (FCVT_LU_S $rs1, timm:$frm)>;
|
|
|
|
// float->int64 with current rounding mode.
|
|
def : Pat<(i64 (any_lrint FPR32:$rs1)), (FCVT_L_S $rs1, 0b111)>;
|
|
def : Pat<(i64 (any_llrint FPR32:$rs1)), (FCVT_L_S $rs1, 0b111)>;
|
|
|
|
// float->int64 rounded to neartest with ties rounded away from zero.
|
|
def : Pat<(i64 (any_lround FPR32:$rs1)), (FCVT_L_S $rs1, 0b100)>;
|
|
def : Pat<(i64 (any_llround FPR32:$rs1)), (FCVT_L_S $rs1, 0b100)>;
|
|
|
|
// [u]int->fp. Match GCC and default to using dynamic rounding mode.
|
|
def : Pat<(any_sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_S_W $rs1, 0b111)>;
|
|
def : Pat<(any_uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_S_WU $rs1, 0b111)>;
|
|
def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_S_L $rs1, 0b111)>;
|
|
def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_S_LU $rs1, 0b111)>;
|
|
} // Predicates = [HasStdExtF, IsRV64]
|