432 lines
18 KiB
TableGen
432 lines
18 KiB
TableGen
//===-- RISCVInstrInfoD.td - RISC-V 'D' instructions -------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instructions from the standard 'D',
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// Double-Precision Floating-Point instruction set extension.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// RISC-V specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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def SDT_RISCVBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
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SDTCisVT<1, i32>,
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SDTCisSameAs<1, 2>]>;
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def SDT_RISCVSplitF64 : SDTypeProfile<2, 1, [SDTCisVT<0, i32>,
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SDTCisVT<1, i32>,
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SDTCisVT<2, f64>]>;
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def RISCVBuildPairF64 : SDNode<"RISCVISD::BuildPairF64", SDT_RISCVBuildPairF64>;
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def RISCVSplitF64 : SDNode<"RISCVISD::SplitF64", SDT_RISCVSplitF64>;
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//===----------------------------------------------------------------------===//
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// Operand and SDNode transformation definitions.
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//===----------------------------------------------------------------------===//
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// Zdinx
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def GPRPF64AsFPR : AsmOperandClass {
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let Name = "GPRPF64AsFPR";
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let ParserMethod = "parseGPRAsFPR";
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let RenderMethod = "addRegOperands";
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}
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def GPRF64AsFPR : AsmOperandClass {
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let Name = "GPRF64AsFPR";
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let ParserMethod = "parseGPRAsFPR";
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let RenderMethod = "addRegOperands";
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}
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def FPR64INX : RegisterOperand<GPRF64> {
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let ParserMatchClass = GPRF64AsFPR;
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let DecoderMethod = "DecodeGPRRegisterClass";
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}
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def FPR64IN32X : RegisterOperand<GPRPF64> {
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let ParserMatchClass = GPRPF64AsFPR;
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}
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def DExt : ExtInfo<0, [HasStdExtD]>;
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def D64Ext : ExtInfo<0, [HasStdExtD, IsRV64]>;
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def ZdinxExt : ExtInfo<1, [HasStdExtZdinx, IsRV64]>;
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def Zdinx32Ext : ExtInfo<2, [HasStdExtZdinx, IsRV32]>;
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def D : ExtInfo_r<DExt, FPR64>;
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def D_INX : ExtInfo_r<ZdinxExt, FPR64INX>;
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def D_IN32X : ExtInfo_r<Zdinx32Ext, FPR64IN32X>;
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def DD : ExtInfo_rr<DExt, FPR64, FPR64>;
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def DD_INX : ExtInfo_rr<ZdinxExt, FPR64INX, FPR64INX>;
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def DD_IN32X : ExtInfo_rr<Zdinx32Ext, FPR64IN32X, FPR64IN32X>;
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def DF : ExtInfo_rr<DExt, FPR64, FPR32>;
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def DF_INX : ExtInfo_rr<ZdinxExt, FPR64INX, FPR32INX>;
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def DF_IN32X : ExtInfo_rr<Zdinx32Ext, FPR64IN32X, FPR32INX>;
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def DX : ExtInfo_rr<DExt, FPR64, GPR>;
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def DX_INX : ExtInfo_rr<ZdinxExt, FPR64INX, GPR>;
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def DX_IN32X : ExtInfo_rr<Zdinx32Ext, FPR64IN32X, GPR>;
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def DX_64 : ExtInfo_rr<D64Ext, FPR64, GPR>;
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def FD : ExtInfo_rr<DExt, FPR32, FPR64>;
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def FD_INX : ExtInfo_rr<ZdinxExt, FPR32INX, FPR64INX>;
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def FD_IN32X : ExtInfo_rr<Zdinx32Ext, FPR32INX, FPR64IN32X>;
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def XD : ExtInfo_rr<DExt, GPR, FPR64>;
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def XD_INX : ExtInfo_rr<ZdinxExt, GPR, FPR64INX>;
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def XD_IN32X : ExtInfo_rr<Zdinx32Ext, GPR, FPR64IN32X>;
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def XD_64 : ExtInfo_rr<D64Ext, GPR, FPR64>;
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defvar DINX = [D, D_INX, D_IN32X];
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defvar DDINX = [DD, DD_INX, DD_IN32X];
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defvar DXINX = [DX, DX_INX, DX_IN32X];
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defvar DFINX = [DF, DF_INX, DF_IN32X];
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defvar FDINX = [FD, FD_INX, FD_IN32X];
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defvar XDINX = [XD, XD_INX, XD_IN32X];
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defvar DXIN64X = [DX_64, DX_INX];
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defvar XDIN64X = [XD_64, XD_INX];
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtD] in {
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def FLD : FPLoad_r<0b011, "fld", FPR64, WriteFLD64>;
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// Operands for stores are in the order srcreg, base, offset rather than
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// reflecting the order these fields are specified in the instruction
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// encoding.
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def FSD : FPStore_r<0b011, "fsd", FPR64, WriteFST64>;
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} // Predicates = [HasStdExtD]
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let SchedRW = [WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64] in {
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defm FMADD_D : FPFMA_rrr_frm_m<OPC_MADD, 0b01, "fmadd.d", DINX>;
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defm FMSUB_D : FPFMA_rrr_frm_m<OPC_MSUB, 0b01, "fmsub.d", DINX>;
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defm FNMSUB_D : FPFMA_rrr_frm_m<OPC_NMSUB, 0b01, "fnmsub.d", DINX>;
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defm FNMADD_D : FPFMA_rrr_frm_m<OPC_NMADD, 0b01, "fnmadd.d", DINX>;
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}
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defm : FPFMADynFrmAlias_m<FMADD_D, "fmadd.d", DINX>;
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defm : FPFMADynFrmAlias_m<FMSUB_D, "fmsub.d", DINX>;
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defm : FPFMADynFrmAlias_m<FNMSUB_D, "fnmsub.d", DINX>;
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defm : FPFMADynFrmAlias_m<FNMADD_D, "fnmadd.d", DINX>;
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let SchedRW = [WriteFAdd64, ReadFAdd64, ReadFAdd64] in {
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defm FADD_D : FPALU_rr_frm_m<0b0000001, "fadd.d", DINX, /*Commutable*/1>;
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defm FSUB_D : FPALU_rr_frm_m<0b0000101, "fsub.d", DINX>;
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}
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let SchedRW = [WriteFMul64, ReadFMul64, ReadFMul64] in
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defm FMUL_D : FPALU_rr_frm_m<0b0001001, "fmul.d", DINX, /*Commutable*/1>;
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let SchedRW = [WriteFDiv64, ReadFDiv64, ReadFDiv64] in
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defm FDIV_D : FPALU_rr_frm_m<0b0001101, "fdiv.d", DINX>;
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defm : FPALUDynFrmAlias_m<FADD_D, "fadd.d", DINX>;
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defm : FPALUDynFrmAlias_m<FSUB_D, "fsub.d", DINX>;
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defm : FPALUDynFrmAlias_m<FMUL_D, "fmul.d", DINX>;
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defm : FPALUDynFrmAlias_m<FDIV_D, "fdiv.d", DINX>;
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defm FSQRT_D : FPUnaryOp_r_frm_m<0b0101101, 0b00000, DDINX, "fsqrt.d">,
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Sched<[WriteFSqrt64, ReadFSqrt64]>;
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defm : FPUnaryOpDynFrmAlias_m<FSQRT_D, "fsqrt.d", DDINX>;
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let SchedRW = [WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64],
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mayRaiseFPException = 0 in {
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defm FSGNJ_D : FPALU_rr_m<0b0010001, 0b000, "fsgnj.d", DINX>;
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defm FSGNJN_D : FPALU_rr_m<0b0010001, 0b001, "fsgnjn.d", DINX>;
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defm FSGNJX_D : FPALU_rr_m<0b0010001, 0b010, "fsgnjx.d", DINX>;
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}
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let SchedRW = [WriteFMinMax64, ReadFMinMax64, ReadFMinMax64] in {
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defm FMIN_D : FPALU_rr_m<0b0010101, 0b000, "fmin.d", DINX, /*Commutable*/1>;
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defm FMAX_D : FPALU_rr_m<0b0010101, 0b001, "fmax.d", DINX, /*Commutable*/1>;
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}
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defm FCVT_S_D : FPUnaryOp_r_frm_m<0b0100000, 0b00001, FDINX, "fcvt.s.d">,
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Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]>;
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defm : FPUnaryOpDynFrmAlias_m<FCVT_S_D, "fcvt.s.d", FDINX>;
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defm FCVT_D_S : FPUnaryOp_r_m<0b0100001, 0b00000, 0b000, DFINX, "fcvt.d.s">,
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Sched<[WriteFCvtF32ToF64, ReadFCvtF32ToF64]>;
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let SchedRW = [WriteFCmp64, ReadFCmp64, ReadFCmp64] in {
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defm FEQ_D : FPCmp_rr_m<0b1010001, 0b010, "feq.d", DINX, /*Commutable*/1>;
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defm FLT_D : FPCmp_rr_m<0b1010001, 0b001, "flt.d", DINX>;
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defm FLE_D : FPCmp_rr_m<0b1010001, 0b000, "fle.d", DINX>;
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}
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defm FCLASS_D : FPUnaryOp_r_m<0b1110001, 0b00000, 0b001, XDINX, "fclass.d">,
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Sched<[WriteFClass64, ReadFClass64]>;
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defm FCVT_W_D : FPUnaryOp_r_frm_m<0b1100001, 0b00000, XDINX, "fcvt.w.d">,
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Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>;
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defm : FPUnaryOpDynFrmAlias_m<FCVT_W_D, "fcvt.w.d", XDINX>;
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defm FCVT_WU_D : FPUnaryOp_r_frm_m<0b1100001, 0b00001, XDINX, "fcvt.wu.d">,
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Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>;
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defm : FPUnaryOpDynFrmAlias_m<FCVT_WU_D, "fcvt.wu.d", XDINX>;
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defm FCVT_D_W : FPUnaryOp_r_m<0b1101001, 0b00000, 0b000, DXINX, "fcvt.d.w">,
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Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]>;
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defm FCVT_D_WU : FPUnaryOp_r_m<0b1101001, 0b00001, 0b000, DXINX, "fcvt.d.wu">,
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Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]>;
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defm FCVT_L_D : FPUnaryOp_r_frm_m<0b1100001, 0b00010, XDIN64X, "fcvt.l.d">,
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Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>;
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defm : FPUnaryOpDynFrmAlias_m<FCVT_L_D, "fcvt.l.d", XDIN64X>;
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defm FCVT_LU_D : FPUnaryOp_r_frm_m<0b1100001, 0b00011, XDIN64X, "fcvt.lu.d">,
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Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>;
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defm : FPUnaryOpDynFrmAlias_m<FCVT_LU_D, "fcvt.lu.d", XDIN64X>;
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let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in
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def FMV_X_D : FPUnaryOp_r<0b1110001, 0b00000, 0b000, GPR, FPR64, "fmv.x.d">,
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Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]>;
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defm FCVT_D_L : FPUnaryOp_r_frm_m<0b1101001, 0b00010, DXIN64X, "fcvt.d.l">,
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Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>;
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defm : FPUnaryOpDynFrmAlias_m<FCVT_D_L, "fcvt.d.l", DXIN64X>;
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defm FCVT_D_LU : FPUnaryOp_r_frm_m<0b1101001, 0b00011, DXIN64X, "fcvt.d.lu">,
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Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>;
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defm : FPUnaryOpDynFrmAlias_m<FCVT_D_LU, "fcvt.d.lu", DXIN64X>;
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let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in
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def FMV_D_X : FPUnaryOp_r<0b1111001, 0b00000, 0b000, FPR64, GPR, "fmv.d.x">,
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Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64]>;
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//===----------------------------------------------------------------------===//
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// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtD] in {
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def : InstAlias<"fld $rd, (${rs1})", (FLD FPR64:$rd, GPR:$rs1, 0), 0>;
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def : InstAlias<"fsd $rs2, (${rs1})", (FSD FPR64:$rs2, GPR:$rs1, 0), 0>;
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def : InstAlias<"fmv.d $rd, $rs", (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
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def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
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def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
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// fgt.d/fge.d are recognised by the GNU assembler but the canonical
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// flt.d/fle.d forms will always be printed. Therefore, set a zero weight.
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def : InstAlias<"fgt.d $rd, $rs, $rt",
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(FLT_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
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def : InstAlias<"fge.d $rd, $rs, $rt",
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(FLE_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
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def PseudoFLD : PseudoFloatLoad<"fld", FPR64>;
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def PseudoFSD : PseudoStore<"fsd", FPR64>;
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let usesCustomInserter = 1 in {
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def PseudoQuietFLE_D : PseudoQuietFCMP<FPR64>;
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def PseudoQuietFLT_D : PseudoQuietFCMP<FPR64>;
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}
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} // Predicates = [HasStdExtD]
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let Predicates = [HasStdExtZdinx, IsRV64] in {
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def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D_INX FPR64INX:$rd, FPR64INX:$rs, FPR64INX:$rs)>;
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def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D_INX FPR64INX:$rd, FPR64INX:$rs, FPR64INX:$rs)>;
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def : InstAlias<"fgt.d $rd, $rs, $rt",
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(FLT_D_INX GPR:$rd, FPR64INX:$rt, FPR64INX:$rs), 0>;
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def : InstAlias<"fge.d $rd, $rs, $rt",
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(FLE_D_INX GPR:$rd, FPR64INX:$rt, FPR64INX:$rs), 0>;
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} // Predicates = [HasStdExtZdinx, IsRV64]
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let Predicates = [HasStdExtZdinx, IsRV32] in {
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def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D_IN32X FPR64IN32X:$rd, FPR64IN32X:$rs, FPR64IN32X:$rs)>;
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def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D_IN32X FPR64IN32X:$rd, FPR64IN32X:$rs, FPR64IN32X:$rs)>;
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def : InstAlias<"fgt.d $rd, $rs, $rt",
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(FLT_D_IN32X GPR:$rd, FPR64IN32X:$rt, FPR64IN32X:$rs), 0>;
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def : InstAlias<"fge.d $rd, $rs, $rt",
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(FLE_D_IN32X GPR:$rd, FPR64IN32X:$rt, FPR64IN32X:$rs), 0>;
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} // Predicates = [HasStdExtZdinx, IsRV32]
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//===----------------------------------------------------------------------===//
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// Pseudo-instructions and codegen patterns
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtD] in {
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/// Float conversion operations
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// f64 -> f32, f32 -> f64
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def : Pat<(any_fpround FPR64:$rs1), (FCVT_S_D FPR64:$rs1, 0b111)>;
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def : Pat<(any_fpextend FPR32:$rs1), (FCVT_D_S FPR32:$rs1)>;
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// [u]int<->double conversion patterns must be gated on IsRV32 or IsRV64, so
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// are defined later.
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/// Float arithmetic operations
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def : PatFprFprDynFrm<any_fadd, FADD_D, FPR64>;
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def : PatFprFprDynFrm<any_fsub, FSUB_D, FPR64>;
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def : PatFprFprDynFrm<any_fmul, FMUL_D, FPR64>;
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def : PatFprFprDynFrm<any_fdiv, FDIV_D, FPR64>;
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def : Pat<(any_fsqrt FPR64:$rs1), (FSQRT_D FPR64:$rs1, 0b111)>;
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def : Pat<(fneg FPR64:$rs1), (FSGNJN_D $rs1, $rs1)>;
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def : Pat<(fabs FPR64:$rs1), (FSGNJX_D $rs1, $rs1)>;
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def : PatFprFpr<fcopysign, FSGNJ_D, FPR64>;
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def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)), (FSGNJN_D $rs1, $rs2)>;
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def : Pat<(fcopysign FPR64:$rs1, FPR32:$rs2), (FSGNJ_D $rs1, (FCVT_D_S $rs2))>;
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def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D $rs2,
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0b111))>;
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// fmadd: rs1 * rs2 + rs3
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def : Pat<(any_fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3),
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(FMADD_D $rs1, $rs2, $rs3, 0b111)>;
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// fmsub: rs1 * rs2 - rs3
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def : Pat<(any_fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)),
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(FMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
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// fnmsub: -rs1 * rs2 + rs3
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def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, FPR64:$rs3),
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(FNMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
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// fnmadd: -rs1 * rs2 - rs3
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def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, (fneg FPR64:$rs3)),
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(FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
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// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA)
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def : Pat<(fneg (any_fma_nsz FPR64:$rs1, FPR64:$rs2, FPR64:$rs3)),
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(FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
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// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches
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// LLVM's fminnum and fmaxnum.
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// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
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def : PatFprFpr<fminnum, FMIN_D, FPR64>;
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def : PatFprFpr<fmaxnum, FMAX_D, FPR64>;
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/// Setcc
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// FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
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// strict versions of those.
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// Match non-signaling FEQ_D
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def : PatSetCC<FPR64, any_fsetcc, SETEQ, FEQ_D>;
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def : PatSetCC<FPR64, any_fsetcc, SETOEQ, FEQ_D>;
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def : PatSetCC<FPR64, strict_fsetcc, SETLT, PseudoQuietFLT_D>;
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def : PatSetCC<FPR64, strict_fsetcc, SETOLT, PseudoQuietFLT_D>;
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def : PatSetCC<FPR64, strict_fsetcc, SETLE, PseudoQuietFLE_D>;
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def : PatSetCC<FPR64, strict_fsetcc, SETOLE, PseudoQuietFLE_D>;
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// Match signaling FEQ_D
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def : Pat<(strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETEQ),
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(AND (FLE_D $rs1, $rs2),
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(FLE_D $rs2, $rs1))>;
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def : Pat<(strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETOEQ),
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(AND (FLE_D $rs1, $rs2),
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(FLE_D $rs2, $rs1))>;
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// If both operands are the same, use a single FLE.
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def : Pat<(strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETEQ),
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(FLE_D $rs1, $rs1)>;
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def : Pat<(strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETOEQ),
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(FLE_D $rs1, $rs1)>;
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def : PatSetCC<FPR64, any_fsetccs, SETLT, FLT_D>;
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def : PatSetCC<FPR64, any_fsetccs, SETOLT, FLT_D>;
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def : PatSetCC<FPR64, any_fsetccs, SETLE, FLE_D>;
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def : PatSetCC<FPR64, any_fsetccs, SETOLE, FLE_D>;
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defm Select_FPR64 : SelectCC_GPR_rrirr<FPR64>;
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def PseudoFROUND_D : PseudoFROUND<FPR64>;
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/// Loads
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defm : UniformLdPat<load, FLD, f64>;
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/// Stores
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defm : UniformStPat<store, FSD, FPR64, f64>;
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/// Pseudo-instructions needed for the soft-float ABI with RV32D
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// Moves two GPRs to an FPR.
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let usesCustomInserter = 1 in
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def BuildPairF64Pseudo
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: Pseudo<(outs FPR64:$dst), (ins GPR:$src1, GPR:$src2),
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[(set FPR64:$dst, (RISCVBuildPairF64 GPR:$src1, GPR:$src2))]>;
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// Moves an FPR to two GPRs.
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let usesCustomInserter = 1 in
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def SplitF64Pseudo
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: Pseudo<(outs GPR:$dst1, GPR:$dst2), (ins FPR64:$src),
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[(set GPR:$dst1, GPR:$dst2, (RISCVSplitF64 FPR64:$src))]>;
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} // Predicates = [HasStdExtD]
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let Predicates = [HasStdExtD, IsRV32] in {
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/// Float constants
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def : Pat<(f64 (fpimm0)), (FCVT_D_W (i32 X0))>;
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def : Pat<(f64 (fpimmneg0)), (FSGNJN_D (FCVT_D_W (i32 X0)),
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(FCVT_D_W (i32 X0)))>;
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// double->[u]int. Round-to-zero must be used.
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def : Pat<(i32 (any_fp_to_sint FPR64:$rs1)), (FCVT_W_D FPR64:$rs1, 0b001)>;
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def : Pat<(i32 (any_fp_to_uint FPR64:$rs1)), (FCVT_WU_D FPR64:$rs1, 0b001)>;
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// Saturating double->[u]int32.
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def : Pat<(i32 (riscv_fcvt_x FPR64:$rs1, timm:$frm)), (FCVT_W_D $rs1, timm:$frm)>;
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def : Pat<(i32 (riscv_fcvt_xu FPR64:$rs1, timm:$frm)), (FCVT_WU_D $rs1, timm:$frm)>;
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// float->int32 with current rounding mode.
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def : Pat<(i32 (any_lrint FPR64:$rs1)), (FCVT_W_D $rs1, 0b111)>;
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// float->int32 rounded to nearest with ties rounded away from zero.
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def : Pat<(i32 (any_lround FPR64:$rs1)), (FCVT_W_D $rs1, 0b100)>;
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// [u]int->double.
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def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_D_W GPR:$rs1)>;
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def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_D_WU GPR:$rs1)>;
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} // Predicates = [HasStdExtD, IsRV32]
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let Predicates = [HasStdExtD, IsRV64] in {
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/// Float constants
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def : Pat<(f64 (fpimm0)), (FMV_D_X (i64 X0))>;
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def : Pat<(f64 (fpimmneg0)), (FSGNJN_D (FMV_D_X (i64 X0)),
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(FMV_D_X (i64 X0)))>;
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// Moves (no conversion)
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def : Pat<(bitconvert (i64 GPR:$rs1)), (FMV_D_X GPR:$rs1)>;
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def : Pat<(i64 (bitconvert FPR64:$rs1)), (FMV_X_D FPR64:$rs1)>;
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// Use target specific isd nodes to help us remember the result is sign
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// extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be
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// duplicated if it has another user that didn't need the sign_extend.
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def : Pat<(riscv_any_fcvt_w_rv64 FPR64:$rs1, timm:$frm), (FCVT_W_D $rs1, timm:$frm)>;
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def : Pat<(riscv_any_fcvt_wu_rv64 FPR64:$rs1, timm:$frm), (FCVT_WU_D $rs1, timm:$frm)>;
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// [u]int32->fp
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def : Pat<(any_sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_D_W $rs1)>;
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def : Pat<(any_uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_D_WU $rs1)>;
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// Saturating double->[u]int64.
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def : Pat<(i64 (riscv_fcvt_x FPR64:$rs1, timm:$frm)), (FCVT_L_D $rs1, timm:$frm)>;
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def : Pat<(i64 (riscv_fcvt_xu FPR64:$rs1, timm:$frm)), (FCVT_LU_D $rs1, timm:$frm)>;
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// double->[u]int64. Round-to-zero must be used.
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def : Pat<(i64 (any_fp_to_sint FPR64:$rs1)), (FCVT_L_D FPR64:$rs1, 0b001)>;
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def : Pat<(i64 (any_fp_to_uint FPR64:$rs1)), (FCVT_LU_D FPR64:$rs1, 0b001)>;
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// double->int64 with current rounding mode.
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def : Pat<(i64 (any_lrint FPR64:$rs1)), (FCVT_L_D $rs1, 0b111)>;
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def : Pat<(i64 (any_llrint FPR64:$rs1)), (FCVT_L_D $rs1, 0b111)>;
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// double->int64 rounded to nearest with ties rounded away from zero.
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def : Pat<(i64 (any_lround FPR64:$rs1)), (FCVT_L_D $rs1, 0b100)>;
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def : Pat<(i64 (any_llround FPR64:$rs1)), (FCVT_L_D $rs1, 0b100)>;
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// [u]int64->fp. Match GCC and default to using dynamic rounding mode.
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def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_D_L GPR:$rs1, 0b111)>;
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def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_D_LU GPR:$rs1, 0b111)>;
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} // Predicates = [HasStdExtD, IsRV64]
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