420 lines
15 KiB
C++
420 lines
15 KiB
C++
//===- RISCVMatInt.cpp - Immediate materialisation -------------*- C++ -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVMatInt.h"
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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static int getInstSeqCost(RISCVMatInt::InstSeq &Res, bool HasRVC) {
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if (!HasRVC)
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return Res.size();
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int Cost = 0;
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for (auto Instr : Res) {
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// Assume instructions that aren't listed aren't compressible.
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bool Compressed = false;
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switch (Instr.Opc) {
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case RISCV::SLLI:
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case RISCV::SRLI:
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Compressed = true;
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break;
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case RISCV::ADDI:
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case RISCV::ADDIW:
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case RISCV::LUI:
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Compressed = isInt<6>(Instr.Imm);
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break;
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}
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// Two RVC instructions take the same space as one RVI instruction, but
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// can take longer to execute than the single RVI instruction. Thus, we
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// consider that two RVC instruction are slightly more costly than one
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// RVI instruction. For longer sequences of RVC instructions the space
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// savings can be worth it, though. The costs below try to model that.
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if (!Compressed)
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Cost += 100; // Baseline cost of one RVI instruction: 100%.
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else
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Cost += 70; // 70% cost of baseline.
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}
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return Cost;
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}
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// Recursively generate a sequence for materializing an integer.
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static void generateInstSeqImpl(int64_t Val,
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const FeatureBitset &ActiveFeatures,
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RISCVMatInt::InstSeq &Res) {
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bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit];
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if (isInt<32>(Val)) {
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// Depending on the active bits in the immediate Value v, the following
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// instruction sequences are emitted:
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//
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// v == 0 : ADDI
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// v[0,12) != 0 && v[12,32) == 0 : ADDI
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// v[0,12) == 0 && v[12,32) != 0 : LUI
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// v[0,32) != 0 : LUI+ADDI(W)
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int64_t Hi20 = ((Val + 0x800) >> 12) & 0xFFFFF;
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int64_t Lo12 = SignExtend64<12>(Val);
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if (Hi20)
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Res.emplace_back(RISCV::LUI, Hi20);
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if (Lo12 || Hi20 == 0) {
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unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI;
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Res.emplace_back(AddiOpc, Lo12);
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}
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return;
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}
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assert(IsRV64 && "Can't emit >32-bit imm for non-RV64 target");
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// Use BSETI for a single bit.
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if (ActiveFeatures[RISCV::FeatureStdExtZbs] && isPowerOf2_64(Val)) {
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Res.emplace_back(RISCV::BSETI, Log2_64(Val));
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return;
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}
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// In the worst case, for a full 64-bit constant, a sequence of 8 instructions
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// (i.e., LUI+ADDIW+SLLI+ADDI+SLLI+ADDI+SLLI+ADDI) has to be emitted. Note
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// that the first two instructions (LUI+ADDIW) can contribute up to 32 bits
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// while the following ADDI instructions contribute up to 12 bits each.
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//
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// On the first glance, implementing this seems to be possible by simply
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// emitting the most significant 32 bits (LUI+ADDIW) followed by as many left
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// shift (SLLI) and immediate additions (ADDI) as needed. However, due to the
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// fact that ADDI performs a sign extended addition, doing it like that would
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// only be possible when at most 11 bits of the ADDI instructions are used.
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// Using all 12 bits of the ADDI instructions, like done by GAS, actually
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// requires that the constant is processed starting with the least significant
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// bit.
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//
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// In the following, constants are processed from LSB to MSB but instruction
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// emission is performed from MSB to LSB by recursively calling
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// generateInstSeq. In each recursion, first the lowest 12 bits are removed
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// from the constant and the optimal shift amount, which can be greater than
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// 12 bits if the constant is sparse, is determined. Then, the shifted
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// remaining constant is processed recursively and gets emitted as soon as it
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// fits into 32 bits. The emission of the shifts and additions is subsequently
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// performed when the recursion returns.
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int64_t Lo12 = SignExtend64<12>(Val);
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Val = (uint64_t)Val - (uint64_t)Lo12;
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int ShiftAmount = 0;
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bool Unsigned = false;
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// Val might now be valid for LUI without needing a shift.
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if (!isInt<32>(Val)) {
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ShiftAmount = findFirstSet((uint64_t)Val);
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Val >>= ShiftAmount;
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// If the remaining bits don't fit in 12 bits, we might be able to reduce the
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// shift amount in order to use LUI which will zero the lower 12 bits.
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if (ShiftAmount > 12 && !isInt<12>(Val)) {
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if (isInt<32>((uint64_t)Val << 12)) {
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// Reduce the shift amount and add zeros to the LSBs so it will match LUI.
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ShiftAmount -= 12;
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Val = (uint64_t)Val << 12;
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} else if (isUInt<32>((uint64_t)Val << 12) &&
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ActiveFeatures[RISCV::FeatureStdExtZba]) {
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// Reduce the shift amount and add zeros to the LSBs so it will match
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// LUI, then shift left with SLLI.UW to clear the upper 32 set bits.
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ShiftAmount -= 12;
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Val = ((uint64_t)Val << 12) | (0xffffffffull << 32);
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Unsigned = true;
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}
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}
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// Try to use SLLI_UW for Val when it is uint32 but not int32.
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if (isUInt<32>((uint64_t)Val) && !isInt<32>((uint64_t)Val) &&
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ActiveFeatures[RISCV::FeatureStdExtZba]) {
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// Use LUI+ADDI or LUI to compose, then clear the upper 32 bits with
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// SLLI_UW.
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Val = ((uint64_t)Val) | (0xffffffffull << 32);
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Unsigned = true;
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}
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}
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generateInstSeqImpl(Val, ActiveFeatures, Res);
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// Skip shift if we were able to use LUI directly.
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if (ShiftAmount) {
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unsigned Opc = Unsigned ? RISCV::SLLI_UW : RISCV::SLLI;
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Res.emplace_back(Opc, ShiftAmount);
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}
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if (Lo12)
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Res.emplace_back(RISCV::ADDI, Lo12);
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}
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static unsigned extractRotateInfo(int64_t Val) {
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// for case: 0b111..1..xxxxxx1..1..
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unsigned LeadingOnes = countLeadingOnes((uint64_t)Val);
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unsigned TrailingOnes = countTrailingOnes((uint64_t)Val);
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if (TrailingOnes > 0 && TrailingOnes < 64 &&
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(LeadingOnes + TrailingOnes) > (64 - 12))
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return 64 - TrailingOnes;
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// for case: 0bxxx1..1..1...xxx
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unsigned UpperTrailingOnes = countTrailingOnes(Hi_32(Val));
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unsigned LowerLeadingOnes = countLeadingOnes(Lo_32(Val));
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if (UpperTrailingOnes < 32 &&
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(UpperTrailingOnes + LowerLeadingOnes) > (64 - 12))
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return 32 - UpperTrailingOnes;
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return 0;
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}
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namespace llvm::RISCVMatInt {
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InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
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RISCVMatInt::InstSeq Res;
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generateInstSeqImpl(Val, ActiveFeatures, Res);
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// If there are trailing zeros, try generating a sign extended constant with
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// no trailing zeros and use a final SLLI to restore them.
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if ((Val & 1) == 0 && Res.size() > 2) {
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unsigned TrailingZeros = countTrailingZeros((uint64_t)Val);
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int64_t ShiftedVal = Val >> TrailingZeros;
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RISCVMatInt::InstSeq TmpSeq;
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generateInstSeqImpl(ShiftedVal, ActiveFeatures, TmpSeq);
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TmpSeq.emplace_back(RISCV::SLLI, TrailingZeros);
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// Keep the new sequence if it is an improvement.
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if (TmpSeq.size() < Res.size()) {
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Res = TmpSeq;
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// A 2 instruction sequence is the best we can do.
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if (Res.size() <= 2)
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return Res;
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}
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}
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// If the constant is positive we might be able to generate a shifted constant
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// with no leading zeros and use a final SRLI to restore them.
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if (Val > 0 && Res.size() > 2) {
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assert(ActiveFeatures[RISCV::Feature64Bit] &&
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"Expected RV32 to only need 2 instructions");
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unsigned LeadingZeros = countLeadingZeros((uint64_t)Val);
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uint64_t ShiftedVal = (uint64_t)Val << LeadingZeros;
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// Fill in the bits that will be shifted out with 1s. An example where this
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// helps is trailing one masks with 32 or more ones. This will generate
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// ADDI -1 and an SRLI.
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ShiftedVal |= maskTrailingOnes<uint64_t>(LeadingZeros);
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RISCVMatInt::InstSeq TmpSeq;
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generateInstSeqImpl(ShiftedVal, ActiveFeatures, TmpSeq);
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TmpSeq.emplace_back(RISCV::SRLI, LeadingZeros);
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// Keep the new sequence if it is an improvement.
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if (TmpSeq.size() < Res.size()) {
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Res = TmpSeq;
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// A 2 instruction sequence is the best we can do.
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if (Res.size() <= 2)
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return Res;
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}
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// Some cases can benefit from filling the lower bits with zeros instead.
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ShiftedVal &= maskTrailingZeros<uint64_t>(LeadingZeros);
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TmpSeq.clear();
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generateInstSeqImpl(ShiftedVal, ActiveFeatures, TmpSeq);
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TmpSeq.emplace_back(RISCV::SRLI, LeadingZeros);
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// Keep the new sequence if it is an improvement.
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if (TmpSeq.size() < Res.size()) {
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Res = TmpSeq;
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// A 2 instruction sequence is the best we can do.
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if (Res.size() <= 2)
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return Res;
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}
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// If we have exactly 32 leading zeros and Zba, we can try using zext.w at
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// the end of the sequence.
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if (LeadingZeros == 32 && ActiveFeatures[RISCV::FeatureStdExtZba]) {
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// Try replacing upper bits with 1.
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uint64_t LeadingOnesVal = Val | maskLeadingOnes<uint64_t>(LeadingZeros);
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TmpSeq.clear();
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generateInstSeqImpl(LeadingOnesVal, ActiveFeatures, TmpSeq);
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TmpSeq.emplace_back(RISCV::ADD_UW, 0);
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// Keep the new sequence if it is an improvement.
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if (TmpSeq.size() < Res.size()) {
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Res = TmpSeq;
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// A 2 instruction sequence is the best we can do.
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if (Res.size() <= 2)
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return Res;
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}
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}
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}
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// Perform optimization with BCLRI/BSETI in the Zbs extension.
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if (Res.size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZbs]) {
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assert(ActiveFeatures[RISCV::Feature64Bit] &&
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"Expected RV32 to only need 2 instructions");
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// 1. For values in range 0xffffffff 7fffffff ~ 0xffffffff 00000000,
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// call generateInstSeqImpl with Val|0x80000000 (which is expected be
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// an int32), then emit (BCLRI r, 31).
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// 2. For values in range 0x80000000 ~ 0xffffffff, call generateInstSeqImpl
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// with Val&~0x80000000 (which is expected to be an int32), then
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// emit (BSETI r, 31).
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int64_t NewVal;
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unsigned Opc;
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if (Val < 0) {
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Opc = RISCV::BCLRI;
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NewVal = Val | 0x80000000ll;
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} else {
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Opc = RISCV::BSETI;
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NewVal = Val & ~0x80000000ll;
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}
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if (isInt<32>(NewVal)) {
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RISCVMatInt::InstSeq TmpSeq;
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generateInstSeqImpl(NewVal, ActiveFeatures, TmpSeq);
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TmpSeq.emplace_back(Opc, 31);
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if (TmpSeq.size() < Res.size())
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Res = TmpSeq;
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}
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// Try to use BCLRI for upper 32 bits if the original lower 32 bits are
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// negative int32, or use BSETI for upper 32 bits if the original lower
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// 32 bits are positive int32.
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int32_t Lo = Lo_32(Val);
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uint32_t Hi = Hi_32(Val);
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Opc = 0;
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RISCVMatInt::InstSeq TmpSeq;
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generateInstSeqImpl(Lo, ActiveFeatures, TmpSeq);
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// Check if it is profitable to use BCLRI/BSETI.
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if (Lo > 0 && TmpSeq.size() + countPopulation(Hi) < Res.size()) {
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Opc = RISCV::BSETI;
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} else if (Lo < 0 && TmpSeq.size() + countPopulation(~Hi) < Res.size()) {
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Opc = RISCV::BCLRI;
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Hi = ~Hi;
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}
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// Search for each bit and build corresponding BCLRI/BSETI.
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if (Opc > 0) {
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while (Hi != 0) {
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unsigned Bit = findFirstSet(Hi, ZB_Undefined);
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TmpSeq.emplace_back(Opc, Bit + 32);
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Hi &= (Hi - 1); // Clear lowest set bit.
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}
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if (TmpSeq.size() < Res.size())
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Res = TmpSeq;
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}
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}
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// Perform optimization with SH*ADD in the Zba extension.
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if (Res.size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZba]) {
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assert(ActiveFeatures[RISCV::Feature64Bit] &&
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"Expected RV32 to only need 2 instructions");
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int64_t Div = 0;
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unsigned Opc = 0;
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RISCVMatInt::InstSeq TmpSeq;
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// Select the opcode and divisor.
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if ((Val % 3) == 0 && isInt<32>(Val / 3)) {
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Div = 3;
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Opc = RISCV::SH1ADD;
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} else if ((Val % 5) == 0 && isInt<32>(Val / 5)) {
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Div = 5;
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Opc = RISCV::SH2ADD;
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} else if ((Val % 9) == 0 && isInt<32>(Val / 9)) {
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Div = 9;
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Opc = RISCV::SH3ADD;
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}
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// Build the new instruction sequence.
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if (Div > 0) {
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generateInstSeqImpl(Val / Div, ActiveFeatures, TmpSeq);
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TmpSeq.emplace_back(Opc, 0);
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if (TmpSeq.size() < Res.size())
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Res = TmpSeq;
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} else {
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// Try to use LUI+SH*ADD+ADDI.
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int64_t Hi52 = ((uint64_t)Val + 0x800ull) & ~0xfffull;
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int64_t Lo12 = SignExtend64<12>(Val);
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Div = 0;
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if (isInt<32>(Hi52 / 3) && (Hi52 % 3) == 0) {
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Div = 3;
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Opc = RISCV::SH1ADD;
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} else if (isInt<32>(Hi52 / 5) && (Hi52 % 5) == 0) {
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Div = 5;
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Opc = RISCV::SH2ADD;
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} else if (isInt<32>(Hi52 / 9) && (Hi52 % 9) == 0) {
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Div = 9;
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Opc = RISCV::SH3ADD;
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}
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// Build the new instruction sequence.
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if (Div > 0) {
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// For Val that has zero Lo12 (implies Val equals to Hi52) should has
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// already been processed to LUI+SH*ADD by previous optimization.
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assert(Lo12 != 0 &&
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"unexpected instruction sequence for immediate materialisation");
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assert(TmpSeq.empty() && "Expected empty TmpSeq");
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generateInstSeqImpl(Hi52 / Div, ActiveFeatures, TmpSeq);
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TmpSeq.emplace_back(Opc, 0);
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TmpSeq.emplace_back(RISCV::ADDI, Lo12);
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if (TmpSeq.size() < Res.size())
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Res = TmpSeq;
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}
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}
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}
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// Perform optimization with rori in the Zbb extension.
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if (Res.size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZbb]) {
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if (unsigned Rotate = extractRotateInfo(Val)) {
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RISCVMatInt::InstSeq TmpSeq;
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uint64_t NegImm12 =
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((uint64_t)Val >> (64 - Rotate)) | ((uint64_t)Val << Rotate);
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assert(isInt<12>(NegImm12));
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TmpSeq.emplace_back(RISCV::ADDI, NegImm12);
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TmpSeq.emplace_back(RISCV::RORI, Rotate);
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Res = TmpSeq;
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}
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}
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return Res;
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}
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int getIntMatCost(const APInt &Val, unsigned Size,
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const FeatureBitset &ActiveFeatures, bool CompressionCost) {
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bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit];
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bool HasRVC = CompressionCost && ActiveFeatures[RISCV::FeatureStdExtC];
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int PlatRegSize = IsRV64 ? 64 : 32;
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// Split the constant into platform register sized chunks, and calculate cost
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// of each chunk.
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int Cost = 0;
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for (unsigned ShiftVal = 0; ShiftVal < Size; ShiftVal += PlatRegSize) {
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APInt Chunk = Val.ashr(ShiftVal).sextOrTrunc(PlatRegSize);
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InstSeq MatSeq = generateInstSeq(Chunk.getSExtValue(), ActiveFeatures);
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Cost += getInstSeqCost(MatSeq, HasRVC);
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}
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return std::max(1, Cost);
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}
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OpndKind Inst::getOpndKind() const {
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switch (Opc) {
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default:
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llvm_unreachable("Unexpected opcode!");
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case RISCV::LUI:
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return RISCVMatInt::Imm;
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case RISCV::ADD_UW:
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return RISCVMatInt::RegX0;
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case RISCV::SH1ADD:
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case RISCV::SH2ADD:
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case RISCV::SH3ADD:
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return RISCVMatInt::RegReg;
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case RISCV::ADDI:
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case RISCV::ADDIW:
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case RISCV::SLLI:
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case RISCV::SRLI:
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case RISCV::SLLI_UW:
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case RISCV::RORI:
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case RISCV::BSETI:
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case RISCV::BCLRI:
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return RISCVMatInt::RegImm;
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}
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}
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} // namespace llvm::RISCVMatInt
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