145 lines
6.0 KiB
TableGen
145 lines
6.0 KiB
TableGen
//- DXIL.td - Describe DXIL operation -------------------------*- tablegen -*-//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This is a target description file for DXIL operation.
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///
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//===----------------------------------------------------------------------===//
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include "llvm/IR/Intrinsics.td"
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class dxil_class<string _name> {
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string name = _name;
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}
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class dxil_category<string _name> {
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string name = _name;
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}
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def Unary : dxil_class<"Unary">;
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def Binary : dxil_class<"Binary">;
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def FlattenedThreadIdInGroupClass : dxil_class<"FlattenedThreadIdInGroup">;
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def ThreadIdInGroupClass : dxil_class<"ThreadIdInGroup">;
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def ThreadIdClass : dxil_class<"ThreadId">;
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def GroupIdClass : dxil_class<"GroupId">;
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def binary_uint : dxil_category<"Binary uint">;
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def unary_float : dxil_category<"Unary float">;
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def ComputeID : dxil_category<"Compute/Mesh/Amplification shader">;
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// The parameter description for a DXIL instruction
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class dxil_param<int _pos, string type, string _name, string _doc,
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bit _is_const = 0, string _enum_name = "",
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int _max_value = 0> {
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int pos = _pos; // position in parameter list
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string llvm_type = type; // llvm type name, $o for overload, $r for resource
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// type, $cb for legacy cbuffer, $u4 for u4 struct
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string name = _name; // short, unique name
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string doc = _doc; // the documentation description of this parameter
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bit is_const =
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_is_const; // whether this argument requires a constant value in the IR
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string enum_name = _enum_name; // the name of the enum type if applicable
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int max_value =
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_max_value; // the maximum value for this parameter if applicable
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}
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// A representation for a DXIL instruction
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class dxil_inst<string _name> {
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string name = _name; // short, unique name
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string dxil_op = ""; // name of DXIL operation
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int dxil_opid = 0; // ID of DXIL operation
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dxil_class op_class; // name of the opcode class
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dxil_category category; // classification for this instruction
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string doc = ""; // the documentation description of this instruction
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list<dxil_param> ops = []; // the operands that this instruction takes
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string oload_types = ""; // overload types if applicable
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string fn_attr = ""; // attribute shorthands: rn=does not access
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// memory,ro=only reads from memory,
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bit is_deriv = 0; // whether this is some kind of derivative
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bit is_gradient = 0; // whether this requires a gradient calculation
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bit is_feedback = 0; // whether this is a sampler feedback op
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bit is_wave = 0; // whether this requires in-wave, cross-lane functionality
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bit requires_uniform_inputs = 0; // whether this operation requires that all
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// of its inputs are uniform across the wave
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// Group dxil operation for stats.
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// Like how many atomic/float/uint/int/... instructions used in the program.
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list<string> stats_group = [];
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}
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class dxil_op<string name, int code_id, dxil_class code_class, dxil_category op_category, string _doc,
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string _oload_types, string _fn_attr, list<dxil_param> op_params,
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list<string> _stats_group = []> : dxil_inst<name> {
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let dxil_op = name;
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let dxil_opid = code_id;
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let doc = _doc;
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let ops = op_params;
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let op_class = code_class;
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let category = op_category;
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let oload_types = _oload_types;
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let fn_attr = _fn_attr;
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let stats_group = _stats_group;
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}
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// The intrinsic which map directly to this dxil op.
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class dxil_map_intrinsic<Intrinsic llvm_intrinsic_> { Intrinsic llvm_intrinsic = llvm_intrinsic_; }
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def Sin : dxil_op<"Sin", 13, Unary, unary_float, "returns sine(theta) for theta in radians.",
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"half;float;", "rn",
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[
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dxil_param<0, "$o", "", "operation result">,
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dxil_param<1, "i32", "opcode", "DXIL opcode">,
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dxil_param<2, "$o", "value", "input value">
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],
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["floats"]>,
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dxil_map_intrinsic<int_sin>;
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def UMax :dxil_op< "UMax", 39, Binary, binary_uint, "unsigned integer maximum. UMax(a,b) = a > b ? a : b",
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"i16;i32;i64;", "rn",
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[
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dxil_param<0, "$o", "", "operation result">,
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dxil_param<1, "i32", "opcode", "DXIL opcode">,
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dxil_param<2, "$o", "a", "input value">,
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dxil_param<3, "$o", "b", "input value">
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],
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["uints"]>,
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dxil_map_intrinsic<int_umax>;
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def ThreadId :dxil_op< "ThreadId", 93, ThreadIdClass, ComputeID, "reads the thread ID", "i32;", "rn",
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[
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dxil_param<0, "i32", "", "thread ID component">,
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dxil_param<1, "i32", "opcode", "DXIL opcode">,
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dxil_param<2, "i32", "component", "component to read (x,y,z)">
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]>,
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dxil_map_intrinsic<int_dx_thread_id>;
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def GroupId :dxil_op< "GroupId", 94, GroupIdClass, ComputeID, "reads the group ID (SV_GroupID)", "i32;", "rn",
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[
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dxil_param<0, "i32", "", "group ID component">,
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dxil_param<1, "i32", "opcode", "DXIL opcode">,
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dxil_param<2, "i32", "component", "component to read">
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]>,
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dxil_map_intrinsic<int_dx_group_id>;
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def ThreadIdInGroup :dxil_op< "ThreadIdInGroup", 95, ThreadIdInGroupClass, ComputeID,
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"reads the thread ID within the group (SV_GroupThreadID)", "i32;", "rn",
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[
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dxil_param<0, "i32", "", "thread ID in group component">,
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dxil_param<1, "i32", "opcode", "DXIL opcode">,
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dxil_param<2, "i32", "component", "component to read (x,y,z)">
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]>,
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dxil_map_intrinsic<int_dx_thread_id_in_group>;
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def FlattenedThreadIdInGroup :dxil_op< "FlattenedThreadIdInGroup", 96, FlattenedThreadIdInGroupClass, ComputeID,
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"provides a flattened index for a given thread within a given group (SV_GroupIndex)", "i32;", "rn",
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[
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dxil_param<0, "i32", "", "result">,
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dxil_param<1, "i32", "opcode", "DXIL opcode">
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]>,
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dxil_map_intrinsic<int_dx_flattened_thread_id_in_group>;
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