274 lines
9.4 KiB
C++
274 lines
9.4 KiB
C++
//===-- RISCVInstructions.h -----------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLDB_SOURCE_PLUGINS_INSTRUCTION_RISCV_RISCVINSTRUCTION_H
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#define LLDB_SOURCE_PLUGINS_INSTRUCTION_RISCV_RISCVINSTRUCTION_H
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#include <cstdint>
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#include <variant>
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#include "llvm/ADT/APFloat.h"
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#include "llvm/ADT/Optional.h"
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namespace lldb_private {
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class EmulateInstructionRISCV;
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struct Rd {
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uint32_t rd;
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bool Write(EmulateInstructionRISCV &emulator, uint64_t value);
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bool WriteAPFloat(EmulateInstructionRISCV &emulator, llvm::APFloat value);
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};
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struct Rs {
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uint32_t rs;
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llvm::Optional<uint64_t> Read(EmulateInstructionRISCV &emulator);
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llvm::Optional<int32_t> ReadI32(EmulateInstructionRISCV &emulator);
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llvm::Optional<int64_t> ReadI64(EmulateInstructionRISCV &emulator);
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llvm::Optional<uint32_t> ReadU32(EmulateInstructionRISCV &emulator);
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llvm::Optional<llvm::APFloat> ReadAPFloat(EmulateInstructionRISCV &emulator,
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bool isDouble);
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};
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#define I_TYPE_INST(NAME) \
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struct NAME { \
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Rd rd; \
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Rs rs1; \
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uint32_t imm; \
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}
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#define S_TYPE_INST(NAME) \
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struct NAME { \
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Rs rs1; \
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Rs rs2; \
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uint32_t imm; \
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}
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#define U_TYPE_INST(NAME) \
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struct NAME { \
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Rd rd; \
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uint32_t imm; \
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}
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/// The memory layout are the same in our code.
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#define J_TYPE_INST(NAME) U_TYPE_INST(NAME)
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#define R_TYPE_INST(NAME) \
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struct NAME { \
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Rd rd; \
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Rs rs1; \
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Rs rs2; \
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}
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#define R_SHAMT_TYPE_INST(NAME) \
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struct NAME { \
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Rd rd; \
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Rs rs1; \
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uint32_t shamt; \
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}
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#define R_RS1_TYPE_INST(NAME) \
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struct NAME { \
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Rd rd; \
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Rs rs1; \
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}
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#define R4_TYPE_INST(NAME) \
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struct NAME { \
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Rd rd; \
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Rs rs1; \
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Rs rs2; \
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Rs rs3; \
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int32_t rm; \
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}
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/// The `inst` fields are used for debugging.
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#define INVALID_INST(NAME) \
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struct NAME { \
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uint32_t inst; \
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}
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// RV32I instructions (The base integer ISA)
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struct B {
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Rs rs1;
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Rs rs2;
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uint32_t imm;
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uint32_t funct3;
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};
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U_TYPE_INST(LUI);
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U_TYPE_INST(AUIPC);
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J_TYPE_INST(JAL);
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I_TYPE_INST(JALR);
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I_TYPE_INST(LB);
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I_TYPE_INST(LH);
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I_TYPE_INST(LW);
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I_TYPE_INST(LBU);
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I_TYPE_INST(LHU);
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S_TYPE_INST(SB);
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S_TYPE_INST(SH);
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S_TYPE_INST(SW);
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I_TYPE_INST(ADDI);
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I_TYPE_INST(SLTI);
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I_TYPE_INST(SLTIU);
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I_TYPE_INST(XORI);
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I_TYPE_INST(ORI);
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I_TYPE_INST(ANDI);
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R_TYPE_INST(ADD);
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R_TYPE_INST(SUB);
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R_TYPE_INST(SLL);
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R_TYPE_INST(SLT);
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R_TYPE_INST(SLTU);
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R_TYPE_INST(XOR);
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R_TYPE_INST(SRL);
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R_TYPE_INST(SRA);
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R_TYPE_INST(OR);
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R_TYPE_INST(AND);
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// RV64I inst (The base integer ISA)
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I_TYPE_INST(LWU);
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I_TYPE_INST(LD);
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S_TYPE_INST(SD);
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R_SHAMT_TYPE_INST(SLLI);
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R_SHAMT_TYPE_INST(SRLI);
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R_SHAMT_TYPE_INST(SRAI);
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I_TYPE_INST(ADDIW);
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R_SHAMT_TYPE_INST(SLLIW);
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R_SHAMT_TYPE_INST(SRLIW);
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R_SHAMT_TYPE_INST(SRAIW);
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R_TYPE_INST(ADDW);
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R_TYPE_INST(SUBW);
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R_TYPE_INST(SLLW);
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R_TYPE_INST(SRLW);
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R_TYPE_INST(SRAW);
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// RV32M inst (The standard integer multiplication and division extension)
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R_TYPE_INST(MUL);
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R_TYPE_INST(MULH);
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R_TYPE_INST(MULHSU);
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R_TYPE_INST(MULHU);
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R_TYPE_INST(DIV);
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R_TYPE_INST(DIVU);
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R_TYPE_INST(REM);
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R_TYPE_INST(REMU);
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// RV64M inst (The standard integer multiplication and division extension)
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R_TYPE_INST(MULW);
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R_TYPE_INST(DIVW);
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R_TYPE_INST(DIVUW);
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R_TYPE_INST(REMW);
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R_TYPE_INST(REMUW);
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// RV32A inst (The standard atomic instruction extension)
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R_RS1_TYPE_INST(LR_W);
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R_TYPE_INST(SC_W);
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R_TYPE_INST(AMOSWAP_W);
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R_TYPE_INST(AMOADD_W);
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R_TYPE_INST(AMOXOR_W);
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R_TYPE_INST(AMOAND_W);
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R_TYPE_INST(AMOOR_W);
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R_TYPE_INST(AMOMIN_W);
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R_TYPE_INST(AMOMAX_W);
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R_TYPE_INST(AMOMINU_W);
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R_TYPE_INST(AMOMAXU_W);
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// RV64A inst (The standard atomic instruction extension)
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R_RS1_TYPE_INST(LR_D);
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R_TYPE_INST(SC_D);
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R_TYPE_INST(AMOSWAP_D);
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R_TYPE_INST(AMOADD_D);
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R_TYPE_INST(AMOXOR_D);
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R_TYPE_INST(AMOAND_D);
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R_TYPE_INST(AMOOR_D);
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R_TYPE_INST(AMOMIN_D);
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R_TYPE_INST(AMOMAX_D);
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R_TYPE_INST(AMOMINU_D);
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R_TYPE_INST(AMOMAXU_D);
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// RV32F inst (The standard single-precision floating-point extension)
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I_TYPE_INST(FLW);
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S_TYPE_INST(FSW);
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R4_TYPE_INST(FMADD_S);
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R4_TYPE_INST(FMSUB_S);
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R4_TYPE_INST(FNMADD_S);
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R4_TYPE_INST(FNMSUB_S);
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R_TYPE_INST(FADD_S);
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R_TYPE_INST(FSUB_S);
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R_TYPE_INST(FMUL_S);
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R_TYPE_INST(FDIV_S);
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R_TYPE_INST(FSQRT_S);
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R_TYPE_INST(FSGNJ_S);
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R_TYPE_INST(FSGNJN_S);
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R_TYPE_INST(FSGNJX_S);
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R_TYPE_INST(FMIN_S);
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R_TYPE_INST(FMAX_S);
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R_TYPE_INST(FCVT_W_S);
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R_TYPE_INST(FCVT_WU_S);
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R_TYPE_INST(FMV_X_W);
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R_TYPE_INST(FEQ_S);
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R_TYPE_INST(FLT_S);
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R_TYPE_INST(FLE_S);
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R_TYPE_INST(FCLASS_S);
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R_TYPE_INST(FCVT_S_W);
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R_TYPE_INST(FCVT_S_WU);
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R_TYPE_INST(FMV_W_X);
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/// Invalid and reserved instructions, the `inst` fields are used for debugging.
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INVALID_INST(INVALID);
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INVALID_INST(RESERVED);
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INVALID_INST(EBREAK);
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INVALID_INST(HINT);
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INVALID_INST(NOP);
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using RISCVInst = std::variant<
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LUI, AUIPC, JAL, JALR, B, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI,
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SLTIU, XORI, ORI, ANDI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND,
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LWU, LD, SD, SLLI, SRLI, SRAI, ADDIW, SLLIW, SRLIW, SRAIW, ADDW, SUBW, SLLW,
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SRLW, SRAW, MUL, MULH, MULHSU, MULHU, DIV, DIVU, REM, REMU, MULW, DIVW,
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DIVUW, REMW, REMUW, LR_W, SC_W, AMOSWAP_W, AMOADD_W, AMOXOR_W, AMOAND_W,
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AMOOR_W, AMOMIN_W, AMOMAX_W, AMOMINU_W, AMOMAXU_W, LR_D, SC_D, AMOSWAP_D,
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AMOADD_D, AMOXOR_D, AMOAND_D, AMOOR_D, AMOMIN_D, AMOMAX_D, AMOMINU_D,
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AMOMAXU_D, FLW, FSW, FMADD_S, FMSUB_S, FNMADD_S, FNMSUB_S, FADD_S, FSUB_S,
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FMUL_S, FDIV_S, FSQRT_S, FSGNJ_S, FSGNJN_S, FSGNJX_S, FMIN_S, FMAX_S,
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FCVT_W_S, FCVT_WU_S, FMV_X_W, FEQ_S, FLT_S, FLE_S, FCLASS_S, FCVT_S_W,
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FCVT_S_WU, FMV_W_X, INVALID, EBREAK, RESERVED, HINT, NOP>;
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struct InstrPattern {
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const char *name;
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/// Bit mask to check the type of a instruction (B-Type, I-Type, J-Type, etc.)
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uint32_t type_mask;
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/// Characteristic value after bitwise-and with type_mask.
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uint32_t eigen;
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RISCVInst (*decode)(uint32_t inst);
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};
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struct DecodeResult {
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RISCVInst decoded;
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uint32_t inst;
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bool is_rvc;
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InstrPattern pattern;
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};
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constexpr uint32_t DecodeRD(uint32_t inst) { return (inst & 0xF80) >> 7; }
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constexpr uint32_t DecodeRS1(uint32_t inst) { return (inst & 0xF8000) >> 15; }
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constexpr uint32_t DecodeRS2(uint32_t inst) { return (inst & 0x1F00000) >> 20; }
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constexpr uint32_t DecodeRS3(uint32_t inst) {
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return (inst & 0xF0000000) >> 27;
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}
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constexpr uint32_t DecodeFunct3(uint32_t inst) { return (inst & 0x7000) >> 12; }
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constexpr uint32_t DecodeFunct2(uint32_t inst) {
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return (inst & 0xE000000) >> 25;
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}
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constexpr uint32_t DecodeFunct7(uint32_t inst) {
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return (inst & 0xFE000000) >> 25;
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}
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constexpr int32_t DecodeRM(uint32_t inst) { return DecodeFunct3(inst); }
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/// RISC-V spec: The upper bits of a valid NaN-boxed value must be all 1s.
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constexpr uint64_t NanBoxing(uint64_t val) {
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return val | 0xFFFF'FFFF'0000'0000;
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}
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constexpr uint32_t NanUnBoxing(uint64_t val) {
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return val & (~0xFFFF'FFFF'0000'0000);
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}
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} // namespace lldb_private
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#endif // LLDB_SOURCE_PLUGINS_INSTRUCTION_RISCV_RISCVINSTRUCTION_H
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