106 lines
3.4 KiB
C++
106 lines
3.4 KiB
C++
//===-- EmulateInstructionRISCV.h -----------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLDB_SOURCE_PLUGINS_INSTRUCTION_RISCV_EMULATEINSTRUCTIONRISCV_H
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#define LLDB_SOURCE_PLUGINS_INSTRUCTION_RISCV_EMULATEINSTRUCTIONRISCV_H
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#include "RISCVInstructions.h"
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#include "lldb/Core/EmulateInstruction.h"
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#include "lldb/Interpreter/OptionValue.h"
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#include "lldb/Utility/Log.h"
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#include "lldb/Utility/RegisterValue.h"
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#include "lldb/Utility/Status.h"
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namespace lldb_private {
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class EmulateInstructionRISCV : public EmulateInstruction {
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public:
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static llvm::StringRef GetPluginNameStatic() { return "riscv"; }
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static llvm::StringRef GetPluginDescriptionStatic() {
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return "Emulate instructions for the RISC-V architecture.";
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}
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static bool SupportsThisInstructionType(InstructionType inst_type) {
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switch (inst_type) {
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case eInstructionTypeAny:
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case eInstructionTypePCModifying:
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return true;
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case eInstructionTypePrologueEpilogue:
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case eInstructionTypeAll:
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return false;
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}
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llvm_unreachable("Fully covered switch above!");
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}
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static bool SupportsThisArch(const ArchSpec &arch);
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static lldb_private::EmulateInstruction *
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CreateInstance(const lldb_private::ArchSpec &arch, InstructionType inst_type);
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static void Initialize();
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static void Terminate();
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public:
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EmulateInstructionRISCV(const ArchSpec &arch) : EmulateInstruction(arch) {}
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llvm::StringRef GetPluginName() override { return GetPluginNameStatic(); }
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bool SupportsEmulatingInstructionsOfType(InstructionType inst_type) override {
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return SupportsThisInstructionType(inst_type);
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}
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bool SetTargetTriple(const ArchSpec &arch) override;
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bool ReadInstruction() override;
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bool EvaluateInstruction(uint32_t options) override;
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bool TestEmulation(Stream *out_stream, ArchSpec &arch,
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OptionValueDictionary *test_data) override;
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llvm::Optional<RegisterInfo> GetRegisterInfo(lldb::RegisterKind reg_kind,
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uint32_t reg_num) override;
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llvm::Optional<lldb::addr_t> ReadPC();
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bool WritePC(lldb::addr_t pc);
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llvm::Optional<DecodeResult> ReadInstructionAt(lldb::addr_t addr);
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llvm::Optional<DecodeResult> Decode(uint32_t inst);
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bool Execute(DecodeResult inst, bool ignore_cond);
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template <typename T>
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std::enable_if_t<std::is_integral_v<T>, llvm::Optional<T>>
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ReadMem(uint64_t addr) {
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EmulateInstructionRISCV::Context ctx;
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ctx.type = EmulateInstruction::eContextRegisterLoad;
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ctx.SetNoArgs();
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bool success = false;
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T result = ReadMemoryUnsigned(ctx, addr, sizeof(T), T(), &success);
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if (!success)
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return {}; // aka return false
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return result;
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}
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template <typename T> bool WriteMem(uint64_t addr, uint64_t value) {
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EmulateInstructionRISCV::Context ctx;
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ctx.type = EmulateInstruction::eContextRegisterStore;
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ctx.SetNoArgs();
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return WriteMemoryUnsigned(ctx, addr, value, sizeof(T));
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}
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llvm::RoundingMode GetRoundingMode();
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bool SetAccruedExceptions(llvm::APFloatBase::opStatus);
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private:
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/// Last decoded instruction from m_opcode
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DecodeResult m_decoded;
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};
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} // namespace lldb_private
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#endif // LLDB_SOURCE_PLUGINS_INSTRUCTION_RISCV_EMULATEINSTRUCTIONRISCV_H
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