39 lines
1.4 KiB
C
39 lines
1.4 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -triple riscv32 -target-feature +zbb -emit-llvm %s -o - \
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// RUN: | FileCheck %s -check-prefix=RV32ZBB
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// RV32ZBB-LABEL: @orc_b_32(
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// RV32ZBB-NEXT: entry:
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// RV32ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
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// RV32ZBB-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
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// RV32ZBB-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
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// RV32ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[TMP0]])
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// RV32ZBB-NEXT: ret i32 [[TMP1]]
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//
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int orc_b_32(int a) {
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return __builtin_riscv_orc_b_32(a);
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}
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// RV32ZBB-LABEL: @clz_32(
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// RV32ZBB-NEXT: entry:
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// RV32ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
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// RV32ZBB-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
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// RV32ZBB-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
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// RV32ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
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// RV32ZBB-NEXT: ret i32 [[TMP1]]
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//
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int clz_32(int a) {
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return __builtin_riscv_clz_32(a);
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}
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// RV32ZBB-LABEL: @ctz_32(
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// RV32ZBB-NEXT: entry:
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// RV32ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
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// RV32ZBB-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
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// RV32ZBB-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
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// RV32ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
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// RV32ZBB-NEXT: ret i32 [[TMP1]]
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//
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int ctz_32(int a) {
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return __builtin_riscv_ctz_32(a);
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} |