210 lines
7.8 KiB
C++
210 lines
7.8 KiB
C++
//===--- LoongArch.cpp - Implement LoongArch target feature support -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements LoongArch TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#include "LoongArch.h"
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#include "clang/Basic/Diagnostic.h"
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#include "clang/Basic/MacroBuilder.h"
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#include "clang/Basic/TargetBuiltins.h"
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#include "llvm/Support/TargetParser.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace clang;
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using namespace clang::targets;
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ArrayRef<const char *> LoongArchTargetInfo::getGCCRegNames() const {
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static const char *const GCCRegNames[] = {
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// General purpose registers.
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"$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", "$r8", "$r9",
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"$r10", "$r11", "$r12", "$r13", "$r14", "$r15", "$r16", "$r17", "$r18",
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"$r19", "$r20", "$r21", "$r22", "$r23", "$r24", "$r25", "$r26", "$r27",
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"$r28", "$r29", "$r30", "$r31",
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// Floating point registers.
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"$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", "$f9",
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"$f10", "$f11", "$f12", "$f13", "$f14", "$f15", "$f16", "$f17", "$f18",
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"$f19", "$f20", "$f21", "$f22", "$f23", "$f24", "$f25", "$f26", "$f27",
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"$f28", "$f29", "$f30", "$f31"};
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return llvm::makeArrayRef(GCCRegNames);
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}
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ArrayRef<TargetInfo::GCCRegAlias>
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LoongArchTargetInfo::getGCCRegAliases() const {
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static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
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{{"$zero"}, "$r0"}, {{"$ra"}, "$r1"}, {{"$tp"}, "$r2"},
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{{"$sp"}, "$r3"}, {{"$a0"}, "$r4"}, {{"$a1"}, "$r5"},
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{{"$a2"}, "$r6"}, {{"$a3"}, "$r7"}, {{"$a4"}, "$r8"},
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{{"$a5"}, "$r9"}, {{"$a6"}, "$r10"}, {{"$a7"}, "$r11"},
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{{"$t0"}, "$r12"}, {{"$t1"}, "$r13"}, {{"$t2"}, "$r14"},
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{{"$t3"}, "$r15"}, {{"$t4"}, "$r16"}, {{"$t5"}, "$r17"},
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{{"$t6"}, "$r18"}, {{"$t7"}, "$r19"}, {{"$t8"}, "$r20"},
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{{"$fp", "$s9"}, "$r22"}, {{"$s0"}, "$r23"}, {{"$s1"}, "$r24"},
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{{"$s2"}, "$r25"}, {{"$s3"}, "$r26"}, {{"$s4"}, "$r27"},
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{{"$s5"}, "$r28"}, {{"$s6"}, "$r29"}, {{"$s7"}, "$r30"},
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{{"$s8"}, "$r31"}, {{"$fa0"}, "$f0"}, {{"$fa1"}, "$f1"},
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{{"$fa2"}, "$f2"}, {{"$fa3"}, "$f3"}, {{"$fa4"}, "$f4"},
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{{"$fa5"}, "$f5"}, {{"$fa6"}, "$f6"}, {{"$fa7"}, "$f7"},
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{{"$ft0"}, "$f8"}, {{"$ft1"}, "$f9"}, {{"$ft2"}, "$f10"},
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{{"$ft3"}, "$f11"}, {{"$ft4"}, "$f12"}, {{"$ft5"}, "$f13"},
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{{"$ft6"}, "$f14"}, {{"$ft7"}, "$f15"}, {{"$ft8"}, "$f16"},
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{{"$ft9"}, "$f17"}, {{"$ft10"}, "$f18"}, {{"$ft11"}, "$f19"},
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{{"$ft12"}, "$f20"}, {{"$ft13"}, "$f21"}, {{"$ft14"}, "$f22"},
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{{"$ft15"}, "$f23"}, {{"$fs0"}, "$f24"}, {{"$fs1"}, "$f25"},
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{{"$fs2"}, "$f26"}, {{"$fs3"}, "$f27"}, {{"$fs4"}, "$f28"},
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{{"$fs5"}, "$f29"}, {{"$fs6"}, "$f30"}, {{"$fs7"}, "$f31"},
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};
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return llvm::makeArrayRef(GCCRegAliases);
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}
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bool LoongArchTargetInfo::validateAsmConstraint(
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const char *&Name, TargetInfo::ConstraintInfo &Info) const {
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// See the GCC definitions here:
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// https://gcc.gnu.org/onlinedocs/gccint/Machine-Constraints.html
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// Note that the 'm' constraint is handled in TargetInfo.
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switch (*Name) {
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default:
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return false;
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case 'f':
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// A floating-point register (if available).
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Info.setAllowsRegister();
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return true;
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case 'k':
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// A memory operand whose address is formed by a base register and
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// (optionally scaled) index register.
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Info.setAllowsMemory();
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return true;
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case 'l':
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// A signed 16-bit constant.
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Info.setRequiresImmediate(-32768, 32767);
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return true;
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case 'I':
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// A signed 12-bit constant (for arithmetic instructions).
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Info.setRequiresImmediate(-2048, 2047);
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return true;
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case 'J':
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// Integer zero.
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Info.setRequiresImmediate(0);
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return true;
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case 'K':
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// An unsigned 12-bit constant (for logic instructions).
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Info.setRequiresImmediate(0, 4095);
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return true;
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case 'Z':
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// ZB: An address that is held in a general-purpose register. The offset is
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// zero.
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// ZC: A memory operand whose address is formed by a base register
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// and offset that is suitable for use in instructions with the same
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// addressing mode as ll.w and sc.w.
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if (Name[1] == 'C' || Name[1] == 'B') {
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Info.setAllowsMemory();
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++Name; // Skip over 'Z'.
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return true;
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}
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return false;
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}
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}
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std::string
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LoongArchTargetInfo::convertConstraint(const char *&Constraint) const {
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std::string R;
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switch (*Constraint) {
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case 'Z':
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// "ZC"/"ZB" are two-character constraints; add "^" hint for later
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// parsing.
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R = "^" + std::string(Constraint, 2);
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++Constraint;
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break;
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default:
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R = TargetInfo::convertConstraint(Constraint);
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break;
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}
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return R;
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}
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void LoongArchTargetInfo::getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const {
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Builder.defineMacro("__loongarch__");
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unsigned GRLen = getRegisterWidth();
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Builder.defineMacro("__loongarch_grlen", Twine(GRLen));
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if (GRLen == 64)
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Builder.defineMacro("__loongarch64");
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if (HasFeatureD)
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Builder.defineMacro("__loongarch_frlen", "64");
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else if (HasFeatureF)
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Builder.defineMacro("__loongarch_frlen", "32");
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else
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Builder.defineMacro("__loongarch_frlen", "0");
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// TODO: define __loongarch_arch and __loongarch_tune.
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StringRef ABI = getABI();
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if (ABI == "lp64d" || ABI == "lp64f" || ABI == "lp64s")
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Builder.defineMacro("__loongarch_lp64");
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if (ABI == "lp64d" || ABI == "ilp32d") {
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Builder.defineMacro("__loongarch_hard_float");
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Builder.defineMacro("__loongarch_double_float");
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} else if (ABI == "lp64f" || ABI == "ilp32f") {
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Builder.defineMacro("__loongarch_hard_float");
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Builder.defineMacro("__loongarch_single_float");
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} else if (ABI == "lp64s" || ABI == "ilp32s") {
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Builder.defineMacro("__loongarch_soft_float");
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}
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}
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const Builtin::Info LoongArchTargetInfo::BuiltinInfo[] = {
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#define BUILTIN(ID, TYPE, ATTRS) \
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{#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
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#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
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{#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
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#include "clang/Basic/BuiltinsLoongArch.def"
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};
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bool LoongArchTargetInfo::initFeatureMap(
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llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
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const std::vector<std::string> &FeaturesVec) const {
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if (getTriple().getArch() == llvm::Triple::loongarch64)
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Features["64bit"] = true;
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return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
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}
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/// Return true if has this feature.
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bool LoongArchTargetInfo::hasFeature(StringRef Feature) const {
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bool Is64Bit = getTriple().getArch() == llvm::Triple::loongarch64;
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// TODO: Handle more features.
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return llvm::StringSwitch<bool>(Feature)
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.Case("loongarch32", !Is64Bit)
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.Case("loongarch64", Is64Bit)
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.Case("32bit", !Is64Bit)
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.Case("64bit", Is64Bit)
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.Default(false);
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}
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ArrayRef<Builtin::Info> LoongArchTargetInfo::getTargetBuiltins() const {
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return llvm::makeArrayRef(BuiltinInfo, clang::LoongArch::LastTSBuiltin -
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Builtin::FirstTSBuiltin);
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}
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bool LoongArchTargetInfo::handleTargetFeatures(
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std::vector<std::string> &Features, DiagnosticsEngine &Diags) {
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for (const auto &Feature : Features) {
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if (Feature == "+d" || Feature == "+f") {
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// "d" implies "f".
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HasFeatureF = true;
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if (Feature == "+d") {
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HasFeatureD = true;
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}
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}
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}
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return true;
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}
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