57 lines
1.5 KiB
Verilog
57 lines
1.5 KiB
Verilog
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module array_6_ext(
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input W0_clk,
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input [8:0] W0_addr,
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input W0_en,
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input [15:0] W0_data,
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input [7:0] W0_mask,
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input R0_clk,
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input [8:0] R0_addr,
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input R0_en,
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output [15:0] R0_data
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);
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reg reg_R0_ren;
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reg [8:0] reg_R0_addr;
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reg [15:0] ram [511:0];
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`ifdef RANDOMIZE_MEM_INIT
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integer initvar;
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initial begin
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#`RANDOMIZE_DELAY begin end
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for (initvar = 0; initvar < 512; initvar = initvar+1)
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ram[initvar] = {1 {$random}};
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reg_R0_addr = {1 {$random}};
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end
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`endif
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integer i;
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always @(posedge R0_clk)
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reg_R0_ren <= R0_en;
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always @(posedge R0_clk)
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if (R0_en) reg_R0_addr <= R0_addr;
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always @(posedge W0_clk)
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if (W0_en) begin
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if (W0_mask[0]) ram[W0_addr][1:0] <= W0_data[1:0];
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if (W0_mask[1]) ram[W0_addr][3:2] <= W0_data[3:2];
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if (W0_mask[2]) ram[W0_addr][5:4] <= W0_data[5:4];
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if (W0_mask[3]) ram[W0_addr][7:6] <= W0_data[7:6];
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if (W0_mask[4]) ram[W0_addr][9:8] <= W0_data[9:8];
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if (W0_mask[5]) ram[W0_addr][11:10] <= W0_data[11:10];
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if (W0_mask[6]) ram[W0_addr][13:12] <= W0_data[13:12];
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if (W0_mask[7]) ram[W0_addr][15:14] <= W0_data[15:14];
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end
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`ifdef RANDOMIZE_GARBAGE_ASSIGN
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reg [31:0] R0_random;
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`ifdef RANDOMIZE_MEM_INIT
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initial begin
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#`RANDOMIZE_DELAY begin end
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R0_random = {$random};
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reg_R0_ren = R0_random[0];
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end
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`endif
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always @(posedge R0_clk) R0_random <= {$random};
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assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[15:0];
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`else
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assign R0_data = ram[reg_R0_addr];
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`endif
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endmodule |