52 lines
1.4 KiB
Verilog
52 lines
1.4 KiB
Verilog
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module array_3_ext(
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input RW0_clk,
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input [8:0] RW0_addr,
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input RW0_en,
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input RW0_wmode,
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input [3:0] RW0_wmask,
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input [319:0] RW0_wdata,
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output [319:0] RW0_rdata
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);
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reg reg_RW0_ren;
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reg [8:0] reg_RW0_addr;
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reg [319:0] ram [511:0];
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`ifdef RANDOMIZE_MEM_INIT
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integer initvar;
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initial begin
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#`RANDOMIZE_DELAY begin end
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for (initvar = 0; initvar < 512; initvar = initvar+1)
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ram[initvar] = {10 {$random}};
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reg_RW0_addr = {1 {$random}};
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end
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`endif
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integer i;
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always @(posedge RW0_clk)
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reg_RW0_ren <= RW0_en && !RW0_wmode;
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always @(posedge RW0_clk)
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if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
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always @(posedge RW0_clk)
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if (RW0_en && RW0_wmode) begin
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for (i=0;i<4;i=i+1) begin
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if (RW0_wmask[i]) begin
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ram[RW0_addr][i*80 +: 80] <= RW0_wdata[i*80 +: 80];
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end
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end
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end
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`ifdef RANDOMIZE_GARBAGE_ASSIGN
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reg [319:0] RW0_random;
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`ifdef RANDOMIZE_MEM_INIT
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initial begin
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#`RANDOMIZE_DELAY begin end
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RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
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reg_RW0_ren = RW0_random[0];
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end
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`endif
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always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
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assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[319:0];
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`else
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assign RW0_rdata = ram[reg_RW0_addr];
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`endif
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endmodule |