444 lines
42 KiB
Systemverilog
444 lines
42 KiB
Systemverilog
// Generated by CIRCT firtool-1.62.0
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// Standard header to adapt well known macros for register randomization.
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_MEM_INIT
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`endif // not def RANDOMIZE
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_REG_INIT
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`endif // not def RANDOMIZE
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// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
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`ifndef RANDOM
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`define RANDOM $random
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`endif // not def RANDOM
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// Users can define INIT_RANDOM as general code that gets injected into the
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// initializer block for modules with registers.
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`ifndef INIT_RANDOM
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`define INIT_RANDOM
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`endif // not def INIT_RANDOM
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// If using random initialization, you can also define RANDOMIZE_DELAY to
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// customize the delay used, otherwise 0.002 is used.
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`ifndef RANDOMIZE_DELAY
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`define RANDOMIZE_DELAY 0.002
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`endif // not def RANDOMIZE_DELAY
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// Define INIT_RANDOM_PROLOG_ for use in our modules below.
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`ifndef INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE
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`ifdef VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
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`else // VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
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`endif // VERILATOR
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`else // RANDOMIZE
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`define INIT_RANDOM_PROLOG_
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`endif // RANDOMIZE
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`endif // not def INIT_RANDOM_PROLOG_
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// Include register initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_REG_
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`define ENABLE_INITIAL_REG_
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`endif // not def ENABLE_INITIAL_REG_
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`endif // not def SYNTHESIS
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// Include rmemory initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_MEM_
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`define ENABLE_INITIAL_MEM_
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`endif // not def ENABLE_INITIAL_MEM_
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`endif // not def SYNTHESIS
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module SRAMTemplate_13( // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7]
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input clock, // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7]
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input reset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7]
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output io_r_req_ready, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_r_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input [8:0] io_r_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_0_entry_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [3:0] io_r_resp_data_0_entry_brSlots_0_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [11:0] io_r_resp_data_0_entry_brSlots_0_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [1:0] io_r_resp_data_0_entry_brSlots_0_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_0_entry_brSlots_0_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_0_entry_brSlots_0_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [3:0] io_r_resp_data_0_entry_tailSlot_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [19:0] io_r_resp_data_0_entry_tailSlot_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [1:0] io_r_resp_data_0_entry_tailSlot_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_0_entry_tailSlot_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_0_entry_tailSlot_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [3:0] io_r_resp_data_0_entry_pftAddr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_0_entry_carry, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_0_entry_isCall, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_0_entry_isRet, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_0_entry_isJalr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_0_entry_last_may_be_rvi_call, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_0_entry_always_taken_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_0_entry_always_taken_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [19:0] io_r_resp_data_0_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_1_entry_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [3:0] io_r_resp_data_1_entry_brSlots_0_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [11:0] io_r_resp_data_1_entry_brSlots_0_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [1:0] io_r_resp_data_1_entry_brSlots_0_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_1_entry_brSlots_0_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_1_entry_brSlots_0_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [3:0] io_r_resp_data_1_entry_tailSlot_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [19:0] io_r_resp_data_1_entry_tailSlot_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [1:0] io_r_resp_data_1_entry_tailSlot_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_1_entry_tailSlot_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_1_entry_tailSlot_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [3:0] io_r_resp_data_1_entry_pftAddr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_1_entry_carry, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_1_entry_isCall, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_1_entry_isRet, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_1_entry_isJalr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_1_entry_last_may_be_rvi_call, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_1_entry_always_taken_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_1_entry_always_taken_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [19:0] io_r_resp_data_1_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_2_entry_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [3:0] io_r_resp_data_2_entry_brSlots_0_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [11:0] io_r_resp_data_2_entry_brSlots_0_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [1:0] io_r_resp_data_2_entry_brSlots_0_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_2_entry_brSlots_0_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_2_entry_brSlots_0_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [3:0] io_r_resp_data_2_entry_tailSlot_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [19:0] io_r_resp_data_2_entry_tailSlot_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [1:0] io_r_resp_data_2_entry_tailSlot_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_2_entry_tailSlot_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_2_entry_tailSlot_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [3:0] io_r_resp_data_2_entry_pftAddr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_2_entry_carry, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_2_entry_isCall, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_2_entry_isRet, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_2_entry_isJalr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_2_entry_last_may_be_rvi_call, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_2_entry_always_taken_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_2_entry_always_taken_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [19:0] io_r_resp_data_2_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_3_entry_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [3:0] io_r_resp_data_3_entry_brSlots_0_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [11:0] io_r_resp_data_3_entry_brSlots_0_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [1:0] io_r_resp_data_3_entry_brSlots_0_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_3_entry_brSlots_0_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_3_entry_brSlots_0_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [3:0] io_r_resp_data_3_entry_tailSlot_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [19:0] io_r_resp_data_3_entry_tailSlot_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [1:0] io_r_resp_data_3_entry_tailSlot_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_3_entry_tailSlot_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_3_entry_tailSlot_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [3:0] io_r_resp_data_3_entry_pftAddr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_3_entry_carry, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_3_entry_isCall, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_3_entry_isRet, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_3_entry_isJalr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_3_entry_last_may_be_rvi_call, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_3_entry_always_taken_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output io_r_resp_data_3_entry_always_taken_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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output [19:0] io_r_resp_data_3_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input [8:0] io_w_req_bits_setIdx, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_0_entry_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input [3:0] io_w_req_bits_data_0_entry_brSlots_0_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input [11:0] io_w_req_bits_data_0_entry_brSlots_0_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input [1:0] io_w_req_bits_data_0_entry_brSlots_0_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_0_entry_brSlots_0_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_0_entry_brSlots_0_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input [3:0] io_w_req_bits_data_0_entry_tailSlot_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input [19:0] io_w_req_bits_data_0_entry_tailSlot_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input [1:0] io_w_req_bits_data_0_entry_tailSlot_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_0_entry_tailSlot_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_0_entry_tailSlot_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input [3:0] io_w_req_bits_data_0_entry_pftAddr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_0_entry_carry, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_0_entry_isCall, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_0_entry_isRet, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_0_entry_isJalr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_0_entry_last_may_be_rvi_call, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_0_entry_always_taken_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_0_entry_always_taken_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input [19:0] io_w_req_bits_data_0_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_1_entry_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input [3:0] io_w_req_bits_data_1_entry_brSlots_0_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input [11:0] io_w_req_bits_data_1_entry_brSlots_0_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input [1:0] io_w_req_bits_data_1_entry_brSlots_0_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_1_entry_brSlots_0_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_1_entry_brSlots_0_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input [3:0] io_w_req_bits_data_1_entry_tailSlot_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input [19:0] io_w_req_bits_data_1_entry_tailSlot_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input [1:0] io_w_req_bits_data_1_entry_tailSlot_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_1_entry_tailSlot_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_1_entry_tailSlot_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input [3:0] io_w_req_bits_data_1_entry_pftAddr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_1_entry_carry, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_1_entry_isCall, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_1_entry_isRet, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_1_entry_isJalr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_1_entry_last_may_be_rvi_call, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_1_entry_always_taken_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_1_entry_always_taken_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input [19:0] io_w_req_bits_data_1_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_2_entry_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input [3:0] io_w_req_bits_data_2_entry_brSlots_0_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input [11:0] io_w_req_bits_data_2_entry_brSlots_0_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input [1:0] io_w_req_bits_data_2_entry_brSlots_0_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_2_entry_brSlots_0_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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input io_w_req_bits_data_2_entry_brSlots_0_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input [3:0] io_w_req_bits_data_2_entry_tailSlot_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input [19:0] io_w_req_bits_data_2_entry_tailSlot_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input [1:0] io_w_req_bits_data_2_entry_tailSlot_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input io_w_req_bits_data_2_entry_tailSlot_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input io_w_req_bits_data_2_entry_tailSlot_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input [3:0] io_w_req_bits_data_2_entry_pftAddr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input io_w_req_bits_data_2_entry_carry, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input io_w_req_bits_data_2_entry_isCall, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input io_w_req_bits_data_2_entry_isRet, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input io_w_req_bits_data_2_entry_isJalr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input io_w_req_bits_data_2_entry_last_may_be_rvi_call, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input io_w_req_bits_data_2_entry_always_taken_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input io_w_req_bits_data_2_entry_always_taken_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input [19:0] io_w_req_bits_data_2_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input io_w_req_bits_data_3_entry_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input [3:0] io_w_req_bits_data_3_entry_brSlots_0_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input [11:0] io_w_req_bits_data_3_entry_brSlots_0_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input [1:0] io_w_req_bits_data_3_entry_brSlots_0_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input io_w_req_bits_data_3_entry_brSlots_0_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input io_w_req_bits_data_3_entry_brSlots_0_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input [3:0] io_w_req_bits_data_3_entry_tailSlot_offset, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input [19:0] io_w_req_bits_data_3_entry_tailSlot_lower, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input [1:0] io_w_req_bits_data_3_entry_tailSlot_tarStat, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input io_w_req_bits_data_3_entry_tailSlot_sharing, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input io_w_req_bits_data_3_entry_tailSlot_valid, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input [3:0] io_w_req_bits_data_3_entry_pftAddr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input io_w_req_bits_data_3_entry_carry, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input io_w_req_bits_data_3_entry_isCall, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input io_w_req_bits_data_3_entry_isRet, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input io_w_req_bits_data_3_entry_isJalr, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input io_w_req_bits_data_3_entry_last_may_be_rvi_call, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input io_w_req_bits_data_3_entry_always_taken_0, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input io_w_req_bits_data_3_entry_always_taken_1, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input [19:0] io_w_req_bits_data_3_tag, // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
|
|
input [3:0] io_w_req_bits_waymask // @[utility/src/main/scala/utility/SRAMTemplate.scala:144:14]
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|
);
|
|
|
|
wire [8:0] setIdx; // @[utility/src/main/scala/utility/SRAMTemplate.scala:174:19]
|
|
wire realRen; // @[utility/src/main/scala/utility/SRAMTemplate.scala:172:38]
|
|
wire wen; // @[utility/src/main/scala/utility/SRAMTemplate.scala:171:52]
|
|
wire [319:0] _array_RW0_rdata; // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26]
|
|
reg _resetState; // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30]
|
|
reg [8:0] _resetSet; // @[src/main/scala/chisel3/util/Counter.scala:61:40]
|
|
assign wen = io_w_req_valid | _resetState; // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :171:52]
|
|
assign realRen = io_r_req_valid & ~wen; // @[utility/src/main/scala/utility/SRAMTemplate.scala:171:52, :172:{38,41}]
|
|
assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx; // @[src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :174:19]
|
|
always @(posedge clock or posedge reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7]
|
|
if (reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7]
|
|
_resetState <= 1'h1; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30]
|
|
_resetSet <= 9'h0; // @[src/main/scala/chisel3/util/Counter.scala:61:40]
|
|
end
|
|
else begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7]
|
|
_resetState <= ~(_resetState & (&_resetSet)) & _resetState; // @[src/main/scala/chisel3/util/Counter.scala:61:40, :73:24, :117:24, :118:{16,23}, utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :160:{24,38}]
|
|
if (_resetState) // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30]
|
|
_resetSet <= 9'(_resetSet + 9'h1); // @[src/main/scala/chisel3/util/Counter.scala:61:40, :77:24]
|
|
end
|
|
end // always @(posedge, posedge)
|
|
`ifdef ENABLE_INITIAL_REG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7]
|
|
`ifdef FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7]
|
|
`FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7]
|
|
`endif // FIRRTL_BEFORE_INITIAL
|
|
logic [31:0] _RANDOM[0:0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7]
|
|
initial begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7]
|
|
`ifdef INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7]
|
|
`INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7]
|
|
`endif // INIT_RANDOM_PROLOG_
|
|
`ifdef RANDOMIZE_REG_INIT // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7]
|
|
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7]
|
|
_resetState = _RANDOM[/*Zero width*/ 1'b0][0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30]
|
|
_resetSet = _RANDOM[/*Zero width*/ 1'b0][9:1]; // @[src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30]
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7]
|
|
_resetState = 1'h1; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30]
|
|
_resetSet = 9'h0; // @[src/main/scala/chisel3/util/Counter.scala:61:40]
|
|
end
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7]
|
|
`FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7]
|
|
`endif // FIRRTL_AFTER_INITIAL
|
|
`endif // ENABLE_INITIAL_REG_
|
|
array_3 array ( // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26]
|
|
.RW0_addr (wen ? setIdx : io_r_req_bits_setIdx), // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :171:52, :174:19]
|
|
.RW0_en (realRen | wen), // @[utility/src/main/scala/utility/SRAMTemplate.scala:154:26, :171:52, :172:38]
|
|
.RW0_clk (clock),
|
|
.RW0_wmode (wen), // @[utility/src/main/scala/utility/SRAMTemplate.scala:171:52]
|
|
.RW0_wdata
|
|
({~_resetState & io_w_req_bits_data_3_entry_valid,
|
|
_resetState ? 4'h0 : io_w_req_bits_data_3_entry_brSlots_0_offset,
|
|
_resetState ? 12'h0 : io_w_req_bits_data_3_entry_brSlots_0_lower,
|
|
_resetState ? 2'h0 : io_w_req_bits_data_3_entry_brSlots_0_tarStat,
|
|
~_resetState & io_w_req_bits_data_3_entry_brSlots_0_sharing,
|
|
~_resetState & io_w_req_bits_data_3_entry_brSlots_0_valid,
|
|
_resetState ? 4'h0 : io_w_req_bits_data_3_entry_tailSlot_offset,
|
|
_resetState ? 20'h0 : io_w_req_bits_data_3_entry_tailSlot_lower,
|
|
_resetState ? 2'h0 : io_w_req_bits_data_3_entry_tailSlot_tarStat,
|
|
~_resetState & io_w_req_bits_data_3_entry_tailSlot_sharing,
|
|
~_resetState & io_w_req_bits_data_3_entry_tailSlot_valid,
|
|
_resetState ? 4'h0 : io_w_req_bits_data_3_entry_pftAddr,
|
|
~_resetState & io_w_req_bits_data_3_entry_carry,
|
|
~_resetState & io_w_req_bits_data_3_entry_isCall,
|
|
~_resetState & io_w_req_bits_data_3_entry_isRet,
|
|
~_resetState & io_w_req_bits_data_3_entry_isJalr,
|
|
~_resetState & io_w_req_bits_data_3_entry_last_may_be_rvi_call,
|
|
~_resetState & io_w_req_bits_data_3_entry_always_taken_1,
|
|
~_resetState & io_w_req_bits_data_3_entry_always_taken_0,
|
|
_resetState ? 20'h0 : io_w_req_bits_data_3_tag,
|
|
~_resetState & io_w_req_bits_data_2_entry_valid,
|
|
_resetState ? 4'h0 : io_w_req_bits_data_2_entry_brSlots_0_offset,
|
|
_resetState ? 12'h0 : io_w_req_bits_data_2_entry_brSlots_0_lower,
|
|
_resetState ? 2'h0 : io_w_req_bits_data_2_entry_brSlots_0_tarStat,
|
|
~_resetState & io_w_req_bits_data_2_entry_brSlots_0_sharing,
|
|
~_resetState & io_w_req_bits_data_2_entry_brSlots_0_valid,
|
|
_resetState ? 4'h0 : io_w_req_bits_data_2_entry_tailSlot_offset,
|
|
_resetState ? 20'h0 : io_w_req_bits_data_2_entry_tailSlot_lower,
|
|
_resetState ? 2'h0 : io_w_req_bits_data_2_entry_tailSlot_tarStat,
|
|
~_resetState & io_w_req_bits_data_2_entry_tailSlot_sharing,
|
|
~_resetState & io_w_req_bits_data_2_entry_tailSlot_valid,
|
|
_resetState ? 4'h0 : io_w_req_bits_data_2_entry_pftAddr,
|
|
~_resetState & io_w_req_bits_data_2_entry_carry,
|
|
~_resetState & io_w_req_bits_data_2_entry_isCall,
|
|
~_resetState & io_w_req_bits_data_2_entry_isRet,
|
|
~_resetState & io_w_req_bits_data_2_entry_isJalr,
|
|
~_resetState & io_w_req_bits_data_2_entry_last_may_be_rvi_call,
|
|
~_resetState & io_w_req_bits_data_2_entry_always_taken_1,
|
|
~_resetState & io_w_req_bits_data_2_entry_always_taken_0,
|
|
_resetState ? 20'h0 : io_w_req_bits_data_2_tag,
|
|
~_resetState & io_w_req_bits_data_1_entry_valid,
|
|
_resetState ? 4'h0 : io_w_req_bits_data_1_entry_brSlots_0_offset,
|
|
_resetState ? 12'h0 : io_w_req_bits_data_1_entry_brSlots_0_lower,
|
|
_resetState ? 2'h0 : io_w_req_bits_data_1_entry_brSlots_0_tarStat,
|
|
~_resetState & io_w_req_bits_data_1_entry_brSlots_0_sharing,
|
|
~_resetState & io_w_req_bits_data_1_entry_brSlots_0_valid,
|
|
_resetState ? 4'h0 : io_w_req_bits_data_1_entry_tailSlot_offset,
|
|
_resetState ? 20'h0 : io_w_req_bits_data_1_entry_tailSlot_lower,
|
|
_resetState ? 2'h0 : io_w_req_bits_data_1_entry_tailSlot_tarStat,
|
|
~_resetState & io_w_req_bits_data_1_entry_tailSlot_sharing,
|
|
~_resetState & io_w_req_bits_data_1_entry_tailSlot_valid,
|
|
_resetState ? 4'h0 : io_w_req_bits_data_1_entry_pftAddr,
|
|
~_resetState & io_w_req_bits_data_1_entry_carry,
|
|
~_resetState & io_w_req_bits_data_1_entry_isCall,
|
|
~_resetState & io_w_req_bits_data_1_entry_isRet,
|
|
~_resetState & io_w_req_bits_data_1_entry_isJalr,
|
|
~_resetState & io_w_req_bits_data_1_entry_last_may_be_rvi_call,
|
|
~_resetState & io_w_req_bits_data_1_entry_always_taken_1,
|
|
~_resetState & io_w_req_bits_data_1_entry_always_taken_0,
|
|
_resetState ? 20'h0 : io_w_req_bits_data_1_tag,
|
|
~_resetState & io_w_req_bits_data_0_entry_valid,
|
|
_resetState ? 4'h0 : io_w_req_bits_data_0_entry_brSlots_0_offset,
|
|
_resetState ? 12'h0 : io_w_req_bits_data_0_entry_brSlots_0_lower,
|
|
_resetState ? 2'h0 : io_w_req_bits_data_0_entry_brSlots_0_tarStat,
|
|
~_resetState & io_w_req_bits_data_0_entry_brSlots_0_sharing,
|
|
~_resetState & io_w_req_bits_data_0_entry_brSlots_0_valid,
|
|
_resetState ? 4'h0 : io_w_req_bits_data_0_entry_tailSlot_offset,
|
|
_resetState ? 20'h0 : io_w_req_bits_data_0_entry_tailSlot_lower,
|
|
_resetState ? 2'h0 : io_w_req_bits_data_0_entry_tailSlot_tarStat,
|
|
~_resetState & io_w_req_bits_data_0_entry_tailSlot_sharing,
|
|
~_resetState & io_w_req_bits_data_0_entry_tailSlot_valid,
|
|
_resetState ? 4'h0 : io_w_req_bits_data_0_entry_pftAddr,
|
|
~_resetState & io_w_req_bits_data_0_entry_carry,
|
|
~_resetState & io_w_req_bits_data_0_entry_isCall,
|
|
~_resetState & io_w_req_bits_data_0_entry_isRet,
|
|
~_resetState & io_w_req_bits_data_0_entry_isJalr,
|
|
~_resetState & io_w_req_bits_data_0_entry_last_may_be_rvi_call,
|
|
~_resetState & io_w_req_bits_data_0_entry_always_taken_1,
|
|
~_resetState & io_w_req_bits_data_0_entry_always_taken_0,
|
|
_resetState ? 20'h0 : io_w_req_bits_data_0_tag}), // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :175:{18,43}, :176:13]
|
|
.RW0_rdata (_array_RW0_rdata),
|
|
.RW0_wmask (_resetState ? 4'hF : io_w_req_bits_waymask) // @[utility/src/main/scala/utility/SRAMTemplate.scala:158:30, :180:{22,39}]
|
|
);
|
|
assign io_r_req_ready = ~_resetState & ~wen; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :158:30, :171:52, :172:41, :222:{21,33}]
|
|
assign io_r_resp_data_0_entry_valid = _array_RW0_rdata[79]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
|
|
assign io_r_resp_data_0_entry_brSlots_0_offset = _array_RW0_rdata[78:75]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
|
|
assign io_r_resp_data_0_entry_brSlots_0_lower = _array_RW0_rdata[74:63]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
|
|
assign io_r_resp_data_0_entry_brSlots_0_tarStat = _array_RW0_rdata[62:61]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
|
|
assign io_r_resp_data_0_entry_brSlots_0_sharing = _array_RW0_rdata[60]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
|
|
assign io_r_resp_data_0_entry_brSlots_0_valid = _array_RW0_rdata[59]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
|
|
assign io_r_resp_data_0_entry_tailSlot_offset = _array_RW0_rdata[58:55]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
|
|
assign io_r_resp_data_0_entry_tailSlot_lower = _array_RW0_rdata[54:35]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
|
|
assign io_r_resp_data_0_entry_tailSlot_tarStat = _array_RW0_rdata[34:33]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
|
|
assign io_r_resp_data_0_entry_tailSlot_sharing = _array_RW0_rdata[32]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
|
|
assign io_r_resp_data_0_entry_tailSlot_valid = _array_RW0_rdata[31]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
|
|
assign io_r_resp_data_0_entry_pftAddr = _array_RW0_rdata[30:27]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
|
|
assign io_r_resp_data_0_entry_carry = _array_RW0_rdata[26]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
|
|
assign io_r_resp_data_0_entry_isCall = _array_RW0_rdata[25]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
|
|
assign io_r_resp_data_0_entry_isRet = _array_RW0_rdata[24]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
|
|
assign io_r_resp_data_0_entry_isJalr = _array_RW0_rdata[23]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
|
|
assign io_r_resp_data_0_entry_last_may_be_rvi_call = _array_RW0_rdata[22]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_0_entry_always_taken_0 = _array_RW0_rdata[20]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_0_entry_always_taken_1 = _array_RW0_rdata[21]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_0_tag = _array_RW0_rdata[19:0]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_1_entry_valid = _array_RW0_rdata[159]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_1_entry_brSlots_0_offset = _array_RW0_rdata[158:155]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_1_entry_brSlots_0_lower = _array_RW0_rdata[154:143]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_1_entry_brSlots_0_tarStat = _array_RW0_rdata[142:141]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_1_entry_brSlots_0_sharing = _array_RW0_rdata[140]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_1_entry_brSlots_0_valid = _array_RW0_rdata[139]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_1_entry_tailSlot_offset = _array_RW0_rdata[138:135]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_1_entry_tailSlot_lower = _array_RW0_rdata[134:115]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_1_entry_tailSlot_tarStat = _array_RW0_rdata[114:113]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_1_entry_tailSlot_sharing = _array_RW0_rdata[112]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_1_entry_tailSlot_valid = _array_RW0_rdata[111]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_1_entry_pftAddr = _array_RW0_rdata[110:107]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_1_entry_carry = _array_RW0_rdata[106]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_1_entry_isCall = _array_RW0_rdata[105]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_1_entry_isRet = _array_RW0_rdata[104]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_1_entry_isJalr = _array_RW0_rdata[103]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_1_entry_last_may_be_rvi_call = _array_RW0_rdata[102]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_1_entry_always_taken_0 = _array_RW0_rdata[100]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_1_entry_always_taken_1 = _array_RW0_rdata[101]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_1_tag = _array_RW0_rdata[99:80]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_2_entry_valid = _array_RW0_rdata[239]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_2_entry_brSlots_0_offset = _array_RW0_rdata[238:235]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_2_entry_brSlots_0_lower = _array_RW0_rdata[234:223]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_2_entry_brSlots_0_tarStat = _array_RW0_rdata[222:221]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_2_entry_brSlots_0_sharing = _array_RW0_rdata[220]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_2_entry_brSlots_0_valid = _array_RW0_rdata[219]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_2_entry_tailSlot_offset = _array_RW0_rdata[218:215]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_2_entry_tailSlot_lower = _array_RW0_rdata[214:195]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_2_entry_tailSlot_tarStat = _array_RW0_rdata[194:193]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_2_entry_tailSlot_sharing = _array_RW0_rdata[192]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_2_entry_tailSlot_valid = _array_RW0_rdata[191]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_2_entry_pftAddr = _array_RW0_rdata[190:187]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_2_entry_carry = _array_RW0_rdata[186]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_2_entry_isCall = _array_RW0_rdata[185]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_2_entry_isRet = _array_RW0_rdata[184]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_2_entry_isJalr = _array_RW0_rdata[183]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_2_entry_last_may_be_rvi_call = _array_RW0_rdata[182]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_2_entry_always_taken_0 = _array_RW0_rdata[180]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_2_entry_always_taken_1 = _array_RW0_rdata[181]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_2_tag = _array_RW0_rdata[179:160]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_3_entry_valid = _array_RW0_rdata[319]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_3_entry_brSlots_0_offset = _array_RW0_rdata[318:315]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_3_entry_brSlots_0_lower = _array_RW0_rdata[314:303]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_3_entry_brSlots_0_tarStat = _array_RW0_rdata[302:301]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_3_entry_brSlots_0_sharing = _array_RW0_rdata[300]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_3_entry_brSlots_0_valid = _array_RW0_rdata[299]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_3_entry_tailSlot_offset = _array_RW0_rdata[298:295]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_3_entry_tailSlot_lower = _array_RW0_rdata[294:275]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_3_entry_tailSlot_tarStat = _array_RW0_rdata[274:273]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_3_entry_tailSlot_sharing = _array_RW0_rdata[272]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_3_entry_tailSlot_valid = _array_RW0_rdata[271]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_3_entry_pftAddr = _array_RW0_rdata[270:267]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_3_entry_carry = _array_RW0_rdata[266]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_3_entry_isCall = _array_RW0_rdata[265]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_3_entry_isRet = _array_RW0_rdata[264]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_3_entry_isJalr = _array_RW0_rdata[263]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_3_entry_last_may_be_rvi_call = _array_RW0_rdata[262]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_3_entry_always_taken_0 = _array_RW0_rdata[260]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_3_entry_always_taken_1 = _array_RW0_rdata[261]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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assign io_r_resp_data_3_tag = _array_RW0_rdata[259:240]; // @[utility/src/main/scala/utility/SRAMTemplate.scala:138:7, :154:26, :219:45]
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endmodule
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