753 lines
35 KiB
Systemverilog
753 lines
35 KiB
Systemverilog
// Generated by CIRCT firtool-1.62.0
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// Standard header to adapt well known macros for register randomization.
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_MEM_INIT
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`endif // not def RANDOMIZE
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_REG_INIT
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`endif // not def RANDOMIZE
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// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
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`ifndef RANDOM
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`define RANDOM $random
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`endif // not def RANDOM
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// Users can define INIT_RANDOM as general code that gets injected into the
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// initializer block for modules with registers.
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`ifndef INIT_RANDOM
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`define INIT_RANDOM
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`endif // not def INIT_RANDOM
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// If using random initialization, you can also define RANDOMIZE_DELAY to
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// customize the delay used, otherwise 0.002 is used.
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`ifndef RANDOMIZE_DELAY
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`define RANDOMIZE_DELAY 0.002
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`endif // not def RANDOMIZE_DELAY
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// Define INIT_RANDOM_PROLOG_ for use in our modules below.
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`ifndef INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE
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`ifdef VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
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`else // VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
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`endif // VERILATOR
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`else // RANDOMIZE
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`define INIT_RANDOM_PROLOG_
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`endif // RANDOMIZE
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`endif // not def INIT_RANDOM_PROLOG_
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// Include register initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_REG_
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`define ENABLE_INITIAL_REG_
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`endif // not def ENABLE_INITIAL_REG_
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`endif // not def SYNTHESIS
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// Include rmemory initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_MEM_
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`define ENABLE_INITIAL_MEM_
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`endif // not def ENABLE_INITIAL_MEM_
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`endif // not def SYNTHESIS
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module TageTable(
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input clock,
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input reset,
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output io_req_ready,
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input io_req_valid,
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input [40:0] io_req_bits_pc,
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input [7:0] io_req_bits_folded_hist_hist_14_folded_hist,
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input [6:0] io_req_bits_folded_hist_hist_7_folded_hist,
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output io_resps_0_valid,
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output [2:0] io_resps_0_bits_ctr,
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output io_resps_0_bits_u,
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output io_resps_0_bits_unconf,
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output io_resps_1_valid,
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output [2:0] io_resps_1_bits_ctr,
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output io_resps_1_bits_u,
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output io_resps_1_bits_unconf,
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input [40:0] io_update_pc,
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input [7:0] io_update_folded_hist_hist_14_folded_hist,
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input [6:0] io_update_folded_hist_hist_7_folded_hist,
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input io_update_mask_0,
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input io_update_mask_1,
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input io_update_takens_0,
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input io_update_takens_1,
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input io_update_alloc_0,
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input io_update_alloc_1,
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input [2:0] io_update_oldCtrs_0,
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input [2:0] io_update_oldCtrs_1,
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input io_update_uMask_0,
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input io_update_uMask_1,
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input io_update_us_0,
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input io_update_us_1,
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input io_update_reset_u_0,
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input io_update_reset_u_1
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);
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wire per_bank_not_silent_update_3_1;
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wire per_bank_not_silent_update_3_0;
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wire per_bank_not_silent_update_2_1;
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wire per_bank_not_silent_update_2_0;
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wire per_bank_not_silent_update_1_1;
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wire per_bank_not_silent_update_1_0;
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wire per_bank_not_silent_update_0_1;
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wire per_bank_not_silent_update_0_0;
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reg powerOnResetState;
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wire _resp_invalid_by_write_T_6;
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wire _bank_wrbypasses_3_1_io_hit;
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wire _bank_wrbypasses_3_1_io_hit_data_0_valid;
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wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits;
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wire _bank_wrbypasses_3_0_io_hit;
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wire _bank_wrbypasses_3_0_io_hit_data_0_valid;
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wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits;
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wire _bank_wrbypasses_2_1_io_hit;
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wire _bank_wrbypasses_2_1_io_hit_data_0_valid;
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wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits;
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wire _bank_wrbypasses_2_0_io_hit;
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wire _bank_wrbypasses_2_0_io_hit_data_0_valid;
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wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits;
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wire _bank_wrbypasses_1_1_io_hit;
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wire _bank_wrbypasses_1_1_io_hit_data_0_valid;
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wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits;
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wire _bank_wrbypasses_1_0_io_hit;
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wire _bank_wrbypasses_1_0_io_hit_data_0_valid;
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wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits;
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wire _bank_wrbypasses_0_1_io_hit;
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wire _bank_wrbypasses_0_1_io_hit_data_0_valid;
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wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits;
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wire _bank_wrbypasses_0_0_io_hit;
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wire _bank_wrbypasses_0_0_io_hit_data_0_valid;
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wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits;
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wire _table_banks_3_io_r_req_ready;
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wire _table_banks_3_io_r_resp_data_0_valid;
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wire [7:0] _table_banks_3_io_r_resp_data_0_tag;
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wire [2:0] _table_banks_3_io_r_resp_data_0_ctr;
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wire _table_banks_3_io_r_resp_data_1_valid;
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wire [7:0] _table_banks_3_io_r_resp_data_1_tag;
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wire [2:0] _table_banks_3_io_r_resp_data_1_ctr;
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wire _table_banks_2_io_r_req_ready;
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wire _table_banks_2_io_r_resp_data_0_valid;
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wire [7:0] _table_banks_2_io_r_resp_data_0_tag;
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wire [2:0] _table_banks_2_io_r_resp_data_0_ctr;
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wire _table_banks_2_io_r_resp_data_1_valid;
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wire [7:0] _table_banks_2_io_r_resp_data_1_tag;
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wire [2:0] _table_banks_2_io_r_resp_data_1_ctr;
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wire _table_banks_1_io_r_req_ready;
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wire _table_banks_1_io_r_resp_data_0_valid;
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wire [7:0] _table_banks_1_io_r_resp_data_0_tag;
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wire [2:0] _table_banks_1_io_r_resp_data_0_ctr;
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wire _table_banks_1_io_r_resp_data_1_valid;
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wire [7:0] _table_banks_1_io_r_resp_data_1_tag;
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wire [2:0] _table_banks_1_io_r_resp_data_1_ctr;
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wire _table_banks_0_io_r_req_ready;
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wire _table_banks_0_io_r_resp_data_0_valid;
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wire [7:0] _table_banks_0_io_r_resp_data_0_tag;
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wire [2:0] _table_banks_0_io_r_resp_data_0_ctr;
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wire _table_banks_0_io_r_resp_data_1_valid;
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wire [7:0] _table_banks_0_io_r_resp_data_1_tag;
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wire [2:0] _table_banks_0_io_r_resp_data_1_ctr;
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wire _us_io_r_req_ready;
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wire _us_io_r_resp_data_0;
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wire _us_io_r_resp_data_1;
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wire _us_extra_reset_T_1 = io_update_mask_0 | io_update_mask_1;
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wire [7:0] _GEN = io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_14_folded_hist;
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wire s0_bank_req_1h_0 = _GEN[1:0] == 2'h0;
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wire s0_bank_req_1h_1 = _GEN[1:0] == 2'h1;
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wire s0_bank_req_1h_2 = _GEN[1:0] == 2'h2;
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wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid;
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wire [8:0] _table_banks_3_io_r_req_bits_setIdx_T = {io_req_bits_pc[11:9], _GEN[7:2]};
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reg [39:0] s1_unhashed_idx;
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reg [7:0] s1_tag;
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reg s1_bank_req_1h_0;
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reg s1_bank_req_1h_1;
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reg s1_bank_req_1h_2;
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reg s1_bank_req_1h_3;
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reg s1_bank_has_write_on_this_req_0;
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reg s1_bank_has_write_on_this_req_1;
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reg s1_bank_has_write_on_this_req_2;
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reg s1_bank_has_write_on_this_req_3;
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wire [2:0] _resp_selected_T_6 =
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(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0)
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| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0)
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| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0)
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| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0);
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wire [2:0] _resp_selected_T_27 =
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(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0)
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| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0)
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| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0)
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| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0);
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wire _unconf_selected_T_6 =
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s1_bank_req_1h_0
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& (_table_banks_0_io_r_resp_data_0_ctr == 3'h4
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| _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1
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& (_table_banks_1_io_r_resp_data_0_ctr == 3'h4
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| _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2
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& (_table_banks_2_io_r_resp_data_0_ctr == 3'h4
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| _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3
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& (_table_banks_3_io_r_resp_data_0_ctr == 3'h4
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| _table_banks_3_io_r_resp_data_0_ctr == 3'h3);
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wire _unconf_selected_T_13 =
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s1_bank_req_1h_0
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& (_table_banks_0_io_r_resp_data_1_ctr == 3'h4
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| _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1
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& (_table_banks_1_io_r_resp_data_1_ctr == 3'h4
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| _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2
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& (_table_banks_2_io_r_resp_data_1_ctr == 3'h4
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| _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3
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& (_table_banks_3_io_r_resp_data_1_ctr == 3'h4
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| _table_banks_3_io_r_resp_data_1_ctr == 3'h3);
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wire _hit_selected_T_6 =
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s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag
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& _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
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| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag
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& _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
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| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag
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& _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
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| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag
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& _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6;
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wire _hit_selected_T_13 =
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s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag
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& _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
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| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag
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& _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
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| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag
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& _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
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| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag
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& _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6;
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assign _resp_invalid_by_write_T_6 =
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s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
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& s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2
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| s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3;
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wire [7:0] _GEN_0 = io_update_pc[8:1] ^ io_update_folded_hist_hist_14_folded_hist;
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wire [7:0] update_tag = _GEN_0 ^ {io_update_folded_hist_hist_7_folded_hist, 1'h0};
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wire update_req_bank_1h_0 = _GEN_0[1:0] == 2'h0;
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wire update_req_bank_1h_1 = _GEN_0[1:0] == 2'h1;
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wire update_req_bank_1h_2 = _GEN_0[1:0] == 2'h2;
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wire [8:0] update_idx_in_bank = {io_update_pc[11:9], _GEN_0[7:2]};
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wire [1:0] per_bank_update_way_mask_0 =
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{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
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& per_bank_not_silent_update_0_1,
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(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
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& per_bank_not_silent_update_0_0};
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wire [1:0] per_bank_update_way_mask_1 =
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{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
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& per_bank_not_silent_update_1_1,
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(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
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& per_bank_not_silent_update_1_0};
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wire [1:0] per_bank_update_way_mask_2 =
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{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
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& per_bank_not_silent_update_2_1,
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(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
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& per_bank_not_silent_update_2_0};
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wire [1:0] per_bank_update_way_mask_3 =
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{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
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& per_bank_not_silent_update_3_1,
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(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
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& per_bank_not_silent_update_3_0};
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wire _s1_bank_has_write_on_this_req_WIRE_0 =
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(|per_bank_update_way_mask_0) & update_req_bank_1h_0;
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wire _s1_bank_has_write_on_this_req_WIRE_1 =
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(|per_bank_update_way_mask_1) & update_req_bank_1h_1;
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wire _s1_bank_has_write_on_this_req_WIRE_2 =
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(|per_bank_update_way_mask_2) & update_req_bank_1h_2;
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wire _s1_bank_has_write_on_this_req_WIRE_3 =
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(|per_bank_update_way_mask_3) & (&(_GEN_0[1:0]));
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wire [2:0] _wrbypass_io_T_6 =
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(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits)
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| (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0);
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wire wrbypass_data_valid =
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(~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1]
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& _bank_wrbypasses_0_1_io_hit)
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& (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1]
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& _bank_wrbypasses_0_1_io_hit_data_0_valid);
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wire _GEN_1 = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0;
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wire [2:0] _GEN_2 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0;
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wire _GEN_3 = (|_GEN_2) | _GEN_1;
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wire _GEN_4 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0;
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wire [2:0] per_bank_update_wdata_0_0_ctr =
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_GEN_4
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? (_GEN_1 ? 3'h4 : 3'h3)
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: wrbypass_data_valid
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? ((&_wrbypass_io_T_6) & _GEN_1
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? 3'h7
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: _wrbypass_io_T_6 == 3'h0 & ~_GEN_1
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? 3'h0
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: _GEN_1 ? 3'(_wrbypass_io_T_6 + 3'h1) : 3'(_wrbypass_io_T_6 - 3'h1))
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: (&_GEN_2) & _GEN_1
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? 3'h7
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: _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0;
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assign per_bank_not_silent_update_0_0 =
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(wrbypass_data_valid
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? ~((&_wrbypass_io_T_6) & _GEN_1 | _wrbypass_io_T_6 == 3'h0 & ~_GEN_1)
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: ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4;
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wire [2:0] _wrbypass_io_T_28 =
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(io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0)
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| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits);
|
|
wire wrbypass_data_valid_1 =
|
|
(io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1])
|
|
& _bank_wrbypasses_0_1_io_hit)
|
|
& (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1])
|
|
& _bank_wrbypasses_0_1_io_hit_data_0_valid);
|
|
wire _GEN_5 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1;
|
|
wire [2:0] _GEN_6 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1;
|
|
wire _GEN_7 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1;
|
|
wire [2:0] per_bank_update_wdata_0_1_ctr =
|
|
_GEN_7
|
|
? (_GEN_5 ? 3'h4 : 3'h3)
|
|
: wrbypass_data_valid_1
|
|
? ((&_wrbypass_io_T_28) & _GEN_5
|
|
? 3'h7
|
|
: _wrbypass_io_T_28 == 3'h0 & ~_GEN_5
|
|
? 3'h0
|
|
: _GEN_5 ? 3'(_wrbypass_io_T_28 + 3'h1) : 3'(_wrbypass_io_T_28 - 3'h1))
|
|
: (&_GEN_6) & _GEN_5
|
|
? 3'h7
|
|
: _GEN_6 == 3'h0 & ~_GEN_5
|
|
? 3'h0
|
|
: _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1);
|
|
assign per_bank_not_silent_update_0_1 =
|
|
(wrbypass_data_valid_1
|
|
? ~((&_wrbypass_io_T_28) & _GEN_5 | _wrbypass_io_T_28 == 3'h0 & ~_GEN_5)
|
|
: ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7;
|
|
wire [2:0] _wrbypass_io_T_50 =
|
|
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits)
|
|
| (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0);
|
|
wire wrbypass_data_valid_2 =
|
|
(~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1]
|
|
& _bank_wrbypasses_1_1_io_hit)
|
|
& (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1]
|
|
& _bank_wrbypasses_1_1_io_hit_data_0_valid);
|
|
wire [2:0] per_bank_update_wdata_1_0_ctr =
|
|
_GEN_4
|
|
? (_GEN_1 ? 3'h4 : 3'h3)
|
|
: wrbypass_data_valid_2
|
|
? ((&_wrbypass_io_T_50) & _GEN_1
|
|
? 3'h7
|
|
: _wrbypass_io_T_50 == 3'h0 & ~_GEN_1
|
|
? 3'h0
|
|
: _GEN_1 ? 3'(_wrbypass_io_T_50 + 3'h1) : 3'(_wrbypass_io_T_50 - 3'h1))
|
|
: (&_GEN_2) & _GEN_1
|
|
? 3'h7
|
|
: _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0;
|
|
assign per_bank_not_silent_update_1_0 =
|
|
(wrbypass_data_valid_2
|
|
? ~((&_wrbypass_io_T_50) & _GEN_1 | _wrbypass_io_T_50 == 3'h0 & ~_GEN_1)
|
|
: ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4;
|
|
wire [2:0] _wrbypass_io_T_72 =
|
|
(io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0)
|
|
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits);
|
|
wire wrbypass_data_valid_3 =
|
|
(io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1])
|
|
& _bank_wrbypasses_1_1_io_hit)
|
|
& (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1])
|
|
& _bank_wrbypasses_1_1_io_hit_data_0_valid);
|
|
wire [2:0] per_bank_update_wdata_1_1_ctr =
|
|
_GEN_7
|
|
? (_GEN_5 ? 3'h4 : 3'h3)
|
|
: wrbypass_data_valid_3
|
|
? ((&_wrbypass_io_T_72) & _GEN_5
|
|
? 3'h7
|
|
: _wrbypass_io_T_72 == 3'h0 & ~_GEN_5
|
|
? 3'h0
|
|
: _GEN_5 ? 3'(_wrbypass_io_T_72 + 3'h1) : 3'(_wrbypass_io_T_72 - 3'h1))
|
|
: (&_GEN_6) & _GEN_5
|
|
? 3'h7
|
|
: _GEN_6 == 3'h0 & ~_GEN_5
|
|
? 3'h0
|
|
: _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1);
|
|
assign per_bank_not_silent_update_1_1 =
|
|
(wrbypass_data_valid_3
|
|
? ~((&_wrbypass_io_T_72) & _GEN_5 | _wrbypass_io_T_72 == 3'h0 & ~_GEN_5)
|
|
: ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7;
|
|
wire [2:0] _wrbypass_io_T_94 =
|
|
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits)
|
|
| (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0);
|
|
wire wrbypass_data_valid_4 =
|
|
(~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1]
|
|
& _bank_wrbypasses_2_1_io_hit)
|
|
& (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1]
|
|
& _bank_wrbypasses_2_1_io_hit_data_0_valid);
|
|
wire [2:0] per_bank_update_wdata_2_0_ctr =
|
|
_GEN_4
|
|
? (_GEN_1 ? 3'h4 : 3'h3)
|
|
: wrbypass_data_valid_4
|
|
? ((&_wrbypass_io_T_94) & _GEN_1
|
|
? 3'h7
|
|
: _wrbypass_io_T_94 == 3'h0 & ~_GEN_1
|
|
? 3'h0
|
|
: _GEN_1 ? 3'(_wrbypass_io_T_94 + 3'h1) : 3'(_wrbypass_io_T_94 - 3'h1))
|
|
: (&_GEN_2) & _GEN_1
|
|
? 3'h7
|
|
: _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0;
|
|
assign per_bank_not_silent_update_2_0 =
|
|
(wrbypass_data_valid_4
|
|
? ~((&_wrbypass_io_T_94) & _GEN_1 | _wrbypass_io_T_94 == 3'h0 & ~_GEN_1)
|
|
: ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4;
|
|
wire [2:0] _wrbypass_io_T_116 =
|
|
(io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0)
|
|
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits);
|
|
wire wrbypass_data_valid_5 =
|
|
(io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1])
|
|
& _bank_wrbypasses_2_1_io_hit)
|
|
& (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1])
|
|
& _bank_wrbypasses_2_1_io_hit_data_0_valid);
|
|
wire [2:0] per_bank_update_wdata_2_1_ctr =
|
|
_GEN_7
|
|
? (_GEN_5 ? 3'h4 : 3'h3)
|
|
: wrbypass_data_valid_5
|
|
? ((&_wrbypass_io_T_116) & _GEN_5
|
|
? 3'h7
|
|
: _wrbypass_io_T_116 == 3'h0 & ~_GEN_5
|
|
? 3'h0
|
|
: _GEN_5
|
|
? 3'(_wrbypass_io_T_116 + 3'h1)
|
|
: 3'(_wrbypass_io_T_116 - 3'h1))
|
|
: (&_GEN_6) & _GEN_5
|
|
? 3'h7
|
|
: _GEN_6 == 3'h0 & ~_GEN_5
|
|
? 3'h0
|
|
: _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1);
|
|
assign per_bank_not_silent_update_2_1 =
|
|
(wrbypass_data_valid_5
|
|
? ~((&_wrbypass_io_T_116) & _GEN_5 | _wrbypass_io_T_116 == 3'h0 & ~_GEN_5)
|
|
: ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7;
|
|
wire [2:0] _wrbypass_io_T_138 =
|
|
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits)
|
|
| (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0);
|
|
wire wrbypass_data_valid_6 =
|
|
(~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1]
|
|
& _bank_wrbypasses_3_1_io_hit)
|
|
& (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1]
|
|
& _bank_wrbypasses_3_1_io_hit_data_0_valid);
|
|
wire [2:0] per_bank_update_wdata_3_0_ctr =
|
|
_GEN_4
|
|
? (_GEN_1 ? 3'h4 : 3'h3)
|
|
: wrbypass_data_valid_6
|
|
? ((&_wrbypass_io_T_138) & _GEN_1
|
|
? 3'h7
|
|
: _wrbypass_io_T_138 == 3'h0 & ~_GEN_1
|
|
? 3'h0
|
|
: _GEN_1
|
|
? 3'(_wrbypass_io_T_138 + 3'h1)
|
|
: 3'(_wrbypass_io_T_138 - 3'h1))
|
|
: (&_GEN_2) & _GEN_1
|
|
? 3'h7
|
|
: _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0;
|
|
assign per_bank_not_silent_update_3_0 =
|
|
(wrbypass_data_valid_6
|
|
? ~((&_wrbypass_io_T_138) & _GEN_1 | _wrbypass_io_T_138 == 3'h0 & ~_GEN_1)
|
|
: ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4;
|
|
wire [2:0] _wrbypass_io_T_160 =
|
|
(io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0)
|
|
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits);
|
|
wire wrbypass_data_valid_7 =
|
|
(io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1])
|
|
& _bank_wrbypasses_3_1_io_hit)
|
|
& (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1])
|
|
& _bank_wrbypasses_3_1_io_hit_data_0_valid);
|
|
wire [2:0] per_bank_update_wdata_3_1_ctr =
|
|
_GEN_7
|
|
? (_GEN_5 ? 3'h4 : 3'h3)
|
|
: wrbypass_data_valid_7
|
|
? ((&_wrbypass_io_T_160) & _GEN_5
|
|
? 3'h7
|
|
: _wrbypass_io_T_160 == 3'h0 & ~_GEN_5
|
|
? 3'h0
|
|
: _GEN_5
|
|
? 3'(_wrbypass_io_T_160 + 3'h1)
|
|
: 3'(_wrbypass_io_T_160 - 3'h1))
|
|
: (&_GEN_6) & _GEN_5
|
|
? 3'h7
|
|
: _GEN_6 == 3'h0 & ~_GEN_5
|
|
? 3'h0
|
|
: _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1);
|
|
assign per_bank_not_silent_update_3_1 =
|
|
(wrbypass_data_valid_7
|
|
? ~((&_wrbypass_io_T_160) & _GEN_5 | _wrbypass_io_T_160 == 3'h0 & ~_GEN_5)
|
|
: ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7;
|
|
always @(posedge clock) begin
|
|
if (_s1_bank_req_1h_T) begin
|
|
s1_unhashed_idx <= io_req_bits_pc[40:1];
|
|
s1_tag <= _GEN ^ {io_req_bits_folded_hist_hist_7_folded_hist, 1'h0};
|
|
s1_bank_req_1h_0 <= s0_bank_req_1h_0;
|
|
s1_bank_req_1h_1 <= s0_bank_req_1h_1;
|
|
s1_bank_req_1h_2 <= s0_bank_req_1h_2;
|
|
s1_bank_req_1h_3 <= &(_GEN[1:0]);
|
|
end
|
|
if (io_req_valid) begin
|
|
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0;
|
|
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1;
|
|
s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2;
|
|
s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3;
|
|
end
|
|
end // always @(posedge)
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset)
|
|
powerOnResetState <= 1'h1;
|
|
else
|
|
powerOnResetState <=
|
|
~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready
|
|
& _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready
|
|
& _table_banks_3_io_r_req_ready) & powerOnResetState;
|
|
end // always @(posedge, posedge)
|
|
`ifdef ENABLE_INITIAL_REG_
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif // FIRRTL_BEFORE_INITIAL
|
|
logic [31:0] _RANDOM[0:3];
|
|
initial begin
|
|
`ifdef INIT_RANDOM_PROLOG_
|
|
`INIT_RANDOM_PROLOG_
|
|
`endif // INIT_RANDOM_PROLOG_
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
|
|
_RANDOM[i[1:0]] = `RANDOM;
|
|
end
|
|
s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][7:0]};
|
|
s1_tag = _RANDOM[2'h1][26:19];
|
|
s1_bank_req_1h_0 = _RANDOM[2'h3][4];
|
|
s1_bank_req_1h_1 = _RANDOM[2'h3][5];
|
|
s1_bank_req_1h_2 = _RANDOM[2'h3][6];
|
|
s1_bank_req_1h_3 = _RANDOM[2'h3][7];
|
|
s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][8];
|
|
s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][9];
|
|
s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][10];
|
|
s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][11];
|
|
powerOnResetState = _RANDOM[2'h3][12];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset)
|
|
powerOnResetState = 1'h1;
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif // FIRRTL_AFTER_INITIAL
|
|
`endif // ENABLE_INITIAL_REG_
|
|
FoldedSRAMTemplate us (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_r_req_ready (_us_io_r_req_ready),
|
|
.io_r_req_valid (_s1_bank_req_1h_T),
|
|
.io_r_req_bits_setIdx ({io_req_bits_pc[11:9], _GEN}),
|
|
.io_r_resp_data_0 (_us_io_r_resp_data_0),
|
|
.io_r_resp_data_1 (_us_io_r_resp_data_1),
|
|
.io_w_req_valid
|
|
(_us_extra_reset_T_1 & (io_update_uMask_0 | io_update_uMask_1)),
|
|
.io_w_req_bits_setIdx ({io_update_pc[11:9], _GEN_0}),
|
|
.io_w_req_bits_data_0
|
|
(~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1),
|
|
.io_w_req_bits_data_1
|
|
(io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1),
|
|
.io_w_req_bits_waymask
|
|
({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1,
|
|
~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}),
|
|
.extra_reset
|
|
((io_update_reset_u_0 | io_update_reset_u_1) & _us_extra_reset_T_1)
|
|
);
|
|
FoldedSRAMTemplate_1 table_banks_0 (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_r_req_ready (_table_banks_0_io_r_req_ready),
|
|
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0),
|
|
.io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T),
|
|
.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
|
|
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
|
|
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
|
|
.io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid),
|
|
.io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag),
|
|
.io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr),
|
|
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0),
|
|
.io_w_req_bits_setIdx (update_idx_in_bank),
|
|
.io_w_req_bits_data_0_tag (update_tag),
|
|
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr),
|
|
.io_w_req_bits_data_1_tag (update_tag),
|
|
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr),
|
|
.io_w_req_bits_waymask (per_bank_update_way_mask_0)
|
|
);
|
|
FoldedSRAMTemplate_1 table_banks_1 (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_r_req_ready (_table_banks_1_io_r_req_ready),
|
|
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1),
|
|
.io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T),
|
|
.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
|
|
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
|
|
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
|
|
.io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid),
|
|
.io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag),
|
|
.io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr),
|
|
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1),
|
|
.io_w_req_bits_setIdx (update_idx_in_bank),
|
|
.io_w_req_bits_data_0_tag (update_tag),
|
|
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr),
|
|
.io_w_req_bits_data_1_tag (update_tag),
|
|
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr),
|
|
.io_w_req_bits_waymask (per_bank_update_way_mask_1)
|
|
);
|
|
FoldedSRAMTemplate_1 table_banks_2 (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_r_req_ready (_table_banks_2_io_r_req_ready),
|
|
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2),
|
|
.io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T),
|
|
.io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid),
|
|
.io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag),
|
|
.io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr),
|
|
.io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid),
|
|
.io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag),
|
|
.io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr),
|
|
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2),
|
|
.io_w_req_bits_setIdx (update_idx_in_bank),
|
|
.io_w_req_bits_data_0_tag (update_tag),
|
|
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr),
|
|
.io_w_req_bits_data_1_tag (update_tag),
|
|
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr),
|
|
.io_w_req_bits_waymask (per_bank_update_way_mask_2)
|
|
);
|
|
FoldedSRAMTemplate_1 table_banks_3 (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_r_req_ready (_table_banks_3_io_r_req_ready),
|
|
.io_r_req_valid (_s1_bank_req_1h_T & (&(_GEN[1:0]))),
|
|
.io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T),
|
|
.io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid),
|
|
.io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag),
|
|
.io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr),
|
|
.io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid),
|
|
.io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag),
|
|
.io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr),
|
|
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3),
|
|
.io_w_req_bits_setIdx (update_idx_in_bank),
|
|
.io_w_req_bits_data_0_tag (update_tag),
|
|
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr),
|
|
.io_w_req_bits_data_1_tag (update_tag),
|
|
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr),
|
|
.io_w_req_bits_waymask (per_bank_update_way_mask_3)
|
|
);
|
|
WrBypass bank_wrbypasses_0_0 (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_wen (io_update_mask_0 & update_req_bank_1h_0),
|
|
.io_write_idx (update_idx_in_bank),
|
|
.io_write_data_0
|
|
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr)
|
|
| (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)),
|
|
.io_hit (_bank_wrbypasses_0_0_io_hit),
|
|
.io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid),
|
|
.io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits)
|
|
);
|
|
WrBypass bank_wrbypasses_0_1 (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_wen (io_update_mask_1 & update_req_bank_1h_0),
|
|
.io_write_idx (update_idx_in_bank),
|
|
.io_write_data_0
|
|
((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0)
|
|
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)),
|
|
.io_hit (_bank_wrbypasses_0_1_io_hit),
|
|
.io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid),
|
|
.io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits)
|
|
);
|
|
WrBypass bank_wrbypasses_1_0 (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_wen (io_update_mask_0 & update_req_bank_1h_1),
|
|
.io_write_idx (update_idx_in_bank),
|
|
.io_write_data_0
|
|
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr)
|
|
| (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)),
|
|
.io_hit (_bank_wrbypasses_1_0_io_hit),
|
|
.io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid),
|
|
.io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits)
|
|
);
|
|
WrBypass bank_wrbypasses_1_1 (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_wen (io_update_mask_1 & update_req_bank_1h_1),
|
|
.io_write_idx (update_idx_in_bank),
|
|
.io_write_data_0
|
|
((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0)
|
|
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)),
|
|
.io_hit (_bank_wrbypasses_1_1_io_hit),
|
|
.io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid),
|
|
.io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits)
|
|
);
|
|
WrBypass bank_wrbypasses_2_0 (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_wen (io_update_mask_0 & update_req_bank_1h_2),
|
|
.io_write_idx (update_idx_in_bank),
|
|
.io_write_data_0
|
|
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr)
|
|
| (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)),
|
|
.io_hit (_bank_wrbypasses_2_0_io_hit),
|
|
.io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid),
|
|
.io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits)
|
|
);
|
|
WrBypass bank_wrbypasses_2_1 (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_wen (io_update_mask_1 & update_req_bank_1h_2),
|
|
.io_write_idx (update_idx_in_bank),
|
|
.io_write_data_0
|
|
((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0)
|
|
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)),
|
|
.io_hit (_bank_wrbypasses_2_1_io_hit),
|
|
.io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid),
|
|
.io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits)
|
|
);
|
|
WrBypass bank_wrbypasses_3_0 (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_wen (io_update_mask_0 & (&(_GEN_0[1:0]))),
|
|
.io_write_idx (update_idx_in_bank),
|
|
.io_write_data_0
|
|
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr)
|
|
| (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)),
|
|
.io_hit (_bank_wrbypasses_3_0_io_hit),
|
|
.io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid),
|
|
.io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits)
|
|
);
|
|
WrBypass bank_wrbypasses_3_1 (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_wen (io_update_mask_1 & (&(_GEN_0[1:0]))),
|
|
.io_write_idx (update_idx_in_bank),
|
|
.io_write_data_0
|
|
((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0)
|
|
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)),
|
|
.io_hit (_bank_wrbypasses_3_1_io_hit),
|
|
.io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid),
|
|
.io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits)
|
|
);
|
|
assign io_req_ready = ~powerOnResetState;
|
|
assign io_resps_0_valid =
|
|
~(s1_unhashed_idx[0]) & _hit_selected_T_6 | s1_unhashed_idx[0] & _hit_selected_T_13;
|
|
assign io_resps_0_bits_ctr =
|
|
(s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_6)
|
|
| (s1_unhashed_idx[0] ? _resp_selected_T_27 : 3'h0);
|
|
assign io_resps_0_bits_u =
|
|
~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0]
|
|
& _us_io_r_resp_data_1;
|
|
assign io_resps_0_bits_unconf =
|
|
~(s1_unhashed_idx[0]) & _unconf_selected_T_6 | s1_unhashed_idx[0]
|
|
& _unconf_selected_T_13;
|
|
assign io_resps_1_valid =
|
|
s1_unhashed_idx[0] & _hit_selected_T_6 | ~(s1_unhashed_idx[0]) & _hit_selected_T_13;
|
|
assign io_resps_1_bits_ctr =
|
|
(s1_unhashed_idx[0] ? _resp_selected_T_6 : 3'h0)
|
|
| (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_27);
|
|
assign io_resps_1_bits_u =
|
|
s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0])
|
|
& _us_io_r_resp_data_1;
|
|
assign io_resps_1_bits_unconf =
|
|
s1_unhashed_idx[0] & _unconf_selected_T_6 | ~(s1_unhashed_idx[0])
|
|
& _unconf_selected_T_13;
|
|
endmodule
|
|
|