189 lines
6.6 KiB
Systemverilog
189 lines
6.6 KiB
Systemverilog
// Generated by CIRCT firtool-1.62.0
|
|
// Standard header to adapt well known macros for register randomization.
|
|
`ifndef RANDOMIZE
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif // RANDOMIZE_MEM_INIT
|
|
`endif // not def RANDOMIZE
|
|
`ifndef RANDOMIZE
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif // RANDOMIZE_REG_INIT
|
|
`endif // not def RANDOMIZE
|
|
|
|
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif // not def RANDOM
|
|
|
|
// Users can define INIT_RANDOM as general code that gets injected into the
|
|
// initializer block for modules with registers.
|
|
`ifndef INIT_RANDOM
|
|
`define INIT_RANDOM
|
|
`endif // not def INIT_RANDOM
|
|
|
|
// If using random initialization, you can also define RANDOMIZE_DELAY to
|
|
// customize the delay used, otherwise 0.002 is used.
|
|
`ifndef RANDOMIZE_DELAY
|
|
`define RANDOMIZE_DELAY 0.002
|
|
`endif // not def RANDOMIZE_DELAY
|
|
|
|
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
|
|
`ifndef INIT_RANDOM_PROLOG_
|
|
`ifdef RANDOMIZE
|
|
`ifdef VERILATOR
|
|
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
|
|
`else // VERILATOR
|
|
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
|
|
`endif // VERILATOR
|
|
`else // RANDOMIZE
|
|
`define INIT_RANDOM_PROLOG_
|
|
`endif // RANDOMIZE
|
|
`endif // not def INIT_RANDOM_PROLOG_
|
|
|
|
// Include register initializers in init blocks unless synthesis is set
|
|
`ifndef SYNTHESIS
|
|
`ifndef ENABLE_INITIAL_REG_
|
|
`define ENABLE_INITIAL_REG_
|
|
`endif // not def ENABLE_INITIAL_REG_
|
|
`endif // not def SYNTHESIS
|
|
|
|
// Include rmemory initializers in init blocks unless synthesis is set
|
|
`ifndef SYNTHESIS
|
|
`ifndef ENABLE_INITIAL_MEM_
|
|
`define ENABLE_INITIAL_MEM_
|
|
`endif // not def ENABLE_INITIAL_MEM_
|
|
`endif // not def SYNTHESIS
|
|
|
|
module TageBTable(
|
|
input clock,
|
|
input reset,
|
|
output io_req_ready,
|
|
input io_req_valid,
|
|
input [40:0] io_req_bits,
|
|
output [1:0] io_s1_cnt_0,
|
|
output [1:0] io_s1_cnt_1,
|
|
input io_update_mask_0,
|
|
input io_update_mask_1,
|
|
input [40:0] io_update_pc,
|
|
input [1:0] io_update_cnt_0,
|
|
input [1:0] io_update_cnt_1,
|
|
input io_update_takens_0,
|
|
input io_update_takens_1
|
|
);
|
|
|
|
wire [1:0] newCtrs_1;
|
|
wire [1:0] newCtrs_0;
|
|
wire _wrbypass_io_hit;
|
|
wire _wrbypass_io_hit_data_0_valid;
|
|
wire [1:0] _wrbypass_io_hit_data_0_bits;
|
|
wire _wrbypass_io_hit_data_1_valid;
|
|
wire [1:0] _wrbypass_io_hit_data_1_bits;
|
|
wire [1:0] _bt_io_r_resp_data_0;
|
|
wire [1:0] _bt_io_r_resp_data_1;
|
|
reg doing_reset;
|
|
reg [10:0] resetRow;
|
|
reg [10:0] s1_idx;
|
|
wire _wrbypass_io_wen_T = io_update_mask_0 | io_update_mask_1;
|
|
wire [1:0] oldCtrs_0 =
|
|
_wrbypass_io_hit
|
|
& (io_update_pc[1] ? _wrbypass_io_hit_data_1_valid : _wrbypass_io_hit_data_0_valid)
|
|
? (io_update_pc[1] ? _wrbypass_io_hit_data_1_bits : _wrbypass_io_hit_data_0_bits)
|
|
: io_update_pc[1] ? io_update_cnt_1 : io_update_cnt_0;
|
|
wire [1:0] oldCtrs_1 =
|
|
_wrbypass_io_hit
|
|
& (io_update_pc[1] ? _wrbypass_io_hit_data_0_valid : _wrbypass_io_hit_data_1_valid)
|
|
? (io_update_pc[1] ? _wrbypass_io_hit_data_0_bits : _wrbypass_io_hit_data_1_bits)
|
|
: io_update_pc[1] ? io_update_cnt_0 : io_update_cnt_1;
|
|
wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0;
|
|
assign newCtrs_0 =
|
|
(&oldCtrs_0) & _GEN
|
|
? 2'h3
|
|
: oldCtrs_0 == 2'h0 & ~_GEN
|
|
? 2'h0
|
|
: _GEN ? 2'(oldCtrs_0 + 2'h1) : 2'(oldCtrs_0 - 2'h1);
|
|
wire _GEN_0 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1;
|
|
assign newCtrs_1 =
|
|
(&oldCtrs_1) & _GEN_0
|
|
? 2'h3
|
|
: oldCtrs_1 == 2'h0 & ~_GEN_0
|
|
? 2'h0
|
|
: _GEN_0 ? 2'(oldCtrs_1 + 2'h1) : 2'(oldCtrs_1 - 2'h1);
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
doing_reset <= 1'h1;
|
|
resetRow <= 11'h0;
|
|
end
|
|
else begin
|
|
doing_reset <= resetRow != 11'h7FF & doing_reset;
|
|
resetRow <= 11'(resetRow + {10'h0, doing_reset});
|
|
end
|
|
end // always @(posedge, posedge)
|
|
always @(posedge clock) begin
|
|
if (io_req_valid)
|
|
s1_idx <= io_req_bits[11:1];
|
|
end // always @(posedge)
|
|
`ifdef ENABLE_INITIAL_REG_
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif // FIRRTL_BEFORE_INITIAL
|
|
logic [31:0] _RANDOM[0:0];
|
|
initial begin
|
|
`ifdef INIT_RANDOM_PROLOG_
|
|
`INIT_RANDOM_PROLOG_
|
|
`endif // INIT_RANDOM_PROLOG_
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
|
|
doing_reset = _RANDOM[/*Zero width*/ 1'b0][0];
|
|
resetRow = _RANDOM[/*Zero width*/ 1'b0][11:1];
|
|
s1_idx = _RANDOM[/*Zero width*/ 1'b0][22:12];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
doing_reset = 1'h1;
|
|
resetRow = 11'h0;
|
|
end
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif // FIRRTL_AFTER_INITIAL
|
|
`endif // ENABLE_INITIAL_REG_
|
|
FoldedSRAMTemplate_20 bt (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_r_req_valid (io_req_valid),
|
|
.io_r_req_bits_setIdx (io_req_bits[11:1]),
|
|
.io_r_resp_data_0 (_bt_io_r_resp_data_0),
|
|
.io_r_resp_data_1 (_bt_io_r_resp_data_1),
|
|
.io_w_req_valid (_wrbypass_io_wen_T | doing_reset),
|
|
.io_w_req_bits_setIdx (doing_reset ? resetRow : io_update_pc[11:1]),
|
|
.io_w_req_bits_data_0 (doing_reset ? 2'h2 : newCtrs_0),
|
|
.io_w_req_bits_data_1 (doing_reset ? 2'h2 : newCtrs_1),
|
|
.io_w_req_bits_waymask
|
|
(doing_reset
|
|
? 2'h3
|
|
: {io_update_mask_0 & io_update_pc[1] | io_update_mask_1 & ~(io_update_pc[1]),
|
|
io_update_mask_0 & ~(io_update_pc[1]) | io_update_mask_1 & io_update_pc[1]})
|
|
);
|
|
WrBypass_32 wrbypass (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_wen (_wrbypass_io_wen_T),
|
|
.io_write_idx (io_update_pc[11:1]),
|
|
.io_write_data_0 (io_update_pc[1] ? newCtrs_1 : newCtrs_0),
|
|
.io_write_data_1 (io_update_pc[1] ? newCtrs_0 : newCtrs_1),
|
|
.io_write_way_mask_0 (io_update_mask_0),
|
|
.io_write_way_mask_1 (io_update_mask_1),
|
|
.io_hit (_wrbypass_io_hit),
|
|
.io_hit_data_0_valid (_wrbypass_io_hit_data_0_valid),
|
|
.io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits),
|
|
.io_hit_data_1_valid (_wrbypass_io_hit_data_1_valid),
|
|
.io_hit_data_1_bits (_wrbypass_io_hit_data_1_bits)
|
|
);
|
|
assign io_req_ready = ~doing_reset;
|
|
assign io_s1_cnt_0 =
|
|
(s1_idx[0] ? 2'h0 : _bt_io_r_resp_data_0) | (s1_idx[0] ? _bt_io_r_resp_data_1 : 2'h0);
|
|
assign io_s1_cnt_1 =
|
|
(s1_idx[0] ? _bt_io_r_resp_data_0 : 2'h0) | (s1_idx[0] ? 2'h0 : _bt_io_r_resp_data_1);
|
|
endmodule
|
|
|