227 lines
9.0 KiB
Systemverilog
227 lines
9.0 KiB
Systemverilog
// Generated by CIRCT firtool-1.62.0
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// Standard header to adapt well known macros for register randomization.
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_MEM_INIT
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`endif // not def RANDOMIZE
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_REG_INIT
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`endif // not def RANDOMIZE
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// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
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`ifndef RANDOM
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`define RANDOM $random
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`endif // not def RANDOM
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// Users can define INIT_RANDOM as general code that gets injected into the
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// initializer block for modules with registers.
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`ifndef INIT_RANDOM
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`define INIT_RANDOM
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`endif // not def INIT_RANDOM
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// If using random initialization, you can also define RANDOMIZE_DELAY to
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// customize the delay used, otherwise 0.002 is used.
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`ifndef RANDOMIZE_DELAY
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`define RANDOMIZE_DELAY 0.002
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`endif // not def RANDOMIZE_DELAY
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// Define INIT_RANDOM_PROLOG_ for use in our modules below.
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`ifndef INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE
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`ifdef VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
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`else // VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
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`endif // VERILATOR
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`else // RANDOMIZE
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`define INIT_RANDOM_PROLOG_
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`endif // RANDOMIZE
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`endif // not def INIT_RANDOM_PROLOG_
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// Include register initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_REG_
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`define ENABLE_INITIAL_REG_
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`endif // not def ENABLE_INITIAL_REG_
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`endif // not def SYNTHESIS
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// Include rmemory initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_MEM_
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`define ENABLE_INITIAL_MEM_
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`endif // not def ENABLE_INITIAL_MEM_
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`endif // not def SYNTHESIS
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module ITTageTable(
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input clock,
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input reset,
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input io_req_valid,
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input [40:0] io_req_bits_pc,
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input [3:0] io_req_bits_folded_hist_hist_12_folded_hist,
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output io_resp_valid,
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output [1:0] io_resp_bits_ctr,
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output [1:0] io_resp_bits_u,
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output [40:0] io_resp_bits_target,
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input [40:0] io_update_pc,
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input [3:0] io_update_folded_hist_hist_12_folded_hist,
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input io_update_valid,
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input io_update_correct,
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input io_update_alloc,
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input [1:0] io_update_oldCtr,
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input io_update_uValid,
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input io_update_u,
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input io_update_reset_u,
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input [40:0] io_update_target,
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input [40:0] io_update_old_target
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);
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wire _resp_invalid_by_write_T_2;
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wire _wrbypass_io_hit;
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wire [1:0] _wrbypass_io_hit_data_0_bits;
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wire _table_banks_1_io_r_resp_data_0_valid;
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wire [8:0] _table_banks_1_io_r_resp_data_0_tag;
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wire [1:0] _table_banks_1_io_r_resp_data_0_ctr;
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wire [40:0] _table_banks_1_io_r_resp_data_0_target;
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wire _table_banks_0_io_r_resp_data_0_valid;
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wire [8:0] _table_banks_0_io_r_resp_data_0_tag;
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wire [1:0] _table_banks_0_io_r_resp_data_0_ctr;
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wire [40:0] _table_banks_0_io_r_resp_data_0_target;
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wire _us_io_rdata_0;
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wire [3:0] _GEN = io_req_bits_pc[4:1] ^ io_req_bits_folded_hist_hist_12_folded_hist;
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reg [8:0] s1_tag;
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reg s1_bank_req_1h_0;
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reg s1_bank_req_1h_1;
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wire [6:0] _table_banks_1_io_r_req_bits_setIdx_T = {io_req_bits_pc[8:5], _GEN[3:1]};
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reg s1_bank_has_write_on_this_req_0;
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reg s1_bank_has_write_on_this_req_1;
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wire [3:0] _GEN_0 = io_update_pc[4:1] ^ io_update_folded_hist_hist_12_folded_hist;
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wire [7:0] update_idx = {io_update_pc[8:5], _GEN_0};
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wire [8:0] update_tag =
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{io_update_pc[17:14],
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{io_update_pc[13], io_update_pc[12:9] ^ io_update_folded_hist_hist_12_folded_hist}
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^ {io_update_folded_hist_hist_12_folded_hist, 1'h0}};
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wire [6:0] update_idx_in_bank = {io_update_pc[8:5], _GEN_0[3:1]};
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assign _resp_invalid_by_write_T_2 =
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s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
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& s1_bank_has_write_on_this_req_1;
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wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(_GEN_0[0]);
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wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & _GEN_0[0];
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wire [1:0] old_ctr =
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_wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr;
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wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0;
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wire [1:0] update_wdata_ctr =
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io_update_alloc
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? 2'h2
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: (&old_ctr) & io_update_correct
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? 2'h3
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: update_wdata_ctr_oldSatNotTaken & ~io_update_correct
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? 2'h0
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: io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1);
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wire [40:0] update_wdata_target =
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io_update_alloc | update_wdata_ctr_oldSatNotTaken
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? io_update_target
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: io_update_old_target;
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always @(posedge clock) begin
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if (io_req_valid) begin
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s1_tag <=
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{io_req_bits_pc[17:14],
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{io_req_bits_pc[13],
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io_req_bits_pc[12:9] ^ io_req_bits_folded_hist_hist_12_folded_hist}
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^ {io_req_bits_folded_hist_hist_12_folded_hist, 1'h0}};
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s1_bank_req_1h_0 <= ~(_GEN[0]);
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s1_bank_req_1h_1 <= _GEN[0];
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s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0;
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s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1;
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end
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end // always @(posedge)
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`ifdef ENABLE_INITIAL_REG_
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`ifdef FIRRTL_BEFORE_INITIAL
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`FIRRTL_BEFORE_INITIAL
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`endif // FIRRTL_BEFORE_INITIAL
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logic [31:0] _RANDOM[0:0];
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initial begin
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`ifdef INIT_RANDOM_PROLOG_
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`INIT_RANDOM_PROLOG_
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`endif // INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE_REG_INIT
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_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
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s1_tag = _RANDOM[/*Zero width*/ 1'b0][16:8];
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s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][17];
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s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][18];
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s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][19];
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s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][20];
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`endif // RANDOMIZE_REG_INIT
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end // initial
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`ifdef FIRRTL_AFTER_INITIAL
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`FIRRTL_AFTER_INITIAL
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`endif // FIRRTL_AFTER_INITIAL
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`endif // ENABLE_INITIAL_REG_
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Folded1WDataModuleTemplate us (
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.clock (clock),
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.reset (reset),
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.io_ren_0 (io_req_valid),
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.io_raddr_0 ({io_req_bits_pc[8:5], _GEN}),
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.io_rdata_0 (_us_io_rdata_0),
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.io_wen (io_update_uValid),
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.io_waddr (update_idx),
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.io_wdata (io_update_u),
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.io_resetEn (io_update_reset_u)
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);
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FoldedSRAMTemplate_21 table_banks_0 (
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.clock (clock),
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.reset (reset),
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.io_r_req_valid (io_req_valid & ~(_GEN[0])),
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.io_r_req_bits_setIdx (_table_banks_1_io_r_req_bits_setIdx_T),
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.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
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.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
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.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
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.io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target),
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.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0),
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.io_w_req_bits_setIdx (update_idx_in_bank),
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.io_w_req_bits_data_0_tag (update_tag),
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.io_w_req_bits_data_0_ctr (update_wdata_ctr),
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.io_w_req_bits_data_0_target (update_wdata_target)
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);
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FoldedSRAMTemplate_21 table_banks_1 (
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.clock (clock),
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.reset (reset),
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.io_r_req_valid (io_req_valid & _GEN[0]),
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.io_r_req_bits_setIdx (_table_banks_1_io_r_req_bits_setIdx_T),
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.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
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.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
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.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
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.io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target),
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.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1),
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.io_w_req_bits_setIdx (update_idx_in_bank),
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.io_w_req_bits_data_0_tag (update_tag),
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.io_w_req_bits_data_0_ctr (update_wdata_ctr),
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.io_w_req_bits_data_0_target (update_wdata_target)
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);
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WrBypass_41 wrbypass (
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.clock (clock),
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.reset (reset),
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.io_wen (io_update_valid),
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.io_write_idx (update_idx),
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.io_write_data_0 (update_wdata_ctr),
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.io_hit (_wrbypass_io_hit),
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.io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits)
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);
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assign io_resp_valid =
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(s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1
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& _table_banks_1_io_r_resp_data_0_valid)
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& ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0)
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| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag
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& ~_resp_invalid_by_write_T_2;
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assign io_resp_bits_ctr =
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(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0)
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| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0);
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assign io_resp_bits_u = {1'h0, _us_io_rdata_0};
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assign io_resp_bits_target =
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(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0)
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| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0);
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endmodule
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