108 lines
3.1 KiB
Systemverilog
108 lines
3.1 KiB
Systemverilog
// Generated by CIRCT firtool-1.62.0
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// Standard header to adapt well known macros for register randomization.
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_MEM_INIT
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`endif // not def RANDOMIZE
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_REG_INIT
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`endif // not def RANDOMIZE
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// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
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`ifndef RANDOM
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`define RANDOM $random
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`endif // not def RANDOM
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// Users can define INIT_RANDOM as general code that gets injected into the
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// initializer block for modules with registers.
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`ifndef INIT_RANDOM
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`define INIT_RANDOM
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`endif // not def INIT_RANDOM
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// If using random initialization, you can also define RANDOMIZE_DELAY to
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// customize the delay used, otherwise 0.002 is used.
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`ifndef RANDOMIZE_DELAY
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`define RANDOMIZE_DELAY 0.002
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`endif // not def RANDOMIZE_DELAY
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// Define INIT_RANDOM_PROLOG_ for use in our modules below.
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`ifndef INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE
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`ifdef VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
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`else // VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
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`endif // VERILATOR
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`else // RANDOMIZE
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`define INIT_RANDOM_PROLOG_
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`endif // RANDOMIZE
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`endif // not def INIT_RANDOM_PROLOG_
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// Include register initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_REG_
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`define ENABLE_INITIAL_REG_
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`endif // not def ENABLE_INITIAL_REG_
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`endif // not def SYNTHESIS
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// Include rmemory initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_MEM_
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`define ENABLE_INITIAL_MEM_
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`endif // not def ENABLE_INITIAL_MEM_
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`endif // not def SYNTHESIS
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module DelayNWithValid(
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input clock,
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input reset,
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input [40:0] io_in_bits,
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input io_in_valid,
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output [40:0] io_out_bits
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);
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reg valid_REG;
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reg [40:0] data;
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reg [40:0] res_bits;
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always @(posedge clock or posedge reset) begin
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if (reset)
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valid_REG <= 1'h0;
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else
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valid_REG <= io_in_valid;
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end // always @(posedge, posedge)
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always @(posedge clock) begin
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if (io_in_valid)
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data <= io_in_bits;
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if (valid_REG)
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res_bits <= data;
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end // always @(posedge)
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`ifdef ENABLE_INITIAL_REG_
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`ifdef FIRRTL_BEFORE_INITIAL
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`FIRRTL_BEFORE_INITIAL
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`endif // FIRRTL_BEFORE_INITIAL
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logic [31:0] _RANDOM[0:2];
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initial begin
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`ifdef INIT_RANDOM_PROLOG_
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`INIT_RANDOM_PROLOG_
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`endif // INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE_REG_INIT
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for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin
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_RANDOM[i] = `RANDOM;
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end
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valid_REG = _RANDOM[2'h0][0];
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data = {_RANDOM[2'h0][31:1], _RANDOM[2'h1][9:0]};
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res_bits = {_RANDOM[2'h1][31:11], _RANDOM[2'h2][19:0]};
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`endif // RANDOMIZE_REG_INIT
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if (reset)
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valid_REG = 1'h0;
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end // initial
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`ifdef FIRRTL_AFTER_INITIAL
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`FIRRTL_AFTER_INITIAL
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`endif // FIRRTL_AFTER_INITIAL
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`endif // ENABLE_INITIAL_REG_
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assign io_out_bits = res_bits;
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endmodule
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