137 lines
4.4 KiB
Systemverilog
137 lines
4.4 KiB
Systemverilog
// Generated by CIRCT firtool-1.62.0
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// Standard header to adapt well known macros for register randomization.
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_MEM_INIT
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`endif // not def RANDOMIZE
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_REG_INIT
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`endif // not def RANDOMIZE
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// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
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`ifndef RANDOM
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`define RANDOM $random
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`endif // not def RANDOM
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// Users can define INIT_RANDOM as general code that gets injected into the
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// initializer block for modules with registers.
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`ifndef INIT_RANDOM
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`define INIT_RANDOM
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`endif // not def INIT_RANDOM
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// If using random initialization, you can also define RANDOMIZE_DELAY to
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// customize the delay used, otherwise 0.002 is used.
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`ifndef RANDOMIZE_DELAY
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`define RANDOMIZE_DELAY 0.002
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`endif // not def RANDOMIZE_DELAY
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// Define INIT_RANDOM_PROLOG_ for use in our modules below.
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`ifndef INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE
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`ifdef VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
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`else // VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
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`endif // VERILATOR
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`else // RANDOMIZE
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`define INIT_RANDOM_PROLOG_
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`endif // RANDOMIZE
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`endif // not def INIT_RANDOM_PROLOG_
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// Include register initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_REG_
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`define ENABLE_INITIAL_REG_
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`endif // not def ENABLE_INITIAL_REG_
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`endif // not def SYNTHESIS
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// Include rmemory initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_MEM_
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`define ENABLE_INITIAL_MEM_
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`endif // not def ENABLE_INITIAL_MEM_
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`endif // not def SYNTHESIS
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module CAMTemplate(
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input clock,
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input [8:0] io_r_req_0_idx,
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output io_r_resp_0_0,
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output io_r_resp_0_1,
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output io_r_resp_0_2,
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output io_r_resp_0_3,
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output io_r_resp_0_4,
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output io_r_resp_0_5,
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output io_r_resp_0_6,
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output io_r_resp_0_7,
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input io_w_valid,
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input [8:0] io_w_bits_data_idx,
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input [2:0] io_w_bits_index
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);
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reg [8:0] array_0;
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reg [8:0] array_1;
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reg [8:0] array_2;
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reg [8:0] array_3;
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reg [8:0] array_4;
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reg [8:0] array_5;
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reg [8:0] array_6;
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reg [8:0] array_7;
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always @(posedge clock) begin
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if (io_w_valid & io_w_bits_index == 3'h0)
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array_0 <= io_w_bits_data_idx;
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if (io_w_valid & io_w_bits_index == 3'h1)
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array_1 <= io_w_bits_data_idx;
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if (io_w_valid & io_w_bits_index == 3'h2)
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array_2 <= io_w_bits_data_idx;
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if (io_w_valid & io_w_bits_index == 3'h3)
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array_3 <= io_w_bits_data_idx;
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if (io_w_valid & io_w_bits_index == 3'h4)
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array_4 <= io_w_bits_data_idx;
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if (io_w_valid & io_w_bits_index == 3'h5)
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array_5 <= io_w_bits_data_idx;
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if (io_w_valid & io_w_bits_index == 3'h6)
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array_6 <= io_w_bits_data_idx;
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if (io_w_valid & (&io_w_bits_index))
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array_7 <= io_w_bits_data_idx;
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end // always @(posedge)
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`ifdef ENABLE_INITIAL_REG_
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`ifdef FIRRTL_BEFORE_INITIAL
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`FIRRTL_BEFORE_INITIAL
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`endif // FIRRTL_BEFORE_INITIAL
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logic [31:0] _RANDOM[0:2];
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initial begin
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`ifdef INIT_RANDOM_PROLOG_
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`INIT_RANDOM_PROLOG_
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`endif // INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE_REG_INIT
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for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin
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_RANDOM[i] = `RANDOM;
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end
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array_0 = _RANDOM[2'h0][8:0];
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array_1 = _RANDOM[2'h0][17:9];
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array_2 = _RANDOM[2'h0][26:18];
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array_3 = {_RANDOM[2'h0][31:27], _RANDOM[2'h1][3:0]};
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array_4 = _RANDOM[2'h1][12:4];
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array_5 = _RANDOM[2'h1][21:13];
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array_6 = _RANDOM[2'h1][30:22];
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array_7 = {_RANDOM[2'h1][31], _RANDOM[2'h2][7:0]};
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`endif // RANDOMIZE_REG_INIT
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end // initial
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`ifdef FIRRTL_AFTER_INITIAL
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`FIRRTL_AFTER_INITIAL
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`endif // FIRRTL_AFTER_INITIAL
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`endif // ENABLE_INITIAL_REG_
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assign io_r_resp_0_0 = io_r_req_0_idx == array_0;
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assign io_r_resp_0_1 = io_r_req_0_idx == array_1;
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assign io_r_resp_0_2 = io_r_req_0_idx == array_2;
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assign io_r_resp_0_3 = io_r_req_0_idx == array_3;
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assign io_r_resp_0_4 = io_r_req_0_idx == array_4;
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assign io_r_resp_0_5 = io_r_req_0_idx == array_5;
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assign io_r_resp_0_6 = io_r_req_0_idx == array_6;
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assign io_r_resp_0_7 = io_r_req_0_idx == array_7;
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endmodule
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