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initial BPU sub moudle build makefile 

contain uFTB,Tage_SC,FTB
This commit is contained in:
Makiras 2024-03-28 06:33:09 +00:00
parent beafd0c694
commit 84acbf4234
60 changed files with 72270 additions and 0 deletions
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.gitignore vendored Normal file
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out
split_verilogs

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Makefile Normal file
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export LANG ?= python
export WAVE ?= true
export VERBOSE ?= false
export EXAMPLE ?= false
export TARGET
default:
echo "TODO"
tage_sc:
make -f ./mk/Tage.mk tage_sc
uftb:
make -f ./mk/uFTB.mk uftb
ftb:
make -f ./mk/FTB.mk ftb
filter:
cat log|grep Cannot |awk '{print $8}'| sort| uniq|tr -d "'"
all: tage_sc uftb ftb

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TOP_ENTRY := ./src/FTB/FTB.sv
TOP_FILES := ./src/FTB.txt
LANG ?= cpp
ifneq ($(TARGET),)
TARGET := $(TARGET)
else
TARGET := out/picker_out_FTB
endif
# if EXAMPLE is set, then _EXAMPLE is set to -e
ifneq ($(EXAMPLE), false)
_EXAMPLE := -e
endif
_EXAMPLE ?=
# if VERBOSE is set, then _VERBOSE is set to -v
ifneq ($(VERBOSE), false)
_VERBOSE := -v
endif
_VERBOSE ?=
# if WAVE is set, then _WAVEFORM is set to -w
ifneq ($(WAVE), false)
ifneq ($(WAVE), true)
_WAVEFORM := -w $(WAVE)
else
_WAVEFORM := -w FTB.fst
endif
endif
_WAVEFORM ?=
ftb:
@echo "Building tage module with parameters: "
@echo "LANG=${LANG}"
@echo "TOP_ENTRY=${TOP_ENTRY}"
@echo "TOP_FILES=${TOP_FILES}"
@echo "TARGET=${TARGET}"
@echo "WAVEFORM=${_WAVEFORM}"
@echo "VERBOSE=${_VERBOSE}"
@echo "EXAMPLE=${_EXAMPLE}"
@mkdir -p out
rm -rf ${TARGET}
picker ${TOP_ENTRY} -f ${TOP_FILES} -l ${LANG} \
-t ${TARGET} ${_WAVEFORM}${_EXAMPLE} ${_VERBOSE}
cd ${TARGET} && make

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TOP_ENTRY := ./src/TageSC/Tage_SC.sv
TOP_FILES := ./src/Tage_SC.txt
LANG ?= cpp
ifneq ($(TARGET),)
TARGET := $(TARGET)
else
TARGET := out/picker_out_TageSC
endif
# if EXAMPLE is set, then _EXAMPLE is set to -e
ifneq ($(EXAMPLE), false)
_EXAMPLE := -e
endif
_EXAMPLE ?=
# if VERBOSE is set, then _VERBOSE is set to -v
ifneq ($(VERBOSE), false)
_VERBOSE := -v
endif
_VERBOSE ?=
# if WAVE is set, then _WAVEFORM is set to -w
ifneq ($(WAVE), false)
ifneq ($(WAVE), true)
_WAVEFORM := -w $(WAVE)
else
_WAVEFORM := -w TageSC.fst
endif
endif
_WAVEFORM ?=
tage_sc:
@echo "Building tage module with parameters: "
@echo "LANG=${LANG}"
@echo "TOP_ENTRY=${TOP_ENTRY}"
@echo "TOP_FILES=${TOP_FILES}"
@echo "TARGET=${TARGET}"
@echo "WAVEFORM=${_WAVEFORM}"
@echo "VERBOSE=${_VERBOSE}"
@echo "EXAMPLE=${_EXAMPLE}"
@mkdir -p out
rm -rf ${TARGET}
picker ${TOP_ENTRY} -f ${TOP_FILES} -l ${LANG} \
-t ${TARGET} ${_WAVEFORM}${_EXAMPLE} ${_VERBOSE}
cd ${TARGET} && make

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TOP_ENTRY := ./src/uFTB/FauFTB.sv
TOP_FILES := ./src/uFTB.txt
LANG ?= cpp
ifneq ($(TARGET),)
TARGET := $(TARGET)
else
TARGET := out/picker_out_uFTB
endif
# if EXAMPLE is set, then _EXAMPLE is set to -e
ifneq ($(EXAMPLE), false)
_EXAMPLE := -e
endif
_EXAMPLE ?=
# if VERBOSE is set, then _VERBOSE is set to -v
ifneq ($(VERBOSE), false)
_VERBOSE := -v
endif
_VERBOSE ?=
# if WAVE is set, then _WAVEFORM is set to -w
ifneq ($(WAVE), false)
ifneq ($(WAVE), true)
_WAVEFORM := -w $(WAVE)
else
_WAVEFORM := -w uFTB.fst
endif
endif
_WAVEFORM ?=
uftb:
@echo "Building tage module with parameters: "
@echo "LANG=${LANG}"
@echo "TOP_ENTRY=${TOP_ENTRY}"
@echo "TOP_FILES=${TOP_FILES}"
@echo "TARGET=${TARGET}"
@echo "WAVEFORM=${_WAVEFORM}"
@echo "VERBOSE=${_VERBOSE}"
@echo "EXAMPLE=${_EXAMPLE}"
@mkdir -p out
rm -rf ${TARGET}
picker ${TOP_ENTRY} -f ${TOP_FILES} -l ${LANG} \
-t ${TARGET} ${_WAVEFORM}${_EXAMPLE} ${_VERBOSE}
cd ${TARGET} && make

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./src/FTB/FTBBank.sv
./src/FTB/FTBEntryGen.sv
./src/FTB/SRAMTemplate_9.sv
./src/FTB/array_3.sv
./src/common/ext_sram.v
./src/common/DelayN_2.sv
./src/common/DelayN_4.sv
./src/common/DelayN_5.sv
./src/common/DelayN_6.sv

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// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module FTBEntryGen( // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7
input [38:0] io_start_addr, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_old_entry_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input [3:0] io_old_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input [11:0] io_old_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input [1:0] io_old_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_old_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_old_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input [3:0] io_old_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input [19:0] io_old_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input [1:0] io_old_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_old_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_old_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input [3:0] io_old_entry_pftAddr, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_old_entry_carry, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_old_entry_isCall, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_old_entry_isRet, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_old_entry_isJalr, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_old_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_old_entry_always_taken_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_old_entry_always_taken_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_brMask_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_brMask_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_brMask_2, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_brMask_3, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_brMask_4, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_brMask_5, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_brMask_6, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_brMask_7, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_brMask_8, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_brMask_9, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_brMask_10, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_brMask_11, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_brMask_12, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_brMask_13, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_brMask_14, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_brMask_15, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_jmpInfo_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_jmpInfo_bits_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_jmpInfo_bits_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_jmpInfo_bits_2, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input [3:0] io_pd_jmpOffset, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input [38:0] io_pd_jalTarget, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_rvcMask_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_rvcMask_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_rvcMask_2, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_rvcMask_3, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_rvcMask_4, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_rvcMask_5, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_rvcMask_6, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_rvcMask_7, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_rvcMask_8, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_rvcMask_9, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_rvcMask_10, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_rvcMask_11, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_rvcMask_12, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_rvcMask_13, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_rvcMask_14, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_pd_rvcMask_15, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_cfiIndex_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input [3:0] io_cfiIndex_bits, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input [38:0] io_target, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_hit, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_mispredict_vec_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_mispredict_vec_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_mispredict_vec_2, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_mispredict_vec_3, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_mispredict_vec_4, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_mispredict_vec_5, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_mispredict_vec_6, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_mispredict_vec_7, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_mispredict_vec_8, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_mispredict_vec_9, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_mispredict_vec_10, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_mispredict_vec_11, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_mispredict_vec_12, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_mispredict_vec_13, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_mispredict_vec_14, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
input io_mispredict_vec_15, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output io_new_entry_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output [3:0] io_new_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output [11:0] io_new_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output [1:0] io_new_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output io_new_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output io_new_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output [3:0] io_new_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output [19:0] io_new_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output [1:0] io_new_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output io_new_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output io_new_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output [3:0] io_new_entry_pftAddr, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output io_new_entry_carry, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output io_new_entry_isCall, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output io_new_entry_isRet, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output io_new_entry_isJalr, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output io_new_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output io_new_entry_always_taken_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output io_new_entry_always_taken_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output io_taken_mask_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output io_taken_mask_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output io_jmp_taken, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output io_mispred_mask_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output io_mispred_mask_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output io_mispred_mask_2, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
output io_is_old_entry // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
);
wire [15:0] _GEN =
{{io_pd_brMask_15},
{io_pd_brMask_14},
{io_pd_brMask_13},
{io_pd_brMask_12},
{io_pd_brMask_11},
{io_pd_brMask_10},
{io_pd_brMask_9},
{io_pd_brMask_8},
{io_pd_brMask_7},
{io_pd_brMask_6},
{io_pd_brMask_5},
{io_pd_brMask_4},
{io_pd_brMask_3},
{io_pd_brMask_2},
{io_pd_brMask_1},
{io_pd_brMask_0}}; // src/main/scala/xiangshan/frontend/NewFtq.scala:253:47
wire init_entry_always_taken_0 = _GEN[io_cfiIndex_bits] & io_cfiIndex_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:253:47
wire init_entry_isJalr =
io_pd_jmpInfo_valid & io_pd_jmpInfo_bits_0 & io_cfiIndex_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:256:62
wire last_jmp_rvi = io_pd_jmpInfo_valid & (&io_pd_jmpOffset) & ~io_pd_rvcMask_15; // src/main/scala/xiangshan/frontend/NewFtq.scala:259:{52,75,78}
wire cfi_is_jalr = io_cfiIndex_bits == io_pd_jmpOffset & init_entry_isJalr; // src/main/scala/xiangshan/frontend/NewFtq.scala:256:62, :262:37, :263:55
wire [37:0] _GEN_0 = cfi_is_jalr ? io_target[38:1] : io_pd_jalTarget[38:1]; // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14, :263:55, :284:64
wire [4:0] _GEN_1 = {1'h0, io_start_addr[4:1]}; // src/main/scala/xiangshan/frontend/NewFtq.scala:250:41, :266:30, :287:40
wire [15:0] _GEN_2 =
{{io_pd_rvcMask_15},
{io_pd_rvcMask_14},
{io_pd_rvcMask_13},
{io_pd_rvcMask_12},
{io_pd_rvcMask_11},
{io_pd_rvcMask_10},
{io_pd_rvcMask_9},
{io_pd_rvcMask_8},
{io_pd_rvcMask_7},
{io_pd_rvcMask_6},
{io_pd_rvcMask_5},
{io_pd_rvcMask_4},
{io_pd_rvcMask_3},
{io_pd_rvcMask_2},
{io_pd_rvcMask_1},
{io_pd_rvcMask_0}}; // src/main/scala/xiangshan/frontend/NewFtq.scala:287:62
wire [4:0] jmpPft =
5'(_GEN_1
+ 5'({1'h0, io_pd_jmpOffset} + {3'h0, _GEN_2[io_pd_jmpOffset] ? 2'h1 : 2'h2})); // src/main/scala/xiangshan/frontend/FTB.scala:60:10, :61:12, src/main/scala/xiangshan/frontend/NewFtq.scala:250:41, :287:{40,56,62}
wire is_new_br =
init_entry_always_taken_0
& {io_old_entry_tailSlot_valid & io_old_entry_tailSlot_offset == io_cfiIndex_bits
& io_old_entry_tailSlot_sharing,
io_old_entry_brSlots_0_valid
& io_old_entry_brSlots_0_offset == io_cfiIndex_bits} == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:194:{32,44}, :195:{42,53}, src/main/scala/xiangshan/frontend/NewFtq.scala:250:41, :253:47, :299:{37,44}, :300:29
wire new_br_insert_onehot_0 =
~io_old_entry_brSlots_0_valid | io_cfiIndex_bits < io_old_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/NewFtq.scala:307:{9,33,50}
wire _new_br_insert_onehot_T_3 =
io_cfiIndex_bits > io_old_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/NewFtq.scala:309:53
wire new_br_insert_onehot_1 =
io_old_entry_brSlots_0_valid & _new_br_insert_onehot_T_3
& (~io_old_entry_tailSlot_valid | io_cfiIndex_bits < io_old_entry_tailSlot_offset); // src/main/scala/xiangshan/frontend/NewFtq.scala:309:{53,83}, :310:{10,36,53}
wire _GEN_3 = io_cfiIndex_bits > io_old_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/NewFtq.scala:322:31
wire _GEN_4 = _GEN_3 | ~io_old_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:314:36, :322:{31,61}, :329:44
wire pft_need_to_change =
is_new_br & io_old_entry_brSlots_0_valid & io_old_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:300:29, :342:38
wire [3:0] new_pft_offset =
{new_br_insert_onehot_1, new_br_insert_onehot_0} == 2'h0
? io_cfiIndex_bits
: io_old_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/NewFtq.scala:250:41, :307:33, :309:83, :346:{10,33,40}
wire [4:0] _old_entry_modified_carry_T_1 = 5'(_GEN_1 + {1'h0, new_pft_offset}); // src/main/scala/xiangshan/frontend/NewFtq.scala:250:41, :287:40, :346:10, :350:59, :351:58
wire _old_target_target_T_9 = io_old_entry_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:60:10, :98:19
wire _old_target_target_T_10 = io_old_entry_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:61:12, :99:19
wire _old_target_target_T_11 = io_old_entry_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/NewFtq.scala:250:41
wire jalr_target_modified =
cfi_is_jalr
& {io_old_entry_tailSlot_sharing
? {(_old_target_target_T_9 ? 26'(io_start_addr[38:13] + 26'h1) : 26'h0)
| (_old_target_target_T_10 ? 26'(io_start_addr[38:13] - 26'h1) : 26'h0)
| (_old_target_target_T_11 ? io_start_addr[38:13] : 26'h0),
io_old_entry_tailSlot_lower[11:0]}
: {(_old_target_target_T_9 ? 18'(io_start_addr[38:21] + 18'h1) : 18'h0)
| (_old_target_target_T_10 ? 18'(io_start_addr[38:21] - 18'h1) : 18'h0)
| (_old_target_target_T_11 ? io_start_addr[38:21] : 18'h0),
io_old_entry_tailSlot_lower},
1'h0} != io_target & ~io_old_entry_tailSlot_sharing; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :92:30, :93:31, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, src/main/scala/xiangshan/frontend/NewFtq.scala:250:41, :263:55, :360:25, :361:{57,72}
wire old_entry_always_taken_always_taken_0 =
io_old_entry_always_taken_0 & io_cfiIndex_valid & io_old_entry_brSlots_0_valid
& io_cfiIndex_bits == io_old_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/NewFtq.scala:371:{65,85}
wire old_entry_always_taken_always_taken_1 =
io_old_entry_always_taken_1 & io_cfiIndex_valid & io_old_entry_tailSlot_valid
& io_old_entry_tailSlot_sharing & io_cfiIndex_bits == io_old_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/NewFtq.scala:371:{65,85}
wire _GEN_5 = is_new_br & new_br_insert_onehot_0; // src/main/scala/xiangshan/frontend/NewFtq.scala:300:29, :307:33, :379:8
wire _GEN_6 = is_new_br & pft_need_to_change; // src/main/scala/xiangshan/frontend/NewFtq.scala:300:29, :342:38, :379:8
wire _GEN_7 = ~is_new_br | ~pft_need_to_change; // src/main/scala/xiangshan/frontend/NewFtq.scala:300:29, :314:36, :342:38, :344:29, :352:45, :379:8
wire [3:0] _io_new_entry_brSlots_0_offset_output =
io_hit
? (_GEN_5 ? io_cfiIndex_bits : io_old_entry_brSlots_0_offset)
: init_entry_always_taken_0 ? io_cfiIndex_bits : 4'h0; // src/main/scala/xiangshan/frontend/NewFtq.scala:250:{28,41}, :253:47, :273:20, :275:25, :379:8, :383:22
wire _io_new_entry_brSlots_0_valid_output =
io_hit ? _GEN_5 | io_old_entry_brSlots_0_valid : init_entry_always_taken_0; // src/main/scala/xiangshan/frontend/NewFtq.scala:253:47, :379:8, :383:22
wire [3:0] _io_new_entry_tailSlot_offset_output =
io_hit
? (is_new_br
? (new_br_insert_onehot_1
? io_cfiIndex_bits
: _GEN_4 ? io_old_entry_tailSlot_offset : io_old_entry_brSlots_0_offset)
: io_old_entry_tailSlot_offset)
: io_pd_jmpInfo_valid ? io_pd_jmpOffset : 4'h0; // src/main/scala/xiangshan/frontend/NewFtq.scala:250:{28,41}, :281:24, :282:32, :300:29, :309:83, :314:36, :317:36, :319:19, :322:61, :329:44, :379:8, :383:22
wire _io_new_entry_tailSlot_sharing_output =
io_hit
& (is_new_br
? new_br_insert_onehot_1 | ~_GEN_3 & io_old_entry_brSlots_0_valid
| io_old_entry_tailSlot_sharing
: ~jalr_target_modified & io_old_entry_tailSlot_sharing); // src/main/scala/xiangshan/frontend/FTB.scala:70:18, src/main/scala/xiangshan/frontend/NewFtq.scala:300:29, :309:83, :314:36, :317:36, :322:{31,61}, :329:44, :358:47, :361:72, :362:31, :379:8, :380:10, :383:22
wire _io_new_entry_tailSlot_valid_output =
io_hit
? (is_new_br
? new_br_insert_onehot_1
| (_GEN_4 ? io_old_entry_tailSlot_valid : io_old_entry_brSlots_0_valid)
: io_old_entry_tailSlot_valid)
: io_pd_jmpInfo_valid
& (io_pd_jmpInfo_valid & ~io_pd_jmpInfo_bits_0 & io_cfiIndex_valid
| init_entry_isJalr); // src/main/scala/xiangshan/frontend/NewFtq.scala:250:28, :255:{42,62}, :256:62, :281:24, :283:{31,49}, :300:29, :309:83, :314:36, :317:36, :318:18, :322:61, :329:44, :379:8, :383:22
wire _io_mispred_mask_1_WIRE_1 =
_io_new_entry_tailSlot_valid_output & _io_new_entry_tailSlot_sharing_output; // src/main/scala/xiangshan/frontend/FTB.scala:203:47, src/main/scala/xiangshan/frontend/NewFtq.scala:383:22
wire [15:0] _GEN_8 =
{{io_mispredict_vec_15},
{io_mispredict_vec_14},
{io_mispredict_vec_13},
{io_mispredict_vec_12},
{io_mispredict_vec_11},
{io_mispredict_vec_10},
{io_mispredict_vec_9},
{io_mispredict_vec_8},
{io_mispredict_vec_7},
{io_mispredict_vec_6},
{io_mispredict_vec_5},
{io_mispredict_vec_4},
{io_mispredict_vec_3},
{io_mispredict_vec_2},
{io_mispredict_vec_1},
{io_mispredict_vec_0}}; // src/main/scala/xiangshan/frontend/NewFtq.scala:391:52
assign io_new_entry_valid = ~io_hit | io_old_entry_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:{22,23}
assign io_new_entry_brSlots_0_offset = _io_new_entry_brSlots_0_offset_output; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22
assign io_new_entry_brSlots_0_lower =
io_hit
? (_GEN_5 ? io_target[12:1] : io_old_entry_brSlots_0_lower)
: init_entry_always_taken_0 ? io_target[12:1] : 12'h0; // src/main/scala/xiangshan/frontend/FTB.scala:62:64, :68:16, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :250:{28,41}, :253:47, :273:20, :379:8, :383:22
assign io_new_entry_brSlots_0_tarStat =
io_hit
? (_GEN_5
? (io_target[38:13] > io_start_addr[38:13]
? 2'h1
: {io_target[38:13] < io_start_addr[38:13], 1'h0})
: io_old_entry_brSlots_0_tarStat)
: init_entry_always_taken_0
? (io_target[38:13] > io_start_addr[38:13]
? 2'h1
: {io_target[38:13] < io_start_addr[38:13], 1'h0})
: 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:60:{10,25}, :61:{12,27}, :64:23, :65:31, :69:18, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :250:{28,41}, :253:47, :273:20, :379:8, :383:22
assign io_new_entry_brSlots_0_sharing =
io_hit & (~is_new_br | ~new_br_insert_onehot_0) & io_old_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:70:18, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :300:29, :307:33, :314:36, :317:36, :379:8, :383:22
assign io_new_entry_brSlots_0_valid = _io_new_entry_brSlots_0_valid_output; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22
assign io_new_entry_tailSlot_offset = _io_new_entry_tailSlot_offset_output; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22
assign io_new_entry_tailSlot_lower =
io_hit
? (is_new_br
? (new_br_insert_onehot_1
? {8'h0, io_target[12:1]}
: _GEN_4
? io_old_entry_tailSlot_lower
: {8'h0, io_old_entry_brSlots_0_lower})
: jalr_target_modified ? io_target[20:1] : io_old_entry_tailSlot_lower)
: io_pd_jmpInfo_valid ? _GEN_0[19:0] : 20'h0; // src/main/scala/xiangshan/frontend/FTB.scala:62:64, :68:16, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :250:{28,41}, :281:24, :284:64, :300:29, :309:83, :314:36, :317:36, :322:61, :329:44, :361:72, :379:8, :380:10, :383:22, utility/src/main/scala/utility/BitUtils.scala:88:41
assign io_new_entry_tailSlot_tarStat =
io_hit
? (is_new_br
? (new_br_insert_onehot_1
? (io_target[38:13] > io_start_addr[38:13]
? 2'h1
: {io_target[38:13] < io_start_addr[38:13], 1'h0})
: _GEN_4 ? io_old_entry_tailSlot_tarStat : io_old_entry_brSlots_0_tarStat)
: jalr_target_modified
? (io_target[38:21] > io_start_addr[38:21]
? 2'h1
: {io_target[38:21] < io_start_addr[38:21], 1'h0})
: io_old_entry_tailSlot_tarStat)
: io_pd_jmpInfo_valid
? (_GEN_0[37:20] > io_start_addr[38:21]
? 2'h1
: {_GEN_0[37:20] < io_start_addr[38:21], 1'h0})
: 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:60:{10,25}, :61:{12,27}, :64:23, :65:31, :69:18, :76:32, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :250:{28,41}, :281:24, :284:64, :300:29, :309:83, :314:36, :317:36, :322:61, :329:44, :361:72, :379:8, :380:10, :383:22
assign io_new_entry_tailSlot_sharing = _io_new_entry_tailSlot_sharing_output; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22
assign io_new_entry_tailSlot_valid = _io_new_entry_tailSlot_valid_output; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22
assign io_new_entry_pftAddr =
io_hit
? (_GEN_6 ? 4'(io_start_addr[4:1] + new_pft_offset) : io_old_entry_pftAddr)
: io_pd_jmpInfo_valid & ~last_jmp_rvi ? jmpPft[3:0] : io_start_addr[4:1]; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :259:75, :266:30, :287:56, :288:{28,43,46}, :346:10, :350:59, :379:8, :383:22
assign io_new_entry_carry =
io_hit
? (_GEN_6 ? _old_entry_modified_carry_T_1[4] : io_old_entry_carry)
: ~(io_pd_jmpInfo_valid & ~last_jmp_rvi) | jmpPft[4]; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :259:75, :287:56, :288:46, :289:{28,43,67}, :351:{58,81}, :379:8, :383:22
assign io_new_entry_isCall =
io_hit
? _GEN_7 & io_old_entry_isCall
: io_pd_jmpInfo_valid & io_pd_jmpInfo_bits_1 & io_cfiIndex_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :257:62, :379:8, :383:22
assign io_new_entry_isRet =
io_hit
? _GEN_7 & io_old_entry_isRet
: io_pd_jmpInfo_valid & io_pd_jmpInfo_bits_2 & io_cfiIndex_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :258:62, :379:8, :383:22
assign io_new_entry_isJalr = io_hit ? _GEN_7 & io_old_entry_isJalr : init_entry_isJalr; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :256:62, :379:8, :383:22
assign io_new_entry_last_may_be_rvi_call =
io_hit
? _GEN_7 & io_old_entry_last_may_be_rvi_call
: (&io_pd_jmpOffset) & ~_GEN_2[io_pd_jmpOffset]; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :259:52, :287:62, :294:{74,77}, :379:8, :383:22
assign io_new_entry_always_taken_0 =
io_hit
? (is_new_br
? new_br_insert_onehot_0 | ~_new_br_insert_onehot_T_3
& io_old_entry_always_taken_0
: jalr_target_modified
? ~jalr_target_modified & io_old_entry_always_taken_0
: old_entry_always_taken_always_taken_0)
: init_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:70:18, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :253:47, :300:29, :307:33, :309:53, :314:36, :317:36, :321:42, :322:61, :323:42, :358:47, :361:72, :362:31, :364:48, :371:65, :379:8, :380:10, :383:22
assign io_new_entry_always_taken_1 =
io_hit
& (is_new_br
? new_br_insert_onehot_1 | ~_GEN_3 & io_old_entry_always_taken_1
: jalr_target_modified
? ~jalr_target_modified & io_old_entry_always_taken_1
: old_entry_always_taken_always_taken_1); // src/main/scala/xiangshan/frontend/FTB.scala:70:18, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :300:29, :309:83, :314:36, :317:36, :321:42, :322:{31,61}, :323:42, :329:44, :358:47, :361:72, :362:31, :364:48, :371:65, :379:8, :380:10, :383:22
assign io_taken_mask_0 =
io_cfiIndex_bits == _io_new_entry_brSlots_0_offset_output & io_cfiIndex_valid
& _io_new_entry_brSlots_0_valid_output; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22, :387:{39,68}
assign io_taken_mask_1 =
io_cfiIndex_bits == _io_new_entry_tailSlot_offset_output & io_cfiIndex_valid
& _io_mispred_mask_1_WIRE_1; // src/main/scala/xiangshan/frontend/FTB.scala:203:47, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22, :387:{39,68}
assign io_jmp_taken =
_io_new_entry_tailSlot_valid_output & ~_io_new_entry_tailSlot_sharing_output
& _io_new_entry_tailSlot_offset_output == io_cfiIndex_bits; // src/main/scala/xiangshan/frontend/FTB.scala:217:23, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22, :389:{41,73}
assign io_mispred_mask_0 =
_io_new_entry_brSlots_0_valid_output & _GEN_8[_io_new_entry_brSlots_0_offset_output]; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22, :391:52
assign io_mispred_mask_1 =
_io_mispred_mask_1_WIRE_1 & _GEN_8[_io_new_entry_tailSlot_offset_output]; // src/main/scala/xiangshan/frontend/FTB.scala:203:47, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22, :391:52
assign io_mispred_mask_2 =
_io_new_entry_tailSlot_valid_output & ~_io_new_entry_tailSlot_sharing_output
& _GEN_8[io_pd_jmpOffset]; // src/main/scala/xiangshan/frontend/FTB.scala:217:23, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22, :391:52, :393:49
assign io_is_old_entry =
io_hit & ~is_new_br & ~jalr_target_modified
& ~(io_old_entry_always_taken_0 & ~old_entry_always_taken_always_taken_0
| io_old_entry_always_taken_1 & ~old_entry_always_taken_always_taken_1); // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :300:29, :361:72, :371:65, :372:{56,59}, :374:65, :397:{29,43,65,68}
endmodule

659
src/FTB/SRAMTemplate_9.sv Normal file
View File

@ -0,0 +1,659 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SRAMTemplate_9( // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
input clock,
input reset,
output io_r_req_ready, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [8:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_0_entry_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [3:0] io_r_resp_data_0_entry_brSlots_0_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [11:0] io_r_resp_data_0_entry_brSlots_0_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [1:0] io_r_resp_data_0_entry_brSlots_0_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_0_entry_brSlots_0_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_0_entry_brSlots_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [3:0] io_r_resp_data_0_entry_tailSlot_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [19:0] io_r_resp_data_0_entry_tailSlot_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [1:0] io_r_resp_data_0_entry_tailSlot_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_0_entry_tailSlot_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_0_entry_tailSlot_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [3:0] io_r_resp_data_0_entry_pftAddr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_0_entry_carry, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_0_entry_isCall, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_0_entry_isRet, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_0_entry_isJalr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_0_entry_last_may_be_rvi_call, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_0_entry_always_taken_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_0_entry_always_taken_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [19:0] io_r_resp_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_1_entry_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [3:0] io_r_resp_data_1_entry_brSlots_0_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [11:0] io_r_resp_data_1_entry_brSlots_0_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [1:0] io_r_resp_data_1_entry_brSlots_0_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_1_entry_brSlots_0_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_1_entry_brSlots_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [3:0] io_r_resp_data_1_entry_tailSlot_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [19:0] io_r_resp_data_1_entry_tailSlot_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [1:0] io_r_resp_data_1_entry_tailSlot_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_1_entry_tailSlot_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_1_entry_tailSlot_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [3:0] io_r_resp_data_1_entry_pftAddr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_1_entry_carry, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_1_entry_isCall, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_1_entry_isRet, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_1_entry_isJalr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_1_entry_last_may_be_rvi_call, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_1_entry_always_taken_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_1_entry_always_taken_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [19:0] io_r_resp_data_1_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_2_entry_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [3:0] io_r_resp_data_2_entry_brSlots_0_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [11:0] io_r_resp_data_2_entry_brSlots_0_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [1:0] io_r_resp_data_2_entry_brSlots_0_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_2_entry_brSlots_0_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_2_entry_brSlots_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [3:0] io_r_resp_data_2_entry_tailSlot_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [19:0] io_r_resp_data_2_entry_tailSlot_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [1:0] io_r_resp_data_2_entry_tailSlot_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_2_entry_tailSlot_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_2_entry_tailSlot_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [3:0] io_r_resp_data_2_entry_pftAddr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_2_entry_carry, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_2_entry_isCall, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_2_entry_isRet, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_2_entry_isJalr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_2_entry_last_may_be_rvi_call, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_2_entry_always_taken_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_2_entry_always_taken_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [19:0] io_r_resp_data_2_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_3_entry_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [3:0] io_r_resp_data_3_entry_brSlots_0_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [11:0] io_r_resp_data_3_entry_brSlots_0_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [1:0] io_r_resp_data_3_entry_brSlots_0_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_3_entry_brSlots_0_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_3_entry_brSlots_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [3:0] io_r_resp_data_3_entry_tailSlot_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [19:0] io_r_resp_data_3_entry_tailSlot_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [1:0] io_r_resp_data_3_entry_tailSlot_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_3_entry_tailSlot_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_3_entry_tailSlot_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [3:0] io_r_resp_data_3_entry_pftAddr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_3_entry_carry, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_3_entry_isCall, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_3_entry_isRet, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_3_entry_isJalr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_3_entry_last_may_be_rvi_call, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_3_entry_always_taken_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_3_entry_always_taken_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [19:0] io_r_resp_data_3_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [8:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_0_entry_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [3:0] io_w_req_bits_data_0_entry_brSlots_0_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [11:0] io_w_req_bits_data_0_entry_brSlots_0_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [1:0] io_w_req_bits_data_0_entry_brSlots_0_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_0_entry_brSlots_0_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_0_entry_brSlots_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [3:0] io_w_req_bits_data_0_entry_tailSlot_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [19:0] io_w_req_bits_data_0_entry_tailSlot_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [1:0] io_w_req_bits_data_0_entry_tailSlot_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_0_entry_tailSlot_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_0_entry_tailSlot_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [3:0] io_w_req_bits_data_0_entry_pftAddr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_0_entry_carry, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_0_entry_isCall, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_0_entry_isRet, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_0_entry_isJalr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_0_entry_last_may_be_rvi_call, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_0_entry_always_taken_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_0_entry_always_taken_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [19:0] io_w_req_bits_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_1_entry_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [3:0] io_w_req_bits_data_1_entry_brSlots_0_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [11:0] io_w_req_bits_data_1_entry_brSlots_0_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [1:0] io_w_req_bits_data_1_entry_brSlots_0_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_1_entry_brSlots_0_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_1_entry_brSlots_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [3:0] io_w_req_bits_data_1_entry_tailSlot_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [19:0] io_w_req_bits_data_1_entry_tailSlot_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [1:0] io_w_req_bits_data_1_entry_tailSlot_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_1_entry_tailSlot_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_1_entry_tailSlot_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [3:0] io_w_req_bits_data_1_entry_pftAddr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_1_entry_carry, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_1_entry_isCall, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_1_entry_isRet, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_1_entry_isJalr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_1_entry_last_may_be_rvi_call, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_1_entry_always_taken_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_1_entry_always_taken_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [19:0] io_w_req_bits_data_1_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_2_entry_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [3:0] io_w_req_bits_data_2_entry_brSlots_0_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [11:0] io_w_req_bits_data_2_entry_brSlots_0_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [1:0] io_w_req_bits_data_2_entry_brSlots_0_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_2_entry_brSlots_0_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_2_entry_brSlots_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [3:0] io_w_req_bits_data_2_entry_tailSlot_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [19:0] io_w_req_bits_data_2_entry_tailSlot_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [1:0] io_w_req_bits_data_2_entry_tailSlot_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_2_entry_tailSlot_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_2_entry_tailSlot_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [3:0] io_w_req_bits_data_2_entry_pftAddr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_2_entry_carry, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_2_entry_isCall, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_2_entry_isRet, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_2_entry_isJalr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_2_entry_last_may_be_rvi_call, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_2_entry_always_taken_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_2_entry_always_taken_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [19:0] io_w_req_bits_data_2_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_3_entry_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [3:0] io_w_req_bits_data_3_entry_brSlots_0_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [11:0] io_w_req_bits_data_3_entry_brSlots_0_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [1:0] io_w_req_bits_data_3_entry_brSlots_0_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_3_entry_brSlots_0_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_3_entry_brSlots_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [3:0] io_w_req_bits_data_3_entry_tailSlot_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [19:0] io_w_req_bits_data_3_entry_tailSlot_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [1:0] io_w_req_bits_data_3_entry_tailSlot_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_3_entry_tailSlot_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_3_entry_tailSlot_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [3:0] io_w_req_bits_data_3_entry_pftAddr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_3_entry_carry, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_3_entry_isCall, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_3_entry_isRet, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_3_entry_isJalr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_3_entry_last_may_be_rvi_call, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_3_entry_always_taken_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_3_entry_always_taken_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [19:0] io_w_req_bits_data_3_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [3:0] io_w_req_bits_waymask // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
);
wire [19:0] _wdata_T_3_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_3_entry_always_taken_1; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_3_entry_always_taken_0; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_3_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_3_entry_isJalr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_3_entry_isRet; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_3_entry_isCall; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_3_entry_carry; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [3:0] _wdata_T_3_entry_pftAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_3_entry_tailSlot_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_3_entry_tailSlot_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [1:0] _wdata_T_3_entry_tailSlot_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [19:0] _wdata_T_3_entry_tailSlot_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [3:0] _wdata_T_3_entry_tailSlot_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_3_entry_brSlots_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_3_entry_brSlots_0_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [1:0] _wdata_T_3_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [11:0] _wdata_T_3_entry_brSlots_0_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [3:0] _wdata_T_3_entry_brSlots_0_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_3_entry_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [19:0] _wdata_T_2_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_2_entry_always_taken_1; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_2_entry_always_taken_0; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_2_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_2_entry_isJalr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_2_entry_isRet; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_2_entry_isCall; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_2_entry_carry; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [3:0] _wdata_T_2_entry_pftAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_2_entry_tailSlot_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_2_entry_tailSlot_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [1:0] _wdata_T_2_entry_tailSlot_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [19:0] _wdata_T_2_entry_tailSlot_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [3:0] _wdata_T_2_entry_tailSlot_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_2_entry_brSlots_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_2_entry_brSlots_0_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [1:0] _wdata_T_2_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [11:0] _wdata_T_2_entry_brSlots_0_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [3:0] _wdata_T_2_entry_brSlots_0_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_2_entry_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [19:0] _wdata_T_1_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_1_entry_always_taken_1; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_1_entry_always_taken_0; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_1_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_1_entry_isJalr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_1_entry_isRet; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_1_entry_isCall; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_1_entry_carry; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [3:0] _wdata_T_1_entry_pftAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_1_entry_tailSlot_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_1_entry_tailSlot_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [1:0] _wdata_T_1_entry_tailSlot_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [19:0] _wdata_T_1_entry_tailSlot_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [3:0] _wdata_T_1_entry_tailSlot_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_1_entry_brSlots_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_1_entry_brSlots_0_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [1:0] _wdata_T_1_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [11:0] _wdata_T_1_entry_brSlots_0_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [3:0] _wdata_T_1_entry_brSlots_0_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_1_entry_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [19:0] _wdata_T_0_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_0_entry_always_taken_1; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_0_entry_always_taken_0; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_0_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_0_entry_isJalr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_0_entry_isRet; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_0_entry_isCall; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_0_entry_carry; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [3:0] _wdata_T_0_entry_pftAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_0_entry_tailSlot_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_0_entry_tailSlot_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [1:0] _wdata_T_0_entry_tailSlot_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [19:0] _wdata_T_0_entry_tailSlot_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [3:0] _wdata_T_0_entry_tailSlot_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_0_entry_brSlots_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_0_entry_brSlots_0_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [1:0] _wdata_T_0_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [11:0] _wdata_T_0_entry_brSlots_0_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [3:0] _wdata_T_0_entry_brSlots_0_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_0_entry_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [8:0] array_MPORT_addr; // utility/src/main/scala/utility/SRAMTemplate.scala:125:19
wire array_raw_rdata_en; // utility/src/main/scala/utility/SRAMTemplate.scala:123:38
wire array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52
wire [319:0] _array_RW0_rdata; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
reg _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30
reg [8:0] _resetSet; // src/main/scala/chisel3/util/Counter.scala:61:40
assign array_MPORT_en = io_w_req_valid | _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :122:52
assign array_raw_rdata_en = io_r_req_valid & ~array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52, :123:{38,41}
assign array_MPORT_addr = _resetState ? _resetSet : io_w_req_bits_setIdx; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :125:19
assign _wdata_T_0_entry_valid = ~_resetState & io_w_req_bits_data_0_entry_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_0_entry_brSlots_0_offset =
_resetState ? 4'h0 : io_w_req_bits_data_0_entry_brSlots_0_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_0_entry_brSlots_0_lower =
_resetState ? 12'h0 : io_w_req_bits_data_0_entry_brSlots_0_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_0_entry_brSlots_0_tarStat =
_resetState ? 2'h0 : io_w_req_bits_data_0_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_0_entry_brSlots_0_sharing =
~_resetState & io_w_req_bits_data_0_entry_brSlots_0_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_0_entry_brSlots_0_valid =
~_resetState & io_w_req_bits_data_0_entry_brSlots_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_0_entry_tailSlot_offset =
_resetState ? 4'h0 : io_w_req_bits_data_0_entry_tailSlot_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_0_entry_tailSlot_lower =
_resetState ? 20'h0 : io_w_req_bits_data_0_entry_tailSlot_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_0_entry_tailSlot_tarStat =
_resetState ? 2'h0 : io_w_req_bits_data_0_entry_tailSlot_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_0_entry_tailSlot_sharing =
~_resetState & io_w_req_bits_data_0_entry_tailSlot_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_0_entry_tailSlot_valid =
~_resetState & io_w_req_bits_data_0_entry_tailSlot_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_0_entry_pftAddr =
_resetState ? 4'h0 : io_w_req_bits_data_0_entry_pftAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_0_entry_carry = ~_resetState & io_w_req_bits_data_0_entry_carry; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_0_entry_isCall = ~_resetState & io_w_req_bits_data_0_entry_isCall; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_0_entry_isRet = ~_resetState & io_w_req_bits_data_0_entry_isRet; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_0_entry_isJalr = ~_resetState & io_w_req_bits_data_0_entry_isJalr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_0_entry_last_may_be_rvi_call =
~_resetState & io_w_req_bits_data_0_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_0_entry_always_taken_0 =
~_resetState & io_w_req_bits_data_0_entry_always_taken_0; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_0_entry_always_taken_1 =
~_resetState & io_w_req_bits_data_0_entry_always_taken_1; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_0_tag = _resetState ? 20'h0 : io_w_req_bits_data_0_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_1_entry_valid = ~_resetState & io_w_req_bits_data_1_entry_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_1_entry_brSlots_0_offset =
_resetState ? 4'h0 : io_w_req_bits_data_1_entry_brSlots_0_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_1_entry_brSlots_0_lower =
_resetState ? 12'h0 : io_w_req_bits_data_1_entry_brSlots_0_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_1_entry_brSlots_0_tarStat =
_resetState ? 2'h0 : io_w_req_bits_data_1_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_1_entry_brSlots_0_sharing =
~_resetState & io_w_req_bits_data_1_entry_brSlots_0_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_1_entry_brSlots_0_valid =
~_resetState & io_w_req_bits_data_1_entry_brSlots_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_1_entry_tailSlot_offset =
_resetState ? 4'h0 : io_w_req_bits_data_1_entry_tailSlot_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_1_entry_tailSlot_lower =
_resetState ? 20'h0 : io_w_req_bits_data_1_entry_tailSlot_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_1_entry_tailSlot_tarStat =
_resetState ? 2'h0 : io_w_req_bits_data_1_entry_tailSlot_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_1_entry_tailSlot_sharing =
~_resetState & io_w_req_bits_data_1_entry_tailSlot_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_1_entry_tailSlot_valid =
~_resetState & io_w_req_bits_data_1_entry_tailSlot_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_1_entry_pftAddr =
_resetState ? 4'h0 : io_w_req_bits_data_1_entry_pftAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_1_entry_carry = ~_resetState & io_w_req_bits_data_1_entry_carry; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_1_entry_isCall = ~_resetState & io_w_req_bits_data_1_entry_isCall; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_1_entry_isRet = ~_resetState & io_w_req_bits_data_1_entry_isRet; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_1_entry_isJalr = ~_resetState & io_w_req_bits_data_1_entry_isJalr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_1_entry_last_may_be_rvi_call =
~_resetState & io_w_req_bits_data_1_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_1_entry_always_taken_0 =
~_resetState & io_w_req_bits_data_1_entry_always_taken_0; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_1_entry_always_taken_1 =
~_resetState & io_w_req_bits_data_1_entry_always_taken_1; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_1_tag = _resetState ? 20'h0 : io_w_req_bits_data_1_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_2_entry_valid = ~_resetState & io_w_req_bits_data_2_entry_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_2_entry_brSlots_0_offset =
_resetState ? 4'h0 : io_w_req_bits_data_2_entry_brSlots_0_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_2_entry_brSlots_0_lower =
_resetState ? 12'h0 : io_w_req_bits_data_2_entry_brSlots_0_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_2_entry_brSlots_0_tarStat =
_resetState ? 2'h0 : io_w_req_bits_data_2_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_2_entry_brSlots_0_sharing =
~_resetState & io_w_req_bits_data_2_entry_brSlots_0_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_2_entry_brSlots_0_valid =
~_resetState & io_w_req_bits_data_2_entry_brSlots_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_2_entry_tailSlot_offset =
_resetState ? 4'h0 : io_w_req_bits_data_2_entry_tailSlot_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_2_entry_tailSlot_lower =
_resetState ? 20'h0 : io_w_req_bits_data_2_entry_tailSlot_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_2_entry_tailSlot_tarStat =
_resetState ? 2'h0 : io_w_req_bits_data_2_entry_tailSlot_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_2_entry_tailSlot_sharing =
~_resetState & io_w_req_bits_data_2_entry_tailSlot_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_2_entry_tailSlot_valid =
~_resetState & io_w_req_bits_data_2_entry_tailSlot_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_2_entry_pftAddr =
_resetState ? 4'h0 : io_w_req_bits_data_2_entry_pftAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_2_entry_carry = ~_resetState & io_w_req_bits_data_2_entry_carry; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_2_entry_isCall = ~_resetState & io_w_req_bits_data_2_entry_isCall; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_2_entry_isRet = ~_resetState & io_w_req_bits_data_2_entry_isRet; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_2_entry_isJalr = ~_resetState & io_w_req_bits_data_2_entry_isJalr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_2_entry_last_may_be_rvi_call =
~_resetState & io_w_req_bits_data_2_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_2_entry_always_taken_0 =
~_resetState & io_w_req_bits_data_2_entry_always_taken_0; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_2_entry_always_taken_1 =
~_resetState & io_w_req_bits_data_2_entry_always_taken_1; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_2_tag = _resetState ? 20'h0 : io_w_req_bits_data_2_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_3_entry_valid = ~_resetState & io_w_req_bits_data_3_entry_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_3_entry_brSlots_0_offset =
_resetState ? 4'h0 : io_w_req_bits_data_3_entry_brSlots_0_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_3_entry_brSlots_0_lower =
_resetState ? 12'h0 : io_w_req_bits_data_3_entry_brSlots_0_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_3_entry_brSlots_0_tarStat =
_resetState ? 2'h0 : io_w_req_bits_data_3_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_3_entry_brSlots_0_sharing =
~_resetState & io_w_req_bits_data_3_entry_brSlots_0_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_3_entry_brSlots_0_valid =
~_resetState & io_w_req_bits_data_3_entry_brSlots_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_3_entry_tailSlot_offset =
_resetState ? 4'h0 : io_w_req_bits_data_3_entry_tailSlot_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_3_entry_tailSlot_lower =
_resetState ? 20'h0 : io_w_req_bits_data_3_entry_tailSlot_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_3_entry_tailSlot_tarStat =
_resetState ? 2'h0 : io_w_req_bits_data_3_entry_tailSlot_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_3_entry_tailSlot_sharing =
~_resetState & io_w_req_bits_data_3_entry_tailSlot_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_3_entry_tailSlot_valid =
~_resetState & io_w_req_bits_data_3_entry_tailSlot_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_3_entry_pftAddr =
_resetState ? 4'h0 : io_w_req_bits_data_3_entry_pftAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_3_entry_carry = ~_resetState & io_w_req_bits_data_3_entry_carry; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_3_entry_isCall = ~_resetState & io_w_req_bits_data_3_entry_isCall; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_3_entry_isRet = ~_resetState & io_w_req_bits_data_3_entry_isRet; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_3_entry_isJalr = ~_resetState & io_w_req_bits_data_3_entry_isJalr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_3_entry_last_may_be_rvi_call =
~_resetState & io_w_req_bits_data_3_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_3_entry_always_taken_0 =
~_resetState & io_w_req_bits_data_3_entry_always_taken_0; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_3_entry_always_taken_1 =
~_resetState & io_w_req_bits_data_3_entry_always_taken_1; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign _wdata_T_3_tag = _resetState ? 20'h0 : io_w_req_bits_data_3_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
always @(posedge clock or posedge reset) begin
if (reset) begin
_resetState <= 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30
_resetSet <= 9'h0; // src/main/scala/chisel3/util/Counter.scala:61:40
end
else begin
_resetState <= ~(_resetState & (&_resetSet)) & _resetState; // src/main/scala/chisel3/util/Counter.scala:61:40, :73:24, :117:24, :118:{16,23}, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :111:{24,38}
if (_resetState) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30
_resetSet <= 9'(_resetSet + 9'h1); // src/main/scala/chisel3/util/Counter.scala:61:40, :77:24
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
_resetState = _RANDOM[/*Zero width*/ 1'b0][0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30
_resetSet = _RANDOM[/*Zero width*/ 1'b0][9:1]; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30
`endif // RANDOMIZE_REG_INIT
if (reset) begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
_resetState = 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30
_resetSet = 9'h0; // src/main/scala/chisel3/util/Counter.scala:61:40
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
array_3 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
.RW0_addr (array_MPORT_en ? array_MPORT_addr : io_r_req_bits_setIdx), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :125:19
.RW0_en (array_raw_rdata_en | array_MPORT_en), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :123:38
.RW0_clk (clock),
.RW0_wmode (array_MPORT_en), // utility/src/main/scala/utility/SRAMTemplate.scala:122:52
.RW0_wdata
({_wdata_T_3_entry_valid,
_wdata_T_3_entry_brSlots_0_offset,
_wdata_T_3_entry_brSlots_0_lower,
_wdata_T_3_entry_brSlots_0_tarStat,
_wdata_T_3_entry_brSlots_0_sharing,
_wdata_T_3_entry_brSlots_0_valid,
_wdata_T_3_entry_tailSlot_offset,
_wdata_T_3_entry_tailSlot_lower,
_wdata_T_3_entry_tailSlot_tarStat,
_wdata_T_3_entry_tailSlot_sharing,
_wdata_T_3_entry_tailSlot_valid,
_wdata_T_3_entry_pftAddr,
_wdata_T_3_entry_carry,
_wdata_T_3_entry_isCall,
_wdata_T_3_entry_isRet,
_wdata_T_3_entry_isJalr,
_wdata_T_3_entry_last_may_be_rvi_call,
_wdata_T_3_entry_always_taken_1,
_wdata_T_3_entry_always_taken_0,
_wdata_T_3_tag,
_wdata_T_2_entry_valid,
_wdata_T_2_entry_brSlots_0_offset,
_wdata_T_2_entry_brSlots_0_lower,
_wdata_T_2_entry_brSlots_0_tarStat,
_wdata_T_2_entry_brSlots_0_sharing,
_wdata_T_2_entry_brSlots_0_valid,
_wdata_T_2_entry_tailSlot_offset,
_wdata_T_2_entry_tailSlot_lower,
_wdata_T_2_entry_tailSlot_tarStat,
_wdata_T_2_entry_tailSlot_sharing,
_wdata_T_2_entry_tailSlot_valid,
_wdata_T_2_entry_pftAddr,
_wdata_T_2_entry_carry,
_wdata_T_2_entry_isCall,
_wdata_T_2_entry_isRet,
_wdata_T_2_entry_isJalr,
_wdata_T_2_entry_last_may_be_rvi_call,
_wdata_T_2_entry_always_taken_1,
_wdata_T_2_entry_always_taken_0,
_wdata_T_2_tag,
_wdata_T_1_entry_valid,
_wdata_T_1_entry_brSlots_0_offset,
_wdata_T_1_entry_brSlots_0_lower,
_wdata_T_1_entry_brSlots_0_tarStat,
_wdata_T_1_entry_brSlots_0_sharing,
_wdata_T_1_entry_brSlots_0_valid,
_wdata_T_1_entry_tailSlot_offset,
_wdata_T_1_entry_tailSlot_lower,
_wdata_T_1_entry_tailSlot_tarStat,
_wdata_T_1_entry_tailSlot_sharing,
_wdata_T_1_entry_tailSlot_valid,
_wdata_T_1_entry_pftAddr,
_wdata_T_1_entry_carry,
_wdata_T_1_entry_isCall,
_wdata_T_1_entry_isRet,
_wdata_T_1_entry_isJalr,
_wdata_T_1_entry_last_may_be_rvi_call,
_wdata_T_1_entry_always_taken_1,
_wdata_T_1_entry_always_taken_0,
_wdata_T_1_tag,
_wdata_T_0_entry_valid,
_wdata_T_0_entry_brSlots_0_offset,
_wdata_T_0_entry_brSlots_0_lower,
_wdata_T_0_entry_brSlots_0_tarStat,
_wdata_T_0_entry_brSlots_0_sharing,
_wdata_T_0_entry_brSlots_0_valid,
_wdata_T_0_entry_tailSlot_offset,
_wdata_T_0_entry_tailSlot_lower,
_wdata_T_0_entry_tailSlot_tarStat,
_wdata_T_0_entry_tailSlot_sharing,
_wdata_T_0_entry_tailSlot_valid,
_wdata_T_0_entry_pftAddr,
_wdata_T_0_entry_carry,
_wdata_T_0_entry_isCall,
_wdata_T_0_entry_isRet,
_wdata_T_0_entry_isJalr,
_wdata_T_0_entry_last_may_be_rvi_call,
_wdata_T_0_entry_always_taken_1,
_wdata_T_0_entry_always_taken_0,
_wdata_T_0_tag}), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :126:26
.RW0_rdata (_array_RW0_rdata),
.RW0_wmask (_resetState ? 4'hF : io_w_req_bits_waymask) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :127:{20,37}
);
assign io_r_req_ready = ~_resetState & ~array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :122:52, :123:41, :157:{21,33}
assign io_r_resp_data_0_entry_valid = _array_RW0_rdata[79]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_0_entry_brSlots_0_offset = _array_RW0_rdata[78:75]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_0_entry_brSlots_0_lower = _array_RW0_rdata[74:63]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_0_entry_brSlots_0_tarStat = _array_RW0_rdata[62:61]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_0_entry_brSlots_0_sharing = _array_RW0_rdata[60]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_0_entry_brSlots_0_valid = _array_RW0_rdata[59]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_0_entry_tailSlot_offset = _array_RW0_rdata[58:55]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_0_entry_tailSlot_lower = _array_RW0_rdata[54:35]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_0_entry_tailSlot_tarStat = _array_RW0_rdata[34:33]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_0_entry_tailSlot_sharing = _array_RW0_rdata[32]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_0_entry_tailSlot_valid = _array_RW0_rdata[31]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_0_entry_pftAddr = _array_RW0_rdata[30:27]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_0_entry_carry = _array_RW0_rdata[26]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_0_entry_isCall = _array_RW0_rdata[25]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_0_entry_isRet = _array_RW0_rdata[24]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_0_entry_isJalr = _array_RW0_rdata[23]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_0_entry_last_may_be_rvi_call = _array_RW0_rdata[22]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_0_entry_always_taken_0 = _array_RW0_rdata[20]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_0_entry_always_taken_1 = _array_RW0_rdata[21]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_0_tag = _array_RW0_rdata[19:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_1_entry_valid = _array_RW0_rdata[159]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_1_entry_brSlots_0_offset = _array_RW0_rdata[158:155]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_1_entry_brSlots_0_lower = _array_RW0_rdata[154:143]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_1_entry_brSlots_0_tarStat = _array_RW0_rdata[142:141]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_1_entry_brSlots_0_sharing = _array_RW0_rdata[140]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_1_entry_brSlots_0_valid = _array_RW0_rdata[139]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_1_entry_tailSlot_offset = _array_RW0_rdata[138:135]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_1_entry_tailSlot_lower = _array_RW0_rdata[134:115]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_1_entry_tailSlot_tarStat = _array_RW0_rdata[114:113]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_1_entry_tailSlot_sharing = _array_RW0_rdata[112]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_1_entry_tailSlot_valid = _array_RW0_rdata[111]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_1_entry_pftAddr = _array_RW0_rdata[110:107]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_1_entry_carry = _array_RW0_rdata[106]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_1_entry_isCall = _array_RW0_rdata[105]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_1_entry_isRet = _array_RW0_rdata[104]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_1_entry_isJalr = _array_RW0_rdata[103]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_1_entry_last_may_be_rvi_call = _array_RW0_rdata[102]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_1_entry_always_taken_0 = _array_RW0_rdata[100]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_1_entry_always_taken_1 = _array_RW0_rdata[101]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_1_tag = _array_RW0_rdata[99:80]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_2_entry_valid = _array_RW0_rdata[239]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_2_entry_brSlots_0_offset = _array_RW0_rdata[238:235]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_2_entry_brSlots_0_lower = _array_RW0_rdata[234:223]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_2_entry_brSlots_0_tarStat = _array_RW0_rdata[222:221]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_2_entry_brSlots_0_sharing = _array_RW0_rdata[220]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_2_entry_brSlots_0_valid = _array_RW0_rdata[219]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_2_entry_tailSlot_offset = _array_RW0_rdata[218:215]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_2_entry_tailSlot_lower = _array_RW0_rdata[214:195]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_2_entry_tailSlot_tarStat = _array_RW0_rdata[194:193]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_2_entry_tailSlot_sharing = _array_RW0_rdata[192]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_2_entry_tailSlot_valid = _array_RW0_rdata[191]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_2_entry_pftAddr = _array_RW0_rdata[190:187]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_2_entry_carry = _array_RW0_rdata[186]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_2_entry_isCall = _array_RW0_rdata[185]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_2_entry_isRet = _array_RW0_rdata[184]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_2_entry_isJalr = _array_RW0_rdata[183]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_2_entry_last_may_be_rvi_call = _array_RW0_rdata[182]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_2_entry_always_taken_0 = _array_RW0_rdata[180]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_2_entry_always_taken_1 = _array_RW0_rdata[181]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_2_tag = _array_RW0_rdata[179:160]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_3_entry_valid = _array_RW0_rdata[319]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_3_entry_brSlots_0_offset = _array_RW0_rdata[318:315]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_3_entry_brSlots_0_lower = _array_RW0_rdata[314:303]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_3_entry_brSlots_0_tarStat = _array_RW0_rdata[302:301]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_3_entry_brSlots_0_sharing = _array_RW0_rdata[300]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_3_entry_brSlots_0_valid = _array_RW0_rdata[299]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_3_entry_tailSlot_offset = _array_RW0_rdata[298:295]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_3_entry_tailSlot_lower = _array_RW0_rdata[294:275]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_3_entry_tailSlot_tarStat = _array_RW0_rdata[274:273]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_3_entry_tailSlot_sharing = _array_RW0_rdata[272]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_3_entry_tailSlot_valid = _array_RW0_rdata[271]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_3_entry_pftAddr = _array_RW0_rdata[270:267]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_3_entry_carry = _array_RW0_rdata[266]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_3_entry_isCall = _array_RW0_rdata[265]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_3_entry_isRet = _array_RW0_rdata[264]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_3_entry_isJalr = _array_RW0_rdata[263]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_3_entry_last_may_be_rvi_call = _array_RW0_rdata[262]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_3_entry_always_taken_0 = _array_RW0_rdata[260]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_3_entry_always_taken_1 = _array_RW0_rdata[261]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
assign io_r_resp_data_3_tag = _array_RW0_rdata[259:240]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45
endmodule

78
src/FTB/array_3.sv Normal file
View File

@ -0,0 +1,78 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module array_3( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
input [8:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [319:0] RW0_wdata,
output [319:0] RW0_rdata,
input [3:0] RW0_wmask
);
array_3_ext array_3_ext ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
);
endmodule

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// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module ITTageTable( // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
input clock,
input reset,
input io_req_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [3:0] io_req_bits_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
output io_resp_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
output [1:0] io_resp_bits_ctr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
output [1:0] io_resp_bits_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
output [38:0] io_resp_bits_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [3:0] io_update_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_correct, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_alloc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [1:0] io_update_oldCtr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_uValid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_reset_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [38:0] io_update_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [38:0] io_update_old_target // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
);
wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73
wire _wrbypass_io_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24
wire [1:0] _wrbypass_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24
wire [8:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [38:0] _table_banks_1_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [8:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [38:0] _table_banks_0_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire _us_io_rdata_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18
reg [255:0] validArray; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27
wire [3:0] _GEN = io_req_bits_pc[4:1] ^ io_req_bits_folded_hist_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43
wire [7:0] s0_idx = {io_req_bits_pc[8:5], _GEN}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:{31,40}
reg [7:0] s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:36
reg [8:0] s1_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:68
reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33
reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33
wire [6:0] _table_banks_1_io_r_req_bits_setIdx_T = {io_req_bits_pc[8:5], _GEN[3:1]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}
wire [255:0] _s1_req_rhit_T = validArray >> s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :213:36, :232:31
reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48
reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48
wire [3:0] _GEN_0 = io_update_pc[4:1] ^ io_update_folded_hist_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43
wire [7:0] update_idx = {io_update_pc[8:5], _GEN_0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:{31,40}
wire [8:0] update_wdata_tag =
{io_update_pc[17:14],
{io_update_pc[13], io_update_pc[12:9] ^ io_update_folded_hist_hist_12_folded_hist}
^ {io_update_folded_hist_hist_12_folded_hist, 1'h0}}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75,82}, :207:43
wire [6:0] update_idx_in_bank = {io_update_pc[8:5], _GEN_0[3:1]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}
assign _resp_invalid_by_write_WIRE =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33, :240:48
wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(_GEN_0[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :255:33
wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & _GEN_0[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :255:33
wire [1:0] old_ctr =
_wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24, :277:20
wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20
wire [1:0] update_wdata_ctr =
io_update_alloc
? 2'h2
: (&old_ctr) & io_update_correct
? 2'h3
: update_wdata_ctr_oldSatNotTaken & ~io_update_correct
? 2'h0
: io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20, :278:28
wire [38:0] update_wdata_target =
io_update_alloc | update_wdata_ctr_oldSatNotTaken
? io_update_target
: io_update_old_target; // src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:281:{29,46}
wire [255:0] _validArray_T =
{io_update_valid & (&update_idx) | validArray[255],
io_update_valid & update_idx == 8'hFE | validArray[254],
io_update_valid & update_idx == 8'hFD | validArray[253],
io_update_valid & update_idx == 8'hFC | validArray[252],
io_update_valid & update_idx == 8'hFB | validArray[251],
io_update_valid & update_idx == 8'hFA | validArray[250],
io_update_valid & update_idx == 8'hF9 | validArray[249],
io_update_valid & update_idx == 8'hF8 | validArray[248],
io_update_valid & update_idx == 8'hF7 | validArray[247],
io_update_valid & update_idx == 8'hF6 | validArray[246],
io_update_valid & update_idx == 8'hF5 | validArray[245],
io_update_valid & update_idx == 8'hF4 | validArray[244],
io_update_valid & update_idx == 8'hF3 | validArray[243],
io_update_valid & update_idx == 8'hF2 | validArray[242],
io_update_valid & update_idx == 8'hF1 | validArray[241],
io_update_valid & update_idx == 8'hF0 | validArray[240],
io_update_valid & update_idx == 8'hEF | validArray[239],
io_update_valid & update_idx == 8'hEE | validArray[238],
io_update_valid & update_idx == 8'hED | validArray[237],
io_update_valid & update_idx == 8'hEC | validArray[236],
io_update_valid & update_idx == 8'hEB | validArray[235],
io_update_valid & update_idx == 8'hEA | validArray[234],
io_update_valid & update_idx == 8'hE9 | validArray[233],
io_update_valid & update_idx == 8'hE8 | validArray[232],
io_update_valid & update_idx == 8'hE7 | validArray[231],
io_update_valid & update_idx == 8'hE6 | validArray[230],
io_update_valid & update_idx == 8'hE5 | validArray[229],
io_update_valid & update_idx == 8'hE4 | validArray[228],
io_update_valid & update_idx == 8'hE3 | validArray[227],
io_update_valid & update_idx == 8'hE2 | validArray[226],
io_update_valid & update_idx == 8'hE1 | validArray[225],
io_update_valid & update_idx == 8'hE0 | validArray[224],
io_update_valid & update_idx == 8'hDF | validArray[223],
io_update_valid & update_idx == 8'hDE | validArray[222],
io_update_valid & update_idx == 8'hDD | validArray[221],
io_update_valid & update_idx == 8'hDC | validArray[220],
io_update_valid & update_idx == 8'hDB | validArray[219],
io_update_valid & update_idx == 8'hDA | validArray[218],
io_update_valid & update_idx == 8'hD9 | validArray[217],
io_update_valid & update_idx == 8'hD8 | validArray[216],
io_update_valid & update_idx == 8'hD7 | validArray[215],
io_update_valid & update_idx == 8'hD6 | validArray[214],
io_update_valid & update_idx == 8'hD5 | validArray[213],
io_update_valid & update_idx == 8'hD4 | validArray[212],
io_update_valid & update_idx == 8'hD3 | validArray[211],
io_update_valid & update_idx == 8'hD2 | validArray[210],
io_update_valid & update_idx == 8'hD1 | validArray[209],
io_update_valid & update_idx == 8'hD0 | validArray[208],
io_update_valid & update_idx == 8'hCF | validArray[207],
io_update_valid & update_idx == 8'hCE | validArray[206],
io_update_valid & update_idx == 8'hCD | validArray[205],
io_update_valid & update_idx == 8'hCC | validArray[204],
io_update_valid & update_idx == 8'hCB | validArray[203],
io_update_valid & update_idx == 8'hCA | validArray[202],
io_update_valid & update_idx == 8'hC9 | validArray[201],
io_update_valid & update_idx == 8'hC8 | validArray[200],
io_update_valid & update_idx == 8'hC7 | validArray[199],
io_update_valid & update_idx == 8'hC6 | validArray[198],
io_update_valid & update_idx == 8'hC5 | validArray[197],
io_update_valid & update_idx == 8'hC4 | validArray[196],
io_update_valid & update_idx == 8'hC3 | validArray[195],
io_update_valid & update_idx == 8'hC2 | validArray[194],
io_update_valid & update_idx == 8'hC1 | validArray[193],
io_update_valid & update_idx == 8'hC0 | validArray[192],
io_update_valid & update_idx == 8'hBF | validArray[191],
io_update_valid & update_idx == 8'hBE | validArray[190],
io_update_valid & update_idx == 8'hBD | validArray[189],
io_update_valid & update_idx == 8'hBC | validArray[188],
io_update_valid & update_idx == 8'hBB | validArray[187],
io_update_valid & update_idx == 8'hBA | validArray[186],
io_update_valid & update_idx == 8'hB9 | validArray[185],
io_update_valid & update_idx == 8'hB8 | validArray[184],
io_update_valid & update_idx == 8'hB7 | validArray[183],
io_update_valid & update_idx == 8'hB6 | validArray[182],
io_update_valid & update_idx == 8'hB5 | validArray[181],
io_update_valid & update_idx == 8'hB4 | validArray[180],
io_update_valid & update_idx == 8'hB3 | validArray[179],
io_update_valid & update_idx == 8'hB2 | validArray[178],
io_update_valid & update_idx == 8'hB1 | validArray[177],
io_update_valid & update_idx == 8'hB0 | validArray[176],
io_update_valid & update_idx == 8'hAF | validArray[175],
io_update_valid & update_idx == 8'hAE | validArray[174],
io_update_valid & update_idx == 8'hAD | validArray[173],
io_update_valid & update_idx == 8'hAC | validArray[172],
io_update_valid & update_idx == 8'hAB | validArray[171],
io_update_valid & update_idx == 8'hAA | validArray[170],
io_update_valid & update_idx == 8'hA9 | validArray[169],
io_update_valid & update_idx == 8'hA8 | validArray[168],
io_update_valid & update_idx == 8'hA7 | validArray[167],
io_update_valid & update_idx == 8'hA6 | validArray[166],
io_update_valid & update_idx == 8'hA5 | validArray[165],
io_update_valid & update_idx == 8'hA4 | validArray[164],
io_update_valid & update_idx == 8'hA3 | validArray[163],
io_update_valid & update_idx == 8'hA2 | validArray[162],
io_update_valid & update_idx == 8'hA1 | validArray[161],
io_update_valid & update_idx == 8'hA0 | validArray[160],
io_update_valid & update_idx == 8'h9F | validArray[159],
io_update_valid & update_idx == 8'h9E | validArray[158],
io_update_valid & update_idx == 8'h9D | validArray[157],
io_update_valid & update_idx == 8'h9C | validArray[156],
io_update_valid & update_idx == 8'h9B | validArray[155],
io_update_valid & update_idx == 8'h9A | validArray[154],
io_update_valid & update_idx == 8'h99 | validArray[153],
io_update_valid & update_idx == 8'h98 | validArray[152],
io_update_valid & update_idx == 8'h97 | validArray[151],
io_update_valid & update_idx == 8'h96 | validArray[150],
io_update_valid & update_idx == 8'h95 | validArray[149],
io_update_valid & update_idx == 8'h94 | validArray[148],
io_update_valid & update_idx == 8'h93 | validArray[147],
io_update_valid & update_idx == 8'h92 | validArray[146],
io_update_valid & update_idx == 8'h91 | validArray[145],
io_update_valid & update_idx == 8'h90 | validArray[144],
io_update_valid & update_idx == 8'h8F | validArray[143],
io_update_valid & update_idx == 8'h8E | validArray[142],
io_update_valid & update_idx == 8'h8D | validArray[141],
io_update_valid & update_idx == 8'h8C | validArray[140],
io_update_valid & update_idx == 8'h8B | validArray[139],
io_update_valid & update_idx == 8'h8A | validArray[138],
io_update_valid & update_idx == 8'h89 | validArray[137],
io_update_valid & update_idx == 8'h88 | validArray[136],
io_update_valid & update_idx == 8'h87 | validArray[135],
io_update_valid & update_idx == 8'h86 | validArray[134],
io_update_valid & update_idx == 8'h85 | validArray[133],
io_update_valid & update_idx == 8'h84 | validArray[132],
io_update_valid & update_idx == 8'h83 | validArray[131],
io_update_valid & update_idx == 8'h82 | validArray[130],
io_update_valid & update_idx == 8'h81 | validArray[129],
io_update_valid & update_idx == 8'h80 | validArray[128],
io_update_valid & update_idx == 8'h7F | validArray[127],
io_update_valid & update_idx == 8'h7E | validArray[126],
io_update_valid & update_idx == 8'h7D | validArray[125],
io_update_valid & update_idx == 8'h7C | validArray[124],
io_update_valid & update_idx == 8'h7B | validArray[123],
io_update_valid & update_idx == 8'h7A | validArray[122],
io_update_valid & update_idx == 8'h79 | validArray[121],
io_update_valid & update_idx == 8'h78 | validArray[120],
io_update_valid & update_idx == 8'h77 | validArray[119],
io_update_valid & update_idx == 8'h76 | validArray[118],
io_update_valid & update_idx == 8'h75 | validArray[117],
io_update_valid & update_idx == 8'h74 | validArray[116],
io_update_valid & update_idx == 8'h73 | validArray[115],
io_update_valid & update_idx == 8'h72 | validArray[114],
io_update_valid & update_idx == 8'h71 | validArray[113],
io_update_valid & update_idx == 8'h70 | validArray[112],
io_update_valid & update_idx == 8'h6F | validArray[111],
io_update_valid & update_idx == 8'h6E | validArray[110],
io_update_valid & update_idx == 8'h6D | validArray[109],
io_update_valid & update_idx == 8'h6C | validArray[108],
io_update_valid & update_idx == 8'h6B | validArray[107],
io_update_valid & update_idx == 8'h6A | validArray[106],
io_update_valid & update_idx == 8'h69 | validArray[105],
io_update_valid & update_idx == 8'h68 | validArray[104],
io_update_valid & update_idx == 8'h67 | validArray[103],
io_update_valid & update_idx == 8'h66 | validArray[102],
io_update_valid & update_idx == 8'h65 | validArray[101],
io_update_valid & update_idx == 8'h64 | validArray[100],
io_update_valid & update_idx == 8'h63 | validArray[99],
io_update_valid & update_idx == 8'h62 | validArray[98],
io_update_valid & update_idx == 8'h61 | validArray[97],
io_update_valid & update_idx == 8'h60 | validArray[96],
io_update_valid & update_idx == 8'h5F | validArray[95],
io_update_valid & update_idx == 8'h5E | validArray[94],
io_update_valid & update_idx == 8'h5D | validArray[93],
io_update_valid & update_idx == 8'h5C | validArray[92],
io_update_valid & update_idx == 8'h5B | validArray[91],
io_update_valid & update_idx == 8'h5A | validArray[90],
io_update_valid & update_idx == 8'h59 | validArray[89],
io_update_valid & update_idx == 8'h58 | validArray[88],
io_update_valid & update_idx == 8'h57 | validArray[87],
io_update_valid & update_idx == 8'h56 | validArray[86],
io_update_valid & update_idx == 8'h55 | validArray[85],
io_update_valid & update_idx == 8'h54 | validArray[84],
io_update_valid & update_idx == 8'h53 | validArray[83],
io_update_valid & update_idx == 8'h52 | validArray[82],
io_update_valid & update_idx == 8'h51 | validArray[81],
io_update_valid & update_idx == 8'h50 | validArray[80],
io_update_valid & update_idx == 8'h4F | validArray[79],
io_update_valid & update_idx == 8'h4E | validArray[78],
io_update_valid & update_idx == 8'h4D | validArray[77],
io_update_valid & update_idx == 8'h4C | validArray[76],
io_update_valid & update_idx == 8'h4B | validArray[75],
io_update_valid & update_idx == 8'h4A | validArray[74],
io_update_valid & update_idx == 8'h49 | validArray[73],
io_update_valid & update_idx == 8'h48 | validArray[72],
io_update_valid & update_idx == 8'h47 | validArray[71],
io_update_valid & update_idx == 8'h46 | validArray[70],
io_update_valid & update_idx == 8'h45 | validArray[69],
io_update_valid & update_idx == 8'h44 | validArray[68],
io_update_valid & update_idx == 8'h43 | validArray[67],
io_update_valid & update_idx == 8'h42 | validArray[66],
io_update_valid & update_idx == 8'h41 | validArray[65],
io_update_valid & update_idx == 8'h40 | validArray[64],
io_update_valid & update_idx == 8'h3F | validArray[63],
io_update_valid & update_idx == 8'h3E | validArray[62],
io_update_valid & update_idx == 8'h3D | validArray[61],
io_update_valid & update_idx == 8'h3C | validArray[60],
io_update_valid & update_idx == 8'h3B | validArray[59],
io_update_valid & update_idx == 8'h3A | validArray[58],
io_update_valid & update_idx == 8'h39 | validArray[57],
io_update_valid & update_idx == 8'h38 | validArray[56],
io_update_valid & update_idx == 8'h37 | validArray[55],
io_update_valid & update_idx == 8'h36 | validArray[54],
io_update_valid & update_idx == 8'h35 | validArray[53],
io_update_valid & update_idx == 8'h34 | validArray[52],
io_update_valid & update_idx == 8'h33 | validArray[51],
io_update_valid & update_idx == 8'h32 | validArray[50],
io_update_valid & update_idx == 8'h31 | validArray[49],
io_update_valid & update_idx == 8'h30 | validArray[48],
io_update_valid & update_idx == 8'h2F | validArray[47],
io_update_valid & update_idx == 8'h2E | validArray[46],
io_update_valid & update_idx == 8'h2D | validArray[45],
io_update_valid & update_idx == 8'h2C | validArray[44],
io_update_valid & update_idx == 8'h2B | validArray[43],
io_update_valid & update_idx == 8'h2A | validArray[42],
io_update_valid & update_idx == 8'h29 | validArray[41],
io_update_valid & update_idx == 8'h28 | validArray[40],
io_update_valid & update_idx == 8'h27 | validArray[39],
io_update_valid & update_idx == 8'h26 | validArray[38],
io_update_valid & update_idx == 8'h25 | validArray[37],
io_update_valid & update_idx == 8'h24 | validArray[36],
io_update_valid & update_idx == 8'h23 | validArray[35],
io_update_valid & update_idx == 8'h22 | validArray[34],
io_update_valid & update_idx == 8'h21 | validArray[33],
io_update_valid & update_idx == 8'h20 | validArray[32],
io_update_valid & update_idx == 8'h1F | validArray[31],
io_update_valid & update_idx == 8'h1E | validArray[30],
io_update_valid & update_idx == 8'h1D | validArray[29],
io_update_valid & update_idx == 8'h1C | validArray[28],
io_update_valid & update_idx == 8'h1B | validArray[27],
io_update_valid & update_idx == 8'h1A | validArray[26],
io_update_valid & update_idx == 8'h19 | validArray[25],
io_update_valid & update_idx == 8'h18 | validArray[24],
io_update_valid & update_idx == 8'h17 | validArray[23],
io_update_valid & update_idx == 8'h16 | validArray[22],
io_update_valid & update_idx == 8'h15 | validArray[21],
io_update_valid & update_idx == 8'h14 | validArray[20],
io_update_valid & update_idx == 8'h13 | validArray[19],
io_update_valid & update_idx == 8'h12 | validArray[18],
io_update_valid & update_idx == 8'h11 | validArray[17],
io_update_valid & update_idx == 8'h10 | validArray[16],
io_update_valid & update_idx == 8'hF | validArray[15],
io_update_valid & update_idx == 8'hE | validArray[14],
io_update_valid & update_idx == 8'hD | validArray[13],
io_update_valid & update_idx == 8'hC | validArray[12],
io_update_valid & update_idx == 8'hB | validArray[11],
io_update_valid & update_idx == 8'hA | validArray[10],
io_update_valid & update_idx == 8'h9 | validArray[9],
io_update_valid & update_idx == 8'h8 | validArray[8],
io_update_valid & update_idx == 8'h7 | validArray[7],
io_update_valid & update_idx == 8'h6 | validArray[6],
io_update_valid & update_idx == 8'h5 | validArray[5],
io_update_valid & update_idx == 8'h4 | validArray[4],
io_update_valid & update_idx == 8'h3 | validArray[3],
io_update_valid & update_idx == 8'h2 | validArray[2],
io_update_valid & update_idx == 8'h1 | validArray[1],
io_update_valid & update_idx == 8'h0 | validArray[0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:40, :200:27, :283:{30,42}, :284:26, :285:31, :286:33
always @(posedge clock or posedge reset) begin
if (reset)
validArray <= 256'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27
else if (io_update_valid) // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
validArray <= _validArray_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :286:33
end // always @(posedge, posedge)
always @(posedge clock) begin
if (io_req_valid) begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
s1_idx <= s0_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:40, :213:36
s1_tag <=
{io_req_bits_pc[17:14],
{io_req_bits_pc[13],
io_req_bits_pc[12:9] ^ io_req_bits_folded_hist_hist_12_folded_hist}
^ {io_req_bits_folded_hist_hist_12_folded_hist, 1'h0}}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75,82}, :207:43, :213:68
s1_bank_req_1h_0 <= ~(_GEN[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :215:33
s1_bank_req_1h_1 <= _GEN[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :215:33
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:8]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
initial begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
for (logic [3:0] i = 4'h0; i < 4'h9; i += 4'h1) begin
_RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
end // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
validArray =
{_RANDOM[4'h0],
_RANDOM[4'h1],
_RANDOM[4'h2],
_RANDOM[4'h3],
_RANDOM[4'h4],
_RANDOM[4'h5],
_RANDOM[4'h6],
_RANDOM[4'h7]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :200:27
s1_idx = _RANDOM[4'h8][7:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36
s1_tag = _RANDOM[4'h8][16:8]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:{36,68}
s1_bank_req_1h_0 = _RANDOM[4'h8][17]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33
s1_bank_req_1h_1 = _RANDOM[4'h8][18]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33
s1_bank_has_write_on_this_req_0 = _RANDOM[4'h8][19]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48
s1_bank_has_write_on_this_req_1 = _RANDOM[4'h8][20]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48
`endif // RANDOMIZE_REG_INIT
if (reset) // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
validArray = 256'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
Folded1WDataModuleTemplate us ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18
.clock (clock),
.reset (reset),
.io_raddr_0 (s0_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:40
.io_rdata_0 (_us_io_rdata_0),
.io_wen (io_update_uValid),
.io_waddr (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:40
.io_wdata (io_update_u),
.io_resetEn (io_update_reset_u)
);
FoldedSRAMTemplate_21 table_banks_0 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & ~(_GEN[0])), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :223:50
.io_r_req_bits_setIdx (_table_banks_1_io_r_req_bits_setIdx_T), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:40
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33
.io_w_req_bits_setIdx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:40
.io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:82
.io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28
.io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29
);
FoldedSRAMTemplate_21 table_banks_1 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & _GEN[0]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :223:50
.io_r_req_bits_setIdx (_table_banks_1_io_r_req_bits_setIdx_T), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:40
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33
.io_w_req_bits_setIdx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:40
.io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:82
.io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28
.io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29
);
WrBypass_41 wrbypass ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24
.clock (clock),
.reset (reset),
.io_wen (io_update_valid),
.io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:40
.io_write_data_0 (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28
.io_hit (_wrbypass_io_hit),
.io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits)
);
assign io_resp_valid =
_s1_req_rhit_T[0]
& ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag
& ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:68, :215:33, :220:11, :232:{31,61}, :235:{50,53}
assign io_resp_bits_ctr =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11
assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :160:86, :217:18, :237:18
assign io_resp_bits_target =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 39'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11
endmodule

496
src/ITTAGE/ITTageTable_1.sv Normal file
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@ -0,0 +1,496 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module ITTageTable_1( // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
input clock,
input reset,
input io_req_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [7:0] io_req_bits_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
output io_resp_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
output [1:0] io_resp_bits_ctr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
output [1:0] io_resp_bits_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
output [38:0] io_resp_bits_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [7:0] io_update_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_correct, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_alloc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [1:0] io_update_oldCtr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_uValid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_reset_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [38:0] io_update_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [38:0] io_update_old_target // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
);
wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73
wire _wrbypass_io_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24
wire [1:0] _wrbypass_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24
wire [8:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [38:0] _table_banks_1_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [8:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [38:0] _table_banks_0_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire _us_io_rdata_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18
reg [255:0] validArray; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27
wire [7:0] s0_idx = io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43
reg [7:0] s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:36
reg [8:0] s1_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:68
reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33
reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33
wire [255:0] _s1_req_rhit_T = validArray >> s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :213:36, :232:31
reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48
reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48
wire [7:0] update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43
wire [8:0] update_wdata_tag =
{io_update_pc[17], io_update_pc[16:9] ^ io_update_folded_hist_hist_14_folded_hist}
^ {io_update_folded_hist_hist_14_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75}, :207:43
assign _resp_invalid_by_write_WIRE =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33, :240:48
wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :255:33
wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :255:33
wire [1:0] old_ctr =
_wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24, :277:20
wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20
wire [1:0] update_wdata_ctr =
io_update_alloc
? 2'h2
: (&old_ctr) & io_update_correct
? 2'h3
: update_wdata_ctr_oldSatNotTaken & ~io_update_correct
? 2'h0
: io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20, :278:28
wire [38:0] update_wdata_target =
io_update_alloc | update_wdata_ctr_oldSatNotTaken
? io_update_target
: io_update_old_target; // src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:281:{29,46}
wire [255:0] _validArray_T =
{io_update_valid & (&update_idx) | validArray[255],
io_update_valid & update_idx == 8'hFE | validArray[254],
io_update_valid & update_idx == 8'hFD | validArray[253],
io_update_valid & update_idx == 8'hFC | validArray[252],
io_update_valid & update_idx == 8'hFB | validArray[251],
io_update_valid & update_idx == 8'hFA | validArray[250],
io_update_valid & update_idx == 8'hF9 | validArray[249],
io_update_valid & update_idx == 8'hF8 | validArray[248],
io_update_valid & update_idx == 8'hF7 | validArray[247],
io_update_valid & update_idx == 8'hF6 | validArray[246],
io_update_valid & update_idx == 8'hF5 | validArray[245],
io_update_valid & update_idx == 8'hF4 | validArray[244],
io_update_valid & update_idx == 8'hF3 | validArray[243],
io_update_valid & update_idx == 8'hF2 | validArray[242],
io_update_valid & update_idx == 8'hF1 | validArray[241],
io_update_valid & update_idx == 8'hF0 | validArray[240],
io_update_valid & update_idx == 8'hEF | validArray[239],
io_update_valid & update_idx == 8'hEE | validArray[238],
io_update_valid & update_idx == 8'hED | validArray[237],
io_update_valid & update_idx == 8'hEC | validArray[236],
io_update_valid & update_idx == 8'hEB | validArray[235],
io_update_valid & update_idx == 8'hEA | validArray[234],
io_update_valid & update_idx == 8'hE9 | validArray[233],
io_update_valid & update_idx == 8'hE8 | validArray[232],
io_update_valid & update_idx == 8'hE7 | validArray[231],
io_update_valid & update_idx == 8'hE6 | validArray[230],
io_update_valid & update_idx == 8'hE5 | validArray[229],
io_update_valid & update_idx == 8'hE4 | validArray[228],
io_update_valid & update_idx == 8'hE3 | validArray[227],
io_update_valid & update_idx == 8'hE2 | validArray[226],
io_update_valid & update_idx == 8'hE1 | validArray[225],
io_update_valid & update_idx == 8'hE0 | validArray[224],
io_update_valid & update_idx == 8'hDF | validArray[223],
io_update_valid & update_idx == 8'hDE | validArray[222],
io_update_valid & update_idx == 8'hDD | validArray[221],
io_update_valid & update_idx == 8'hDC | validArray[220],
io_update_valid & update_idx == 8'hDB | validArray[219],
io_update_valid & update_idx == 8'hDA | validArray[218],
io_update_valid & update_idx == 8'hD9 | validArray[217],
io_update_valid & update_idx == 8'hD8 | validArray[216],
io_update_valid & update_idx == 8'hD7 | validArray[215],
io_update_valid & update_idx == 8'hD6 | validArray[214],
io_update_valid & update_idx == 8'hD5 | validArray[213],
io_update_valid & update_idx == 8'hD4 | validArray[212],
io_update_valid & update_idx == 8'hD3 | validArray[211],
io_update_valid & update_idx == 8'hD2 | validArray[210],
io_update_valid & update_idx == 8'hD1 | validArray[209],
io_update_valid & update_idx == 8'hD0 | validArray[208],
io_update_valid & update_idx == 8'hCF | validArray[207],
io_update_valid & update_idx == 8'hCE | validArray[206],
io_update_valid & update_idx == 8'hCD | validArray[205],
io_update_valid & update_idx == 8'hCC | validArray[204],
io_update_valid & update_idx == 8'hCB | validArray[203],
io_update_valid & update_idx == 8'hCA | validArray[202],
io_update_valid & update_idx == 8'hC9 | validArray[201],
io_update_valid & update_idx == 8'hC8 | validArray[200],
io_update_valid & update_idx == 8'hC7 | validArray[199],
io_update_valid & update_idx == 8'hC6 | validArray[198],
io_update_valid & update_idx == 8'hC5 | validArray[197],
io_update_valid & update_idx == 8'hC4 | validArray[196],
io_update_valid & update_idx == 8'hC3 | validArray[195],
io_update_valid & update_idx == 8'hC2 | validArray[194],
io_update_valid & update_idx == 8'hC1 | validArray[193],
io_update_valid & update_idx == 8'hC0 | validArray[192],
io_update_valid & update_idx == 8'hBF | validArray[191],
io_update_valid & update_idx == 8'hBE | validArray[190],
io_update_valid & update_idx == 8'hBD | validArray[189],
io_update_valid & update_idx == 8'hBC | validArray[188],
io_update_valid & update_idx == 8'hBB | validArray[187],
io_update_valid & update_idx == 8'hBA | validArray[186],
io_update_valid & update_idx == 8'hB9 | validArray[185],
io_update_valid & update_idx == 8'hB8 | validArray[184],
io_update_valid & update_idx == 8'hB7 | validArray[183],
io_update_valid & update_idx == 8'hB6 | validArray[182],
io_update_valid & update_idx == 8'hB5 | validArray[181],
io_update_valid & update_idx == 8'hB4 | validArray[180],
io_update_valid & update_idx == 8'hB3 | validArray[179],
io_update_valid & update_idx == 8'hB2 | validArray[178],
io_update_valid & update_idx == 8'hB1 | validArray[177],
io_update_valid & update_idx == 8'hB0 | validArray[176],
io_update_valid & update_idx == 8'hAF | validArray[175],
io_update_valid & update_idx == 8'hAE | validArray[174],
io_update_valid & update_idx == 8'hAD | validArray[173],
io_update_valid & update_idx == 8'hAC | validArray[172],
io_update_valid & update_idx == 8'hAB | validArray[171],
io_update_valid & update_idx == 8'hAA | validArray[170],
io_update_valid & update_idx == 8'hA9 | validArray[169],
io_update_valid & update_idx == 8'hA8 | validArray[168],
io_update_valid & update_idx == 8'hA7 | validArray[167],
io_update_valid & update_idx == 8'hA6 | validArray[166],
io_update_valid & update_idx == 8'hA5 | validArray[165],
io_update_valid & update_idx == 8'hA4 | validArray[164],
io_update_valid & update_idx == 8'hA3 | validArray[163],
io_update_valid & update_idx == 8'hA2 | validArray[162],
io_update_valid & update_idx == 8'hA1 | validArray[161],
io_update_valid & update_idx == 8'hA0 | validArray[160],
io_update_valid & update_idx == 8'h9F | validArray[159],
io_update_valid & update_idx == 8'h9E | validArray[158],
io_update_valid & update_idx == 8'h9D | validArray[157],
io_update_valid & update_idx == 8'h9C | validArray[156],
io_update_valid & update_idx == 8'h9B | validArray[155],
io_update_valid & update_idx == 8'h9A | validArray[154],
io_update_valid & update_idx == 8'h99 | validArray[153],
io_update_valid & update_idx == 8'h98 | validArray[152],
io_update_valid & update_idx == 8'h97 | validArray[151],
io_update_valid & update_idx == 8'h96 | validArray[150],
io_update_valid & update_idx == 8'h95 | validArray[149],
io_update_valid & update_idx == 8'h94 | validArray[148],
io_update_valid & update_idx == 8'h93 | validArray[147],
io_update_valid & update_idx == 8'h92 | validArray[146],
io_update_valid & update_idx == 8'h91 | validArray[145],
io_update_valid & update_idx == 8'h90 | validArray[144],
io_update_valid & update_idx == 8'h8F | validArray[143],
io_update_valid & update_idx == 8'h8E | validArray[142],
io_update_valid & update_idx == 8'h8D | validArray[141],
io_update_valid & update_idx == 8'h8C | validArray[140],
io_update_valid & update_idx == 8'h8B | validArray[139],
io_update_valid & update_idx == 8'h8A | validArray[138],
io_update_valid & update_idx == 8'h89 | validArray[137],
io_update_valid & update_idx == 8'h88 | validArray[136],
io_update_valid & update_idx == 8'h87 | validArray[135],
io_update_valid & update_idx == 8'h86 | validArray[134],
io_update_valid & update_idx == 8'h85 | validArray[133],
io_update_valid & update_idx == 8'h84 | validArray[132],
io_update_valid & update_idx == 8'h83 | validArray[131],
io_update_valid & update_idx == 8'h82 | validArray[130],
io_update_valid & update_idx == 8'h81 | validArray[129],
io_update_valid & update_idx == 8'h80 | validArray[128],
io_update_valid & update_idx == 8'h7F | validArray[127],
io_update_valid & update_idx == 8'h7E | validArray[126],
io_update_valid & update_idx == 8'h7D | validArray[125],
io_update_valid & update_idx == 8'h7C | validArray[124],
io_update_valid & update_idx == 8'h7B | validArray[123],
io_update_valid & update_idx == 8'h7A | validArray[122],
io_update_valid & update_idx == 8'h79 | validArray[121],
io_update_valid & update_idx == 8'h78 | validArray[120],
io_update_valid & update_idx == 8'h77 | validArray[119],
io_update_valid & update_idx == 8'h76 | validArray[118],
io_update_valid & update_idx == 8'h75 | validArray[117],
io_update_valid & update_idx == 8'h74 | validArray[116],
io_update_valid & update_idx == 8'h73 | validArray[115],
io_update_valid & update_idx == 8'h72 | validArray[114],
io_update_valid & update_idx == 8'h71 | validArray[113],
io_update_valid & update_idx == 8'h70 | validArray[112],
io_update_valid & update_idx == 8'h6F | validArray[111],
io_update_valid & update_idx == 8'h6E | validArray[110],
io_update_valid & update_idx == 8'h6D | validArray[109],
io_update_valid & update_idx == 8'h6C | validArray[108],
io_update_valid & update_idx == 8'h6B | validArray[107],
io_update_valid & update_idx == 8'h6A | validArray[106],
io_update_valid & update_idx == 8'h69 | validArray[105],
io_update_valid & update_idx == 8'h68 | validArray[104],
io_update_valid & update_idx == 8'h67 | validArray[103],
io_update_valid & update_idx == 8'h66 | validArray[102],
io_update_valid & update_idx == 8'h65 | validArray[101],
io_update_valid & update_idx == 8'h64 | validArray[100],
io_update_valid & update_idx == 8'h63 | validArray[99],
io_update_valid & update_idx == 8'h62 | validArray[98],
io_update_valid & update_idx == 8'h61 | validArray[97],
io_update_valid & update_idx == 8'h60 | validArray[96],
io_update_valid & update_idx == 8'h5F | validArray[95],
io_update_valid & update_idx == 8'h5E | validArray[94],
io_update_valid & update_idx == 8'h5D | validArray[93],
io_update_valid & update_idx == 8'h5C | validArray[92],
io_update_valid & update_idx == 8'h5B | validArray[91],
io_update_valid & update_idx == 8'h5A | validArray[90],
io_update_valid & update_idx == 8'h59 | validArray[89],
io_update_valid & update_idx == 8'h58 | validArray[88],
io_update_valid & update_idx == 8'h57 | validArray[87],
io_update_valid & update_idx == 8'h56 | validArray[86],
io_update_valid & update_idx == 8'h55 | validArray[85],
io_update_valid & update_idx == 8'h54 | validArray[84],
io_update_valid & update_idx == 8'h53 | validArray[83],
io_update_valid & update_idx == 8'h52 | validArray[82],
io_update_valid & update_idx == 8'h51 | validArray[81],
io_update_valid & update_idx == 8'h50 | validArray[80],
io_update_valid & update_idx == 8'h4F | validArray[79],
io_update_valid & update_idx == 8'h4E | validArray[78],
io_update_valid & update_idx == 8'h4D | validArray[77],
io_update_valid & update_idx == 8'h4C | validArray[76],
io_update_valid & update_idx == 8'h4B | validArray[75],
io_update_valid & update_idx == 8'h4A | validArray[74],
io_update_valid & update_idx == 8'h49 | validArray[73],
io_update_valid & update_idx == 8'h48 | validArray[72],
io_update_valid & update_idx == 8'h47 | validArray[71],
io_update_valid & update_idx == 8'h46 | validArray[70],
io_update_valid & update_idx == 8'h45 | validArray[69],
io_update_valid & update_idx == 8'h44 | validArray[68],
io_update_valid & update_idx == 8'h43 | validArray[67],
io_update_valid & update_idx == 8'h42 | validArray[66],
io_update_valid & update_idx == 8'h41 | validArray[65],
io_update_valid & update_idx == 8'h40 | validArray[64],
io_update_valid & update_idx == 8'h3F | validArray[63],
io_update_valid & update_idx == 8'h3E | validArray[62],
io_update_valid & update_idx == 8'h3D | validArray[61],
io_update_valid & update_idx == 8'h3C | validArray[60],
io_update_valid & update_idx == 8'h3B | validArray[59],
io_update_valid & update_idx == 8'h3A | validArray[58],
io_update_valid & update_idx == 8'h39 | validArray[57],
io_update_valid & update_idx == 8'h38 | validArray[56],
io_update_valid & update_idx == 8'h37 | validArray[55],
io_update_valid & update_idx == 8'h36 | validArray[54],
io_update_valid & update_idx == 8'h35 | validArray[53],
io_update_valid & update_idx == 8'h34 | validArray[52],
io_update_valid & update_idx == 8'h33 | validArray[51],
io_update_valid & update_idx == 8'h32 | validArray[50],
io_update_valid & update_idx == 8'h31 | validArray[49],
io_update_valid & update_idx == 8'h30 | validArray[48],
io_update_valid & update_idx == 8'h2F | validArray[47],
io_update_valid & update_idx == 8'h2E | validArray[46],
io_update_valid & update_idx == 8'h2D | validArray[45],
io_update_valid & update_idx == 8'h2C | validArray[44],
io_update_valid & update_idx == 8'h2B | validArray[43],
io_update_valid & update_idx == 8'h2A | validArray[42],
io_update_valid & update_idx == 8'h29 | validArray[41],
io_update_valid & update_idx == 8'h28 | validArray[40],
io_update_valid & update_idx == 8'h27 | validArray[39],
io_update_valid & update_idx == 8'h26 | validArray[38],
io_update_valid & update_idx == 8'h25 | validArray[37],
io_update_valid & update_idx == 8'h24 | validArray[36],
io_update_valid & update_idx == 8'h23 | validArray[35],
io_update_valid & update_idx == 8'h22 | validArray[34],
io_update_valid & update_idx == 8'h21 | validArray[33],
io_update_valid & update_idx == 8'h20 | validArray[32],
io_update_valid & update_idx == 8'h1F | validArray[31],
io_update_valid & update_idx == 8'h1E | validArray[30],
io_update_valid & update_idx == 8'h1D | validArray[29],
io_update_valid & update_idx == 8'h1C | validArray[28],
io_update_valid & update_idx == 8'h1B | validArray[27],
io_update_valid & update_idx == 8'h1A | validArray[26],
io_update_valid & update_idx == 8'h19 | validArray[25],
io_update_valid & update_idx == 8'h18 | validArray[24],
io_update_valid & update_idx == 8'h17 | validArray[23],
io_update_valid & update_idx == 8'h16 | validArray[22],
io_update_valid & update_idx == 8'h15 | validArray[21],
io_update_valid & update_idx == 8'h14 | validArray[20],
io_update_valid & update_idx == 8'h13 | validArray[19],
io_update_valid & update_idx == 8'h12 | validArray[18],
io_update_valid & update_idx == 8'h11 | validArray[17],
io_update_valid & update_idx == 8'h10 | validArray[16],
io_update_valid & update_idx == 8'hF | validArray[15],
io_update_valid & update_idx == 8'hE | validArray[14],
io_update_valid & update_idx == 8'hD | validArray[13],
io_update_valid & update_idx == 8'hC | validArray[12],
io_update_valid & update_idx == 8'hB | validArray[11],
io_update_valid & update_idx == 8'hA | validArray[10],
io_update_valid & update_idx == 8'h9 | validArray[9],
io_update_valid & update_idx == 8'h8 | validArray[8],
io_update_valid & update_idx == 8'h7 | validArray[7],
io_update_valid & update_idx == 8'h6 | validArray[6],
io_update_valid & update_idx == 8'h5 | validArray[5],
io_update_valid & update_idx == 8'h4 | validArray[4],
io_update_valid & update_idx == 8'h3 | validArray[3],
io_update_valid & update_idx == 8'h2 | validArray[2],
io_update_valid & update_idx == 8'h1 | validArray[1],
io_update_valid & update_idx == 8'h0 | validArray[0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :200:27, :283:{30,42}, :284:26, :285:31, :286:33
always @(posedge clock or posedge reset) begin
if (reset)
validArray <= 256'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27
else if (io_update_valid) // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
validArray <= _validArray_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :286:33
end // always @(posedge, posedge)
always @(posedge clock) begin
if (io_req_valid) begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
s1_idx <= s0_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :213:36
s1_tag <=
{io_req_bits_pc[17],
io_req_bits_pc[16:9] ^ io_req_bits_folded_hist_hist_14_folded_hist}
^ {io_req_bits_folded_hist_hist_14_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75}, :207:43, :213:68
s1_bank_req_1h_0 <= ~(s0_idx[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :215:33
s1_bank_req_1h_1 <= s0_idx[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :215:33
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:8]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
initial begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
for (logic [3:0] i = 4'h0; i < 4'h9; i += 4'h1) begin
_RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
end // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
validArray =
{_RANDOM[4'h0],
_RANDOM[4'h1],
_RANDOM[4'h2],
_RANDOM[4'h3],
_RANDOM[4'h4],
_RANDOM[4'h5],
_RANDOM[4'h6],
_RANDOM[4'h7]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :200:27
s1_idx = _RANDOM[4'h8][7:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36
s1_tag = _RANDOM[4'h8][16:8]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:{36,68}
s1_bank_req_1h_0 = _RANDOM[4'h8][17]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33
s1_bank_req_1h_1 = _RANDOM[4'h8][18]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33
s1_bank_has_write_on_this_req_0 = _RANDOM[4'h8][19]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48
s1_bank_has_write_on_this_req_1 = _RANDOM[4'h8][20]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48
`endif // RANDOMIZE_REG_INIT
if (reset) // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
validArray = 256'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
Folded1WDataModuleTemplate us ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18
.clock (clock),
.reset (reset),
.io_raddr_0 (s0_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31
.io_rdata_0 (_us_io_rdata_0),
.io_wen (io_update_uValid),
.io_waddr (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31
.io_wdata (io_update_u),
.io_resetEn (io_update_reset_u)
);
FoldedSRAMTemplate_21 table_banks_0 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & ~(s0_idx[0])), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :223:50
.io_r_req_bits_setIdx (s0_idx[7:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33
.io_w_req_bits_setIdx (update_idx[7:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}
.io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61
.io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28
.io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29
);
FoldedSRAMTemplate_21 table_banks_1 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & s0_idx[0]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :223:50
.io_r_req_bits_setIdx (s0_idx[7:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33
.io_w_req_bits_setIdx (update_idx[7:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}
.io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61
.io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28
.io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29
);
WrBypass_41 wrbypass ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24
.clock (clock),
.reset (reset),
.io_wen (io_update_valid),
.io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31
.io_write_data_0 (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28
.io_hit (_wrbypass_io_hit),
.io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits)
);
assign io_resp_valid =
_s1_req_rhit_T[0]
& ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag
& ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:68, :215:33, :220:11, :232:{31,61}, :235:{50,53}
assign io_resp_bits_ctr =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11
assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :160:86, :217:18, :237:18
assign io_resp_bits_target =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 39'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11
endmodule

761
src/ITTAGE/ITTageTable_2.sv Normal file
View File

@ -0,0 +1,761 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module ITTageTable_2( // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
input clock,
input reset,
input io_req_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [8:0] io_req_bits_folded_hist_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [7:0] io_req_bits_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
output io_resp_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
output [1:0] io_resp_bits_ctr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
output [1:0] io_resp_bits_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
output [38:0] io_resp_bits_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [8:0] io_update_folded_hist_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [7:0] io_update_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_correct, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_alloc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [1:0] io_update_oldCtr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_uValid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_reset_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [38:0] io_update_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [38:0] io_update_old_target // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
);
wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73
wire _wrbypass_io_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24
wire [1:0] _wrbypass_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24
wire [8:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [38:0] _table_banks_1_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [8:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [38:0] _table_banks_0_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire _us_io_rdata_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18
reg [511:0] validArray; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27
wire [8:0] s0_idx = io_req_bits_pc[9:1] ^ io_req_bits_folded_hist_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43
reg [8:0] s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:36
reg [8:0] s1_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:68
reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33
reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33
wire [511:0] _s1_req_rhit_T = validArray >> s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :213:36, :232:31
reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48
reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48
wire [8:0] update_idx = io_update_pc[9:1] ^ io_update_folded_hist_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43
wire [8:0] update_wdata_tag =
io_update_pc[18:10] ^ io_update_folded_hist_hist_13_folded_hist
^ {io_update_folded_hist_hist_4_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75}, :207:43
assign _resp_invalid_by_write_WIRE =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33, :240:48
wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :255:33
wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :255:33
wire [1:0] old_ctr =
_wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24, :277:20
wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20
wire [1:0] update_wdata_ctr =
io_update_alloc
? 2'h2
: (&old_ctr) & io_update_correct
? 2'h3
: update_wdata_ctr_oldSatNotTaken & ~io_update_correct
? 2'h0
: io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20, :278:28
wire [38:0] update_wdata_target =
io_update_alloc | update_wdata_ctr_oldSatNotTaken
? io_update_target
: io_update_old_target; // src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:281:{29,46}
wire [511:0] _validArray_T =
{io_update_valid & (&update_idx) | validArray[511],
io_update_valid & update_idx == 9'h1FE | validArray[510],
io_update_valid & update_idx == 9'h1FD | validArray[509],
io_update_valid & update_idx == 9'h1FC | validArray[508],
io_update_valid & update_idx == 9'h1FB | validArray[507],
io_update_valid & update_idx == 9'h1FA | validArray[506],
io_update_valid & update_idx == 9'h1F9 | validArray[505],
io_update_valid & update_idx == 9'h1F8 | validArray[504],
io_update_valid & update_idx == 9'h1F7 | validArray[503],
io_update_valid & update_idx == 9'h1F6 | validArray[502],
io_update_valid & update_idx == 9'h1F5 | validArray[501],
io_update_valid & update_idx == 9'h1F4 | validArray[500],
io_update_valid & update_idx == 9'h1F3 | validArray[499],
io_update_valid & update_idx == 9'h1F2 | validArray[498],
io_update_valid & update_idx == 9'h1F1 | validArray[497],
io_update_valid & update_idx == 9'h1F0 | validArray[496],
io_update_valid & update_idx == 9'h1EF | validArray[495],
io_update_valid & update_idx == 9'h1EE | validArray[494],
io_update_valid & update_idx == 9'h1ED | validArray[493],
io_update_valid & update_idx == 9'h1EC | validArray[492],
io_update_valid & update_idx == 9'h1EB | validArray[491],
io_update_valid & update_idx == 9'h1EA | validArray[490],
io_update_valid & update_idx == 9'h1E9 | validArray[489],
io_update_valid & update_idx == 9'h1E8 | validArray[488],
io_update_valid & update_idx == 9'h1E7 | validArray[487],
io_update_valid & update_idx == 9'h1E6 | validArray[486],
io_update_valid & update_idx == 9'h1E5 | validArray[485],
io_update_valid & update_idx == 9'h1E4 | validArray[484],
io_update_valid & update_idx == 9'h1E3 | validArray[483],
io_update_valid & update_idx == 9'h1E2 | validArray[482],
io_update_valid & update_idx == 9'h1E1 | validArray[481],
io_update_valid & update_idx == 9'h1E0 | validArray[480],
io_update_valid & update_idx == 9'h1DF | validArray[479],
io_update_valid & update_idx == 9'h1DE | validArray[478],
io_update_valid & update_idx == 9'h1DD | validArray[477],
io_update_valid & update_idx == 9'h1DC | validArray[476],
io_update_valid & update_idx == 9'h1DB | validArray[475],
io_update_valid & update_idx == 9'h1DA | validArray[474],
io_update_valid & update_idx == 9'h1D9 | validArray[473],
io_update_valid & update_idx == 9'h1D8 | validArray[472],
io_update_valid & update_idx == 9'h1D7 | validArray[471],
io_update_valid & update_idx == 9'h1D6 | validArray[470],
io_update_valid & update_idx == 9'h1D5 | validArray[469],
io_update_valid & update_idx == 9'h1D4 | validArray[468],
io_update_valid & update_idx == 9'h1D3 | validArray[467],
io_update_valid & update_idx == 9'h1D2 | validArray[466],
io_update_valid & update_idx == 9'h1D1 | validArray[465],
io_update_valid & update_idx == 9'h1D0 | validArray[464],
io_update_valid & update_idx == 9'h1CF | validArray[463],
io_update_valid & update_idx == 9'h1CE | validArray[462],
io_update_valid & update_idx == 9'h1CD | validArray[461],
io_update_valid & update_idx == 9'h1CC | validArray[460],
io_update_valid & update_idx == 9'h1CB | validArray[459],
io_update_valid & update_idx == 9'h1CA | validArray[458],
io_update_valid & update_idx == 9'h1C9 | validArray[457],
io_update_valid & update_idx == 9'h1C8 | validArray[456],
io_update_valid & update_idx == 9'h1C7 | validArray[455],
io_update_valid & update_idx == 9'h1C6 | validArray[454],
io_update_valid & update_idx == 9'h1C5 | validArray[453],
io_update_valid & update_idx == 9'h1C4 | validArray[452],
io_update_valid & update_idx == 9'h1C3 | validArray[451],
io_update_valid & update_idx == 9'h1C2 | validArray[450],
io_update_valid & update_idx == 9'h1C1 | validArray[449],
io_update_valid & update_idx == 9'h1C0 | validArray[448],
io_update_valid & update_idx == 9'h1BF | validArray[447],
io_update_valid & update_idx == 9'h1BE | validArray[446],
io_update_valid & update_idx == 9'h1BD | validArray[445],
io_update_valid & update_idx == 9'h1BC | validArray[444],
io_update_valid & update_idx == 9'h1BB | validArray[443],
io_update_valid & update_idx == 9'h1BA | validArray[442],
io_update_valid & update_idx == 9'h1B9 | validArray[441],
io_update_valid & update_idx == 9'h1B8 | validArray[440],
io_update_valid & update_idx == 9'h1B7 | validArray[439],
io_update_valid & update_idx == 9'h1B6 | validArray[438],
io_update_valid & update_idx == 9'h1B5 | validArray[437],
io_update_valid & update_idx == 9'h1B4 | validArray[436],
io_update_valid & update_idx == 9'h1B3 | validArray[435],
io_update_valid & update_idx == 9'h1B2 | validArray[434],
io_update_valid & update_idx == 9'h1B1 | validArray[433],
io_update_valid & update_idx == 9'h1B0 | validArray[432],
io_update_valid & update_idx == 9'h1AF | validArray[431],
io_update_valid & update_idx == 9'h1AE | validArray[430],
io_update_valid & update_idx == 9'h1AD | validArray[429],
io_update_valid & update_idx == 9'h1AC | validArray[428],
io_update_valid & update_idx == 9'h1AB | validArray[427],
io_update_valid & update_idx == 9'h1AA | validArray[426],
io_update_valid & update_idx == 9'h1A9 | validArray[425],
io_update_valid & update_idx == 9'h1A8 | validArray[424],
io_update_valid & update_idx == 9'h1A7 | validArray[423],
io_update_valid & update_idx == 9'h1A6 | validArray[422],
io_update_valid & update_idx == 9'h1A5 | validArray[421],
io_update_valid & update_idx == 9'h1A4 | validArray[420],
io_update_valid & update_idx == 9'h1A3 | validArray[419],
io_update_valid & update_idx == 9'h1A2 | validArray[418],
io_update_valid & update_idx == 9'h1A1 | validArray[417],
io_update_valid & update_idx == 9'h1A0 | validArray[416],
io_update_valid & update_idx == 9'h19F | validArray[415],
io_update_valid & update_idx == 9'h19E | validArray[414],
io_update_valid & update_idx == 9'h19D | validArray[413],
io_update_valid & update_idx == 9'h19C | validArray[412],
io_update_valid & update_idx == 9'h19B | validArray[411],
io_update_valid & update_idx == 9'h19A | validArray[410],
io_update_valid & update_idx == 9'h199 | validArray[409],
io_update_valid & update_idx == 9'h198 | validArray[408],
io_update_valid & update_idx == 9'h197 | validArray[407],
io_update_valid & update_idx == 9'h196 | validArray[406],
io_update_valid & update_idx == 9'h195 | validArray[405],
io_update_valid & update_idx == 9'h194 | validArray[404],
io_update_valid & update_idx == 9'h193 | validArray[403],
io_update_valid & update_idx == 9'h192 | validArray[402],
io_update_valid & update_idx == 9'h191 | validArray[401],
io_update_valid & update_idx == 9'h190 | validArray[400],
io_update_valid & update_idx == 9'h18F | validArray[399],
io_update_valid & update_idx == 9'h18E | validArray[398],
io_update_valid & update_idx == 9'h18D | validArray[397],
io_update_valid & update_idx == 9'h18C | validArray[396],
io_update_valid & update_idx == 9'h18B | validArray[395],
io_update_valid & update_idx == 9'h18A | validArray[394],
io_update_valid & update_idx == 9'h189 | validArray[393],
io_update_valid & update_idx == 9'h188 | validArray[392],
io_update_valid & update_idx == 9'h187 | validArray[391],
io_update_valid & update_idx == 9'h186 | validArray[390],
io_update_valid & update_idx == 9'h185 | validArray[389],
io_update_valid & update_idx == 9'h184 | validArray[388],
io_update_valid & update_idx == 9'h183 | validArray[387],
io_update_valid & update_idx == 9'h182 | validArray[386],
io_update_valid & update_idx == 9'h181 | validArray[385],
io_update_valid & update_idx == 9'h180 | validArray[384],
io_update_valid & update_idx == 9'h17F | validArray[383],
io_update_valid & update_idx == 9'h17E | validArray[382],
io_update_valid & update_idx == 9'h17D | validArray[381],
io_update_valid & update_idx == 9'h17C | validArray[380],
io_update_valid & update_idx == 9'h17B | validArray[379],
io_update_valid & update_idx == 9'h17A | validArray[378],
io_update_valid & update_idx == 9'h179 | validArray[377],
io_update_valid & update_idx == 9'h178 | validArray[376],
io_update_valid & update_idx == 9'h177 | validArray[375],
io_update_valid & update_idx == 9'h176 | validArray[374],
io_update_valid & update_idx == 9'h175 | validArray[373],
io_update_valid & update_idx == 9'h174 | validArray[372],
io_update_valid & update_idx == 9'h173 | validArray[371],
io_update_valid & update_idx == 9'h172 | validArray[370],
io_update_valid & update_idx == 9'h171 | validArray[369],
io_update_valid & update_idx == 9'h170 | validArray[368],
io_update_valid & update_idx == 9'h16F | validArray[367],
io_update_valid & update_idx == 9'h16E | validArray[366],
io_update_valid & update_idx == 9'h16D | validArray[365],
io_update_valid & update_idx == 9'h16C | validArray[364],
io_update_valid & update_idx == 9'h16B | validArray[363],
io_update_valid & update_idx == 9'h16A | validArray[362],
io_update_valid & update_idx == 9'h169 | validArray[361],
io_update_valid & update_idx == 9'h168 | validArray[360],
io_update_valid & update_idx == 9'h167 | validArray[359],
io_update_valid & update_idx == 9'h166 | validArray[358],
io_update_valid & update_idx == 9'h165 | validArray[357],
io_update_valid & update_idx == 9'h164 | validArray[356],
io_update_valid & update_idx == 9'h163 | validArray[355],
io_update_valid & update_idx == 9'h162 | validArray[354],
io_update_valid & update_idx == 9'h161 | validArray[353],
io_update_valid & update_idx == 9'h160 | validArray[352],
io_update_valid & update_idx == 9'h15F | validArray[351],
io_update_valid & update_idx == 9'h15E | validArray[350],
io_update_valid & update_idx == 9'h15D | validArray[349],
io_update_valid & update_idx == 9'h15C | validArray[348],
io_update_valid & update_idx == 9'h15B | validArray[347],
io_update_valid & update_idx == 9'h15A | validArray[346],
io_update_valid & update_idx == 9'h159 | validArray[345],
io_update_valid & update_idx == 9'h158 | validArray[344],
io_update_valid & update_idx == 9'h157 | validArray[343],
io_update_valid & update_idx == 9'h156 | validArray[342],
io_update_valid & update_idx == 9'h155 | validArray[341],
io_update_valid & update_idx == 9'h154 | validArray[340],
io_update_valid & update_idx == 9'h153 | validArray[339],
io_update_valid & update_idx == 9'h152 | validArray[338],
io_update_valid & update_idx == 9'h151 | validArray[337],
io_update_valid & update_idx == 9'h150 | validArray[336],
io_update_valid & update_idx == 9'h14F | validArray[335],
io_update_valid & update_idx == 9'h14E | validArray[334],
io_update_valid & update_idx == 9'h14D | validArray[333],
io_update_valid & update_idx == 9'h14C | validArray[332],
io_update_valid & update_idx == 9'h14B | validArray[331],
io_update_valid & update_idx == 9'h14A | validArray[330],
io_update_valid & update_idx == 9'h149 | validArray[329],
io_update_valid & update_idx == 9'h148 | validArray[328],
io_update_valid & update_idx == 9'h147 | validArray[327],
io_update_valid & update_idx == 9'h146 | validArray[326],
io_update_valid & update_idx == 9'h145 | validArray[325],
io_update_valid & update_idx == 9'h144 | validArray[324],
io_update_valid & update_idx == 9'h143 | validArray[323],
io_update_valid & update_idx == 9'h142 | validArray[322],
io_update_valid & update_idx == 9'h141 | validArray[321],
io_update_valid & update_idx == 9'h140 | validArray[320],
io_update_valid & update_idx == 9'h13F | validArray[319],
io_update_valid & update_idx == 9'h13E | validArray[318],
io_update_valid & update_idx == 9'h13D | validArray[317],
io_update_valid & update_idx == 9'h13C | validArray[316],
io_update_valid & update_idx == 9'h13B | validArray[315],
io_update_valid & update_idx == 9'h13A | validArray[314],
io_update_valid & update_idx == 9'h139 | validArray[313],
io_update_valid & update_idx == 9'h138 | validArray[312],
io_update_valid & update_idx == 9'h137 | validArray[311],
io_update_valid & update_idx == 9'h136 | validArray[310],
io_update_valid & update_idx == 9'h135 | validArray[309],
io_update_valid & update_idx == 9'h134 | validArray[308],
io_update_valid & update_idx == 9'h133 | validArray[307],
io_update_valid & update_idx == 9'h132 | validArray[306],
io_update_valid & update_idx == 9'h131 | validArray[305],
io_update_valid & update_idx == 9'h130 | validArray[304],
io_update_valid & update_idx == 9'h12F | validArray[303],
io_update_valid & update_idx == 9'h12E | validArray[302],
io_update_valid & update_idx == 9'h12D | validArray[301],
io_update_valid & update_idx == 9'h12C | validArray[300],
io_update_valid & update_idx == 9'h12B | validArray[299],
io_update_valid & update_idx == 9'h12A | validArray[298],
io_update_valid & update_idx == 9'h129 | validArray[297],
io_update_valid & update_idx == 9'h128 | validArray[296],
io_update_valid & update_idx == 9'h127 | validArray[295],
io_update_valid & update_idx == 9'h126 | validArray[294],
io_update_valid & update_idx == 9'h125 | validArray[293],
io_update_valid & update_idx == 9'h124 | validArray[292],
io_update_valid & update_idx == 9'h123 | validArray[291],
io_update_valid & update_idx == 9'h122 | validArray[290],
io_update_valid & update_idx == 9'h121 | validArray[289],
io_update_valid & update_idx == 9'h120 | validArray[288],
io_update_valid & update_idx == 9'h11F | validArray[287],
io_update_valid & update_idx == 9'h11E | validArray[286],
io_update_valid & update_idx == 9'h11D | validArray[285],
io_update_valid & update_idx == 9'h11C | validArray[284],
io_update_valid & update_idx == 9'h11B | validArray[283],
io_update_valid & update_idx == 9'h11A | validArray[282],
io_update_valid & update_idx == 9'h119 | validArray[281],
io_update_valid & update_idx == 9'h118 | validArray[280],
io_update_valid & update_idx == 9'h117 | validArray[279],
io_update_valid & update_idx == 9'h116 | validArray[278],
io_update_valid & update_idx == 9'h115 | validArray[277],
io_update_valid & update_idx == 9'h114 | validArray[276],
io_update_valid & update_idx == 9'h113 | validArray[275],
io_update_valid & update_idx == 9'h112 | validArray[274],
io_update_valid & update_idx == 9'h111 | validArray[273],
io_update_valid & update_idx == 9'h110 | validArray[272],
io_update_valid & update_idx == 9'h10F | validArray[271],
io_update_valid & update_idx == 9'h10E | validArray[270],
io_update_valid & update_idx == 9'h10D | validArray[269],
io_update_valid & update_idx == 9'h10C | validArray[268],
io_update_valid & update_idx == 9'h10B | validArray[267],
io_update_valid & update_idx == 9'h10A | validArray[266],
io_update_valid & update_idx == 9'h109 | validArray[265],
io_update_valid & update_idx == 9'h108 | validArray[264],
io_update_valid & update_idx == 9'h107 | validArray[263],
io_update_valid & update_idx == 9'h106 | validArray[262],
io_update_valid & update_idx == 9'h105 | validArray[261],
io_update_valid & update_idx == 9'h104 | validArray[260],
io_update_valid & update_idx == 9'h103 | validArray[259],
io_update_valid & update_idx == 9'h102 | validArray[258],
io_update_valid & update_idx == 9'h101 | validArray[257],
io_update_valid & update_idx == 9'h100 | validArray[256],
io_update_valid & update_idx == 9'hFF | validArray[255],
io_update_valid & update_idx == 9'hFE | validArray[254],
io_update_valid & update_idx == 9'hFD | validArray[253],
io_update_valid & update_idx == 9'hFC | validArray[252],
io_update_valid & update_idx == 9'hFB | validArray[251],
io_update_valid & update_idx == 9'hFA | validArray[250],
io_update_valid & update_idx == 9'hF9 | validArray[249],
io_update_valid & update_idx == 9'hF8 | validArray[248],
io_update_valid & update_idx == 9'hF7 | validArray[247],
io_update_valid & update_idx == 9'hF6 | validArray[246],
io_update_valid & update_idx == 9'hF5 | validArray[245],
io_update_valid & update_idx == 9'hF4 | validArray[244],
io_update_valid & update_idx == 9'hF3 | validArray[243],
io_update_valid & update_idx == 9'hF2 | validArray[242],
io_update_valid & update_idx == 9'hF1 | validArray[241],
io_update_valid & update_idx == 9'hF0 | validArray[240],
io_update_valid & update_idx == 9'hEF | validArray[239],
io_update_valid & update_idx == 9'hEE | validArray[238],
io_update_valid & update_idx == 9'hED | validArray[237],
io_update_valid & update_idx == 9'hEC | validArray[236],
io_update_valid & update_idx == 9'hEB | validArray[235],
io_update_valid & update_idx == 9'hEA | validArray[234],
io_update_valid & update_idx == 9'hE9 | validArray[233],
io_update_valid & update_idx == 9'hE8 | validArray[232],
io_update_valid & update_idx == 9'hE7 | validArray[231],
io_update_valid & update_idx == 9'hE6 | validArray[230],
io_update_valid & update_idx == 9'hE5 | validArray[229],
io_update_valid & update_idx == 9'hE4 | validArray[228],
io_update_valid & update_idx == 9'hE3 | validArray[227],
io_update_valid & update_idx == 9'hE2 | validArray[226],
io_update_valid & update_idx == 9'hE1 | validArray[225],
io_update_valid & update_idx == 9'hE0 | validArray[224],
io_update_valid & update_idx == 9'hDF | validArray[223],
io_update_valid & update_idx == 9'hDE | validArray[222],
io_update_valid & update_idx == 9'hDD | validArray[221],
io_update_valid & update_idx == 9'hDC | validArray[220],
io_update_valid & update_idx == 9'hDB | validArray[219],
io_update_valid & update_idx == 9'hDA | validArray[218],
io_update_valid & update_idx == 9'hD9 | validArray[217],
io_update_valid & update_idx == 9'hD8 | validArray[216],
io_update_valid & update_idx == 9'hD7 | validArray[215],
io_update_valid & update_idx == 9'hD6 | validArray[214],
io_update_valid & update_idx == 9'hD5 | validArray[213],
io_update_valid & update_idx == 9'hD4 | validArray[212],
io_update_valid & update_idx == 9'hD3 | validArray[211],
io_update_valid & update_idx == 9'hD2 | validArray[210],
io_update_valid & update_idx == 9'hD1 | validArray[209],
io_update_valid & update_idx == 9'hD0 | validArray[208],
io_update_valid & update_idx == 9'hCF | validArray[207],
io_update_valid & update_idx == 9'hCE | validArray[206],
io_update_valid & update_idx == 9'hCD | validArray[205],
io_update_valid & update_idx == 9'hCC | validArray[204],
io_update_valid & update_idx == 9'hCB | validArray[203],
io_update_valid & update_idx == 9'hCA | validArray[202],
io_update_valid & update_idx == 9'hC9 | validArray[201],
io_update_valid & update_idx == 9'hC8 | validArray[200],
io_update_valid & update_idx == 9'hC7 | validArray[199],
io_update_valid & update_idx == 9'hC6 | validArray[198],
io_update_valid & update_idx == 9'hC5 | validArray[197],
io_update_valid & update_idx == 9'hC4 | validArray[196],
io_update_valid & update_idx == 9'hC3 | validArray[195],
io_update_valid & update_idx == 9'hC2 | validArray[194],
io_update_valid & update_idx == 9'hC1 | validArray[193],
io_update_valid & update_idx == 9'hC0 | validArray[192],
io_update_valid & update_idx == 9'hBF | validArray[191],
io_update_valid & update_idx == 9'hBE | validArray[190],
io_update_valid & update_idx == 9'hBD | validArray[189],
io_update_valid & update_idx == 9'hBC | validArray[188],
io_update_valid & update_idx == 9'hBB | validArray[187],
io_update_valid & update_idx == 9'hBA | validArray[186],
io_update_valid & update_idx == 9'hB9 | validArray[185],
io_update_valid & update_idx == 9'hB8 | validArray[184],
io_update_valid & update_idx == 9'hB7 | validArray[183],
io_update_valid & update_idx == 9'hB6 | validArray[182],
io_update_valid & update_idx == 9'hB5 | validArray[181],
io_update_valid & update_idx == 9'hB4 | validArray[180],
io_update_valid & update_idx == 9'hB3 | validArray[179],
io_update_valid & update_idx == 9'hB2 | validArray[178],
io_update_valid & update_idx == 9'hB1 | validArray[177],
io_update_valid & update_idx == 9'hB0 | validArray[176],
io_update_valid & update_idx == 9'hAF | validArray[175],
io_update_valid & update_idx == 9'hAE | validArray[174],
io_update_valid & update_idx == 9'hAD | validArray[173],
io_update_valid & update_idx == 9'hAC | validArray[172],
io_update_valid & update_idx == 9'hAB | validArray[171],
io_update_valid & update_idx == 9'hAA | validArray[170],
io_update_valid & update_idx == 9'hA9 | validArray[169],
io_update_valid & update_idx == 9'hA8 | validArray[168],
io_update_valid & update_idx == 9'hA7 | validArray[167],
io_update_valid & update_idx == 9'hA6 | validArray[166],
io_update_valid & update_idx == 9'hA5 | validArray[165],
io_update_valid & update_idx == 9'hA4 | validArray[164],
io_update_valid & update_idx == 9'hA3 | validArray[163],
io_update_valid & update_idx == 9'hA2 | validArray[162],
io_update_valid & update_idx == 9'hA1 | validArray[161],
io_update_valid & update_idx == 9'hA0 | validArray[160],
io_update_valid & update_idx == 9'h9F | validArray[159],
io_update_valid & update_idx == 9'h9E | validArray[158],
io_update_valid & update_idx == 9'h9D | validArray[157],
io_update_valid & update_idx == 9'h9C | validArray[156],
io_update_valid & update_idx == 9'h9B | validArray[155],
io_update_valid & update_idx == 9'h9A | validArray[154],
io_update_valid & update_idx == 9'h99 | validArray[153],
io_update_valid & update_idx == 9'h98 | validArray[152],
io_update_valid & update_idx == 9'h97 | validArray[151],
io_update_valid & update_idx == 9'h96 | validArray[150],
io_update_valid & update_idx == 9'h95 | validArray[149],
io_update_valid & update_idx == 9'h94 | validArray[148],
io_update_valid & update_idx == 9'h93 | validArray[147],
io_update_valid & update_idx == 9'h92 | validArray[146],
io_update_valid & update_idx == 9'h91 | validArray[145],
io_update_valid & update_idx == 9'h90 | validArray[144],
io_update_valid & update_idx == 9'h8F | validArray[143],
io_update_valid & update_idx == 9'h8E | validArray[142],
io_update_valid & update_idx == 9'h8D | validArray[141],
io_update_valid & update_idx == 9'h8C | validArray[140],
io_update_valid & update_idx == 9'h8B | validArray[139],
io_update_valid & update_idx == 9'h8A | validArray[138],
io_update_valid & update_idx == 9'h89 | validArray[137],
io_update_valid & update_idx == 9'h88 | validArray[136],
io_update_valid & update_idx == 9'h87 | validArray[135],
io_update_valid & update_idx == 9'h86 | validArray[134],
io_update_valid & update_idx == 9'h85 | validArray[133],
io_update_valid & update_idx == 9'h84 | validArray[132],
io_update_valid & update_idx == 9'h83 | validArray[131],
io_update_valid & update_idx == 9'h82 | validArray[130],
io_update_valid & update_idx == 9'h81 | validArray[129],
io_update_valid & update_idx == 9'h80 | validArray[128],
io_update_valid & update_idx == 9'h7F | validArray[127],
io_update_valid & update_idx == 9'h7E | validArray[126],
io_update_valid & update_idx == 9'h7D | validArray[125],
io_update_valid & update_idx == 9'h7C | validArray[124],
io_update_valid & update_idx == 9'h7B | validArray[123],
io_update_valid & update_idx == 9'h7A | validArray[122],
io_update_valid & update_idx == 9'h79 | validArray[121],
io_update_valid & update_idx == 9'h78 | validArray[120],
io_update_valid & update_idx == 9'h77 | validArray[119],
io_update_valid & update_idx == 9'h76 | validArray[118],
io_update_valid & update_idx == 9'h75 | validArray[117],
io_update_valid & update_idx == 9'h74 | validArray[116],
io_update_valid & update_idx == 9'h73 | validArray[115],
io_update_valid & update_idx == 9'h72 | validArray[114],
io_update_valid & update_idx == 9'h71 | validArray[113],
io_update_valid & update_idx == 9'h70 | validArray[112],
io_update_valid & update_idx == 9'h6F | validArray[111],
io_update_valid & update_idx == 9'h6E | validArray[110],
io_update_valid & update_idx == 9'h6D | validArray[109],
io_update_valid & update_idx == 9'h6C | validArray[108],
io_update_valid & update_idx == 9'h6B | validArray[107],
io_update_valid & update_idx == 9'h6A | validArray[106],
io_update_valid & update_idx == 9'h69 | validArray[105],
io_update_valid & update_idx == 9'h68 | validArray[104],
io_update_valid & update_idx == 9'h67 | validArray[103],
io_update_valid & update_idx == 9'h66 | validArray[102],
io_update_valid & update_idx == 9'h65 | validArray[101],
io_update_valid & update_idx == 9'h64 | validArray[100],
io_update_valid & update_idx == 9'h63 | validArray[99],
io_update_valid & update_idx == 9'h62 | validArray[98],
io_update_valid & update_idx == 9'h61 | validArray[97],
io_update_valid & update_idx == 9'h60 | validArray[96],
io_update_valid & update_idx == 9'h5F | validArray[95],
io_update_valid & update_idx == 9'h5E | validArray[94],
io_update_valid & update_idx == 9'h5D | validArray[93],
io_update_valid & update_idx == 9'h5C | validArray[92],
io_update_valid & update_idx == 9'h5B | validArray[91],
io_update_valid & update_idx == 9'h5A | validArray[90],
io_update_valid & update_idx == 9'h59 | validArray[89],
io_update_valid & update_idx == 9'h58 | validArray[88],
io_update_valid & update_idx == 9'h57 | validArray[87],
io_update_valid & update_idx == 9'h56 | validArray[86],
io_update_valid & update_idx == 9'h55 | validArray[85],
io_update_valid & update_idx == 9'h54 | validArray[84],
io_update_valid & update_idx == 9'h53 | validArray[83],
io_update_valid & update_idx == 9'h52 | validArray[82],
io_update_valid & update_idx == 9'h51 | validArray[81],
io_update_valid & update_idx == 9'h50 | validArray[80],
io_update_valid & update_idx == 9'h4F | validArray[79],
io_update_valid & update_idx == 9'h4E | validArray[78],
io_update_valid & update_idx == 9'h4D | validArray[77],
io_update_valid & update_idx == 9'h4C | validArray[76],
io_update_valid & update_idx == 9'h4B | validArray[75],
io_update_valid & update_idx == 9'h4A | validArray[74],
io_update_valid & update_idx == 9'h49 | validArray[73],
io_update_valid & update_idx == 9'h48 | validArray[72],
io_update_valid & update_idx == 9'h47 | validArray[71],
io_update_valid & update_idx == 9'h46 | validArray[70],
io_update_valid & update_idx == 9'h45 | validArray[69],
io_update_valid & update_idx == 9'h44 | validArray[68],
io_update_valid & update_idx == 9'h43 | validArray[67],
io_update_valid & update_idx == 9'h42 | validArray[66],
io_update_valid & update_idx == 9'h41 | validArray[65],
io_update_valid & update_idx == 9'h40 | validArray[64],
io_update_valid & update_idx == 9'h3F | validArray[63],
io_update_valid & update_idx == 9'h3E | validArray[62],
io_update_valid & update_idx == 9'h3D | validArray[61],
io_update_valid & update_idx == 9'h3C | validArray[60],
io_update_valid & update_idx == 9'h3B | validArray[59],
io_update_valid & update_idx == 9'h3A | validArray[58],
io_update_valid & update_idx == 9'h39 | validArray[57],
io_update_valid & update_idx == 9'h38 | validArray[56],
io_update_valid & update_idx == 9'h37 | validArray[55],
io_update_valid & update_idx == 9'h36 | validArray[54],
io_update_valid & update_idx == 9'h35 | validArray[53],
io_update_valid & update_idx == 9'h34 | validArray[52],
io_update_valid & update_idx == 9'h33 | validArray[51],
io_update_valid & update_idx == 9'h32 | validArray[50],
io_update_valid & update_idx == 9'h31 | validArray[49],
io_update_valid & update_idx == 9'h30 | validArray[48],
io_update_valid & update_idx == 9'h2F | validArray[47],
io_update_valid & update_idx == 9'h2E | validArray[46],
io_update_valid & update_idx == 9'h2D | validArray[45],
io_update_valid & update_idx == 9'h2C | validArray[44],
io_update_valid & update_idx == 9'h2B | validArray[43],
io_update_valid & update_idx == 9'h2A | validArray[42],
io_update_valid & update_idx == 9'h29 | validArray[41],
io_update_valid & update_idx == 9'h28 | validArray[40],
io_update_valid & update_idx == 9'h27 | validArray[39],
io_update_valid & update_idx == 9'h26 | validArray[38],
io_update_valid & update_idx == 9'h25 | validArray[37],
io_update_valid & update_idx == 9'h24 | validArray[36],
io_update_valid & update_idx == 9'h23 | validArray[35],
io_update_valid & update_idx == 9'h22 | validArray[34],
io_update_valid & update_idx == 9'h21 | validArray[33],
io_update_valid & update_idx == 9'h20 | validArray[32],
io_update_valid & update_idx == 9'h1F | validArray[31],
io_update_valid & update_idx == 9'h1E | validArray[30],
io_update_valid & update_idx == 9'h1D | validArray[29],
io_update_valid & update_idx == 9'h1C | validArray[28],
io_update_valid & update_idx == 9'h1B | validArray[27],
io_update_valid & update_idx == 9'h1A | validArray[26],
io_update_valid & update_idx == 9'h19 | validArray[25],
io_update_valid & update_idx == 9'h18 | validArray[24],
io_update_valid & update_idx == 9'h17 | validArray[23],
io_update_valid & update_idx == 9'h16 | validArray[22],
io_update_valid & update_idx == 9'h15 | validArray[21],
io_update_valid & update_idx == 9'h14 | validArray[20],
io_update_valid & update_idx == 9'h13 | validArray[19],
io_update_valid & update_idx == 9'h12 | validArray[18],
io_update_valid & update_idx == 9'h11 | validArray[17],
io_update_valid & update_idx == 9'h10 | validArray[16],
io_update_valid & update_idx == 9'hF | validArray[15],
io_update_valid & update_idx == 9'hE | validArray[14],
io_update_valid & update_idx == 9'hD | validArray[13],
io_update_valid & update_idx == 9'hC | validArray[12],
io_update_valid & update_idx == 9'hB | validArray[11],
io_update_valid & update_idx == 9'hA | validArray[10],
io_update_valid & update_idx == 9'h9 | validArray[9],
io_update_valid & update_idx == 9'h8 | validArray[8],
io_update_valid & update_idx == 9'h7 | validArray[7],
io_update_valid & update_idx == 9'h6 | validArray[6],
io_update_valid & update_idx == 9'h5 | validArray[5],
io_update_valid & update_idx == 9'h4 | validArray[4],
io_update_valid & update_idx == 9'h3 | validArray[3],
io_update_valid & update_idx == 9'h2 | validArray[2],
io_update_valid & update_idx == 9'h1 | validArray[1],
io_update_valid & update_idx == 9'h0 | validArray[0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :200:27, :283:{30,42}, :284:26, :285:31, :286:33
always @(posedge clock or posedge reset) begin
if (reset)
validArray <= 512'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27
else if (io_update_valid) // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
validArray <= _validArray_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :286:33
end // always @(posedge, posedge)
always @(posedge clock) begin
if (io_req_valid) begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
s1_idx <= s0_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :213:36
s1_tag <=
io_req_bits_pc[18:10] ^ io_req_bits_folded_hist_hist_13_folded_hist
^ {io_req_bits_folded_hist_hist_4_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75}, :207:43, :213:68
s1_bank_req_1h_0 <= ~(s0_idx[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :215:33
s1_bank_req_1h_1 <= s0_idx[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :215:33
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:16]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
initial begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
for (logic [4:0] i = 5'h0; i < 5'h11; i += 5'h1) begin
_RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
end // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
validArray =
{_RANDOM[5'h0],
_RANDOM[5'h1],
_RANDOM[5'h2],
_RANDOM[5'h3],
_RANDOM[5'h4],
_RANDOM[5'h5],
_RANDOM[5'h6],
_RANDOM[5'h7],
_RANDOM[5'h8],
_RANDOM[5'h9],
_RANDOM[5'hA],
_RANDOM[5'hB],
_RANDOM[5'hC],
_RANDOM[5'hD],
_RANDOM[5'hE],
_RANDOM[5'hF]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :200:27
s1_idx = _RANDOM[5'h10][8:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36
s1_tag = _RANDOM[5'h10][17:9]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:{36,68}
s1_bank_req_1h_0 = _RANDOM[5'h10][18]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33
s1_bank_req_1h_1 = _RANDOM[5'h10][19]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33
s1_bank_has_write_on_this_req_0 = _RANDOM[5'h10][20]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48
s1_bank_has_write_on_this_req_1 = _RANDOM[5'h10][21]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48
`endif // RANDOMIZE_REG_INIT
if (reset) // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
validArray = 512'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
Folded1WDataModuleTemplate_2 us ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18
.clock (clock),
.reset (reset),
.io_raddr_0 (s0_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31
.io_rdata_0 (_us_io_rdata_0),
.io_wen (io_update_uValid),
.io_waddr (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31
.io_wdata (io_update_u),
.io_resetEn (io_update_reset_u)
);
FoldedSRAMTemplate_25 table_banks_0 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & ~(s0_idx[0])), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :223:50
.io_r_req_bits_setIdx (s0_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33
.io_w_req_bits_setIdx (update_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}
.io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61
.io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28
.io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29
);
FoldedSRAMTemplate_25 table_banks_1 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & s0_idx[0]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :223:50
.io_r_req_bits_setIdx (s0_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33
.io_w_req_bits_setIdx (update_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}
.io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61
.io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28
.io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29
);
WrBypass_43 wrbypass ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24
.clock (clock),
.reset (reset),
.io_wen (io_update_valid),
.io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31
.io_write_data_0 (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28
.io_hit (_wrbypass_io_hit),
.io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits)
);
assign io_resp_valid =
_s1_req_rhit_T[0]
& ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag
& ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:68, :215:33, :220:11, :232:{31,61}, :235:{50,53}, :285:31
assign io_resp_bits_ctr =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11
assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :160:86, :217:18, :237:18
assign io_resp_bits_target =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 39'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11
endmodule

761
src/ITTAGE/ITTageTable_3.sv Normal file
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@ -0,0 +1,761 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module ITTageTable_3( // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
input clock,
input reset,
input io_req_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [8:0] io_req_bits_folded_hist_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [7:0] io_req_bits_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
output io_resp_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
output [1:0] io_resp_bits_ctr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
output [1:0] io_resp_bits_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
output [38:0] io_resp_bits_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [8:0] io_update_folded_hist_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [7:0] io_update_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_correct, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_alloc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [1:0] io_update_oldCtr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_uValid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_reset_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [38:0] io_update_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [38:0] io_update_old_target // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
);
wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73
wire _wrbypass_io_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24
wire [1:0] _wrbypass_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24
wire [8:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [38:0] _table_banks_1_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [8:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [38:0] _table_banks_0_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire _us_io_rdata_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18
reg [511:0] validArray; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27
wire [8:0] s0_idx = io_req_bits_pc[9:1] ^ io_req_bits_folded_hist_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43
reg [8:0] s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:36
reg [8:0] s1_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:68
reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33
reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33
wire [511:0] _s1_req_rhit_T = validArray >> s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :213:36, :232:31
reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48
reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48
wire [8:0] update_idx = io_update_pc[9:1] ^ io_update_folded_hist_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43
wire [8:0] update_wdata_tag =
io_update_pc[18:10] ^ io_update_folded_hist_hist_6_folded_hist
^ {io_update_folded_hist_hist_2_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75}, :207:43
assign _resp_invalid_by_write_WIRE =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33, :240:48
wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :255:33
wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :255:33
wire [1:0] old_ctr =
_wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24, :277:20
wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20
wire [1:0] update_wdata_ctr =
io_update_alloc
? 2'h2
: (&old_ctr) & io_update_correct
? 2'h3
: update_wdata_ctr_oldSatNotTaken & ~io_update_correct
? 2'h0
: io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20, :278:28
wire [38:0] update_wdata_target =
io_update_alloc | update_wdata_ctr_oldSatNotTaken
? io_update_target
: io_update_old_target; // src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:281:{29,46}
wire [511:0] _validArray_T =
{io_update_valid & (&update_idx) | validArray[511],
io_update_valid & update_idx == 9'h1FE | validArray[510],
io_update_valid & update_idx == 9'h1FD | validArray[509],
io_update_valid & update_idx == 9'h1FC | validArray[508],
io_update_valid & update_idx == 9'h1FB | validArray[507],
io_update_valid & update_idx == 9'h1FA | validArray[506],
io_update_valid & update_idx == 9'h1F9 | validArray[505],
io_update_valid & update_idx == 9'h1F8 | validArray[504],
io_update_valid & update_idx == 9'h1F7 | validArray[503],
io_update_valid & update_idx == 9'h1F6 | validArray[502],
io_update_valid & update_idx == 9'h1F5 | validArray[501],
io_update_valid & update_idx == 9'h1F4 | validArray[500],
io_update_valid & update_idx == 9'h1F3 | validArray[499],
io_update_valid & update_idx == 9'h1F2 | validArray[498],
io_update_valid & update_idx == 9'h1F1 | validArray[497],
io_update_valid & update_idx == 9'h1F0 | validArray[496],
io_update_valid & update_idx == 9'h1EF | validArray[495],
io_update_valid & update_idx == 9'h1EE | validArray[494],
io_update_valid & update_idx == 9'h1ED | validArray[493],
io_update_valid & update_idx == 9'h1EC | validArray[492],
io_update_valid & update_idx == 9'h1EB | validArray[491],
io_update_valid & update_idx == 9'h1EA | validArray[490],
io_update_valid & update_idx == 9'h1E9 | validArray[489],
io_update_valid & update_idx == 9'h1E8 | validArray[488],
io_update_valid & update_idx == 9'h1E7 | validArray[487],
io_update_valid & update_idx == 9'h1E6 | validArray[486],
io_update_valid & update_idx == 9'h1E5 | validArray[485],
io_update_valid & update_idx == 9'h1E4 | validArray[484],
io_update_valid & update_idx == 9'h1E3 | validArray[483],
io_update_valid & update_idx == 9'h1E2 | validArray[482],
io_update_valid & update_idx == 9'h1E1 | validArray[481],
io_update_valid & update_idx == 9'h1E0 | validArray[480],
io_update_valid & update_idx == 9'h1DF | validArray[479],
io_update_valid & update_idx == 9'h1DE | validArray[478],
io_update_valid & update_idx == 9'h1DD | validArray[477],
io_update_valid & update_idx == 9'h1DC | validArray[476],
io_update_valid & update_idx == 9'h1DB | validArray[475],
io_update_valid & update_idx == 9'h1DA | validArray[474],
io_update_valid & update_idx == 9'h1D9 | validArray[473],
io_update_valid & update_idx == 9'h1D8 | validArray[472],
io_update_valid & update_idx == 9'h1D7 | validArray[471],
io_update_valid & update_idx == 9'h1D6 | validArray[470],
io_update_valid & update_idx == 9'h1D5 | validArray[469],
io_update_valid & update_idx == 9'h1D4 | validArray[468],
io_update_valid & update_idx == 9'h1D3 | validArray[467],
io_update_valid & update_idx == 9'h1D2 | validArray[466],
io_update_valid & update_idx == 9'h1D1 | validArray[465],
io_update_valid & update_idx == 9'h1D0 | validArray[464],
io_update_valid & update_idx == 9'h1CF | validArray[463],
io_update_valid & update_idx == 9'h1CE | validArray[462],
io_update_valid & update_idx == 9'h1CD | validArray[461],
io_update_valid & update_idx == 9'h1CC | validArray[460],
io_update_valid & update_idx == 9'h1CB | validArray[459],
io_update_valid & update_idx == 9'h1CA | validArray[458],
io_update_valid & update_idx == 9'h1C9 | validArray[457],
io_update_valid & update_idx == 9'h1C8 | validArray[456],
io_update_valid & update_idx == 9'h1C7 | validArray[455],
io_update_valid & update_idx == 9'h1C6 | validArray[454],
io_update_valid & update_idx == 9'h1C5 | validArray[453],
io_update_valid & update_idx == 9'h1C4 | validArray[452],
io_update_valid & update_idx == 9'h1C3 | validArray[451],
io_update_valid & update_idx == 9'h1C2 | validArray[450],
io_update_valid & update_idx == 9'h1C1 | validArray[449],
io_update_valid & update_idx == 9'h1C0 | validArray[448],
io_update_valid & update_idx == 9'h1BF | validArray[447],
io_update_valid & update_idx == 9'h1BE | validArray[446],
io_update_valid & update_idx == 9'h1BD | validArray[445],
io_update_valid & update_idx == 9'h1BC | validArray[444],
io_update_valid & update_idx == 9'h1BB | validArray[443],
io_update_valid & update_idx == 9'h1BA | validArray[442],
io_update_valid & update_idx == 9'h1B9 | validArray[441],
io_update_valid & update_idx == 9'h1B8 | validArray[440],
io_update_valid & update_idx == 9'h1B7 | validArray[439],
io_update_valid & update_idx == 9'h1B6 | validArray[438],
io_update_valid & update_idx == 9'h1B5 | validArray[437],
io_update_valid & update_idx == 9'h1B4 | validArray[436],
io_update_valid & update_idx == 9'h1B3 | validArray[435],
io_update_valid & update_idx == 9'h1B2 | validArray[434],
io_update_valid & update_idx == 9'h1B1 | validArray[433],
io_update_valid & update_idx == 9'h1B0 | validArray[432],
io_update_valid & update_idx == 9'h1AF | validArray[431],
io_update_valid & update_idx == 9'h1AE | validArray[430],
io_update_valid & update_idx == 9'h1AD | validArray[429],
io_update_valid & update_idx == 9'h1AC | validArray[428],
io_update_valid & update_idx == 9'h1AB | validArray[427],
io_update_valid & update_idx == 9'h1AA | validArray[426],
io_update_valid & update_idx == 9'h1A9 | validArray[425],
io_update_valid & update_idx == 9'h1A8 | validArray[424],
io_update_valid & update_idx == 9'h1A7 | validArray[423],
io_update_valid & update_idx == 9'h1A6 | validArray[422],
io_update_valid & update_idx == 9'h1A5 | validArray[421],
io_update_valid & update_idx == 9'h1A4 | validArray[420],
io_update_valid & update_idx == 9'h1A3 | validArray[419],
io_update_valid & update_idx == 9'h1A2 | validArray[418],
io_update_valid & update_idx == 9'h1A1 | validArray[417],
io_update_valid & update_idx == 9'h1A0 | validArray[416],
io_update_valid & update_idx == 9'h19F | validArray[415],
io_update_valid & update_idx == 9'h19E | validArray[414],
io_update_valid & update_idx == 9'h19D | validArray[413],
io_update_valid & update_idx == 9'h19C | validArray[412],
io_update_valid & update_idx == 9'h19B | validArray[411],
io_update_valid & update_idx == 9'h19A | validArray[410],
io_update_valid & update_idx == 9'h199 | validArray[409],
io_update_valid & update_idx == 9'h198 | validArray[408],
io_update_valid & update_idx == 9'h197 | validArray[407],
io_update_valid & update_idx == 9'h196 | validArray[406],
io_update_valid & update_idx == 9'h195 | validArray[405],
io_update_valid & update_idx == 9'h194 | validArray[404],
io_update_valid & update_idx == 9'h193 | validArray[403],
io_update_valid & update_idx == 9'h192 | validArray[402],
io_update_valid & update_idx == 9'h191 | validArray[401],
io_update_valid & update_idx == 9'h190 | validArray[400],
io_update_valid & update_idx == 9'h18F | validArray[399],
io_update_valid & update_idx == 9'h18E | validArray[398],
io_update_valid & update_idx == 9'h18D | validArray[397],
io_update_valid & update_idx == 9'h18C | validArray[396],
io_update_valid & update_idx == 9'h18B | validArray[395],
io_update_valid & update_idx == 9'h18A | validArray[394],
io_update_valid & update_idx == 9'h189 | validArray[393],
io_update_valid & update_idx == 9'h188 | validArray[392],
io_update_valid & update_idx == 9'h187 | validArray[391],
io_update_valid & update_idx == 9'h186 | validArray[390],
io_update_valid & update_idx == 9'h185 | validArray[389],
io_update_valid & update_idx == 9'h184 | validArray[388],
io_update_valid & update_idx == 9'h183 | validArray[387],
io_update_valid & update_idx == 9'h182 | validArray[386],
io_update_valid & update_idx == 9'h181 | validArray[385],
io_update_valid & update_idx == 9'h180 | validArray[384],
io_update_valid & update_idx == 9'h17F | validArray[383],
io_update_valid & update_idx == 9'h17E | validArray[382],
io_update_valid & update_idx == 9'h17D | validArray[381],
io_update_valid & update_idx == 9'h17C | validArray[380],
io_update_valid & update_idx == 9'h17B | validArray[379],
io_update_valid & update_idx == 9'h17A | validArray[378],
io_update_valid & update_idx == 9'h179 | validArray[377],
io_update_valid & update_idx == 9'h178 | validArray[376],
io_update_valid & update_idx == 9'h177 | validArray[375],
io_update_valid & update_idx == 9'h176 | validArray[374],
io_update_valid & update_idx == 9'h175 | validArray[373],
io_update_valid & update_idx == 9'h174 | validArray[372],
io_update_valid & update_idx == 9'h173 | validArray[371],
io_update_valid & update_idx == 9'h172 | validArray[370],
io_update_valid & update_idx == 9'h171 | validArray[369],
io_update_valid & update_idx == 9'h170 | validArray[368],
io_update_valid & update_idx == 9'h16F | validArray[367],
io_update_valid & update_idx == 9'h16E | validArray[366],
io_update_valid & update_idx == 9'h16D | validArray[365],
io_update_valid & update_idx == 9'h16C | validArray[364],
io_update_valid & update_idx == 9'h16B | validArray[363],
io_update_valid & update_idx == 9'h16A | validArray[362],
io_update_valid & update_idx == 9'h169 | validArray[361],
io_update_valid & update_idx == 9'h168 | validArray[360],
io_update_valid & update_idx == 9'h167 | validArray[359],
io_update_valid & update_idx == 9'h166 | validArray[358],
io_update_valid & update_idx == 9'h165 | validArray[357],
io_update_valid & update_idx == 9'h164 | validArray[356],
io_update_valid & update_idx == 9'h163 | validArray[355],
io_update_valid & update_idx == 9'h162 | validArray[354],
io_update_valid & update_idx == 9'h161 | validArray[353],
io_update_valid & update_idx == 9'h160 | validArray[352],
io_update_valid & update_idx == 9'h15F | validArray[351],
io_update_valid & update_idx == 9'h15E | validArray[350],
io_update_valid & update_idx == 9'h15D | validArray[349],
io_update_valid & update_idx == 9'h15C | validArray[348],
io_update_valid & update_idx == 9'h15B | validArray[347],
io_update_valid & update_idx == 9'h15A | validArray[346],
io_update_valid & update_idx == 9'h159 | validArray[345],
io_update_valid & update_idx == 9'h158 | validArray[344],
io_update_valid & update_idx == 9'h157 | validArray[343],
io_update_valid & update_idx == 9'h156 | validArray[342],
io_update_valid & update_idx == 9'h155 | validArray[341],
io_update_valid & update_idx == 9'h154 | validArray[340],
io_update_valid & update_idx == 9'h153 | validArray[339],
io_update_valid & update_idx == 9'h152 | validArray[338],
io_update_valid & update_idx == 9'h151 | validArray[337],
io_update_valid & update_idx == 9'h150 | validArray[336],
io_update_valid & update_idx == 9'h14F | validArray[335],
io_update_valid & update_idx == 9'h14E | validArray[334],
io_update_valid & update_idx == 9'h14D | validArray[333],
io_update_valid & update_idx == 9'h14C | validArray[332],
io_update_valid & update_idx == 9'h14B | validArray[331],
io_update_valid & update_idx == 9'h14A | validArray[330],
io_update_valid & update_idx == 9'h149 | validArray[329],
io_update_valid & update_idx == 9'h148 | validArray[328],
io_update_valid & update_idx == 9'h147 | validArray[327],
io_update_valid & update_idx == 9'h146 | validArray[326],
io_update_valid & update_idx == 9'h145 | validArray[325],
io_update_valid & update_idx == 9'h144 | validArray[324],
io_update_valid & update_idx == 9'h143 | validArray[323],
io_update_valid & update_idx == 9'h142 | validArray[322],
io_update_valid & update_idx == 9'h141 | validArray[321],
io_update_valid & update_idx == 9'h140 | validArray[320],
io_update_valid & update_idx == 9'h13F | validArray[319],
io_update_valid & update_idx == 9'h13E | validArray[318],
io_update_valid & update_idx == 9'h13D | validArray[317],
io_update_valid & update_idx == 9'h13C | validArray[316],
io_update_valid & update_idx == 9'h13B | validArray[315],
io_update_valid & update_idx == 9'h13A | validArray[314],
io_update_valid & update_idx == 9'h139 | validArray[313],
io_update_valid & update_idx == 9'h138 | validArray[312],
io_update_valid & update_idx == 9'h137 | validArray[311],
io_update_valid & update_idx == 9'h136 | validArray[310],
io_update_valid & update_idx == 9'h135 | validArray[309],
io_update_valid & update_idx == 9'h134 | validArray[308],
io_update_valid & update_idx == 9'h133 | validArray[307],
io_update_valid & update_idx == 9'h132 | validArray[306],
io_update_valid & update_idx == 9'h131 | validArray[305],
io_update_valid & update_idx == 9'h130 | validArray[304],
io_update_valid & update_idx == 9'h12F | validArray[303],
io_update_valid & update_idx == 9'h12E | validArray[302],
io_update_valid & update_idx == 9'h12D | validArray[301],
io_update_valid & update_idx == 9'h12C | validArray[300],
io_update_valid & update_idx == 9'h12B | validArray[299],
io_update_valid & update_idx == 9'h12A | validArray[298],
io_update_valid & update_idx == 9'h129 | validArray[297],
io_update_valid & update_idx == 9'h128 | validArray[296],
io_update_valid & update_idx == 9'h127 | validArray[295],
io_update_valid & update_idx == 9'h126 | validArray[294],
io_update_valid & update_idx == 9'h125 | validArray[293],
io_update_valid & update_idx == 9'h124 | validArray[292],
io_update_valid & update_idx == 9'h123 | validArray[291],
io_update_valid & update_idx == 9'h122 | validArray[290],
io_update_valid & update_idx == 9'h121 | validArray[289],
io_update_valid & update_idx == 9'h120 | validArray[288],
io_update_valid & update_idx == 9'h11F | validArray[287],
io_update_valid & update_idx == 9'h11E | validArray[286],
io_update_valid & update_idx == 9'h11D | validArray[285],
io_update_valid & update_idx == 9'h11C | validArray[284],
io_update_valid & update_idx == 9'h11B | validArray[283],
io_update_valid & update_idx == 9'h11A | validArray[282],
io_update_valid & update_idx == 9'h119 | validArray[281],
io_update_valid & update_idx == 9'h118 | validArray[280],
io_update_valid & update_idx == 9'h117 | validArray[279],
io_update_valid & update_idx == 9'h116 | validArray[278],
io_update_valid & update_idx == 9'h115 | validArray[277],
io_update_valid & update_idx == 9'h114 | validArray[276],
io_update_valid & update_idx == 9'h113 | validArray[275],
io_update_valid & update_idx == 9'h112 | validArray[274],
io_update_valid & update_idx == 9'h111 | validArray[273],
io_update_valid & update_idx == 9'h110 | validArray[272],
io_update_valid & update_idx == 9'h10F | validArray[271],
io_update_valid & update_idx == 9'h10E | validArray[270],
io_update_valid & update_idx == 9'h10D | validArray[269],
io_update_valid & update_idx == 9'h10C | validArray[268],
io_update_valid & update_idx == 9'h10B | validArray[267],
io_update_valid & update_idx == 9'h10A | validArray[266],
io_update_valid & update_idx == 9'h109 | validArray[265],
io_update_valid & update_idx == 9'h108 | validArray[264],
io_update_valid & update_idx == 9'h107 | validArray[263],
io_update_valid & update_idx == 9'h106 | validArray[262],
io_update_valid & update_idx == 9'h105 | validArray[261],
io_update_valid & update_idx == 9'h104 | validArray[260],
io_update_valid & update_idx == 9'h103 | validArray[259],
io_update_valid & update_idx == 9'h102 | validArray[258],
io_update_valid & update_idx == 9'h101 | validArray[257],
io_update_valid & update_idx == 9'h100 | validArray[256],
io_update_valid & update_idx == 9'hFF | validArray[255],
io_update_valid & update_idx == 9'hFE | validArray[254],
io_update_valid & update_idx == 9'hFD | validArray[253],
io_update_valid & update_idx == 9'hFC | validArray[252],
io_update_valid & update_idx == 9'hFB | validArray[251],
io_update_valid & update_idx == 9'hFA | validArray[250],
io_update_valid & update_idx == 9'hF9 | validArray[249],
io_update_valid & update_idx == 9'hF8 | validArray[248],
io_update_valid & update_idx == 9'hF7 | validArray[247],
io_update_valid & update_idx == 9'hF6 | validArray[246],
io_update_valid & update_idx == 9'hF5 | validArray[245],
io_update_valid & update_idx == 9'hF4 | validArray[244],
io_update_valid & update_idx == 9'hF3 | validArray[243],
io_update_valid & update_idx == 9'hF2 | validArray[242],
io_update_valid & update_idx == 9'hF1 | validArray[241],
io_update_valid & update_idx == 9'hF0 | validArray[240],
io_update_valid & update_idx == 9'hEF | validArray[239],
io_update_valid & update_idx == 9'hEE | validArray[238],
io_update_valid & update_idx == 9'hED | validArray[237],
io_update_valid & update_idx == 9'hEC | validArray[236],
io_update_valid & update_idx == 9'hEB | validArray[235],
io_update_valid & update_idx == 9'hEA | validArray[234],
io_update_valid & update_idx == 9'hE9 | validArray[233],
io_update_valid & update_idx == 9'hE8 | validArray[232],
io_update_valid & update_idx == 9'hE7 | validArray[231],
io_update_valid & update_idx == 9'hE6 | validArray[230],
io_update_valid & update_idx == 9'hE5 | validArray[229],
io_update_valid & update_idx == 9'hE4 | validArray[228],
io_update_valid & update_idx == 9'hE3 | validArray[227],
io_update_valid & update_idx == 9'hE2 | validArray[226],
io_update_valid & update_idx == 9'hE1 | validArray[225],
io_update_valid & update_idx == 9'hE0 | validArray[224],
io_update_valid & update_idx == 9'hDF | validArray[223],
io_update_valid & update_idx == 9'hDE | validArray[222],
io_update_valid & update_idx == 9'hDD | validArray[221],
io_update_valid & update_idx == 9'hDC | validArray[220],
io_update_valid & update_idx == 9'hDB | validArray[219],
io_update_valid & update_idx == 9'hDA | validArray[218],
io_update_valid & update_idx == 9'hD9 | validArray[217],
io_update_valid & update_idx == 9'hD8 | validArray[216],
io_update_valid & update_idx == 9'hD7 | validArray[215],
io_update_valid & update_idx == 9'hD6 | validArray[214],
io_update_valid & update_idx == 9'hD5 | validArray[213],
io_update_valid & update_idx == 9'hD4 | validArray[212],
io_update_valid & update_idx == 9'hD3 | validArray[211],
io_update_valid & update_idx == 9'hD2 | validArray[210],
io_update_valid & update_idx == 9'hD1 | validArray[209],
io_update_valid & update_idx == 9'hD0 | validArray[208],
io_update_valid & update_idx == 9'hCF | validArray[207],
io_update_valid & update_idx == 9'hCE | validArray[206],
io_update_valid & update_idx == 9'hCD | validArray[205],
io_update_valid & update_idx == 9'hCC | validArray[204],
io_update_valid & update_idx == 9'hCB | validArray[203],
io_update_valid & update_idx == 9'hCA | validArray[202],
io_update_valid & update_idx == 9'hC9 | validArray[201],
io_update_valid & update_idx == 9'hC8 | validArray[200],
io_update_valid & update_idx == 9'hC7 | validArray[199],
io_update_valid & update_idx == 9'hC6 | validArray[198],
io_update_valid & update_idx == 9'hC5 | validArray[197],
io_update_valid & update_idx == 9'hC4 | validArray[196],
io_update_valid & update_idx == 9'hC3 | validArray[195],
io_update_valid & update_idx == 9'hC2 | validArray[194],
io_update_valid & update_idx == 9'hC1 | validArray[193],
io_update_valid & update_idx == 9'hC0 | validArray[192],
io_update_valid & update_idx == 9'hBF | validArray[191],
io_update_valid & update_idx == 9'hBE | validArray[190],
io_update_valid & update_idx == 9'hBD | validArray[189],
io_update_valid & update_idx == 9'hBC | validArray[188],
io_update_valid & update_idx == 9'hBB | validArray[187],
io_update_valid & update_idx == 9'hBA | validArray[186],
io_update_valid & update_idx == 9'hB9 | validArray[185],
io_update_valid & update_idx == 9'hB8 | validArray[184],
io_update_valid & update_idx == 9'hB7 | validArray[183],
io_update_valid & update_idx == 9'hB6 | validArray[182],
io_update_valid & update_idx == 9'hB5 | validArray[181],
io_update_valid & update_idx == 9'hB4 | validArray[180],
io_update_valid & update_idx == 9'hB3 | validArray[179],
io_update_valid & update_idx == 9'hB2 | validArray[178],
io_update_valid & update_idx == 9'hB1 | validArray[177],
io_update_valid & update_idx == 9'hB0 | validArray[176],
io_update_valid & update_idx == 9'hAF | validArray[175],
io_update_valid & update_idx == 9'hAE | validArray[174],
io_update_valid & update_idx == 9'hAD | validArray[173],
io_update_valid & update_idx == 9'hAC | validArray[172],
io_update_valid & update_idx == 9'hAB | validArray[171],
io_update_valid & update_idx == 9'hAA | validArray[170],
io_update_valid & update_idx == 9'hA9 | validArray[169],
io_update_valid & update_idx == 9'hA8 | validArray[168],
io_update_valid & update_idx == 9'hA7 | validArray[167],
io_update_valid & update_idx == 9'hA6 | validArray[166],
io_update_valid & update_idx == 9'hA5 | validArray[165],
io_update_valid & update_idx == 9'hA4 | validArray[164],
io_update_valid & update_idx == 9'hA3 | validArray[163],
io_update_valid & update_idx == 9'hA2 | validArray[162],
io_update_valid & update_idx == 9'hA1 | validArray[161],
io_update_valid & update_idx == 9'hA0 | validArray[160],
io_update_valid & update_idx == 9'h9F | validArray[159],
io_update_valid & update_idx == 9'h9E | validArray[158],
io_update_valid & update_idx == 9'h9D | validArray[157],
io_update_valid & update_idx == 9'h9C | validArray[156],
io_update_valid & update_idx == 9'h9B | validArray[155],
io_update_valid & update_idx == 9'h9A | validArray[154],
io_update_valid & update_idx == 9'h99 | validArray[153],
io_update_valid & update_idx == 9'h98 | validArray[152],
io_update_valid & update_idx == 9'h97 | validArray[151],
io_update_valid & update_idx == 9'h96 | validArray[150],
io_update_valid & update_idx == 9'h95 | validArray[149],
io_update_valid & update_idx == 9'h94 | validArray[148],
io_update_valid & update_idx == 9'h93 | validArray[147],
io_update_valid & update_idx == 9'h92 | validArray[146],
io_update_valid & update_idx == 9'h91 | validArray[145],
io_update_valid & update_idx == 9'h90 | validArray[144],
io_update_valid & update_idx == 9'h8F | validArray[143],
io_update_valid & update_idx == 9'h8E | validArray[142],
io_update_valid & update_idx == 9'h8D | validArray[141],
io_update_valid & update_idx == 9'h8C | validArray[140],
io_update_valid & update_idx == 9'h8B | validArray[139],
io_update_valid & update_idx == 9'h8A | validArray[138],
io_update_valid & update_idx == 9'h89 | validArray[137],
io_update_valid & update_idx == 9'h88 | validArray[136],
io_update_valid & update_idx == 9'h87 | validArray[135],
io_update_valid & update_idx == 9'h86 | validArray[134],
io_update_valid & update_idx == 9'h85 | validArray[133],
io_update_valid & update_idx == 9'h84 | validArray[132],
io_update_valid & update_idx == 9'h83 | validArray[131],
io_update_valid & update_idx == 9'h82 | validArray[130],
io_update_valid & update_idx == 9'h81 | validArray[129],
io_update_valid & update_idx == 9'h80 | validArray[128],
io_update_valid & update_idx == 9'h7F | validArray[127],
io_update_valid & update_idx == 9'h7E | validArray[126],
io_update_valid & update_idx == 9'h7D | validArray[125],
io_update_valid & update_idx == 9'h7C | validArray[124],
io_update_valid & update_idx == 9'h7B | validArray[123],
io_update_valid & update_idx == 9'h7A | validArray[122],
io_update_valid & update_idx == 9'h79 | validArray[121],
io_update_valid & update_idx == 9'h78 | validArray[120],
io_update_valid & update_idx == 9'h77 | validArray[119],
io_update_valid & update_idx == 9'h76 | validArray[118],
io_update_valid & update_idx == 9'h75 | validArray[117],
io_update_valid & update_idx == 9'h74 | validArray[116],
io_update_valid & update_idx == 9'h73 | validArray[115],
io_update_valid & update_idx == 9'h72 | validArray[114],
io_update_valid & update_idx == 9'h71 | validArray[113],
io_update_valid & update_idx == 9'h70 | validArray[112],
io_update_valid & update_idx == 9'h6F | validArray[111],
io_update_valid & update_idx == 9'h6E | validArray[110],
io_update_valid & update_idx == 9'h6D | validArray[109],
io_update_valid & update_idx == 9'h6C | validArray[108],
io_update_valid & update_idx == 9'h6B | validArray[107],
io_update_valid & update_idx == 9'h6A | validArray[106],
io_update_valid & update_idx == 9'h69 | validArray[105],
io_update_valid & update_idx == 9'h68 | validArray[104],
io_update_valid & update_idx == 9'h67 | validArray[103],
io_update_valid & update_idx == 9'h66 | validArray[102],
io_update_valid & update_idx == 9'h65 | validArray[101],
io_update_valid & update_idx == 9'h64 | validArray[100],
io_update_valid & update_idx == 9'h63 | validArray[99],
io_update_valid & update_idx == 9'h62 | validArray[98],
io_update_valid & update_idx == 9'h61 | validArray[97],
io_update_valid & update_idx == 9'h60 | validArray[96],
io_update_valid & update_idx == 9'h5F | validArray[95],
io_update_valid & update_idx == 9'h5E | validArray[94],
io_update_valid & update_idx == 9'h5D | validArray[93],
io_update_valid & update_idx == 9'h5C | validArray[92],
io_update_valid & update_idx == 9'h5B | validArray[91],
io_update_valid & update_idx == 9'h5A | validArray[90],
io_update_valid & update_idx == 9'h59 | validArray[89],
io_update_valid & update_idx == 9'h58 | validArray[88],
io_update_valid & update_idx == 9'h57 | validArray[87],
io_update_valid & update_idx == 9'h56 | validArray[86],
io_update_valid & update_idx == 9'h55 | validArray[85],
io_update_valid & update_idx == 9'h54 | validArray[84],
io_update_valid & update_idx == 9'h53 | validArray[83],
io_update_valid & update_idx == 9'h52 | validArray[82],
io_update_valid & update_idx == 9'h51 | validArray[81],
io_update_valid & update_idx == 9'h50 | validArray[80],
io_update_valid & update_idx == 9'h4F | validArray[79],
io_update_valid & update_idx == 9'h4E | validArray[78],
io_update_valid & update_idx == 9'h4D | validArray[77],
io_update_valid & update_idx == 9'h4C | validArray[76],
io_update_valid & update_idx == 9'h4B | validArray[75],
io_update_valid & update_idx == 9'h4A | validArray[74],
io_update_valid & update_idx == 9'h49 | validArray[73],
io_update_valid & update_idx == 9'h48 | validArray[72],
io_update_valid & update_idx == 9'h47 | validArray[71],
io_update_valid & update_idx == 9'h46 | validArray[70],
io_update_valid & update_idx == 9'h45 | validArray[69],
io_update_valid & update_idx == 9'h44 | validArray[68],
io_update_valid & update_idx == 9'h43 | validArray[67],
io_update_valid & update_idx == 9'h42 | validArray[66],
io_update_valid & update_idx == 9'h41 | validArray[65],
io_update_valid & update_idx == 9'h40 | validArray[64],
io_update_valid & update_idx == 9'h3F | validArray[63],
io_update_valid & update_idx == 9'h3E | validArray[62],
io_update_valid & update_idx == 9'h3D | validArray[61],
io_update_valid & update_idx == 9'h3C | validArray[60],
io_update_valid & update_idx == 9'h3B | validArray[59],
io_update_valid & update_idx == 9'h3A | validArray[58],
io_update_valid & update_idx == 9'h39 | validArray[57],
io_update_valid & update_idx == 9'h38 | validArray[56],
io_update_valid & update_idx == 9'h37 | validArray[55],
io_update_valid & update_idx == 9'h36 | validArray[54],
io_update_valid & update_idx == 9'h35 | validArray[53],
io_update_valid & update_idx == 9'h34 | validArray[52],
io_update_valid & update_idx == 9'h33 | validArray[51],
io_update_valid & update_idx == 9'h32 | validArray[50],
io_update_valid & update_idx == 9'h31 | validArray[49],
io_update_valid & update_idx == 9'h30 | validArray[48],
io_update_valid & update_idx == 9'h2F | validArray[47],
io_update_valid & update_idx == 9'h2E | validArray[46],
io_update_valid & update_idx == 9'h2D | validArray[45],
io_update_valid & update_idx == 9'h2C | validArray[44],
io_update_valid & update_idx == 9'h2B | validArray[43],
io_update_valid & update_idx == 9'h2A | validArray[42],
io_update_valid & update_idx == 9'h29 | validArray[41],
io_update_valid & update_idx == 9'h28 | validArray[40],
io_update_valid & update_idx == 9'h27 | validArray[39],
io_update_valid & update_idx == 9'h26 | validArray[38],
io_update_valid & update_idx == 9'h25 | validArray[37],
io_update_valid & update_idx == 9'h24 | validArray[36],
io_update_valid & update_idx == 9'h23 | validArray[35],
io_update_valid & update_idx == 9'h22 | validArray[34],
io_update_valid & update_idx == 9'h21 | validArray[33],
io_update_valid & update_idx == 9'h20 | validArray[32],
io_update_valid & update_idx == 9'h1F | validArray[31],
io_update_valid & update_idx == 9'h1E | validArray[30],
io_update_valid & update_idx == 9'h1D | validArray[29],
io_update_valid & update_idx == 9'h1C | validArray[28],
io_update_valid & update_idx == 9'h1B | validArray[27],
io_update_valid & update_idx == 9'h1A | validArray[26],
io_update_valid & update_idx == 9'h19 | validArray[25],
io_update_valid & update_idx == 9'h18 | validArray[24],
io_update_valid & update_idx == 9'h17 | validArray[23],
io_update_valid & update_idx == 9'h16 | validArray[22],
io_update_valid & update_idx == 9'h15 | validArray[21],
io_update_valid & update_idx == 9'h14 | validArray[20],
io_update_valid & update_idx == 9'h13 | validArray[19],
io_update_valid & update_idx == 9'h12 | validArray[18],
io_update_valid & update_idx == 9'h11 | validArray[17],
io_update_valid & update_idx == 9'h10 | validArray[16],
io_update_valid & update_idx == 9'hF | validArray[15],
io_update_valid & update_idx == 9'hE | validArray[14],
io_update_valid & update_idx == 9'hD | validArray[13],
io_update_valid & update_idx == 9'hC | validArray[12],
io_update_valid & update_idx == 9'hB | validArray[11],
io_update_valid & update_idx == 9'hA | validArray[10],
io_update_valid & update_idx == 9'h9 | validArray[9],
io_update_valid & update_idx == 9'h8 | validArray[8],
io_update_valid & update_idx == 9'h7 | validArray[7],
io_update_valid & update_idx == 9'h6 | validArray[6],
io_update_valid & update_idx == 9'h5 | validArray[5],
io_update_valid & update_idx == 9'h4 | validArray[4],
io_update_valid & update_idx == 9'h3 | validArray[3],
io_update_valid & update_idx == 9'h2 | validArray[2],
io_update_valid & update_idx == 9'h1 | validArray[1],
io_update_valid & update_idx == 9'h0 | validArray[0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :200:27, :283:{30,42}, :284:26, :285:31, :286:33
always @(posedge clock or posedge reset) begin
if (reset)
validArray <= 512'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27
else if (io_update_valid) // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
validArray <= _validArray_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :286:33
end // always @(posedge, posedge)
always @(posedge clock) begin
if (io_req_valid) begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
s1_idx <= s0_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :213:36
s1_tag <=
io_req_bits_pc[18:10] ^ io_req_bits_folded_hist_hist_6_folded_hist
^ {io_req_bits_folded_hist_hist_2_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75}, :207:43, :213:68
s1_bank_req_1h_0 <= ~(s0_idx[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :215:33
s1_bank_req_1h_1 <= s0_idx[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :215:33
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:16]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
initial begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
for (logic [4:0] i = 5'h0; i < 5'h11; i += 5'h1) begin
_RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
end // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
validArray =
{_RANDOM[5'h0],
_RANDOM[5'h1],
_RANDOM[5'h2],
_RANDOM[5'h3],
_RANDOM[5'h4],
_RANDOM[5'h5],
_RANDOM[5'h6],
_RANDOM[5'h7],
_RANDOM[5'h8],
_RANDOM[5'h9],
_RANDOM[5'hA],
_RANDOM[5'hB],
_RANDOM[5'hC],
_RANDOM[5'hD],
_RANDOM[5'hE],
_RANDOM[5'hF]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :200:27
s1_idx = _RANDOM[5'h10][8:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36
s1_tag = _RANDOM[5'h10][17:9]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:{36,68}
s1_bank_req_1h_0 = _RANDOM[5'h10][18]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33
s1_bank_req_1h_1 = _RANDOM[5'h10][19]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33
s1_bank_has_write_on_this_req_0 = _RANDOM[5'h10][20]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48
s1_bank_has_write_on_this_req_1 = _RANDOM[5'h10][21]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48
`endif // RANDOMIZE_REG_INIT
if (reset) // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
validArray = 512'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
Folded1WDataModuleTemplate_2 us ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18
.clock (clock),
.reset (reset),
.io_raddr_0 (s0_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31
.io_rdata_0 (_us_io_rdata_0),
.io_wen (io_update_uValid),
.io_waddr (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31
.io_wdata (io_update_u),
.io_resetEn (io_update_reset_u)
);
FoldedSRAMTemplate_25 table_banks_0 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & ~(s0_idx[0])), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :223:50
.io_r_req_bits_setIdx (s0_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33
.io_w_req_bits_setIdx (update_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}
.io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61
.io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28
.io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29
);
FoldedSRAMTemplate_25 table_banks_1 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & s0_idx[0]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :223:50
.io_r_req_bits_setIdx (s0_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33
.io_w_req_bits_setIdx (update_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}
.io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61
.io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28
.io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29
);
WrBypass_43 wrbypass ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24
.clock (clock),
.reset (reset),
.io_wen (io_update_valid),
.io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31
.io_write_data_0 (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28
.io_hit (_wrbypass_io_hit),
.io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits)
);
assign io_resp_valid =
_s1_req_rhit_T[0]
& ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag
& ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:68, :215:33, :220:11, :232:{31,61}, :235:{50,53}, :285:31
assign io_resp_bits_ctr =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11
assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :160:86, :217:18, :237:18
assign io_resp_bits_target =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 39'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11
endmodule

761
src/ITTAGE/ITTageTable_4.sv Normal file
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@ -0,0 +1,761 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module ITTageTable_4( // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
input clock,
input reset,
input io_req_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [8:0] io_req_bits_folded_hist_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [7:0] io_req_bits_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
output io_resp_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
output [1:0] io_resp_bits_ctr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
output [1:0] io_resp_bits_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
output [38:0] io_resp_bits_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [8:0] io_update_folded_hist_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [7:0] io_update_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_correct, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_alloc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [1:0] io_update_oldCtr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_uValid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input io_update_reset_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [38:0] io_update_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
input [38:0] io_update_old_target // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
);
wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73
wire _wrbypass_io_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24
wire [1:0] _wrbypass_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24
wire [8:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [38:0] _table_banks_1_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [8:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire [38:0] _table_banks_0_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
wire _us_io_rdata_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18
reg [511:0] validArray; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27
wire [8:0] s0_idx = io_req_bits_pc[9:1] ^ io_req_bits_folded_hist_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43
reg [8:0] s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:36
reg [8:0] s1_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:68
reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33
reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33
wire [511:0] _s1_req_rhit_T = validArray >> s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :213:36, :232:31
reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48
reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48
wire [8:0] update_idx = io_update_pc[9:1] ^ io_update_folded_hist_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43
wire [8:0] update_wdata_tag =
io_update_pc[18:10] ^ io_update_folded_hist_hist_10_folded_hist
^ {io_update_folded_hist_hist_3_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75}, :207:43
assign _resp_invalid_by_write_WIRE =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33, :240:48
wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :255:33
wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :255:33
wire [1:0] old_ctr =
_wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24, :277:20
wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20
wire [1:0] update_wdata_ctr =
io_update_alloc
? 2'h2
: (&old_ctr) & io_update_correct
? 2'h3
: update_wdata_ctr_oldSatNotTaken & ~io_update_correct
? 2'h0
: io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20, :278:28
wire [38:0] update_wdata_target =
io_update_alloc | update_wdata_ctr_oldSatNotTaken
? io_update_target
: io_update_old_target; // src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:281:{29,46}
wire [511:0] _validArray_T =
{io_update_valid & (&update_idx) | validArray[511],
io_update_valid & update_idx == 9'h1FE | validArray[510],
io_update_valid & update_idx == 9'h1FD | validArray[509],
io_update_valid & update_idx == 9'h1FC | validArray[508],
io_update_valid & update_idx == 9'h1FB | validArray[507],
io_update_valid & update_idx == 9'h1FA | validArray[506],
io_update_valid & update_idx == 9'h1F9 | validArray[505],
io_update_valid & update_idx == 9'h1F8 | validArray[504],
io_update_valid & update_idx == 9'h1F7 | validArray[503],
io_update_valid & update_idx == 9'h1F6 | validArray[502],
io_update_valid & update_idx == 9'h1F5 | validArray[501],
io_update_valid & update_idx == 9'h1F4 | validArray[500],
io_update_valid & update_idx == 9'h1F3 | validArray[499],
io_update_valid & update_idx == 9'h1F2 | validArray[498],
io_update_valid & update_idx == 9'h1F1 | validArray[497],
io_update_valid & update_idx == 9'h1F0 | validArray[496],
io_update_valid & update_idx == 9'h1EF | validArray[495],
io_update_valid & update_idx == 9'h1EE | validArray[494],
io_update_valid & update_idx == 9'h1ED | validArray[493],
io_update_valid & update_idx == 9'h1EC | validArray[492],
io_update_valid & update_idx == 9'h1EB | validArray[491],
io_update_valid & update_idx == 9'h1EA | validArray[490],
io_update_valid & update_idx == 9'h1E9 | validArray[489],
io_update_valid & update_idx == 9'h1E8 | validArray[488],
io_update_valid & update_idx == 9'h1E7 | validArray[487],
io_update_valid & update_idx == 9'h1E6 | validArray[486],
io_update_valid & update_idx == 9'h1E5 | validArray[485],
io_update_valid & update_idx == 9'h1E4 | validArray[484],
io_update_valid & update_idx == 9'h1E3 | validArray[483],
io_update_valid & update_idx == 9'h1E2 | validArray[482],
io_update_valid & update_idx == 9'h1E1 | validArray[481],
io_update_valid & update_idx == 9'h1E0 | validArray[480],
io_update_valid & update_idx == 9'h1DF | validArray[479],
io_update_valid & update_idx == 9'h1DE | validArray[478],
io_update_valid & update_idx == 9'h1DD | validArray[477],
io_update_valid & update_idx == 9'h1DC | validArray[476],
io_update_valid & update_idx == 9'h1DB | validArray[475],
io_update_valid & update_idx == 9'h1DA | validArray[474],
io_update_valid & update_idx == 9'h1D9 | validArray[473],
io_update_valid & update_idx == 9'h1D8 | validArray[472],
io_update_valid & update_idx == 9'h1D7 | validArray[471],
io_update_valid & update_idx == 9'h1D6 | validArray[470],
io_update_valid & update_idx == 9'h1D5 | validArray[469],
io_update_valid & update_idx == 9'h1D4 | validArray[468],
io_update_valid & update_idx == 9'h1D3 | validArray[467],
io_update_valid & update_idx == 9'h1D2 | validArray[466],
io_update_valid & update_idx == 9'h1D1 | validArray[465],
io_update_valid & update_idx == 9'h1D0 | validArray[464],
io_update_valid & update_idx == 9'h1CF | validArray[463],
io_update_valid & update_idx == 9'h1CE | validArray[462],
io_update_valid & update_idx == 9'h1CD | validArray[461],
io_update_valid & update_idx == 9'h1CC | validArray[460],
io_update_valid & update_idx == 9'h1CB | validArray[459],
io_update_valid & update_idx == 9'h1CA | validArray[458],
io_update_valid & update_idx == 9'h1C9 | validArray[457],
io_update_valid & update_idx == 9'h1C8 | validArray[456],
io_update_valid & update_idx == 9'h1C7 | validArray[455],
io_update_valid & update_idx == 9'h1C6 | validArray[454],
io_update_valid & update_idx == 9'h1C5 | validArray[453],
io_update_valid & update_idx == 9'h1C4 | validArray[452],
io_update_valid & update_idx == 9'h1C3 | validArray[451],
io_update_valid & update_idx == 9'h1C2 | validArray[450],
io_update_valid & update_idx == 9'h1C1 | validArray[449],
io_update_valid & update_idx == 9'h1C0 | validArray[448],
io_update_valid & update_idx == 9'h1BF | validArray[447],
io_update_valid & update_idx == 9'h1BE | validArray[446],
io_update_valid & update_idx == 9'h1BD | validArray[445],
io_update_valid & update_idx == 9'h1BC | validArray[444],
io_update_valid & update_idx == 9'h1BB | validArray[443],
io_update_valid & update_idx == 9'h1BA | validArray[442],
io_update_valid & update_idx == 9'h1B9 | validArray[441],
io_update_valid & update_idx == 9'h1B8 | validArray[440],
io_update_valid & update_idx == 9'h1B7 | validArray[439],
io_update_valid & update_idx == 9'h1B6 | validArray[438],
io_update_valid & update_idx == 9'h1B5 | validArray[437],
io_update_valid & update_idx == 9'h1B4 | validArray[436],
io_update_valid & update_idx == 9'h1B3 | validArray[435],
io_update_valid & update_idx == 9'h1B2 | validArray[434],
io_update_valid & update_idx == 9'h1B1 | validArray[433],
io_update_valid & update_idx == 9'h1B0 | validArray[432],
io_update_valid & update_idx == 9'h1AF | validArray[431],
io_update_valid & update_idx == 9'h1AE | validArray[430],
io_update_valid & update_idx == 9'h1AD | validArray[429],
io_update_valid & update_idx == 9'h1AC | validArray[428],
io_update_valid & update_idx == 9'h1AB | validArray[427],
io_update_valid & update_idx == 9'h1AA | validArray[426],
io_update_valid & update_idx == 9'h1A9 | validArray[425],
io_update_valid & update_idx == 9'h1A8 | validArray[424],
io_update_valid & update_idx == 9'h1A7 | validArray[423],
io_update_valid & update_idx == 9'h1A6 | validArray[422],
io_update_valid & update_idx == 9'h1A5 | validArray[421],
io_update_valid & update_idx == 9'h1A4 | validArray[420],
io_update_valid & update_idx == 9'h1A3 | validArray[419],
io_update_valid & update_idx == 9'h1A2 | validArray[418],
io_update_valid & update_idx == 9'h1A1 | validArray[417],
io_update_valid & update_idx == 9'h1A0 | validArray[416],
io_update_valid & update_idx == 9'h19F | validArray[415],
io_update_valid & update_idx == 9'h19E | validArray[414],
io_update_valid & update_idx == 9'h19D | validArray[413],
io_update_valid & update_idx == 9'h19C | validArray[412],
io_update_valid & update_idx == 9'h19B | validArray[411],
io_update_valid & update_idx == 9'h19A | validArray[410],
io_update_valid & update_idx == 9'h199 | validArray[409],
io_update_valid & update_idx == 9'h198 | validArray[408],
io_update_valid & update_idx == 9'h197 | validArray[407],
io_update_valid & update_idx == 9'h196 | validArray[406],
io_update_valid & update_idx == 9'h195 | validArray[405],
io_update_valid & update_idx == 9'h194 | validArray[404],
io_update_valid & update_idx == 9'h193 | validArray[403],
io_update_valid & update_idx == 9'h192 | validArray[402],
io_update_valid & update_idx == 9'h191 | validArray[401],
io_update_valid & update_idx == 9'h190 | validArray[400],
io_update_valid & update_idx == 9'h18F | validArray[399],
io_update_valid & update_idx == 9'h18E | validArray[398],
io_update_valid & update_idx == 9'h18D | validArray[397],
io_update_valid & update_idx == 9'h18C | validArray[396],
io_update_valid & update_idx == 9'h18B | validArray[395],
io_update_valid & update_idx == 9'h18A | validArray[394],
io_update_valid & update_idx == 9'h189 | validArray[393],
io_update_valid & update_idx == 9'h188 | validArray[392],
io_update_valid & update_idx == 9'h187 | validArray[391],
io_update_valid & update_idx == 9'h186 | validArray[390],
io_update_valid & update_idx == 9'h185 | validArray[389],
io_update_valid & update_idx == 9'h184 | validArray[388],
io_update_valid & update_idx == 9'h183 | validArray[387],
io_update_valid & update_idx == 9'h182 | validArray[386],
io_update_valid & update_idx == 9'h181 | validArray[385],
io_update_valid & update_idx == 9'h180 | validArray[384],
io_update_valid & update_idx == 9'h17F | validArray[383],
io_update_valid & update_idx == 9'h17E | validArray[382],
io_update_valid & update_idx == 9'h17D | validArray[381],
io_update_valid & update_idx == 9'h17C | validArray[380],
io_update_valid & update_idx == 9'h17B | validArray[379],
io_update_valid & update_idx == 9'h17A | validArray[378],
io_update_valid & update_idx == 9'h179 | validArray[377],
io_update_valid & update_idx == 9'h178 | validArray[376],
io_update_valid & update_idx == 9'h177 | validArray[375],
io_update_valid & update_idx == 9'h176 | validArray[374],
io_update_valid & update_idx == 9'h175 | validArray[373],
io_update_valid & update_idx == 9'h174 | validArray[372],
io_update_valid & update_idx == 9'h173 | validArray[371],
io_update_valid & update_idx == 9'h172 | validArray[370],
io_update_valid & update_idx == 9'h171 | validArray[369],
io_update_valid & update_idx == 9'h170 | validArray[368],
io_update_valid & update_idx == 9'h16F | validArray[367],
io_update_valid & update_idx == 9'h16E | validArray[366],
io_update_valid & update_idx == 9'h16D | validArray[365],
io_update_valid & update_idx == 9'h16C | validArray[364],
io_update_valid & update_idx == 9'h16B | validArray[363],
io_update_valid & update_idx == 9'h16A | validArray[362],
io_update_valid & update_idx == 9'h169 | validArray[361],
io_update_valid & update_idx == 9'h168 | validArray[360],
io_update_valid & update_idx == 9'h167 | validArray[359],
io_update_valid & update_idx == 9'h166 | validArray[358],
io_update_valid & update_idx == 9'h165 | validArray[357],
io_update_valid & update_idx == 9'h164 | validArray[356],
io_update_valid & update_idx == 9'h163 | validArray[355],
io_update_valid & update_idx == 9'h162 | validArray[354],
io_update_valid & update_idx == 9'h161 | validArray[353],
io_update_valid & update_idx == 9'h160 | validArray[352],
io_update_valid & update_idx == 9'h15F | validArray[351],
io_update_valid & update_idx == 9'h15E | validArray[350],
io_update_valid & update_idx == 9'h15D | validArray[349],
io_update_valid & update_idx == 9'h15C | validArray[348],
io_update_valid & update_idx == 9'h15B | validArray[347],
io_update_valid & update_idx == 9'h15A | validArray[346],
io_update_valid & update_idx == 9'h159 | validArray[345],
io_update_valid & update_idx == 9'h158 | validArray[344],
io_update_valid & update_idx == 9'h157 | validArray[343],
io_update_valid & update_idx == 9'h156 | validArray[342],
io_update_valid & update_idx == 9'h155 | validArray[341],
io_update_valid & update_idx == 9'h154 | validArray[340],
io_update_valid & update_idx == 9'h153 | validArray[339],
io_update_valid & update_idx == 9'h152 | validArray[338],
io_update_valid & update_idx == 9'h151 | validArray[337],
io_update_valid & update_idx == 9'h150 | validArray[336],
io_update_valid & update_idx == 9'h14F | validArray[335],
io_update_valid & update_idx == 9'h14E | validArray[334],
io_update_valid & update_idx == 9'h14D | validArray[333],
io_update_valid & update_idx == 9'h14C | validArray[332],
io_update_valid & update_idx == 9'h14B | validArray[331],
io_update_valid & update_idx == 9'h14A | validArray[330],
io_update_valid & update_idx == 9'h149 | validArray[329],
io_update_valid & update_idx == 9'h148 | validArray[328],
io_update_valid & update_idx == 9'h147 | validArray[327],
io_update_valid & update_idx == 9'h146 | validArray[326],
io_update_valid & update_idx == 9'h145 | validArray[325],
io_update_valid & update_idx == 9'h144 | validArray[324],
io_update_valid & update_idx == 9'h143 | validArray[323],
io_update_valid & update_idx == 9'h142 | validArray[322],
io_update_valid & update_idx == 9'h141 | validArray[321],
io_update_valid & update_idx == 9'h140 | validArray[320],
io_update_valid & update_idx == 9'h13F | validArray[319],
io_update_valid & update_idx == 9'h13E | validArray[318],
io_update_valid & update_idx == 9'h13D | validArray[317],
io_update_valid & update_idx == 9'h13C | validArray[316],
io_update_valid & update_idx == 9'h13B | validArray[315],
io_update_valid & update_idx == 9'h13A | validArray[314],
io_update_valid & update_idx == 9'h139 | validArray[313],
io_update_valid & update_idx == 9'h138 | validArray[312],
io_update_valid & update_idx == 9'h137 | validArray[311],
io_update_valid & update_idx == 9'h136 | validArray[310],
io_update_valid & update_idx == 9'h135 | validArray[309],
io_update_valid & update_idx == 9'h134 | validArray[308],
io_update_valid & update_idx == 9'h133 | validArray[307],
io_update_valid & update_idx == 9'h132 | validArray[306],
io_update_valid & update_idx == 9'h131 | validArray[305],
io_update_valid & update_idx == 9'h130 | validArray[304],
io_update_valid & update_idx == 9'h12F | validArray[303],
io_update_valid & update_idx == 9'h12E | validArray[302],
io_update_valid & update_idx == 9'h12D | validArray[301],
io_update_valid & update_idx == 9'h12C | validArray[300],
io_update_valid & update_idx == 9'h12B | validArray[299],
io_update_valid & update_idx == 9'h12A | validArray[298],
io_update_valid & update_idx == 9'h129 | validArray[297],
io_update_valid & update_idx == 9'h128 | validArray[296],
io_update_valid & update_idx == 9'h127 | validArray[295],
io_update_valid & update_idx == 9'h126 | validArray[294],
io_update_valid & update_idx == 9'h125 | validArray[293],
io_update_valid & update_idx == 9'h124 | validArray[292],
io_update_valid & update_idx == 9'h123 | validArray[291],
io_update_valid & update_idx == 9'h122 | validArray[290],
io_update_valid & update_idx == 9'h121 | validArray[289],
io_update_valid & update_idx == 9'h120 | validArray[288],
io_update_valid & update_idx == 9'h11F | validArray[287],
io_update_valid & update_idx == 9'h11E | validArray[286],
io_update_valid & update_idx == 9'h11D | validArray[285],
io_update_valid & update_idx == 9'h11C | validArray[284],
io_update_valid & update_idx == 9'h11B | validArray[283],
io_update_valid & update_idx == 9'h11A | validArray[282],
io_update_valid & update_idx == 9'h119 | validArray[281],
io_update_valid & update_idx == 9'h118 | validArray[280],
io_update_valid & update_idx == 9'h117 | validArray[279],
io_update_valid & update_idx == 9'h116 | validArray[278],
io_update_valid & update_idx == 9'h115 | validArray[277],
io_update_valid & update_idx == 9'h114 | validArray[276],
io_update_valid & update_idx == 9'h113 | validArray[275],
io_update_valid & update_idx == 9'h112 | validArray[274],
io_update_valid & update_idx == 9'h111 | validArray[273],
io_update_valid & update_idx == 9'h110 | validArray[272],
io_update_valid & update_idx == 9'h10F | validArray[271],
io_update_valid & update_idx == 9'h10E | validArray[270],
io_update_valid & update_idx == 9'h10D | validArray[269],
io_update_valid & update_idx == 9'h10C | validArray[268],
io_update_valid & update_idx == 9'h10B | validArray[267],
io_update_valid & update_idx == 9'h10A | validArray[266],
io_update_valid & update_idx == 9'h109 | validArray[265],
io_update_valid & update_idx == 9'h108 | validArray[264],
io_update_valid & update_idx == 9'h107 | validArray[263],
io_update_valid & update_idx == 9'h106 | validArray[262],
io_update_valid & update_idx == 9'h105 | validArray[261],
io_update_valid & update_idx == 9'h104 | validArray[260],
io_update_valid & update_idx == 9'h103 | validArray[259],
io_update_valid & update_idx == 9'h102 | validArray[258],
io_update_valid & update_idx == 9'h101 | validArray[257],
io_update_valid & update_idx == 9'h100 | validArray[256],
io_update_valid & update_idx == 9'hFF | validArray[255],
io_update_valid & update_idx == 9'hFE | validArray[254],
io_update_valid & update_idx == 9'hFD | validArray[253],
io_update_valid & update_idx == 9'hFC | validArray[252],
io_update_valid & update_idx == 9'hFB | validArray[251],
io_update_valid & update_idx == 9'hFA | validArray[250],
io_update_valid & update_idx == 9'hF9 | validArray[249],
io_update_valid & update_idx == 9'hF8 | validArray[248],
io_update_valid & update_idx == 9'hF7 | validArray[247],
io_update_valid & update_idx == 9'hF6 | validArray[246],
io_update_valid & update_idx == 9'hF5 | validArray[245],
io_update_valid & update_idx == 9'hF4 | validArray[244],
io_update_valid & update_idx == 9'hF3 | validArray[243],
io_update_valid & update_idx == 9'hF2 | validArray[242],
io_update_valid & update_idx == 9'hF1 | validArray[241],
io_update_valid & update_idx == 9'hF0 | validArray[240],
io_update_valid & update_idx == 9'hEF | validArray[239],
io_update_valid & update_idx == 9'hEE | validArray[238],
io_update_valid & update_idx == 9'hED | validArray[237],
io_update_valid & update_idx == 9'hEC | validArray[236],
io_update_valid & update_idx == 9'hEB | validArray[235],
io_update_valid & update_idx == 9'hEA | validArray[234],
io_update_valid & update_idx == 9'hE9 | validArray[233],
io_update_valid & update_idx == 9'hE8 | validArray[232],
io_update_valid & update_idx == 9'hE7 | validArray[231],
io_update_valid & update_idx == 9'hE6 | validArray[230],
io_update_valid & update_idx == 9'hE5 | validArray[229],
io_update_valid & update_idx == 9'hE4 | validArray[228],
io_update_valid & update_idx == 9'hE3 | validArray[227],
io_update_valid & update_idx == 9'hE2 | validArray[226],
io_update_valid & update_idx == 9'hE1 | validArray[225],
io_update_valid & update_idx == 9'hE0 | validArray[224],
io_update_valid & update_idx == 9'hDF | validArray[223],
io_update_valid & update_idx == 9'hDE | validArray[222],
io_update_valid & update_idx == 9'hDD | validArray[221],
io_update_valid & update_idx == 9'hDC | validArray[220],
io_update_valid & update_idx == 9'hDB | validArray[219],
io_update_valid & update_idx == 9'hDA | validArray[218],
io_update_valid & update_idx == 9'hD9 | validArray[217],
io_update_valid & update_idx == 9'hD8 | validArray[216],
io_update_valid & update_idx == 9'hD7 | validArray[215],
io_update_valid & update_idx == 9'hD6 | validArray[214],
io_update_valid & update_idx == 9'hD5 | validArray[213],
io_update_valid & update_idx == 9'hD4 | validArray[212],
io_update_valid & update_idx == 9'hD3 | validArray[211],
io_update_valid & update_idx == 9'hD2 | validArray[210],
io_update_valid & update_idx == 9'hD1 | validArray[209],
io_update_valid & update_idx == 9'hD0 | validArray[208],
io_update_valid & update_idx == 9'hCF | validArray[207],
io_update_valid & update_idx == 9'hCE | validArray[206],
io_update_valid & update_idx == 9'hCD | validArray[205],
io_update_valid & update_idx == 9'hCC | validArray[204],
io_update_valid & update_idx == 9'hCB | validArray[203],
io_update_valid & update_idx == 9'hCA | validArray[202],
io_update_valid & update_idx == 9'hC9 | validArray[201],
io_update_valid & update_idx == 9'hC8 | validArray[200],
io_update_valid & update_idx == 9'hC7 | validArray[199],
io_update_valid & update_idx == 9'hC6 | validArray[198],
io_update_valid & update_idx == 9'hC5 | validArray[197],
io_update_valid & update_idx == 9'hC4 | validArray[196],
io_update_valid & update_idx == 9'hC3 | validArray[195],
io_update_valid & update_idx == 9'hC2 | validArray[194],
io_update_valid & update_idx == 9'hC1 | validArray[193],
io_update_valid & update_idx == 9'hC0 | validArray[192],
io_update_valid & update_idx == 9'hBF | validArray[191],
io_update_valid & update_idx == 9'hBE | validArray[190],
io_update_valid & update_idx == 9'hBD | validArray[189],
io_update_valid & update_idx == 9'hBC | validArray[188],
io_update_valid & update_idx == 9'hBB | validArray[187],
io_update_valid & update_idx == 9'hBA | validArray[186],
io_update_valid & update_idx == 9'hB9 | validArray[185],
io_update_valid & update_idx == 9'hB8 | validArray[184],
io_update_valid & update_idx == 9'hB7 | validArray[183],
io_update_valid & update_idx == 9'hB6 | validArray[182],
io_update_valid & update_idx == 9'hB5 | validArray[181],
io_update_valid & update_idx == 9'hB4 | validArray[180],
io_update_valid & update_idx == 9'hB3 | validArray[179],
io_update_valid & update_idx == 9'hB2 | validArray[178],
io_update_valid & update_idx == 9'hB1 | validArray[177],
io_update_valid & update_idx == 9'hB0 | validArray[176],
io_update_valid & update_idx == 9'hAF | validArray[175],
io_update_valid & update_idx == 9'hAE | validArray[174],
io_update_valid & update_idx == 9'hAD | validArray[173],
io_update_valid & update_idx == 9'hAC | validArray[172],
io_update_valid & update_idx == 9'hAB | validArray[171],
io_update_valid & update_idx == 9'hAA | validArray[170],
io_update_valid & update_idx == 9'hA9 | validArray[169],
io_update_valid & update_idx == 9'hA8 | validArray[168],
io_update_valid & update_idx == 9'hA7 | validArray[167],
io_update_valid & update_idx == 9'hA6 | validArray[166],
io_update_valid & update_idx == 9'hA5 | validArray[165],
io_update_valid & update_idx == 9'hA4 | validArray[164],
io_update_valid & update_idx == 9'hA3 | validArray[163],
io_update_valid & update_idx == 9'hA2 | validArray[162],
io_update_valid & update_idx == 9'hA1 | validArray[161],
io_update_valid & update_idx == 9'hA0 | validArray[160],
io_update_valid & update_idx == 9'h9F | validArray[159],
io_update_valid & update_idx == 9'h9E | validArray[158],
io_update_valid & update_idx == 9'h9D | validArray[157],
io_update_valid & update_idx == 9'h9C | validArray[156],
io_update_valid & update_idx == 9'h9B | validArray[155],
io_update_valid & update_idx == 9'h9A | validArray[154],
io_update_valid & update_idx == 9'h99 | validArray[153],
io_update_valid & update_idx == 9'h98 | validArray[152],
io_update_valid & update_idx == 9'h97 | validArray[151],
io_update_valid & update_idx == 9'h96 | validArray[150],
io_update_valid & update_idx == 9'h95 | validArray[149],
io_update_valid & update_idx == 9'h94 | validArray[148],
io_update_valid & update_idx == 9'h93 | validArray[147],
io_update_valid & update_idx == 9'h92 | validArray[146],
io_update_valid & update_idx == 9'h91 | validArray[145],
io_update_valid & update_idx == 9'h90 | validArray[144],
io_update_valid & update_idx == 9'h8F | validArray[143],
io_update_valid & update_idx == 9'h8E | validArray[142],
io_update_valid & update_idx == 9'h8D | validArray[141],
io_update_valid & update_idx == 9'h8C | validArray[140],
io_update_valid & update_idx == 9'h8B | validArray[139],
io_update_valid & update_idx == 9'h8A | validArray[138],
io_update_valid & update_idx == 9'h89 | validArray[137],
io_update_valid & update_idx == 9'h88 | validArray[136],
io_update_valid & update_idx == 9'h87 | validArray[135],
io_update_valid & update_idx == 9'h86 | validArray[134],
io_update_valid & update_idx == 9'h85 | validArray[133],
io_update_valid & update_idx == 9'h84 | validArray[132],
io_update_valid & update_idx == 9'h83 | validArray[131],
io_update_valid & update_idx == 9'h82 | validArray[130],
io_update_valid & update_idx == 9'h81 | validArray[129],
io_update_valid & update_idx == 9'h80 | validArray[128],
io_update_valid & update_idx == 9'h7F | validArray[127],
io_update_valid & update_idx == 9'h7E | validArray[126],
io_update_valid & update_idx == 9'h7D | validArray[125],
io_update_valid & update_idx == 9'h7C | validArray[124],
io_update_valid & update_idx == 9'h7B | validArray[123],
io_update_valid & update_idx == 9'h7A | validArray[122],
io_update_valid & update_idx == 9'h79 | validArray[121],
io_update_valid & update_idx == 9'h78 | validArray[120],
io_update_valid & update_idx == 9'h77 | validArray[119],
io_update_valid & update_idx == 9'h76 | validArray[118],
io_update_valid & update_idx == 9'h75 | validArray[117],
io_update_valid & update_idx == 9'h74 | validArray[116],
io_update_valid & update_idx == 9'h73 | validArray[115],
io_update_valid & update_idx == 9'h72 | validArray[114],
io_update_valid & update_idx == 9'h71 | validArray[113],
io_update_valid & update_idx == 9'h70 | validArray[112],
io_update_valid & update_idx == 9'h6F | validArray[111],
io_update_valid & update_idx == 9'h6E | validArray[110],
io_update_valid & update_idx == 9'h6D | validArray[109],
io_update_valid & update_idx == 9'h6C | validArray[108],
io_update_valid & update_idx == 9'h6B | validArray[107],
io_update_valid & update_idx == 9'h6A | validArray[106],
io_update_valid & update_idx == 9'h69 | validArray[105],
io_update_valid & update_idx == 9'h68 | validArray[104],
io_update_valid & update_idx == 9'h67 | validArray[103],
io_update_valid & update_idx == 9'h66 | validArray[102],
io_update_valid & update_idx == 9'h65 | validArray[101],
io_update_valid & update_idx == 9'h64 | validArray[100],
io_update_valid & update_idx == 9'h63 | validArray[99],
io_update_valid & update_idx == 9'h62 | validArray[98],
io_update_valid & update_idx == 9'h61 | validArray[97],
io_update_valid & update_idx == 9'h60 | validArray[96],
io_update_valid & update_idx == 9'h5F | validArray[95],
io_update_valid & update_idx == 9'h5E | validArray[94],
io_update_valid & update_idx == 9'h5D | validArray[93],
io_update_valid & update_idx == 9'h5C | validArray[92],
io_update_valid & update_idx == 9'h5B | validArray[91],
io_update_valid & update_idx == 9'h5A | validArray[90],
io_update_valid & update_idx == 9'h59 | validArray[89],
io_update_valid & update_idx == 9'h58 | validArray[88],
io_update_valid & update_idx == 9'h57 | validArray[87],
io_update_valid & update_idx == 9'h56 | validArray[86],
io_update_valid & update_idx == 9'h55 | validArray[85],
io_update_valid & update_idx == 9'h54 | validArray[84],
io_update_valid & update_idx == 9'h53 | validArray[83],
io_update_valid & update_idx == 9'h52 | validArray[82],
io_update_valid & update_idx == 9'h51 | validArray[81],
io_update_valid & update_idx == 9'h50 | validArray[80],
io_update_valid & update_idx == 9'h4F | validArray[79],
io_update_valid & update_idx == 9'h4E | validArray[78],
io_update_valid & update_idx == 9'h4D | validArray[77],
io_update_valid & update_idx == 9'h4C | validArray[76],
io_update_valid & update_idx == 9'h4B | validArray[75],
io_update_valid & update_idx == 9'h4A | validArray[74],
io_update_valid & update_idx == 9'h49 | validArray[73],
io_update_valid & update_idx == 9'h48 | validArray[72],
io_update_valid & update_idx == 9'h47 | validArray[71],
io_update_valid & update_idx == 9'h46 | validArray[70],
io_update_valid & update_idx == 9'h45 | validArray[69],
io_update_valid & update_idx == 9'h44 | validArray[68],
io_update_valid & update_idx == 9'h43 | validArray[67],
io_update_valid & update_idx == 9'h42 | validArray[66],
io_update_valid & update_idx == 9'h41 | validArray[65],
io_update_valid & update_idx == 9'h40 | validArray[64],
io_update_valid & update_idx == 9'h3F | validArray[63],
io_update_valid & update_idx == 9'h3E | validArray[62],
io_update_valid & update_idx == 9'h3D | validArray[61],
io_update_valid & update_idx == 9'h3C | validArray[60],
io_update_valid & update_idx == 9'h3B | validArray[59],
io_update_valid & update_idx == 9'h3A | validArray[58],
io_update_valid & update_idx == 9'h39 | validArray[57],
io_update_valid & update_idx == 9'h38 | validArray[56],
io_update_valid & update_idx == 9'h37 | validArray[55],
io_update_valid & update_idx == 9'h36 | validArray[54],
io_update_valid & update_idx == 9'h35 | validArray[53],
io_update_valid & update_idx == 9'h34 | validArray[52],
io_update_valid & update_idx == 9'h33 | validArray[51],
io_update_valid & update_idx == 9'h32 | validArray[50],
io_update_valid & update_idx == 9'h31 | validArray[49],
io_update_valid & update_idx == 9'h30 | validArray[48],
io_update_valid & update_idx == 9'h2F | validArray[47],
io_update_valid & update_idx == 9'h2E | validArray[46],
io_update_valid & update_idx == 9'h2D | validArray[45],
io_update_valid & update_idx == 9'h2C | validArray[44],
io_update_valid & update_idx == 9'h2B | validArray[43],
io_update_valid & update_idx == 9'h2A | validArray[42],
io_update_valid & update_idx == 9'h29 | validArray[41],
io_update_valid & update_idx == 9'h28 | validArray[40],
io_update_valid & update_idx == 9'h27 | validArray[39],
io_update_valid & update_idx == 9'h26 | validArray[38],
io_update_valid & update_idx == 9'h25 | validArray[37],
io_update_valid & update_idx == 9'h24 | validArray[36],
io_update_valid & update_idx == 9'h23 | validArray[35],
io_update_valid & update_idx == 9'h22 | validArray[34],
io_update_valid & update_idx == 9'h21 | validArray[33],
io_update_valid & update_idx == 9'h20 | validArray[32],
io_update_valid & update_idx == 9'h1F | validArray[31],
io_update_valid & update_idx == 9'h1E | validArray[30],
io_update_valid & update_idx == 9'h1D | validArray[29],
io_update_valid & update_idx == 9'h1C | validArray[28],
io_update_valid & update_idx == 9'h1B | validArray[27],
io_update_valid & update_idx == 9'h1A | validArray[26],
io_update_valid & update_idx == 9'h19 | validArray[25],
io_update_valid & update_idx == 9'h18 | validArray[24],
io_update_valid & update_idx == 9'h17 | validArray[23],
io_update_valid & update_idx == 9'h16 | validArray[22],
io_update_valid & update_idx == 9'h15 | validArray[21],
io_update_valid & update_idx == 9'h14 | validArray[20],
io_update_valid & update_idx == 9'h13 | validArray[19],
io_update_valid & update_idx == 9'h12 | validArray[18],
io_update_valid & update_idx == 9'h11 | validArray[17],
io_update_valid & update_idx == 9'h10 | validArray[16],
io_update_valid & update_idx == 9'hF | validArray[15],
io_update_valid & update_idx == 9'hE | validArray[14],
io_update_valid & update_idx == 9'hD | validArray[13],
io_update_valid & update_idx == 9'hC | validArray[12],
io_update_valid & update_idx == 9'hB | validArray[11],
io_update_valid & update_idx == 9'hA | validArray[10],
io_update_valid & update_idx == 9'h9 | validArray[9],
io_update_valid & update_idx == 9'h8 | validArray[8],
io_update_valid & update_idx == 9'h7 | validArray[7],
io_update_valid & update_idx == 9'h6 | validArray[6],
io_update_valid & update_idx == 9'h5 | validArray[5],
io_update_valid & update_idx == 9'h4 | validArray[4],
io_update_valid & update_idx == 9'h3 | validArray[3],
io_update_valid & update_idx == 9'h2 | validArray[2],
io_update_valid & update_idx == 9'h1 | validArray[1],
io_update_valid & update_idx == 9'h0 | validArray[0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :200:27, :283:{30,42}, :284:26, :285:31, :286:33
always @(posedge clock or posedge reset) begin
if (reset)
validArray <= 512'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27
else if (io_update_valid) // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
validArray <= _validArray_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :286:33
end // always @(posedge, posedge)
always @(posedge clock) begin
if (io_req_valid) begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14
s1_idx <= s0_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :213:36
s1_tag <=
io_req_bits_pc[18:10] ^ io_req_bits_folded_hist_hist_10_folded_hist
^ {io_req_bits_folded_hist_hist_3_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75}, :207:43, :213:68
s1_bank_req_1h_0 <= ~(s0_idx[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :215:33
s1_bank_req_1h_1 <= s0_idx[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :215:33
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:16]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
initial begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
for (logic [4:0] i = 5'h0; i < 5'h11; i += 5'h1) begin
_RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
end // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
validArray =
{_RANDOM[5'h0],
_RANDOM[5'h1],
_RANDOM[5'h2],
_RANDOM[5'h3],
_RANDOM[5'h4],
_RANDOM[5'h5],
_RANDOM[5'h6],
_RANDOM[5'h7],
_RANDOM[5'h8],
_RANDOM[5'h9],
_RANDOM[5'hA],
_RANDOM[5'hB],
_RANDOM[5'hC],
_RANDOM[5'hD],
_RANDOM[5'hE],
_RANDOM[5'hF]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :200:27
s1_idx = _RANDOM[5'h10][8:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36
s1_tag = _RANDOM[5'h10][17:9]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:{36,68}
s1_bank_req_1h_0 = _RANDOM[5'h10][18]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33
s1_bank_req_1h_1 = _RANDOM[5'h10][19]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33
s1_bank_has_write_on_this_req_0 = _RANDOM[5'h10][20]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48
s1_bank_has_write_on_this_req_1 = _RANDOM[5'h10][21]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48
`endif // RANDOMIZE_REG_INIT
if (reset) // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
validArray = 512'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
Folded1WDataModuleTemplate_2 us ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18
.clock (clock),
.reset (reset),
.io_raddr_0 (s0_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31
.io_rdata_0 (_us_io_rdata_0),
.io_wen (io_update_uValid),
.io_waddr (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31
.io_wdata (io_update_u),
.io_resetEn (io_update_reset_u)
);
FoldedSRAMTemplate_25 table_banks_0 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & ~(s0_idx[0])), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :223:50
.io_r_req_bits_setIdx (s0_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33
.io_w_req_bits_setIdx (update_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}
.io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61
.io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28
.io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29
);
FoldedSRAMTemplate_25 table_banks_1 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & s0_idx[0]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :223:50
.io_r_req_bits_setIdx (s0_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33
.io_w_req_bits_setIdx (update_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40}
.io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61
.io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28
.io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29
);
WrBypass_43 wrbypass ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24
.clock (clock),
.reset (reset),
.io_wen (io_update_valid),
.io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31
.io_write_data_0 (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28
.io_hit (_wrbypass_io_hit),
.io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits)
);
assign io_resp_valid =
_s1_req_rhit_T[0]
& ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag
& ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:68, :215:33, :220:11, :232:{31,61}, :235:{50,53}, :285:31
assign io_resp_bits_ctr =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11
assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :160:86, :217:18, :237:18
assign io_resp_bits_target =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 39'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11
endmodule

136
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@ -0,0 +1,136 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module CAMTemplate( // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
input clock,
input [8:0] io_r_req_0_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_0, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_1, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_2, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_3, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_4, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_5, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_6, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_7, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
input io_w_valid, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
input [8:0] io_w_bits_data_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
input [2:0] io_w_bits_index // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
);
reg [8:0] array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [8:0] array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [8:0] array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [8:0] array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [8:0] array_4; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [8:0] array_5; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [8:0] array_6; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [8:0] array_7; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
always @(posedge clock) begin
if (io_w_valid & io_w_bits_index == 3'h0) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_0 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 3'h1) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_1 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 3'h2) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_2 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 3'h3) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_3 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 3'h4) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_4 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 3'h5) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_5 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 3'h6) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_6 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & (&io_w_bits_index)) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_7 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:2]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
initial begin // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin
_RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
end // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
array_0 = _RANDOM[2'h0][8:0]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_1 = _RANDOM[2'h0][17:9]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_2 = _RANDOM[2'h0][26:18]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_3 = {_RANDOM[2'h0][31:27], _RANDOM[2'h1][3:0]}; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_4 = _RANDOM[2'h1][12:4]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_5 = _RANDOM[2'h1][21:13]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_6 = _RANDOM[2'h1][30:22]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_7 = {_RANDOM[2'h1][31], _RANDOM[2'h2][7:0]}; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_r_resp_0_0 = io_r_req_0_idx == array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_1 = io_r_req_0_idx == array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_2 = io_r_req_0_idx == array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_3 = io_r_req_0_idx == array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_4 = io_r_req_0_idx == array_4; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_5 = io_r_req_0_idx == array_5; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_6 = io_r_req_0_idx == array_6; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_7 = io_r_req_0_idx == array_7; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
endmodule

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@ -0,0 +1,136 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module CAMTemplate_32( // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
input clock,
input [10:0] io_r_req_0_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_0, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_1, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_2, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_3, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_4, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_5, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_6, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_7, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
input io_w_valid, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
input [10:0] io_w_bits_data_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
input [2:0] io_w_bits_index // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
);
reg [10:0] array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [10:0] array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [10:0] array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [10:0] array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [10:0] array_4; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [10:0] array_5; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [10:0] array_6; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [10:0] array_7; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
always @(posedge clock) begin
if (io_w_valid & io_w_bits_index == 3'h0) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_0 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 3'h1) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_1 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 3'h2) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_2 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 3'h3) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_3 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 3'h4) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_4 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 3'h5) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_5 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 3'h6) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_6 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & (&io_w_bits_index)) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_7 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:2]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
initial begin // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin
_RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
end // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
array_0 = _RANDOM[2'h0][10:0]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_1 = _RANDOM[2'h0][21:11]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_2 = {_RANDOM[2'h0][31:22], _RANDOM[2'h1][0]}; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_3 = _RANDOM[2'h1][11:1]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_4 = _RANDOM[2'h1][22:12]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_5 = {_RANDOM[2'h1][31:23], _RANDOM[2'h2][1:0]}; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_6 = _RANDOM[2'h2][12:2]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_7 = _RANDOM[2'h2][23:13]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_r_resp_0_0 = io_r_req_0_idx == array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_1 = io_r_req_0_idx == array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_2 = io_r_req_0_idx == array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_3 = io_r_req_0_idx == array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_4 = io_r_req_0_idx == array_4; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_5 = io_r_req_0_idx == array_5; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_6 = io_r_req_0_idx == array_6; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_7 = io_r_req_0_idx == array_7; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
endmodule

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// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module CAMTemplate_33( // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
input clock,
input [7:0] io_r_req_0_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_0, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_1, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_2, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_3, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_4, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_5, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_6, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_7, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_8, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_9, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_10, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_11, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_12, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_13, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_14, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_15, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
input io_w_valid, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
input [7:0] io_w_bits_data_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
input [3:0] io_w_bits_index // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
);
reg [7:0] array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [7:0] array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [7:0] array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [7:0] array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [7:0] array_4; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [7:0] array_5; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [7:0] array_6; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [7:0] array_7; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [7:0] array_8; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [7:0] array_9; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [7:0] array_10; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [7:0] array_11; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [7:0] array_12; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [7:0] array_13; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [7:0] array_14; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [7:0] array_15; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
always @(posedge clock) begin
if (io_w_valid & io_w_bits_index == 4'h0) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_0 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 4'h1) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_1 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 4'h2) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_2 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 4'h3) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_3 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 4'h4) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_4 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 4'h5) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_5 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 4'h6) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_6 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 4'h7) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_7 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 4'h8) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_8 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 4'h9) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_9 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 4'hA) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_10 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 4'hB) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_11 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 4'hC) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_12 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 4'hD) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_13 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 4'hE) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_14 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & (&io_w_bits_index)) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_15 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:3]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
initial begin // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
_RANDOM[i[1:0]] = `RANDOM; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
end // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
array_0 = _RANDOM[2'h0][7:0]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_1 = _RANDOM[2'h0][15:8]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_2 = _RANDOM[2'h0][23:16]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_3 = _RANDOM[2'h0][31:24]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_4 = _RANDOM[2'h1][7:0]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_5 = _RANDOM[2'h1][15:8]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_6 = _RANDOM[2'h1][23:16]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_7 = _RANDOM[2'h1][31:24]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_8 = _RANDOM[2'h2][7:0]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_9 = _RANDOM[2'h2][15:8]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_10 = _RANDOM[2'h2][23:16]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_11 = _RANDOM[2'h2][31:24]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_12 = _RANDOM[2'h3][7:0]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_13 = _RANDOM[2'h3][15:8]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_14 = _RANDOM[2'h3][23:16]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_15 = _RANDOM[2'h3][31:24]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_r_resp_0_0 = io_r_req_0_idx == array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_1 = io_r_req_0_idx == array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_2 = io_r_req_0_idx == array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_3 = io_r_req_0_idx == array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_4 = io_r_req_0_idx == array_4; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_5 = io_r_req_0_idx == array_5; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_6 = io_r_req_0_idx == array_6; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_7 = io_r_req_0_idx == array_7; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_8 = io_r_req_0_idx == array_8; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_9 = io_r_req_0_idx == array_9; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_10 = io_r_req_0_idx == array_10; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_11 = io_r_req_0_idx == array_11; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_12 = io_r_req_0_idx == array_12; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_13 = io_r_req_0_idx == array_13; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_14 = io_r_req_0_idx == array_14; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_15 = io_r_req_0_idx == array_15; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
endmodule

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@ -0,0 +1,209 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module FoldedSRAMTemplate( // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
input clock,
input reset,
output io_r_req_ready, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [10:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
output io_r_resp_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
output io_r_resp_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [10:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input io_w_req_bits_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input io_w_req_bits_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [1:0] io_w_req_bits_waymask, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input extra_reset // utility/src/main/scala/utility/SRAMTemplate.scala:169:44
);
wire _array_io_r_resp_data_0; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire _array_io_r_resp_data_1; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire _array_io_r_resp_data_2; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire _array_io_r_resp_data_3; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire _array_io_r_resp_data_4; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire _array_io_r_resp_data_5; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire _array_io_r_resp_data_6; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire _array_io_r_resp_data_7; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire _array_io_r_resp_data_8; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire _array_io_r_resp_data_9; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire _array_io_r_resp_data_10; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire _array_io_r_resp_data_11; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire _array_io_r_resp_data_12; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire _array_io_r_resp_data_13; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire _array_io_r_resp_data_14; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire _array_io_r_resp_data_15; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
reg [2:0] ridx; // utility/src/main/scala/utility/SRAMTemplate.scala:189:21
reg holdRidx_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44
reg [2:0] holdRidx_hold_data; // utility/src/main/scala/utility/Hold.scala:24:82
wire [2:0] holdRidx = holdRidx_REG ? ridx : holdRidx_hold_data; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:189:21, :198:44
reg holdRidx_REG_1; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44
reg [2:0] holdRidx_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82
wire [2:0] holdRidx_1 = holdRidx_REG_1 ? ridx : holdRidx_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:189:21, :198:44
wire _wmask_T_3 = io_w_req_bits_setIdx[2:0] == 3'h0; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69
wire _wmask_T_9 = io_w_req_bits_setIdx[2:0] == 3'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69
wire _wmask_T_15 = io_w_req_bits_setIdx[2:0] == 3'h2; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69
wire _wmask_T_21 = io_w_req_bits_setIdx[2:0] == 3'h3; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69
wire _wmask_T_27 = io_w_req_bits_setIdx[2:0] == 3'h4; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69
wire _wmask_T_33 = io_w_req_bits_setIdx[2:0] == 3'h5; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69
wire _wmask_T_39 = io_w_req_bits_setIdx[2:0] == 3'h6; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69
always @(posedge clock) begin
ridx <= io_r_req_bits_setIdx[2:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:189:{21,58}
holdRidx_REG <= io_r_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44
if (holdRidx_REG) // utility/src/main/scala/utility/SRAMTemplate.scala:198:44
holdRidx_hold_data <= ridx; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:189:21
holdRidx_REG_1 <= io_r_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44
if (holdRidx_REG_1) // utility/src/main/scala/utility/SRAMTemplate.scala:198:44
holdRidx_hold_data_1 <= ridx; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:189:21
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
`ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
`FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
`ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
`INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
ridx = _RANDOM[/*Zero width*/ 1'b0][2:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21
holdRidx_REG = _RANDOM[/*Zero width*/ 1'b0][3]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21, :198:44
holdRidx_hold_data = _RANDOM[/*Zero width*/ 1'b0][6:4]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21
holdRidx_REG_1 = _RANDOM[/*Zero width*/ 1'b0][7]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21, :198:44
holdRidx_hold_data_1 = _RANDOM[/*Zero width*/ 1'b0][10:8]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
`FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
SRAMTemplate_10 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
.clock (clock),
.reset (reset),
.io_r_req_ready (io_r_req_ready),
.io_r_req_valid (io_r_req_valid),
.io_r_req_bits_setIdx (io_r_req_bits_setIdx[10:3]), // utility/src/main/scala/utility/SRAMTemplate.scala:188:36
.io_r_resp_data_0 (_array_io_r_resp_data_0),
.io_r_resp_data_1 (_array_io_r_resp_data_1),
.io_r_resp_data_2 (_array_io_r_resp_data_2),
.io_r_resp_data_3 (_array_io_r_resp_data_3),
.io_r_resp_data_4 (_array_io_r_resp_data_4),
.io_r_resp_data_5 (_array_io_r_resp_data_5),
.io_r_resp_data_6 (_array_io_r_resp_data_6),
.io_r_resp_data_7 (_array_io_r_resp_data_7),
.io_r_resp_data_8 (_array_io_r_resp_data_8),
.io_r_resp_data_9 (_array_io_r_resp_data_9),
.io_r_resp_data_10 (_array_io_r_resp_data_10),
.io_r_resp_data_11 (_array_io_r_resp_data_11),
.io_r_resp_data_12 (_array_io_r_resp_data_12),
.io_r_resp_data_13 (_array_io_r_resp_data_13),
.io_r_resp_data_14 (_array_io_r_resp_data_14),
.io_r_resp_data_15 (_array_io_r_resp_data_15),
.io_w_req_valid (io_w_req_valid),
.io_w_req_bits_setIdx (io_w_req_bits_setIdx[10:3]), // utility/src/main/scala/utility/SRAMTemplate.scala:205:36
.io_w_req_bits_data_0 (io_w_req_bits_data_0),
.io_w_req_bits_data_1 (io_w_req_bits_data_1),
.io_w_req_bits_data_2 (io_w_req_bits_data_0),
.io_w_req_bits_data_3 (io_w_req_bits_data_1),
.io_w_req_bits_data_4 (io_w_req_bits_data_0),
.io_w_req_bits_data_5 (io_w_req_bits_data_1),
.io_w_req_bits_data_6 (io_w_req_bits_data_0),
.io_w_req_bits_data_7 (io_w_req_bits_data_1),
.io_w_req_bits_data_8 (io_w_req_bits_data_0),
.io_w_req_bits_data_9 (io_w_req_bits_data_1),
.io_w_req_bits_data_10 (io_w_req_bits_data_0),
.io_w_req_bits_data_11 (io_w_req_bits_data_1),
.io_w_req_bits_data_12 (io_w_req_bits_data_0),
.io_w_req_bits_data_13 (io_w_req_bits_data_1),
.io_w_req_bits_data_14 (io_w_req_bits_data_0),
.io_w_req_bits_data_15 (io_w_req_bits_data_1),
.io_w_req_bits_waymask
({(&(io_w_req_bits_setIdx[2:0])) & io_w_req_bits_waymask[1],
(&(io_w_req_bits_setIdx[2:0])) & io_w_req_bits_waymask[0],
_wmask_T_39 & io_w_req_bits_waymask[1],
_wmask_T_39 & io_w_req_bits_waymask[0],
_wmask_T_33 & io_w_req_bits_waymask[1],
_wmask_T_33 & io_w_req_bits_waymask[0],
_wmask_T_27 & io_w_req_bits_waymask[1],
_wmask_T_27 & io_w_req_bits_waymask[0],
_wmask_T_21 & io_w_req_bits_waymask[1],
_wmask_T_21 & io_w_req_bits_waymask[0],
_wmask_T_15 & io_w_req_bits_waymask[1],
_wmask_T_15 & io_w_req_bits_waymask[0],
_wmask_T_9 & io_w_req_bits_waymask[1],
_wmask_T_9 & io_w_req_bits_waymask[0],
_wmask_T_3 & io_w_req_bits_waymask[1],
_wmask_T_3 & io_w_req_bits_waymask[0]}), // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:{69,82,110,122}
.extra_reset (extra_reset)
);
assign io_r_resp_data_0 =
holdRidx == 3'h0 & _array_io_r_resp_data_0 | holdRidx == 3'h1
& _array_io_r_resp_data_2 | holdRidx == 3'h2 & _array_io_r_resp_data_4
| holdRidx == 3'h3 & _array_io_r_resp_data_6 | holdRidx == 3'h4
& _array_io_r_resp_data_8 | holdRidx == 3'h5 & _array_io_r_resp_data_10
| holdRidx == 3'h6 & _array_io_r_resp_data_12 | (&holdRidx)
& _array_io_r_resp_data_14; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :179:21, :210:69
assign io_r_resp_data_1 =
holdRidx_1 == 3'h0 & _array_io_r_resp_data_1 | holdRidx_1 == 3'h1
& _array_io_r_resp_data_3 | holdRidx_1 == 3'h2 & _array_io_r_resp_data_5
| holdRidx_1 == 3'h3 & _array_io_r_resp_data_7 | holdRidx_1 == 3'h4
& _array_io_r_resp_data_9 | holdRidx_1 == 3'h5 & _array_io_r_resp_data_11
| holdRidx_1 == 3'h6 & _array_io_r_resp_data_13 | (&holdRidx_1)
& _array_io_r_resp_data_15; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :179:21, :210:69
endmodule

100
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@ -0,0 +1,100 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module FoldedSRAMTemplate_1( // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
input clock,
input reset,
output io_r_req_ready, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [8:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
output io_r_resp_data_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
output [7:0] io_r_resp_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
output [2:0] io_r_resp_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
output io_r_resp_data_1_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
output [7:0] io_r_resp_data_1_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
output [2:0] io_r_resp_data_1_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [8:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [7:0] io_w_req_bits_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [2:0] io_w_req_bits_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [7:0] io_w_req_bits_data_1_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [2:0] io_w_req_bits_data_1_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [1:0] io_w_req_bits_waymask // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
);
SRAMTemplate_11 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
.clock (clock),
.reset (reset),
.io_r_req_ready (io_r_req_ready),
.io_r_req_valid (io_r_req_valid),
.io_r_req_bits_setIdx (io_r_req_bits_setIdx),
.io_r_resp_data_0_valid (io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (io_r_resp_data_1_ctr),
.io_w_req_valid (io_w_req_valid),
.io_w_req_bits_setIdx (io_w_req_bits_setIdx),
.io_w_req_bits_data_0_tag (io_w_req_bits_data_0_tag),
.io_w_req_bits_data_0_ctr (io_w_req_bits_data_0_ctr),
.io_w_req_bits_data_1_tag (io_w_req_bits_data_1_tag),
.io_w_req_bits_data_1_ctr (io_w_req_bits_data_1_ctr),
.io_w_req_bits_waymask (io_w_req_bits_waymask)
);
endmodule

163
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@ -0,0 +1,163 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module FoldedSRAMTemplate_20( // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
input clock,
input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [10:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
output [1:0] io_r_resp_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
output [1:0] io_r_resp_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [10:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [1:0] io_w_req_bits_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [1:0] io_w_req_bits_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [1:0] io_w_req_bits_waymask // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
);
wire [1:0] _array_io_r_resp_data_0; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire [1:0] _array_io_r_resp_data_1; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire [1:0] _array_io_r_resp_data_2; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire [1:0] _array_io_r_resp_data_3; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire [1:0] _array_io_r_resp_data_4; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire [1:0] _array_io_r_resp_data_5; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire [1:0] _array_io_r_resp_data_6; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire [1:0] _array_io_r_resp_data_7; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
reg [1:0] ridx; // utility/src/main/scala/utility/SRAMTemplate.scala:189:21
reg holdRidx_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44
reg [1:0] holdRidx_hold_data; // utility/src/main/scala/utility/Hold.scala:24:82
wire [1:0] holdRidx = holdRidx_REG ? ridx : holdRidx_hold_data; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:189:21, :198:44
reg holdRidx_REG_1; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44
reg [1:0] holdRidx_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82
wire [1:0] holdRidx_1 = holdRidx_REG_1 ? ridx : holdRidx_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:189:21, :198:44
wire _wmask_T_3 = io_w_req_bits_setIdx[1:0] == 2'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69
wire _wmask_T_9 = io_w_req_bits_setIdx[1:0] == 2'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69
wire _wmask_T_15 = io_w_req_bits_setIdx[1:0] == 2'h2; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69
always @(posedge clock) begin
ridx <= io_r_req_bits_setIdx[1:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:189:{21,58}
holdRidx_REG <= io_r_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44
if (holdRidx_REG) // utility/src/main/scala/utility/SRAMTemplate.scala:198:44
holdRidx_hold_data <= ridx; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:189:21
holdRidx_REG_1 <= io_r_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44
if (holdRidx_REG_1) // utility/src/main/scala/utility/SRAMTemplate.scala:198:44
holdRidx_hold_data_1 <= ridx; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:189:21
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
`ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
`FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
`ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
`INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
ridx = _RANDOM[/*Zero width*/ 1'b0][1:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21
holdRidx_REG = _RANDOM[/*Zero width*/ 1'b0][2]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21, :198:44
holdRidx_hold_data = _RANDOM[/*Zero width*/ 1'b0][4:3]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21
holdRidx_REG_1 = _RANDOM[/*Zero width*/ 1'b0][5]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21, :198:44
holdRidx_hold_data_1 = _RANDOM[/*Zero width*/ 1'b0][7:6]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
`FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
SRAMTemplate_30 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
.clock (clock),
.io_r_req_valid (io_r_req_valid),
.io_r_req_bits_setIdx (io_r_req_bits_setIdx[10:2]), // utility/src/main/scala/utility/SRAMTemplate.scala:188:36
.io_r_resp_data_0 (_array_io_r_resp_data_0),
.io_r_resp_data_1 (_array_io_r_resp_data_1),
.io_r_resp_data_2 (_array_io_r_resp_data_2),
.io_r_resp_data_3 (_array_io_r_resp_data_3),
.io_r_resp_data_4 (_array_io_r_resp_data_4),
.io_r_resp_data_5 (_array_io_r_resp_data_5),
.io_r_resp_data_6 (_array_io_r_resp_data_6),
.io_r_resp_data_7 (_array_io_r_resp_data_7),
.io_w_req_valid (io_w_req_valid),
.io_w_req_bits_setIdx (io_w_req_bits_setIdx[10:2]), // utility/src/main/scala/utility/SRAMTemplate.scala:205:36
.io_w_req_bits_data_0 (io_w_req_bits_data_0),
.io_w_req_bits_data_1 (io_w_req_bits_data_1),
.io_w_req_bits_data_2 (io_w_req_bits_data_0),
.io_w_req_bits_data_3 (io_w_req_bits_data_1),
.io_w_req_bits_data_4 (io_w_req_bits_data_0),
.io_w_req_bits_data_5 (io_w_req_bits_data_1),
.io_w_req_bits_data_6 (io_w_req_bits_data_0),
.io_w_req_bits_data_7 (io_w_req_bits_data_1),
.io_w_req_bits_waymask
({(&(io_w_req_bits_setIdx[1:0])) & io_w_req_bits_waymask[1],
(&(io_w_req_bits_setIdx[1:0])) & io_w_req_bits_waymask[0],
_wmask_T_15 & io_w_req_bits_waymask[1],
_wmask_T_15 & io_w_req_bits_waymask[0],
_wmask_T_9 & io_w_req_bits_waymask[1],
_wmask_T_9 & io_w_req_bits_waymask[0],
_wmask_T_3 & io_w_req_bits_waymask[1],
_wmask_T_3 & io_w_req_bits_waymask[0]}) // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:{69,82,110,122}
);
assign io_r_resp_data_0 =
(holdRidx == 2'h0 ? _array_io_r_resp_data_0 : 2'h0)
| (holdRidx == 2'h1 ? _array_io_r_resp_data_2 : 2'h0)
| (holdRidx == 2'h2 ? _array_io_r_resp_data_4 : 2'h0)
| ((&holdRidx) ? _array_io_r_resp_data_6 : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :179:21, :210:69
assign io_r_resp_data_1 =
(holdRidx_1 == 2'h0 ? _array_io_r_resp_data_1 : 2'h0)
| (holdRidx_1 == 2'h1 ? _array_io_r_resp_data_3 : 2'h0)
| (holdRidx_1 == 2'h2 ? _array_io_r_resp_data_5 : 2'h0)
| ((&holdRidx_1) ? _array_io_r_resp_data_7 : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :179:21, :210:69
endmodule

253
src/TageSC/SCTable.sv Normal file
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@ -0,0 +1,253 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SCTable( // src/main/scala/xiangshan/frontend/SC.scala:66:7
input clock,
input reset,
input io_req_valid, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/SC.scala:68:14
output [5:0] io_resp_ctrs_0_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14
output [5:0] io_resp_ctrs_0_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14
output [5:0] io_resp_ctrs_1_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14
output [5:0] io_resp_ctrs_1_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input io_update_mask_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input io_update_mask_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input [5:0] io_update_oldCtrs_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input [5:0] io_update_oldCtrs_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input io_update_tagePreds_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input io_update_tagePreds_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input io_update_takens_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input io_update_takens_1 // src/main/scala/xiangshan/frontend/SC.scala:68:14
);
wire _wrbypasses_1_io_hit; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire _wrbypasses_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire [5:0] _wrbypasses_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire _wrbypasses_1_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire [5:0] _wrbypasses_1_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire _wrbypasses_0_io_hit; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire _wrbypasses_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire [5:0] _wrbypasses_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire _wrbypasses_0_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire [5:0] _wrbypasses_0_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire [5:0] _table_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/SC.scala:71:21
wire [5:0] _table_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/SC.scala:71:21
wire [5:0] _table_io_r_resp_data_2; // src/main/scala/xiangshan/frontend/SC.scala:71:21
wire [5:0] _table_io_r_resp_data_3; // src/main/scala/xiangshan/frontend/SC.scala:71:21
reg [38:0] s1_pc; // src/main/scala/xiangshan/frontend/SC.scala:99:24
wire per_br_update_way_mask_0_0 =
io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1
& io_update_pc[1] & ~io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{69,78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42
wire per_br_update_way_mask_0_1 =
io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1
& io_update_pc[1] & io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:{69,78}, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42
wire per_br_update_way_mask_1_0 =
io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1
& ~(io_update_pc[1]) & ~io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92
wire per_br_update_way_mask_1_1 =
io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1
& ~(io_update_pc[1]) & io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:78, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92
wire ctrPos =
~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42
wire [5:0] oldCtr =
(~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit)
& (ctrPos
? ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1]
& _wrbypasses_1_io_hit_data_1_valid
: ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1]
& _wrbypasses_1_io_hit_data_0_valid)
? (ctrPos
? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits)
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0)
: (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0))
: (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0)
| (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42
wire taken =
~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42
wire [5:0] per_br_update_wdata_packed_0_1 =
oldCtr == 6'h1F & taken
? 6'h1F
: oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:102:27, :103:30, :104:{8,21}, :105:{10,26,29}, :106:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21
wire ctrPos_1 =
io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92
wire [5:0] oldCtr_1 =
(io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit)
& (ctrPos_1
? io_update_pc[1] & _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1])
& _wrbypasses_1_io_hit_data_1_valid
: io_update_pc[1] & _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _wrbypasses_1_io_hit_data_0_valid)
? (ctrPos_1
? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0)
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits)
: (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0)
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits))
: (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0)
| (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92
wire taken_1 =
io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92
wire [5:0] per_br_update_wdata_packed_1_1 =
oldCtr_1 == 6'h1F & taken_1
? 6'h1F
: oldCtr_1 == 6'h20 & ~taken_1
? 6'h20
: taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:102:27, :103:30, :104:{8,21}, :105:{10,26,29}, :106:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21
wire [5:0] _GEN =
(io_update_pc[1] ? 6'h0 : per_br_update_wdata_packed_0_1)
| (io_update_pc[1] ? per_br_update_wdata_packed_1_1 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:104:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42
wire [5:0] _GEN_0 =
(io_update_pc[1] ? per_br_update_wdata_packed_0_1 : 6'h0)
| (io_update_pc[1] ? 6'h0 : per_br_update_wdata_packed_1_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:104:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42
always @(posedge clock) begin
if (io_req_valid) // src/main/scala/xiangshan/frontend/SC.scala:68:14
s1_pc <= io_req_bits_pc; // src/main/scala/xiangshan/frontend/SC.scala:99:24
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:1]; // src/main/scala/xiangshan/frontend/SC.scala:66:7
initial begin // src/main/scala/xiangshan/frontend/SC.scala:66:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/SC.scala:66:7
for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
_RANDOM[i[0]] = `RANDOM; // src/main/scala/xiangshan/frontend/SC.scala:66:7
end // src/main/scala/xiangshan/frontend/SC.scala:66:7
s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][14:0]}; // src/main/scala/xiangshan/frontend/SC.scala:66:7, :99:24
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
SRAMTemplate_31 table_0 ( // src/main/scala/xiangshan/frontend/SC.scala:71:21
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid),
.io_r_req_bits_setIdx (io_req_bits_pc[8:1]), // src/main/scala/xiangshan/frontend/SC.scala:89:{11,29}
.io_r_resp_data_0 (_table_io_r_resp_data_0),
.io_r_resp_data_1 (_table_io_r_resp_data_1),
.io_r_resp_data_2 (_table_io_r_resp_data_2),
.io_r_resp_data_3 (_table_io_r_resp_data_3),
.io_w_req_valid (io_update_mask_0 | io_update_mask_1), // src/main/scala/xiangshan/frontend/SC.scala:130:36
.io_w_req_bits_setIdx (io_update_pc[8:1]), // src/main/scala/xiangshan/frontend/SC.scala:89:29, :117:42
.io_w_req_bits_data_0 (per_br_update_wdata_packed_0_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8
.io_w_req_bits_data_1 (per_br_update_wdata_packed_0_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8
.io_w_req_bits_data_2 (per_br_update_wdata_packed_1_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8
.io_w_req_bits_data_3 (per_br_update_wdata_packed_1_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8
.io_w_req_bits_waymask
({per_br_update_way_mask_1_1,
per_br_update_way_mask_1_0,
per_br_update_way_mask_0_1,
per_br_update_way_mask_0_0}) // src/main/scala/xiangshan/frontend/SC.scala:121:15, :124:15, :133:29
);
WrBypass_33 wrbypasses_0 ( // src/main/scala/xiangshan/frontend/SC.scala:139:42
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0),
.io_write_idx (io_update_pc[8:1]), // src/main/scala/xiangshan/frontend/SC.scala:89:29, :117:42
.io_write_data_0 (_GEN), // src/main/scala/chisel3/util/Mux.scala:30:73
.io_write_data_1 (_GEN), // src/main/scala/chisel3/util/Mux.scala:30:73
.io_write_way_mask_0
(~(io_update_pc[1]) & per_br_update_way_mask_0_0 | io_update_pc[1]
& per_br_update_way_mask_1_0), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42
.io_write_way_mask_1
(~(io_update_pc[1]) & per_br_update_way_mask_0_1 | io_update_pc[1]
& per_br_update_way_mask_1_1), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42
.io_hit (_wrbypasses_0_io_hit),
.io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits)
);
WrBypass_33 wrbypasses_1 ( // src/main/scala/xiangshan/frontend/SC.scala:139:42
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1),
.io_write_idx (io_update_pc[8:1]), // src/main/scala/xiangshan/frontend/SC.scala:89:29, :117:42
.io_write_data_0 (_GEN_0), // src/main/scala/chisel3/util/Mux.scala:30:73
.io_write_data_1 (_GEN_0), // src/main/scala/chisel3/util/Mux.scala:30:73
.io_write_way_mask_0
(io_update_pc[1] & per_br_update_way_mask_0_0 | ~(io_update_pc[1])
& per_br_update_way_mask_1_0), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92
.io_write_way_mask_1
(io_update_pc[1] & per_br_update_way_mask_0_1 | ~(io_update_pc[1])
& per_br_update_way_mask_1_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92
.io_hit (_wrbypasses_1_io_hit),
.io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypasses_1_io_hit_data_1_bits)
);
assign io_resp_ctrs_0_0 =
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0)
| (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42
assign io_resp_ctrs_0_1 =
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1)
| (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42
assign io_resp_ctrs_1_0 =
(s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0)
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42
assign io_resp_ctrs_1_1 =
(s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0)
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42
endmodule

259
src/TageSC/SCTable_1.sv Normal file
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@ -0,0 +1,259 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SCTable_1( // src/main/scala/xiangshan/frontend/SC.scala:66:7
input clock,
input reset,
input io_req_valid, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input [3:0] io_req_bits_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/SC.scala:68:14
output [5:0] io_resp_ctrs_0_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14
output [5:0] io_resp_ctrs_0_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14
output [5:0] io_resp_ctrs_1_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14
output [5:0] io_resp_ctrs_1_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input [3:0] io_update_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input io_update_mask_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input io_update_mask_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input [5:0] io_update_oldCtrs_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input [5:0] io_update_oldCtrs_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input io_update_tagePreds_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input io_update_tagePreds_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input io_update_takens_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input io_update_takens_1 // src/main/scala/xiangshan/frontend/SC.scala:68:14
);
wire _wrbypasses_1_io_hit; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire _wrbypasses_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire [5:0] _wrbypasses_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire _wrbypasses_1_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire [5:0] _wrbypasses_1_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire _wrbypasses_0_io_hit; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire _wrbypasses_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire [5:0] _wrbypasses_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire _wrbypasses_0_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire [5:0] _wrbypasses_0_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire [5:0] _table_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/SC.scala:71:21
wire [5:0] _table_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/SC.scala:71:21
wire [5:0] _table_io_r_resp_data_2; // src/main/scala/xiangshan/frontend/SC.scala:71:21
wire [5:0] _table_io_r_resp_data_3; // src/main/scala/xiangshan/frontend/SC.scala:71:21
reg [38:0] s1_pc; // src/main/scala/xiangshan/frontend/SC.scala:99:24
wire per_br_update_way_mask_0_0 =
io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1
& io_update_pc[1] & ~io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{69,78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42
wire per_br_update_way_mask_0_1 =
io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1
& io_update_pc[1] & io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:{69,78}, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42
wire per_br_update_way_mask_1_0 =
io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1
& ~(io_update_pc[1]) & ~io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92
wire per_br_update_way_mask_1_1 =
io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1
& ~(io_update_pc[1]) & io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:78, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92
wire [7:0] update_idx =
{io_update_pc[8:5], io_update_pc[4:1] ^ io_update_folded_hist_hist_12_folded_hist}; // src/main/scala/xiangshan/frontend/SC.scala:86:{31,40}, :117:42
wire ctrPos =
~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42
wire [5:0] oldCtr =
(~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit)
& (ctrPos
? ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1]
& _wrbypasses_1_io_hit_data_1_valid
: ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1]
& _wrbypasses_1_io_hit_data_0_valid)
? (ctrPos
? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits)
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0)
: (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0))
: (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0)
| (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42
wire taken =
~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42
wire [5:0] per_br_update_wdata_packed_0_1 =
oldCtr == 6'h1F & taken
? 6'h1F
: oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:102:27, :103:30, :104:{8,21}, :105:{10,26,29}, :106:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21
wire ctrPos_1 =
io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92
wire [5:0] oldCtr_1 =
(io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit)
& (ctrPos_1
? io_update_pc[1] & _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1])
& _wrbypasses_1_io_hit_data_1_valid
: io_update_pc[1] & _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _wrbypasses_1_io_hit_data_0_valid)
? (ctrPos_1
? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0)
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits)
: (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0)
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits))
: (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0)
| (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92
wire taken_1 =
io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92
wire [5:0] per_br_update_wdata_packed_1_1 =
oldCtr_1 == 6'h1F & taken_1
? 6'h1F
: oldCtr_1 == 6'h20 & ~taken_1
? 6'h20
: taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:102:27, :103:30, :104:{8,21}, :105:{10,26,29}, :106:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21
wire [5:0] _GEN =
(io_update_pc[1] ? 6'h0 : per_br_update_wdata_packed_0_1)
| (io_update_pc[1] ? per_br_update_wdata_packed_1_1 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:104:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42
wire [5:0] _GEN_0 =
(io_update_pc[1] ? per_br_update_wdata_packed_0_1 : 6'h0)
| (io_update_pc[1] ? 6'h0 : per_br_update_wdata_packed_1_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:104:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42
always @(posedge clock) begin
if (io_req_valid) // src/main/scala/xiangshan/frontend/SC.scala:68:14
s1_pc <= io_req_bits_pc; // src/main/scala/xiangshan/frontend/SC.scala:99:24
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:1]; // src/main/scala/xiangshan/frontend/SC.scala:66:7
initial begin // src/main/scala/xiangshan/frontend/SC.scala:66:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/SC.scala:66:7
for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
_RANDOM[i[0]] = `RANDOM; // src/main/scala/xiangshan/frontend/SC.scala:66:7
end // src/main/scala/xiangshan/frontend/SC.scala:66:7
s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][14:0]}; // src/main/scala/xiangshan/frontend/SC.scala:66:7, :99:24
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
SRAMTemplate_31 table_0 ( // src/main/scala/xiangshan/frontend/SC.scala:71:21
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid),
.io_r_req_bits_setIdx
({io_req_bits_pc[8:5],
io_req_bits_pc[4:1] ^ io_req_bits_folded_hist_hist_12_folded_hist}), // src/main/scala/xiangshan/frontend/SC.scala:86:{12,31,40}
.io_r_resp_data_0 (_table_io_r_resp_data_0),
.io_r_resp_data_1 (_table_io_r_resp_data_1),
.io_r_resp_data_2 (_table_io_r_resp_data_2),
.io_r_resp_data_3 (_table_io_r_resp_data_3),
.io_w_req_valid (io_update_mask_0 | io_update_mask_1), // src/main/scala/xiangshan/frontend/SC.scala:130:36
.io_w_req_bits_setIdx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:40
.io_w_req_bits_data_0 (per_br_update_wdata_packed_0_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8
.io_w_req_bits_data_1 (per_br_update_wdata_packed_0_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8
.io_w_req_bits_data_2 (per_br_update_wdata_packed_1_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8
.io_w_req_bits_data_3 (per_br_update_wdata_packed_1_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8
.io_w_req_bits_waymask
({per_br_update_way_mask_1_1,
per_br_update_way_mask_1_0,
per_br_update_way_mask_0_1,
per_br_update_way_mask_0_0}) // src/main/scala/xiangshan/frontend/SC.scala:121:15, :124:15, :133:29
);
WrBypass_33 wrbypasses_0 ( // src/main/scala/xiangshan/frontend/SC.scala:139:42
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0),
.io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:40
.io_write_data_0 (_GEN), // src/main/scala/chisel3/util/Mux.scala:30:73
.io_write_data_1 (_GEN), // src/main/scala/chisel3/util/Mux.scala:30:73
.io_write_way_mask_0
(~(io_update_pc[1]) & per_br_update_way_mask_0_0 | io_update_pc[1]
& per_br_update_way_mask_1_0), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42
.io_write_way_mask_1
(~(io_update_pc[1]) & per_br_update_way_mask_0_1 | io_update_pc[1]
& per_br_update_way_mask_1_1), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42
.io_hit (_wrbypasses_0_io_hit),
.io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits)
);
WrBypass_33 wrbypasses_1 ( // src/main/scala/xiangshan/frontend/SC.scala:139:42
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1),
.io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:40
.io_write_data_0 (_GEN_0), // src/main/scala/chisel3/util/Mux.scala:30:73
.io_write_data_1 (_GEN_0), // src/main/scala/chisel3/util/Mux.scala:30:73
.io_write_way_mask_0
(io_update_pc[1] & per_br_update_way_mask_0_0 | ~(io_update_pc[1])
& per_br_update_way_mask_1_0), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92
.io_write_way_mask_1
(io_update_pc[1] & per_br_update_way_mask_0_1 | ~(io_update_pc[1])
& per_br_update_way_mask_1_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92
.io_hit (_wrbypasses_1_io_hit),
.io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypasses_1_io_hit_data_1_bits)
);
assign io_resp_ctrs_0_0 =
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0)
| (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42
assign io_resp_ctrs_0_1 =
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1)
| (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42
assign io_resp_ctrs_1_0 =
(s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0)
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42
assign io_resp_ctrs_1_1 =
(s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0)
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42
endmodule

257
src/TageSC/SCTable_2.sv Normal file
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@ -0,0 +1,257 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SCTable_2( // src/main/scala/xiangshan/frontend/SC.scala:66:7
input clock,
input reset,
input io_req_valid, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input [7:0] io_req_bits_folded_hist_hist_11_folded_hist, // src/main/scala/xiangshan/frontend/SC.scala:68:14
output [5:0] io_resp_ctrs_0_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14
output [5:0] io_resp_ctrs_0_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14
output [5:0] io_resp_ctrs_1_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14
output [5:0] io_resp_ctrs_1_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input [7:0] io_update_folded_hist_hist_11_folded_hist, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input io_update_mask_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input io_update_mask_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input [5:0] io_update_oldCtrs_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input [5:0] io_update_oldCtrs_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input io_update_tagePreds_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input io_update_tagePreds_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input io_update_takens_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input io_update_takens_1 // src/main/scala/xiangshan/frontend/SC.scala:68:14
);
wire _wrbypasses_1_io_hit; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire _wrbypasses_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire [5:0] _wrbypasses_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire _wrbypasses_1_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire [5:0] _wrbypasses_1_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire _wrbypasses_0_io_hit; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire _wrbypasses_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire [5:0] _wrbypasses_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire _wrbypasses_0_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire [5:0] _wrbypasses_0_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire [5:0] _table_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/SC.scala:71:21
wire [5:0] _table_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/SC.scala:71:21
wire [5:0] _table_io_r_resp_data_2; // src/main/scala/xiangshan/frontend/SC.scala:71:21
wire [5:0] _table_io_r_resp_data_3; // src/main/scala/xiangshan/frontend/SC.scala:71:21
reg [38:0] s1_pc; // src/main/scala/xiangshan/frontend/SC.scala:99:24
wire per_br_update_way_mask_0_0 =
io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1
& io_update_pc[1] & ~io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{69,78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42
wire per_br_update_way_mask_0_1 =
io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1
& io_update_pc[1] & io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:{69,78}, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42
wire per_br_update_way_mask_1_0 =
io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1
& ~(io_update_pc[1]) & ~io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92
wire per_br_update_way_mask_1_1 =
io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1
& ~(io_update_pc[1]) & io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:78, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92
wire [7:0] update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/SC.scala:86:31, :117:42
wire ctrPos =
~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42
wire [5:0] oldCtr =
(~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit)
& (ctrPos
? ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1]
& _wrbypasses_1_io_hit_data_1_valid
: ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1]
& _wrbypasses_1_io_hit_data_0_valid)
? (ctrPos
? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits)
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0)
: (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0))
: (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0)
| (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42
wire taken =
~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42
wire [5:0] per_br_update_wdata_packed_0_1 =
oldCtr == 6'h1F & taken
? 6'h1F
: oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:102:27, :103:30, :104:{8,21}, :105:{10,26,29}, :106:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21
wire ctrPos_1 =
io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92
wire [5:0] oldCtr_1 =
(io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit)
& (ctrPos_1
? io_update_pc[1] & _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1])
& _wrbypasses_1_io_hit_data_1_valid
: io_update_pc[1] & _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _wrbypasses_1_io_hit_data_0_valid)
? (ctrPos_1
? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0)
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits)
: (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0)
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits))
: (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0)
| (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92
wire taken_1 =
io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92
wire [5:0] per_br_update_wdata_packed_1_1 =
oldCtr_1 == 6'h1F & taken_1
? 6'h1F
: oldCtr_1 == 6'h20 & ~taken_1
? 6'h20
: taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:102:27, :103:30, :104:{8,21}, :105:{10,26,29}, :106:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21
wire [5:0] _GEN =
(io_update_pc[1] ? 6'h0 : per_br_update_wdata_packed_0_1)
| (io_update_pc[1] ? per_br_update_wdata_packed_1_1 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:104:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42
wire [5:0] _GEN_0 =
(io_update_pc[1] ? per_br_update_wdata_packed_0_1 : 6'h0)
| (io_update_pc[1] ? 6'h0 : per_br_update_wdata_packed_1_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:104:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42
always @(posedge clock) begin
if (io_req_valid) // src/main/scala/xiangshan/frontend/SC.scala:68:14
s1_pc <= io_req_bits_pc; // src/main/scala/xiangshan/frontend/SC.scala:99:24
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:1]; // src/main/scala/xiangshan/frontend/SC.scala:66:7
initial begin // src/main/scala/xiangshan/frontend/SC.scala:66:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/SC.scala:66:7
for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
_RANDOM[i[0]] = `RANDOM; // src/main/scala/xiangshan/frontend/SC.scala:66:7
end // src/main/scala/xiangshan/frontend/SC.scala:66:7
s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][14:0]}; // src/main/scala/xiangshan/frontend/SC.scala:66:7, :99:24
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
SRAMTemplate_31 table_0 ( // src/main/scala/xiangshan/frontend/SC.scala:71:21
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid),
.io_r_req_bits_setIdx
(io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_11_folded_hist), // src/main/scala/xiangshan/frontend/SC.scala:86:{12,31}
.io_r_resp_data_0 (_table_io_r_resp_data_0),
.io_r_resp_data_1 (_table_io_r_resp_data_1),
.io_r_resp_data_2 (_table_io_r_resp_data_2),
.io_r_resp_data_3 (_table_io_r_resp_data_3),
.io_w_req_valid (io_update_mask_0 | io_update_mask_1), // src/main/scala/xiangshan/frontend/SC.scala:130:36
.io_w_req_bits_setIdx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:31
.io_w_req_bits_data_0 (per_br_update_wdata_packed_0_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8
.io_w_req_bits_data_1 (per_br_update_wdata_packed_0_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8
.io_w_req_bits_data_2 (per_br_update_wdata_packed_1_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8
.io_w_req_bits_data_3 (per_br_update_wdata_packed_1_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8
.io_w_req_bits_waymask
({per_br_update_way_mask_1_1,
per_br_update_way_mask_1_0,
per_br_update_way_mask_0_1,
per_br_update_way_mask_0_0}) // src/main/scala/xiangshan/frontend/SC.scala:121:15, :124:15, :133:29
);
WrBypass_33 wrbypasses_0 ( // src/main/scala/xiangshan/frontend/SC.scala:139:42
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0),
.io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:31
.io_write_data_0 (_GEN), // src/main/scala/chisel3/util/Mux.scala:30:73
.io_write_data_1 (_GEN), // src/main/scala/chisel3/util/Mux.scala:30:73
.io_write_way_mask_0
(~(io_update_pc[1]) & per_br_update_way_mask_0_0 | io_update_pc[1]
& per_br_update_way_mask_1_0), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42
.io_write_way_mask_1
(~(io_update_pc[1]) & per_br_update_way_mask_0_1 | io_update_pc[1]
& per_br_update_way_mask_1_1), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42
.io_hit (_wrbypasses_0_io_hit),
.io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits)
);
WrBypass_33 wrbypasses_1 ( // src/main/scala/xiangshan/frontend/SC.scala:139:42
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1),
.io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:31
.io_write_data_0 (_GEN_0), // src/main/scala/chisel3/util/Mux.scala:30:73
.io_write_data_1 (_GEN_0), // src/main/scala/chisel3/util/Mux.scala:30:73
.io_write_way_mask_0
(io_update_pc[1] & per_br_update_way_mask_0_0 | ~(io_update_pc[1])
& per_br_update_way_mask_1_0), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92
.io_write_way_mask_1
(io_update_pc[1] & per_br_update_way_mask_0_1 | ~(io_update_pc[1])
& per_br_update_way_mask_1_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92
.io_hit (_wrbypasses_1_io_hit),
.io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypasses_1_io_hit_data_1_bits)
);
assign io_resp_ctrs_0_0 =
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0)
| (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42
assign io_resp_ctrs_0_1 =
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1)
| (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42
assign io_resp_ctrs_1_0 =
(s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0)
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42
assign io_resp_ctrs_1_1 =
(s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0)
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42
endmodule

257
src/TageSC/SCTable_3.sv Normal file
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@ -0,0 +1,257 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SCTable_3( // src/main/scala/xiangshan/frontend/SC.scala:66:7
input clock,
input reset,
input io_req_valid, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input [7:0] io_req_bits_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/SC.scala:68:14
output [5:0] io_resp_ctrs_0_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14
output [5:0] io_resp_ctrs_0_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14
output [5:0] io_resp_ctrs_1_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14
output [5:0] io_resp_ctrs_1_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input [7:0] io_update_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input io_update_mask_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input io_update_mask_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input [5:0] io_update_oldCtrs_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input [5:0] io_update_oldCtrs_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input io_update_tagePreds_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input io_update_tagePreds_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input io_update_takens_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14
input io_update_takens_1 // src/main/scala/xiangshan/frontend/SC.scala:68:14
);
wire _wrbypasses_1_io_hit; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire _wrbypasses_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire [5:0] _wrbypasses_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire _wrbypasses_1_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire [5:0] _wrbypasses_1_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire _wrbypasses_0_io_hit; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire _wrbypasses_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire [5:0] _wrbypasses_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire _wrbypasses_0_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire [5:0] _wrbypasses_0_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42
wire [5:0] _table_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/SC.scala:71:21
wire [5:0] _table_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/SC.scala:71:21
wire [5:0] _table_io_r_resp_data_2; // src/main/scala/xiangshan/frontend/SC.scala:71:21
wire [5:0] _table_io_r_resp_data_3; // src/main/scala/xiangshan/frontend/SC.scala:71:21
reg [38:0] s1_pc; // src/main/scala/xiangshan/frontend/SC.scala:99:24
wire per_br_update_way_mask_0_0 =
io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1
& io_update_pc[1] & ~io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{69,78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42
wire per_br_update_way_mask_0_1 =
io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1
& io_update_pc[1] & io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:{69,78}, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42
wire per_br_update_way_mask_1_0 =
io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1
& ~(io_update_pc[1]) & ~io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92
wire per_br_update_way_mask_1_1 =
io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1
& ~(io_update_pc[1]) & io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:78, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92
wire [7:0] update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/SC.scala:86:31, :117:42
wire ctrPos =
~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42
wire [5:0] oldCtr =
(~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit)
& (ctrPos
? ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1]
& _wrbypasses_1_io_hit_data_1_valid
: ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1]
& _wrbypasses_1_io_hit_data_0_valid)
? (ctrPos
? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits)
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0)
: (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0))
: (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0)
| (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42
wire taken =
~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42
wire [5:0] per_br_update_wdata_packed_0_1 =
oldCtr == 6'h1F & taken
? 6'h1F
: oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:102:27, :103:30, :104:{8,21}, :105:{10,26,29}, :106:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21
wire ctrPos_1 =
io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92
wire [5:0] oldCtr_1 =
(io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit)
& (ctrPos_1
? io_update_pc[1] & _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1])
& _wrbypasses_1_io_hit_data_1_valid
: io_update_pc[1] & _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _wrbypasses_1_io_hit_data_0_valid)
? (ctrPos_1
? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0)
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits)
: (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0)
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits))
: (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0)
| (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92
wire taken_1 =
io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92
wire [5:0] per_br_update_wdata_packed_1_1 =
oldCtr_1 == 6'h1F & taken_1
? 6'h1F
: oldCtr_1 == 6'h20 & ~taken_1
? 6'h20
: taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:102:27, :103:30, :104:{8,21}, :105:{10,26,29}, :106:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21
wire [5:0] _GEN =
(io_update_pc[1] ? 6'h0 : per_br_update_wdata_packed_0_1)
| (io_update_pc[1] ? per_br_update_wdata_packed_1_1 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:104:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42
wire [5:0] _GEN_0 =
(io_update_pc[1] ? per_br_update_wdata_packed_0_1 : 6'h0)
| (io_update_pc[1] ? 6'h0 : per_br_update_wdata_packed_1_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:104:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42
always @(posedge clock) begin
if (io_req_valid) // src/main/scala/xiangshan/frontend/SC.scala:68:14
s1_pc <= io_req_bits_pc; // src/main/scala/xiangshan/frontend/SC.scala:99:24
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:1]; // src/main/scala/xiangshan/frontend/SC.scala:66:7
initial begin // src/main/scala/xiangshan/frontend/SC.scala:66:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/SC.scala:66:7
for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
_RANDOM[i[0]] = `RANDOM; // src/main/scala/xiangshan/frontend/SC.scala:66:7
end // src/main/scala/xiangshan/frontend/SC.scala:66:7
s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][14:0]}; // src/main/scala/xiangshan/frontend/SC.scala:66:7, :99:24
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
SRAMTemplate_31 table_0 ( // src/main/scala/xiangshan/frontend/SC.scala:71:21
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid),
.io_r_req_bits_setIdx
(io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_2_folded_hist), // src/main/scala/xiangshan/frontend/SC.scala:86:{12,31}
.io_r_resp_data_0 (_table_io_r_resp_data_0),
.io_r_resp_data_1 (_table_io_r_resp_data_1),
.io_r_resp_data_2 (_table_io_r_resp_data_2),
.io_r_resp_data_3 (_table_io_r_resp_data_3),
.io_w_req_valid (io_update_mask_0 | io_update_mask_1), // src/main/scala/xiangshan/frontend/SC.scala:130:36
.io_w_req_bits_setIdx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:31
.io_w_req_bits_data_0 (per_br_update_wdata_packed_0_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8
.io_w_req_bits_data_1 (per_br_update_wdata_packed_0_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8
.io_w_req_bits_data_2 (per_br_update_wdata_packed_1_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8
.io_w_req_bits_data_3 (per_br_update_wdata_packed_1_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8
.io_w_req_bits_waymask
({per_br_update_way_mask_1_1,
per_br_update_way_mask_1_0,
per_br_update_way_mask_0_1,
per_br_update_way_mask_0_0}) // src/main/scala/xiangshan/frontend/SC.scala:121:15, :124:15, :133:29
);
WrBypass_33 wrbypasses_0 ( // src/main/scala/xiangshan/frontend/SC.scala:139:42
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0),
.io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:31
.io_write_data_0 (_GEN), // src/main/scala/chisel3/util/Mux.scala:30:73
.io_write_data_1 (_GEN), // src/main/scala/chisel3/util/Mux.scala:30:73
.io_write_way_mask_0
(~(io_update_pc[1]) & per_br_update_way_mask_0_0 | io_update_pc[1]
& per_br_update_way_mask_1_0), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42
.io_write_way_mask_1
(~(io_update_pc[1]) & per_br_update_way_mask_0_1 | io_update_pc[1]
& per_br_update_way_mask_1_1), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42
.io_hit (_wrbypasses_0_io_hit),
.io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits)
);
WrBypass_33 wrbypasses_1 ( // src/main/scala/xiangshan/frontend/SC.scala:139:42
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1),
.io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:31
.io_write_data_0 (_GEN_0), // src/main/scala/chisel3/util/Mux.scala:30:73
.io_write_data_1 (_GEN_0), // src/main/scala/chisel3/util/Mux.scala:30:73
.io_write_way_mask_0
(io_update_pc[1] & per_br_update_way_mask_0_0 | ~(io_update_pc[1])
& per_br_update_way_mask_1_0), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92
.io_write_way_mask_1
(io_update_pc[1] & per_br_update_way_mask_0_1 | ~(io_update_pc[1])
& per_br_update_way_mask_1_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92
.io_hit (_wrbypasses_1_io_hit),
.io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypasses_1_io_hit_data_1_bits)
);
assign io_resp_ctrs_0_0 =
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0)
| (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42
assign io_resp_ctrs_0_1 =
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1)
| (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42
assign io_resp_ctrs_1_0 =
(s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0)
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42
assign io_resp_ctrs_1_1 =
(s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0)
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42
endmodule

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src/TageSC/SRAMTemplate_10.sv Normal file
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@ -0,0 +1,277 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SRAMTemplate_10( // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
input clock,
input reset,
output io_r_req_ready, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [7:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_2, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_3, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_4, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_5, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_6, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_7, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_8, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_9, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_10, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_11, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_12, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_13, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_14, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_15, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [7:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_2, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_3, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_4, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_5, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_6, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_7, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_8, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_9, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_10, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_11, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_12, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_13, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_14, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_bits_data_15, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [15:0] io_w_req_bits_waymask, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input extra_reset // utility/src/main/scala/utility/SRAMTemplate.scala:102:44
);
wire wdata_15; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire wdata_14; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire wdata_13; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire wdata_12; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire wdata_11; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire wdata_10; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire wdata_9; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire wdata_8; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire wdata_7; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire wdata_6; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire wdata_5; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire wdata_4; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire wdata_3; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire wdata_2; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire wdata_1; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire wdata_0; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [7:0] array_MPORT_addr; // utility/src/main/scala/utility/SRAMTemplate.scala:125:19
wire array_raw_rdata_en; // utility/src/main/scala/utility/SRAMTemplate.scala:123:38
wire array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52
wire [15:0] _array_RW0_rdata; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
reg _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30
reg [7:0] _resetSet; // src/main/scala/chisel3/util/Counter.scala:61:40
assign array_MPORT_en = io_w_req_valid | _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :122:52
assign array_raw_rdata_en = io_r_req_valid & ~array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52, :123:{38,41}
assign array_MPORT_addr = _resetState ? _resetSet : io_w_req_bits_setIdx; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :125:19
assign wdata_0 = ~_resetState & io_w_req_bits_data_0; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign wdata_1 = ~_resetState & io_w_req_bits_data_1; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign wdata_2 = ~_resetState & io_w_req_bits_data_2; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign wdata_3 = ~_resetState & io_w_req_bits_data_3; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign wdata_4 = ~_resetState & io_w_req_bits_data_4; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign wdata_5 = ~_resetState & io_w_req_bits_data_5; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign wdata_6 = ~_resetState & io_w_req_bits_data_6; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign wdata_7 = ~_resetState & io_w_req_bits_data_7; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign wdata_8 = ~_resetState & io_w_req_bits_data_8; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign wdata_9 = ~_resetState & io_w_req_bits_data_9; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign wdata_10 = ~_resetState & io_w_req_bits_data_10; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign wdata_11 = ~_resetState & io_w_req_bits_data_11; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign wdata_12 = ~_resetState & io_w_req_bits_data_12; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign wdata_13 = ~_resetState & io_w_req_bits_data_13; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign wdata_14 = ~_resetState & io_w_req_bits_data_14; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
assign wdata_15 = ~_resetState & io_w_req_bits_data_15; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26
reg rdata_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:153:59
reg rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82
reg rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82
reg rdata_hold_data_2; // utility/src/main/scala/utility/Hold.scala:24:82
reg rdata_hold_data_3; // utility/src/main/scala/utility/Hold.scala:24:82
reg rdata_hold_data_4; // utility/src/main/scala/utility/Hold.scala:24:82
reg rdata_hold_data_5; // utility/src/main/scala/utility/Hold.scala:24:82
reg rdata_hold_data_6; // utility/src/main/scala/utility/Hold.scala:24:82
reg rdata_hold_data_7; // utility/src/main/scala/utility/Hold.scala:24:82
reg rdata_hold_data_8; // utility/src/main/scala/utility/Hold.scala:24:82
reg rdata_hold_data_9; // utility/src/main/scala/utility/Hold.scala:24:82
reg rdata_hold_data_10; // utility/src/main/scala/utility/Hold.scala:24:82
reg rdata_hold_data_11; // utility/src/main/scala/utility/Hold.scala:24:82
reg rdata_hold_data_12; // utility/src/main/scala/utility/Hold.scala:24:82
reg rdata_hold_data_13; // utility/src/main/scala/utility/Hold.scala:24:82
reg rdata_hold_data_14; // utility/src/main/scala/utility/Hold.scala:24:82
reg rdata_hold_data_15; // utility/src/main/scala/utility/Hold.scala:24:82
always @(posedge clock or posedge reset) begin
if (reset) begin
_resetState <= 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30
_resetSet <= 8'h0; // src/main/scala/chisel3/util/Counter.scala:61:40
end
else begin
_resetState <= extra_reset | ~(_resetState & (&_resetSet)) & _resetState; // src/main/scala/chisel3/util/Counter.scala:61:40, :73:24, :117:24, :118:{16,23}, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :111:{24,38}, :113:30, :114:21
if (_resetState) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30
_resetSet <= 8'(_resetSet + 8'h1); // src/main/scala/chisel3/util/Counter.scala:61:40, :77:24
end
end // always @(posedge, posedge)
always @(posedge clock) begin
rdata_REG <= array_raw_rdata_en; // utility/src/main/scala/utility/SRAMTemplate.scala:123:38, :153:59
if (rdata_REG) begin // utility/src/main/scala/utility/SRAMTemplate.scala:153:59
rdata_hold_data_0 <= _array_RW0_rdata[0]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26
rdata_hold_data_1 <= _array_RW0_rdata[1]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26
rdata_hold_data_2 <= _array_RW0_rdata[2]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26
rdata_hold_data_3 <= _array_RW0_rdata[3]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26
rdata_hold_data_4 <= _array_RW0_rdata[4]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26
rdata_hold_data_5 <= _array_RW0_rdata[5]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26
rdata_hold_data_6 <= _array_RW0_rdata[6]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26
rdata_hold_data_7 <= _array_RW0_rdata[7]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26
rdata_hold_data_8 <= _array_RW0_rdata[8]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26
rdata_hold_data_9 <= _array_RW0_rdata[9]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26
rdata_hold_data_10 <= _array_RW0_rdata[10]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26
rdata_hold_data_11 <= _array_RW0_rdata[11]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26
rdata_hold_data_12 <= _array_RW0_rdata[12]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26
rdata_hold_data_13 <= _array_RW0_rdata[13]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26
rdata_hold_data_14 <= _array_RW0_rdata[14]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26
rdata_hold_data_15 <= _array_RW0_rdata[15]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:33]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
for (logic [5:0] i = 6'h0; i < 6'h22; i += 6'h1) begin
_RANDOM[i] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
end // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
_resetState = _RANDOM[6'h0][0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30
_resetSet = _RANDOM[6'h0][8:1]; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30
rdata_REG = _RANDOM[6'h21][10]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59
rdata_hold_data_0 = _RANDOM[6'h21][11]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59
rdata_hold_data_1 = _RANDOM[6'h21][12]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59
rdata_hold_data_2 = _RANDOM[6'h21][13]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59
rdata_hold_data_3 = _RANDOM[6'h21][14]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59
rdata_hold_data_4 = _RANDOM[6'h21][15]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59
rdata_hold_data_5 = _RANDOM[6'h21][16]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59
rdata_hold_data_6 = _RANDOM[6'h21][17]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59
rdata_hold_data_7 = _RANDOM[6'h21][18]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59
rdata_hold_data_8 = _RANDOM[6'h21][19]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59
rdata_hold_data_9 = _RANDOM[6'h21][20]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59
rdata_hold_data_10 = _RANDOM[6'h21][21]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59
rdata_hold_data_11 = _RANDOM[6'h21][22]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59
rdata_hold_data_12 = _RANDOM[6'h21][23]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59
rdata_hold_data_13 = _RANDOM[6'h21][24]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59
rdata_hold_data_14 = _RANDOM[6'h21][25]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59
rdata_hold_data_15 = _RANDOM[6'h21][26]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59
`endif // RANDOMIZE_REG_INIT
if (reset) begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
_resetState = 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30
_resetSet = 8'h0; // src/main/scala/chisel3/util/Counter.scala:61:40
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
array_4 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
.RW0_addr (array_MPORT_en ? array_MPORT_addr : io_r_req_bits_setIdx), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :125:19
.RW0_en (array_raw_rdata_en | array_MPORT_en), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :123:38
.RW0_clk (clock),
.RW0_wmode (array_MPORT_en), // utility/src/main/scala/utility/SRAMTemplate.scala:122:52
.RW0_wdata
({wdata_15,
wdata_14,
wdata_13,
wdata_12,
wdata_11,
wdata_10,
wdata_9,
wdata_8,
wdata_7,
wdata_6,
wdata_5,
wdata_4,
wdata_3,
wdata_2,
wdata_1,
wdata_0}), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :126:26
.RW0_rdata (_array_RW0_rdata),
.RW0_wmask (_resetState ? 16'hFFFF : io_w_req_bits_waymask) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :127:{20,37}
);
assign io_r_req_ready = ~_resetState & ~array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :122:52, :123:41, :157:{21,33}
assign io_r_resp_data_0 = rdata_REG ? _array_RW0_rdata[0] : rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59
assign io_r_resp_data_1 = rdata_REG ? _array_RW0_rdata[1] : rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59
assign io_r_resp_data_2 = rdata_REG ? _array_RW0_rdata[2] : rdata_hold_data_2; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59
assign io_r_resp_data_3 = rdata_REG ? _array_RW0_rdata[3] : rdata_hold_data_3; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59
assign io_r_resp_data_4 = rdata_REG ? _array_RW0_rdata[4] : rdata_hold_data_4; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59
assign io_r_resp_data_5 = rdata_REG ? _array_RW0_rdata[5] : rdata_hold_data_5; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59
assign io_r_resp_data_6 = rdata_REG ? _array_RW0_rdata[6] : rdata_hold_data_6; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59
assign io_r_resp_data_7 = rdata_REG ? _array_RW0_rdata[7] : rdata_hold_data_7; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59
assign io_r_resp_data_8 = rdata_REG ? _array_RW0_rdata[8] : rdata_hold_data_8; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59
assign io_r_resp_data_9 = rdata_REG ? _array_RW0_rdata[9] : rdata_hold_data_9; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59
assign io_r_resp_data_10 = rdata_REG ? _array_RW0_rdata[10] : rdata_hold_data_10; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59
assign io_r_resp_data_11 = rdata_REG ? _array_RW0_rdata[11] : rdata_hold_data_11; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59
assign io_r_resp_data_12 = rdata_REG ? _array_RW0_rdata[12] : rdata_hold_data_12; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59
assign io_r_resp_data_13 = rdata_REG ? _array_RW0_rdata[13] : rdata_hold_data_13; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59
assign io_r_resp_data_14 = rdata_REG ? _array_RW0_rdata[14] : rdata_hold_data_14; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59
assign io_r_resp_data_15 = rdata_REG ? _array_RW0_rdata[15] : rdata_hold_data_15; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59
endmodule

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@ -0,0 +1,174 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SRAMTemplate_11( // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
input clock,
input reset,
output io_r_req_ready, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [8:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [7:0] io_r_resp_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [2:0] io_r_resp_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output io_r_resp_data_1_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [7:0] io_r_resp_data_1_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [2:0] io_r_resp_data_1_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [8:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [7:0] io_w_req_bits_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [2:0] io_w_req_bits_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [7:0] io_w_req_bits_data_1_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [2:0] io_w_req_bits_data_1_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [1:0] io_w_req_bits_waymask // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
);
wire [2:0] _wdata_T_1_ctr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [7:0] _wdata_T_1_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_1_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :98:14, :126:26
wire [2:0] _wdata_T_0_ctr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [7:0] _wdata_T_0_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire _wdata_T_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :98:14, :126:26
wire [8:0] array_MPORT_addr; // utility/src/main/scala/utility/SRAMTemplate.scala:125:19
wire array_raw_rdata_en; // utility/src/main/scala/utility/SRAMTemplate.scala:123:38
wire array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52
wire [23:0] _array_RW0_rdata; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
reg _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30
reg [8:0] _resetSet; // src/main/scala/chisel3/util/Counter.scala:61:40
assign array_MPORT_en = io_w_req_valid | _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :122:52
assign array_raw_rdata_en = io_r_req_valid & ~array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52, :123:{38,41}
assign array_MPORT_addr = _resetState ? _resetSet : io_w_req_bits_setIdx; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :125:19
assign _wdata_T_0_valid = ~_resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :98:14, :109:30, :126:26
assign _wdata_T_0_tag = _resetState ? 8'h0 : io_w_req_bits_data_0_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_0_ctr = _resetState ? 3'h0 : io_w_req_bits_data_0_ctr; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :126:26
assign _wdata_T_1_valid = ~_resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :98:14, :109:30, :126:26
assign _wdata_T_1_tag = _resetState ? 8'h0 : io_w_req_bits_data_1_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_1_ctr = _resetState ? 3'h0 : io_w_req_bits_data_1_ctr; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :126:26
reg rdata_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:153:59
reg [11:0] rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82
reg [11:0] rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82
wire [11:0] _rdata_WIRE = rdata_REG ? _array_RW0_rdata[11:0] : rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :153:59
wire [11:0] _rdata_WIRE_1 = rdata_REG ? _array_RW0_rdata[23:12] : rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :153:59
always @(posedge clock or posedge reset) begin
if (reset) begin
_resetState <= 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:98:14, :109:30
_resetSet <= 9'h0; // src/main/scala/chisel3/util/Counter.scala:61:40
end
else begin
_resetState <= ~(_resetState & (&_resetSet)) & _resetState; // src/main/scala/chisel3/util/Counter.scala:61:40, :73:24, :117:24, :118:{16,23}, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :111:{24,38}
if (_resetState) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30
_resetSet <= 9'(_resetSet + 9'h1); // src/main/scala/chisel3/util/Counter.scala:61:40, :77:24
end
end // always @(posedge, posedge)
always @(posedge clock) begin
rdata_REG <= array_raw_rdata_en; // utility/src/main/scala/utility/SRAMTemplate.scala:123:38, :153:59
if (rdata_REG) begin // utility/src/main/scala/utility/SRAMTemplate.scala:153:59
rdata_hold_data_0 <= _array_RW0_rdata[11:0]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26
rdata_hold_data_1 <= _array_RW0_rdata[23:12]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:5]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
for (logic [2:0] i = 3'h0; i < 3'h6; i += 3'h1) begin
_RANDOM[i] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
end // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
_resetState = _RANDOM[3'h0][0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30
_resetSet = _RANDOM[3'h0][9:1]; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30
rdata_REG = _RANDOM[3'h4][31]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59
rdata_hold_data_0 = _RANDOM[3'h5][11:0]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7
rdata_hold_data_1 = _RANDOM[3'h5][23:12]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`endif // RANDOMIZE_REG_INIT
if (reset) begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
_resetState = 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:98:14, :109:30
_resetSet = 9'h0; // src/main/scala/chisel3/util/Counter.scala:61:40
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
array_5 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
.RW0_addr (array_MPORT_en ? array_MPORT_addr : io_r_req_bits_setIdx), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :125:19
.RW0_en (array_raw_rdata_en | array_MPORT_en), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :123:38
.RW0_clk (clock),
.RW0_wmode (array_MPORT_en), // utility/src/main/scala/utility/SRAMTemplate.scala:122:52
.RW0_wdata
({_wdata_T_1_valid,
_wdata_T_1_tag,
_wdata_T_1_ctr,
_wdata_T_0_valid,
_wdata_T_0_tag,
_wdata_T_0_ctr}), // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :98:14, :105:26, :126:26
.RW0_rdata (_array_RW0_rdata),
.RW0_wmask (_resetState ? 2'h3 : io_w_req_bits_waymask) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :127:{20,37}
);
assign io_r_req_ready = ~_resetState & ~array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :122:52, :123:41, :157:{21,33}
assign io_r_resp_data_0_valid = _rdata_WIRE[11]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45
assign io_r_resp_data_0_tag = _rdata_WIRE[10:3]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45
assign io_r_resp_data_0_ctr = _rdata_WIRE[2:0]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45
assign io_r_resp_data_1_valid = _rdata_WIRE_1[11]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45
assign io_r_resp_data_1_tag = _rdata_WIRE_1[10:3]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45
assign io_r_resp_data_1_ctr = _rdata_WIRE_1[2:0]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45
endmodule

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@ -0,0 +1,209 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SRAMTemplate_30( // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
input clock,
input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [8:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [1:0] io_r_resp_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [1:0] io_r_resp_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [1:0] io_r_resp_data_2, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [1:0] io_r_resp_data_3, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [1:0] io_r_resp_data_4, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [1:0] io_r_resp_data_5, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [1:0] io_r_resp_data_6, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [1:0] io_r_resp_data_7, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [8:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [1:0] io_w_req_bits_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [1:0] io_w_req_bits_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [1:0] io_w_req_bits_data_2, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [1:0] io_w_req_bits_data_3, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [1:0] io_w_req_bits_data_4, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [1:0] io_w_req_bits_data_5, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [1:0] io_w_req_bits_data_6, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [1:0] io_w_req_bits_data_7, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [7:0] io_w_req_bits_waymask // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
);
wire [15:0] _array_R0_data; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
reg [1:0] bypass_wdata_REG_0; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54
reg [1:0] bypass_wdata_REG_1; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54
reg [1:0] bypass_wdata_REG_2; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54
reg [1:0] bypass_wdata_REG_3; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54
reg [1:0] bypass_wdata_REG_4; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54
reg [1:0] bypass_wdata_REG_5; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54
reg [1:0] bypass_wdata_REG_6; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54
reg [1:0] bypass_wdata_REG_7; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54
reg bypass_mask_need_check; // utility/src/main/scala/utility/SRAMTemplate.scala:135:29
reg [8:0] bypass_mask_waddr_reg; // utility/src/main/scala/utility/SRAMTemplate.scala:136:28
reg [8:0] bypass_mask_raddr_reg; // utility/src/main/scala/utility/SRAMTemplate.scala:137:28
reg [7:0] bypass_mask_bypass_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:139:76
wire [7:0] bypass_mask =
{8{bypass_mask_need_check & bypass_mask_waddr_reg == bypass_mask_raddr_reg}}
& bypass_mask_bypass_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:135:29, :136:28, :137:28, :139:{22,39,52,67,76}
wire [1:0] mem_rdata_0 = bypass_mask[0] ? bypass_wdata_REG_0 : _array_R0_data[1:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30
wire [1:0] mem_rdata_1 = bypass_mask[1] ? bypass_wdata_REG_1 : _array_R0_data[3:2]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30
wire [1:0] mem_rdata_2 = bypass_mask[2] ? bypass_wdata_REG_2 : _array_R0_data[5:4]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30
wire [1:0] mem_rdata_3 = bypass_mask[3] ? bypass_wdata_REG_3 : _array_R0_data[7:6]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30
wire [1:0] mem_rdata_4 = bypass_mask[4] ? bypass_wdata_REG_4 : _array_R0_data[9:8]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30
wire [1:0] mem_rdata_5 = bypass_mask[5] ? bypass_wdata_REG_5 : _array_R0_data[11:10]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30
wire [1:0] mem_rdata_6 = bypass_mask[6] ? bypass_wdata_REG_6 : _array_R0_data[13:12]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30
wire [1:0] mem_rdata_7 = bypass_mask[7] ? bypass_wdata_REG_7 : _array_R0_data[15:14]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30
reg rdata_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:153:59
reg [1:0] rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82
reg [1:0] rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82
reg [1:0] rdata_hold_data_2; // utility/src/main/scala/utility/Hold.scala:24:82
reg [1:0] rdata_hold_data_3; // utility/src/main/scala/utility/Hold.scala:24:82
reg [1:0] rdata_hold_data_4; // utility/src/main/scala/utility/Hold.scala:24:82
reg [1:0] rdata_hold_data_5; // utility/src/main/scala/utility/Hold.scala:24:82
reg [1:0] rdata_hold_data_6; // utility/src/main/scala/utility/Hold.scala:24:82
reg [1:0] rdata_hold_data_7; // utility/src/main/scala/utility/Hold.scala:24:82
always @(posedge clock) begin
bypass_wdata_REG_0 <= io_w_req_bits_data_0; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54
bypass_wdata_REG_1 <= io_w_req_bits_data_1; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54
bypass_wdata_REG_2 <= io_w_req_bits_data_2; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54
bypass_wdata_REG_3 <= io_w_req_bits_data_3; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54
bypass_wdata_REG_4 <= io_w_req_bits_data_4; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54
bypass_wdata_REG_5 <= io_w_req_bits_data_5; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54
bypass_wdata_REG_6 <= io_w_req_bits_data_6; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54
bypass_wdata_REG_7 <= io_w_req_bits_data_7; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54
bypass_mask_need_check <= io_r_req_valid & io_w_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:135:{29,34}
bypass_mask_waddr_reg <= io_w_req_bits_setIdx; // utility/src/main/scala/utility/SRAMTemplate.scala:136:28
bypass_mask_raddr_reg <= io_r_req_bits_setIdx; // utility/src/main/scala/utility/SRAMTemplate.scala:137:28
bypass_mask_bypass_REG <= io_w_req_bits_waymask; // utility/src/main/scala/utility/SRAMTemplate.scala:139:76
rdata_REG <= io_r_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:153:59
if (rdata_REG) begin // utility/src/main/scala/utility/SRAMTemplate.scala:153:59
rdata_hold_data_0 <= mem_rdata_0; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30
rdata_hold_data_1 <= mem_rdata_1; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30
rdata_hold_data_2 <= mem_rdata_2; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30
rdata_hold_data_3 <= mem_rdata_3; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30
rdata_hold_data_4 <= mem_rdata_4; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30
rdata_hold_data_5 <= mem_rdata_5; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30
rdata_hold_data_6 <= mem_rdata_6; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30
rdata_hold_data_7 <= mem_rdata_7; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:1]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
_RANDOM[i[0]] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
end // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
bypass_wdata_REG_0 = _RANDOM[1'h0][1:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54
bypass_wdata_REG_1 = _RANDOM[1'h0][3:2]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54
bypass_wdata_REG_2 = _RANDOM[1'h0][5:4]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54
bypass_wdata_REG_3 = _RANDOM[1'h0][7:6]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54
bypass_wdata_REG_4 = _RANDOM[1'h0][9:8]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54
bypass_wdata_REG_5 = _RANDOM[1'h0][11:10]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54
bypass_wdata_REG_6 = _RANDOM[1'h0][13:12]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54
bypass_wdata_REG_7 = _RANDOM[1'h0][15:14]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54
bypass_mask_need_check = _RANDOM[1'h0][16]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :135:29, :142:54
bypass_mask_waddr_reg = _RANDOM[1'h0][25:17]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :136:28, :142:54
bypass_mask_raddr_reg = {_RANDOM[1'h0][31:26], _RANDOM[1'h1][2:0]}; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28, :142:54
bypass_mask_bypass_REG = _RANDOM[1'h1][10:3]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28, :139:76
rdata_REG = _RANDOM[1'h1][11]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28, :153:59
rdata_hold_data_0 = _RANDOM[1'h1][13:12]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28
rdata_hold_data_1 = _RANDOM[1'h1][15:14]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28
rdata_hold_data_2 = _RANDOM[1'h1][17:16]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28
rdata_hold_data_3 = _RANDOM[1'h1][19:18]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28
rdata_hold_data_4 = _RANDOM[1'h1][21:20]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28
rdata_hold_data_5 = _RANDOM[1'h1][23:22]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28
rdata_hold_data_6 = _RANDOM[1'h1][25:24]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28
rdata_hold_data_7 = _RANDOM[1'h1][27:26]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
array_6 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
.R0_addr (io_r_req_bits_setIdx),
.R0_en (io_r_req_valid),
.R0_clk (clock),
.R0_data (_array_R0_data),
.W0_addr (io_w_req_bits_setIdx),
.W0_en (io_w_req_valid),
.W0_clk (clock),
.W0_data
({io_w_req_bits_data_7,
io_w_req_bits_data_6,
io_w_req_bits_data_5,
io_w_req_bits_data_4,
io_w_req_bits_data_3,
io_w_req_bits_data_2,
io_w_req_bits_data_1,
io_w_req_bits_data_0}), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
.W0_mask (io_w_req_bits_waymask)
);
assign io_r_resp_data_0 = rdata_REG ? mem_rdata_0 : rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59
assign io_r_resp_data_1 = rdata_REG ? mem_rdata_1 : rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59
assign io_r_resp_data_2 = rdata_REG ? mem_rdata_2 : rdata_hold_data_2; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59
assign io_r_resp_data_3 = rdata_REG ? mem_rdata_3 : rdata_hold_data_3; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59
assign io_r_resp_data_4 = rdata_REG ? mem_rdata_4 : rdata_hold_data_4; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59
assign io_r_resp_data_5 = rdata_REG ? mem_rdata_5 : rdata_hold_data_5; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59
assign io_r_resp_data_6 = rdata_REG ? mem_rdata_6 : rdata_hold_data_6; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59
assign io_r_resp_data_7 = rdata_REG ? mem_rdata_7 : rdata_hold_data_7; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59
endmodule

189
src/TageSC/SRAMTemplate_31.sv Normal file
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@ -0,0 +1,189 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SRAMTemplate_31( // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
input clock,
input reset,
input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [7:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [5:0] io_r_resp_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [5:0] io_r_resp_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [5:0] io_r_resp_data_2, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [5:0] io_r_resp_data_3, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [7:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [5:0] io_w_req_bits_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [5:0] io_w_req_bits_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [5:0] io_w_req_bits_data_2, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [5:0] io_w_req_bits_data_3, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [3:0] io_w_req_bits_waymask // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
);
wire [5:0] wdata_3; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [5:0] wdata_2; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [5:0] wdata_1; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [5:0] wdata_0; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [23:0] _array_R0_data; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
reg _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30
reg [7:0] _resetSet; // src/main/scala/chisel3/util/Counter.scala:61:40
assign wdata_0 = _resetState ? 6'h0 : io_w_req_bits_data_0; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign wdata_1 = _resetState ? 6'h0 : io_w_req_bits_data_1; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign wdata_2 = _resetState ? 6'h0 : io_w_req_bits_data_2; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign wdata_3 = _resetState ? 6'h0 : io_w_req_bits_data_3; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
reg [5:0] bypass_wdata_REG_0; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54
reg [5:0] bypass_wdata_REG_1; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54
reg [5:0] bypass_wdata_REG_2; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54
reg [5:0] bypass_wdata_REG_3; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54
reg bypass_mask_need_check; // utility/src/main/scala/utility/SRAMTemplate.scala:135:29
reg [7:0] bypass_mask_waddr_reg; // utility/src/main/scala/utility/SRAMTemplate.scala:136:28
reg [7:0] bypass_mask_raddr_reg; // utility/src/main/scala/utility/SRAMTemplate.scala:137:28
reg [3:0] bypass_mask_bypass_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:139:76
wire [3:0] bypass_mask =
{4{bypass_mask_need_check & bypass_mask_waddr_reg == bypass_mask_raddr_reg}}
& bypass_mask_bypass_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:135:29, :136:28, :137:28, :139:{22,39,52,67,76}
wire [5:0] mem_rdata_0 = bypass_mask[0] ? bypass_wdata_REG_0 : _array_R0_data[5:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30
wire [5:0] mem_rdata_1 = bypass_mask[1] ? bypass_wdata_REG_1 : _array_R0_data[11:6]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30
wire [5:0] mem_rdata_2 = bypass_mask[2] ? bypass_wdata_REG_2 : _array_R0_data[17:12]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30
wire [5:0] mem_rdata_3 = bypass_mask[3] ? bypass_wdata_REG_3 : _array_R0_data[23:18]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30
reg rdata_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:153:59
reg [5:0] rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82
reg [5:0] rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82
reg [5:0] rdata_hold_data_2; // utility/src/main/scala/utility/Hold.scala:24:82
reg [5:0] rdata_hold_data_3; // utility/src/main/scala/utility/Hold.scala:24:82
always @(posedge clock or posedge reset) begin
if (reset) begin
_resetState <= 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30
_resetSet <= 8'h0; // src/main/scala/chisel3/util/Counter.scala:61:40
end
else begin
_resetState <= ~(_resetState & (&_resetSet)) & _resetState; // src/main/scala/chisel3/util/Counter.scala:61:40, :73:24, :117:24, :118:{16,23}, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :111:{24,38}
if (_resetState) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30
_resetSet <= 8'(_resetSet + 8'h1); // src/main/scala/chisel3/util/Counter.scala:61:40, :77:24
end
end // always @(posedge, posedge)
always @(posedge clock) begin
bypass_wdata_REG_0 <= io_w_req_bits_data_0; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54
bypass_wdata_REG_1 <= io_w_req_bits_data_1; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54
bypass_wdata_REG_2 <= io_w_req_bits_data_2; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54
bypass_wdata_REG_3 <= io_w_req_bits_data_3; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54
bypass_mask_need_check <= io_r_req_valid & io_w_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:135:{29,34}
bypass_mask_waddr_reg <= io_w_req_bits_setIdx; // utility/src/main/scala/utility/SRAMTemplate.scala:136:28
bypass_mask_raddr_reg <= io_r_req_bits_setIdx; // utility/src/main/scala/utility/SRAMTemplate.scala:137:28
bypass_mask_bypass_REG <= io_w_req_bits_waymask; // utility/src/main/scala/utility/SRAMTemplate.scala:139:76
rdata_REG <= io_r_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:153:59
if (rdata_REG) begin // utility/src/main/scala/utility/SRAMTemplate.scala:153:59
rdata_hold_data_0 <= mem_rdata_0; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30
rdata_hold_data_1 <= mem_rdata_1; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30
rdata_hold_data_2 <= mem_rdata_2; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30
rdata_hold_data_3 <= mem_rdata_3; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:2]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin
_RANDOM[i] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
end // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
_resetState = _RANDOM[2'h0][0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30
_resetSet = _RANDOM[2'h0][8:1]; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30
bypass_wdata_REG_0 = _RANDOM[2'h0][14:9]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :142:54
bypass_wdata_REG_1 = _RANDOM[2'h0][20:15]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :142:54
bypass_wdata_REG_2 = _RANDOM[2'h0][26:21]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :142:54
bypass_wdata_REG_3 = {_RANDOM[2'h0][31:27], _RANDOM[2'h1][0]}; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :142:54
bypass_mask_need_check = _RANDOM[2'h1][1]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :135:29, :142:54
bypass_mask_waddr_reg = _RANDOM[2'h1][9:2]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :136:28, :142:54
bypass_mask_raddr_reg = _RANDOM[2'h1][17:10]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28, :142:54
bypass_mask_bypass_REG = _RANDOM[2'h1][21:18]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :139:76, :142:54
rdata_REG = _RANDOM[2'h1][22]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54, :153:59
rdata_hold_data_0 = _RANDOM[2'h1][28:23]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54
rdata_hold_data_1 = {_RANDOM[2'h1][31:29], _RANDOM[2'h2][2:0]}; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54
rdata_hold_data_2 = _RANDOM[2'h2][8:3]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7
rdata_hold_data_3 = _RANDOM[2'h2][14:9]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`endif // RANDOMIZE_REG_INIT
if (reset) begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
_resetState = 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30
_resetSet = 8'h0; // src/main/scala/chisel3/util/Counter.scala:61:40
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
array_7 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
.R0_addr (io_r_req_bits_setIdx),
.R0_en (io_r_req_valid),
.R0_clk (clock),
.R0_data (_array_R0_data),
.W0_addr (_resetState ? _resetSet : io_w_req_bits_setIdx), // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :125:19
.W0_en (io_w_req_valid | _resetState), // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :122:52
.W0_clk (clock),
.W0_data ({wdata_3, wdata_2, wdata_1, wdata_0}), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :126:26
.W0_mask (_resetState ? 4'hF : io_w_req_bits_waymask) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :127:{20,37}
);
assign io_r_resp_data_0 = rdata_REG ? mem_rdata_0 : rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59
assign io_r_resp_data_1 = rdata_REG ? mem_rdata_1 : rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59
assign io_r_resp_data_2 = rdata_REG ? mem_rdata_2 : rdata_hold_data_2; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59
assign io_r_resp_data_3 = rdata_REG ? mem_rdata_3 : rdata_hold_data_3; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59
endmodule

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src/TageSC/TageBTable.sv Normal file
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@ -0,0 +1,187 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module TageBTable( // src/main/scala/xiangshan/frontend/Tage.scala:137:7
input clock,
input reset,
output io_req_ready, // src/main/scala/xiangshan/frontend/Tage.scala:138:14
input io_req_valid, // src/main/scala/xiangshan/frontend/Tage.scala:138:14
input [38:0] io_req_bits, // src/main/scala/xiangshan/frontend/Tage.scala:138:14
output [1:0] io_s1_cnt_0, // src/main/scala/xiangshan/frontend/Tage.scala:138:14
output [1:0] io_s1_cnt_1, // src/main/scala/xiangshan/frontend/Tage.scala:138:14
input io_update_mask_0, // src/main/scala/xiangshan/frontend/Tage.scala:138:14
input io_update_mask_1, // src/main/scala/xiangshan/frontend/Tage.scala:138:14
input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/Tage.scala:138:14
input [1:0] io_update_cnt_0, // src/main/scala/xiangshan/frontend/Tage.scala:138:14
input [1:0] io_update_cnt_1, // src/main/scala/xiangshan/frontend/Tage.scala:138:14
input io_update_takens_0, // src/main/scala/xiangshan/frontend/Tage.scala:138:14
input io_update_takens_1 // src/main/scala/xiangshan/frontend/Tage.scala:138:14
);
wire [1:0] newCtrs_1; // src/main/scala/xiangshan/frontend/Tage.scala:213:8
wire [1:0] newCtrs_0; // src/main/scala/xiangshan/frontend/Tage.scala:213:8
wire _wrbypass_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:192:24
wire _wrbypass_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:192:24
wire [1:0] _wrbypass_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:192:24
wire _wrbypass_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:192:24
wire [1:0] _wrbypass_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/Tage.scala:192:24
wire [1:0] _bt_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/Tage.scala:154:18
wire [1:0] _bt_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/Tage.scala:154:18
reg doing_reset; // src/main/scala/xiangshan/frontend/Tage.scala:166:28
reg [10:0] resetRow; // src/main/scala/xiangshan/frontend/Tage.scala:167:25
reg [10:0] s1_idx; // src/main/scala/xiangshan/frontend/Tage.scala:181:25
wire _wrbypass_io_wen_T = io_update_mask_0 | io_update_mask_1; // src/main/scala/xiangshan/frontend/Tage.scala:193:45
wire [1:0] oldCtrs_0 =
_wrbypass_io_hit
& (io_update_pc[1] ? _wrbypass_io_hit_data_1_valid : _wrbypass_io_hit_data_0_valid)
? (io_update_pc[1] ? _wrbypass_io_hit_data_1_bits : _wrbypass_io_hit_data_0_bits)
: io_update_pc[1] ? io_update_cnt_1 : io_update_cnt_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :192:24, :205:{10,27}
wire [1:0] oldCtrs_1 =
_wrbypass_io_hit
& (io_update_pc[1] ? _wrbypass_io_hit_data_0_valid : _wrbypass_io_hit_data_1_valid)
? (io_update_pc[1] ? _wrbypass_io_hit_data_0_bits : _wrbypass_io_hit_data_1_bits)
: io_update_pc[1] ? io_update_cnt_0 : io_update_cnt_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :192:24, :205:{10,27}
wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :213:21
assign newCtrs_0 =
(&oldCtrs_0) & _GEN
? 2'h3
: oldCtrs_0 == 2'h0 & ~_GEN
? 2'h0
: _GEN ? 2'(oldCtrs_0 + 2'h1) : 2'(oldCtrs_0 - 2'h1); // src/main/scala/xiangshan/frontend/Tage.scala:205:10, :211:27, :212:30, :213:{8,21}, :214:{10,26,29}, :215:{12,24,35}, :234:36
wire _GEN_0 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :213:21
assign newCtrs_1 =
(&oldCtrs_1) & _GEN_0
? 2'h3
: oldCtrs_1 == 2'h0 & ~_GEN_0
? 2'h0
: _GEN_0 ? 2'(oldCtrs_1 + 2'h1) : 2'(oldCtrs_1 - 2'h1); // src/main/scala/xiangshan/frontend/Tage.scala:205:10, :211:27, :212:30, :213:{8,21}, :214:{10,26,29}, :215:{12,24,35}, :234:36
always @(posedge clock or posedge reset) begin
if (reset) begin
doing_reset <= 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28
resetRow <= 11'h0; // src/main/scala/xiangshan/frontend/Tage.scala:167:25
end
else begin
doing_reset <= resetRow != 11'h7FF & doing_reset; // src/main/scala/xiangshan/frontend/Tage.scala:166:28, :167:25, :169:{18,36,50}
resetRow <= 11'(resetRow + {10'h0, doing_reset}); // src/main/scala/xiangshan/frontend/Tage.scala:166:28, :167:25, :168:24
end
end // always @(posedge, posedge)
always @(posedge clock) begin
if (io_req_valid) // src/main/scala/xiangshan/frontend/Tage.scala:138:14
s1_idx <= io_req_bits[11:1]; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:399:65, src/main/scala/xiangshan/frontend/Tage.scala:181:25
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/Tage.scala:137:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:137:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:137:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0]; // src/main/scala/xiangshan/frontend/Tage.scala:137:7
initial begin // src/main/scala/xiangshan/frontend/Tage.scala:137:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:137:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:137:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/Tage.scala:137:7
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // src/main/scala/xiangshan/frontend/Tage.scala:137:7
doing_reset = _RANDOM[/*Zero width*/ 1'b0][0]; // src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28
resetRow = _RANDOM[/*Zero width*/ 1'b0][11:1]; // src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28, :167:25
s1_idx = _RANDOM[/*Zero width*/ 1'b0][22:12]; // src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28, :181:25
`endif // RANDOMIZE_REG_INIT
if (reset) begin // src/main/scala/xiangshan/frontend/Tage.scala:137:7
doing_reset = 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28
resetRow = 11'h0; // src/main/scala/xiangshan/frontend/Tage.scala:167:25
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:137:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:137:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
FoldedSRAMTemplate_20 bt ( // src/main/scala/xiangshan/frontend/Tage.scala:154:18
.clock (clock),
.io_r_req_valid (io_req_valid),
.io_r_req_bits_setIdx (io_req_bits[11:1]), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:399:65
.io_r_resp_data_0 (_bt_io_r_resp_data_0),
.io_r_resp_data_1 (_bt_io_r_resp_data_1),
.io_w_req_valid (_wrbypass_io_wen_T | doing_reset), // src/main/scala/xiangshan/frontend/Tage.scala:166:28, :193:45, :231:41
.io_w_req_bits_setIdx (doing_reset ? resetRow : io_update_pc[11:1]), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:399:65, src/main/scala/xiangshan/frontend/Tage.scala:166:28, :167:25, :233:17
.io_w_req_bits_data_0 (doing_reset ? 2'h2 : newCtrs_0), // src/main/scala/xiangshan/frontend/Tage.scala:166:28, :213:8, :232:{15,36}
.io_w_req_bits_data_1 (doing_reset ? 2'h2 : newCtrs_1), // src/main/scala/xiangshan/frontend/Tage.scala:166:28, :213:8, :232:{15,36}
.io_w_req_bits_waymask
(doing_reset
? 2'h3
: {io_update_mask_0 & io_update_pc[1] | io_update_mask_1 & ~(io_update_pc[1]),
io_update_mask_0 & ~(io_update_pc[1]) | io_update_mask_1 & io_update_pc[1]}) // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :166:28, :211:27, :226:{26,55}, :227:15, :228:6, :234:18
);
WrBypass_32 wrbypass ( // src/main/scala/xiangshan/frontend/Tage.scala:192:24
.clock (clock),
.reset (reset),
.io_wen (_wrbypass_io_wen_T), // src/main/scala/xiangshan/frontend/Tage.scala:193:45
.io_write_idx (io_update_pc[11:1]), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:399:65
.io_write_data_0 (io_update_pc[1] ? newCtrs_1 : newCtrs_0), // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :198:32, :213:8
.io_write_data_1 (io_update_pc[1] ? newCtrs_0 : newCtrs_1), // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :198:32, :213:8
.io_write_way_mask_0 (io_update_mask_0),
.io_write_way_mask_1 (io_update_mask_1),
.io_hit (_wrbypass_io_hit),
.io_hit_data_0_valid (_wrbypass_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypass_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypass_io_hit_data_1_bits)
);
assign io_req_ready = ~doing_reset; // src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28, :172:19
assign io_s1_cnt_0 =
(s1_idx[0] ? 2'h0 : _bt_io_r_resp_data_0) | (s1_idx[0] ? _bt_io_r_resp_data_1 : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :137:7, :154:18, :181:25, :234:36
assign io_s1_cnt_1 =
(s1_idx[0] ? _bt_io_r_resp_data_0 : 2'h0) | (s1_idx[0] ? 2'h0 : _bt_io_r_resp_data_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :137:7, :154:18, :181:25, :234:36
endmodule

762
src/TageSC/TageTable.sv Normal file
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@ -0,0 +1,762 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module TageTable( // src/main/scala/xiangshan/frontend/Tage.scala:240:7
input clock,
input reset,
output io_req_ready, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_req_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [7:0] io_req_bits_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [6:0] io_req_bits_folded_hist_hist_7_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output io_resps_0_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output [2:0] io_resps_0_bits_ctr, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output io_resps_0_bits_u, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output io_resps_0_bits_unconf, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output io_resps_1_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output [2:0] io_resps_1_bits_ctr, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output io_resps_1_bits_u, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output io_resps_1_bits_unconf, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [7:0] io_update_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [6:0] io_update_folded_hist_hist_7_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_mask_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_mask_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_takens_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_takens_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_alloc_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_alloc_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [2:0] io_update_oldCtrs_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [2:0] io_update_oldCtrs_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_uMask_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_uMask_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_us_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_us_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_reset_u_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_reset_u_1 // src/main/scala/xiangshan/frontend/Tage.scala:245:14
);
wire per_bank_not_silent_update_3_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_3_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_2_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_2_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_1_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_1_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_0_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_0_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
reg powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:399:34
wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73
wire _bank_wrbypasses_3_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_3_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_3_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_3_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_2_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_2_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_2_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_2_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_1_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_1_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_1_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_1_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_0_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_0_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_0_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_0_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _table_banks_3_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_3_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_3_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_3_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_3_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_3_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_3_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_2_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_2_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_2_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_2_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_2_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_2_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_2_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_1_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_1_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_1_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_1_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_1_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_0_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_0_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_0_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_0_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_0_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _us_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:310:18
wire _us_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/Tage.scala:310:18
wire _us_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/Tage.scala:310:18
wire [7:0] _GEN = io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43
wire s0_bank_req_1h_0 = _GEN[1:0] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}
wire s0_bank_req_1h_1 = _GEN[1:0] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}
wire s0_bank_req_1h_2 = _GEN[1:0] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}
wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid; // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:399:34, :407:19
wire [8:0] _table_banks_3_io_r_req_bits_setIdx_T = {io_req_bits_pc[11:9], _GEN[7:2]}; // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
reg [37:0] s1_unhashed_idx; // src/main/scala/xiangshan/frontend/Tage.scala:330:34
reg [7:0] s1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:332:25
reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:334:33
reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:334:33
reg s1_bank_req_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:334:33
reg s1_bank_req_1h_3; // src/main/scala/xiangshan/frontend/Tage.scala:334:33
reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/Tage.scala:335:48
reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/Tage.scala:335:48
reg s1_bank_has_write_on_this_req_2; // src/main/scala/xiangshan/frontend/Tage.scala:335:48
reg s1_bank_has_write_on_this_req_3; // src/main/scala/xiangshan/frontend/Tage.scala:335:48
wire [2:0] _resp_selected_WIRE_1 =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33
wire [2:0] _resp_selected_WIRE_5 =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33
wire _unconf_selected_WIRE =
s1_bank_req_1h_0
& (_table_banks_0_io_r_resp_data_0_ctr == 3'h4
| _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1
& (_table_banks_1_io_r_resp_data_0_ctr == 3'h4
| _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2
& (_table_banks_2_io_r_resp_data_0_ctr == 3'h4
| _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3
& (_table_banks_3_io_r_resp_data_0_ctr == 3'h4
| _table_banks_3_io_r_resp_data_0_ctr == 3'h3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14
wire _unconf_selected_WIRE_1 =
s1_bank_req_1h_0
& (_table_banks_0_io_r_resp_data_1_ctr == 3'h4
| _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1
& (_table_banks_1_io_r_resp_data_1_ctr == 3'h4
| _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2
& (_table_banks_2_io_r_resp_data_1_ctr == 3'h4
| _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3
& (_table_banks_3_io_r_resp_data_1_ctr == 3'h4
| _table_banks_3_io_r_resp_data_1_ctr == 3'h3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14
wire _hit_selected_WIRE =
s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag
& _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE
| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag
& _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE
| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag
& _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE
| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag
& _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82}
wire _hit_selected_WIRE_1 =
s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag
& _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE
| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag
& _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE
| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag
& _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE
| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag
& _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82}
assign _resp_invalid_by_write_WIRE =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2
| s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:334:33, :335:48
wire [7:0] _GEN_0 = io_update_pc[8:1] ^ io_update_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43
wire [7:0] per_bank_update_wdata_3_1_tag =
_GEN_0 ^ {io_update_folded_hist_hist_7_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :290:29, :291:{38,52}
wire update_req_bank_1h_0 = _GEN_0[1:0] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}
wire update_req_bank_1h_1 = _GEN_0[1:0] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}
wire update_req_bank_1h_2 = _GEN_0[1:0] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}
wire [8:0] update_idx_in_bank = {io_update_pc[11:9], _GEN_0[7:2]}; // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
wire [1:0] per_bank_update_way_mask_0 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_0_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_0_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81
wire [1:0] per_bank_update_way_mask_1 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_1_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_1_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81
wire [1:0] per_bank_update_way_mask_2 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_2_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_2_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81
wire [1:0] per_bank_update_way_mask_3 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_3_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_3_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81
wire _s1_bank_has_write_on_this_req_WIRE_0 =
(|per_bank_update_way_mask_0) & update_req_bank_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49}
wire _s1_bank_has_write_on_this_req_WIRE_1 =
(|per_bank_update_way_mask_1) & update_req_bank_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49}
wire _s1_bank_has_write_on_this_req_WIRE_2 =
(|per_bank_update_way_mask_2) & update_req_bank_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49}
wire _s1_bank_has_write_on_this_req_WIRE_3 =
(|per_bank_update_way_mask_3) & (&(_GEN_0[1:0])); // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :384:11, :391:{45,49}
wire [2:0] _wrbypass_io_WIRE_2 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid =
(~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_0_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_0_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46
wire _GEN_1 = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14
wire [2:0] _GEN_2 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43
wire _GEN_3 = (|_GEN_2) | _GEN_1; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :97:10, src/main/scala/xiangshan/frontend/Tage.scala:449:14
wire _GEN_4 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12
wire [2:0] per_bank_update_wdata_0_0_ctr =
_GEN_4
? (_GEN_1 ? 3'h4 : 3'h3)
: wrbypass_data_valid
? ((&_wrbypass_io_WIRE_2) & _GEN_1
? 3'h7
: _wrbypass_io_WIRE_2 == 3'h0 & ~_GEN_1
? 3'h0
: _GEN_1
? 3'(_wrbypass_io_WIRE_2 + 3'h1)
: 3'(_wrbypass_io_WIRE_2 - 3'h1))
: (&_GEN_2) & _GEN_1
? 3'h7
: _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_0_0 =
(wrbypass_data_valid
? ~((&_wrbypass_io_WIRE_2) & _GEN_1 | _wrbypass_io_WIRE_2 == 3'h0 & ~_GEN_1)
: ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_11 =
(io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_1 =
(io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_0_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_0_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46
wire _GEN_5 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14
wire [2:0] _GEN_6 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43
wire _GEN_7 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12
wire [2:0] per_bank_update_wdata_0_1_ctr =
_GEN_7
? (_GEN_5 ? 3'h4 : 3'h3)
: wrbypass_data_valid_1
? ((&_wrbypass_io_WIRE_11) & _GEN_5
? 3'h7
: _wrbypass_io_WIRE_11 == 3'h0 & ~_GEN_5
? 3'h0
: _GEN_5
? 3'(_wrbypass_io_WIRE_11 + 3'h1)
: 3'(_wrbypass_io_WIRE_11 - 3'h1))
: (&_GEN_6) & _GEN_5
? 3'h7
: _GEN_6 == 3'h0 & ~_GEN_5
? 3'h0
: _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_0_1 =
(wrbypass_data_valid_1
? ~((&_wrbypass_io_WIRE_11) & _GEN_5 | _wrbypass_io_WIRE_11 == 3'h0 & ~_GEN_5)
: ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_20 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_2 =
(~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_1_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_1_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46
wire [2:0] per_bank_update_wdata_1_0_ctr =
_GEN_4
? (_GEN_1 ? 3'h4 : 3'h3)
: wrbypass_data_valid_2
? ((&_wrbypass_io_WIRE_20) & _GEN_1
? 3'h7
: _wrbypass_io_WIRE_20 == 3'h0 & ~_GEN_1
? 3'h0
: _GEN_1
? 3'(_wrbypass_io_WIRE_20 + 3'h1)
: 3'(_wrbypass_io_WIRE_20 - 3'h1))
: (&_GEN_2) & _GEN_1
? 3'h7
: _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_1_0 =
(wrbypass_data_valid_2
? ~((&_wrbypass_io_WIRE_20) & _GEN_1 | _wrbypass_io_WIRE_20 == 3'h0 & ~_GEN_1)
: ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_29 =
(io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_3 =
(io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_1_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_1_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46
wire [2:0] per_bank_update_wdata_1_1_ctr =
_GEN_7
? (_GEN_5 ? 3'h4 : 3'h3)
: wrbypass_data_valid_3
? ((&_wrbypass_io_WIRE_29) & _GEN_5
? 3'h7
: _wrbypass_io_WIRE_29 == 3'h0 & ~_GEN_5
? 3'h0
: _GEN_5
? 3'(_wrbypass_io_WIRE_29 + 3'h1)
: 3'(_wrbypass_io_WIRE_29 - 3'h1))
: (&_GEN_6) & _GEN_5
? 3'h7
: _GEN_6 == 3'h0 & ~_GEN_5
? 3'h0
: _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_1_1 =
(wrbypass_data_valid_3
? ~((&_wrbypass_io_WIRE_29) & _GEN_5 | _wrbypass_io_WIRE_29 == 3'h0 & ~_GEN_5)
: ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_38 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_4 =
(~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_2_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_2_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46
wire [2:0] per_bank_update_wdata_2_0_ctr =
_GEN_4
? (_GEN_1 ? 3'h4 : 3'h3)
: wrbypass_data_valid_4
? ((&_wrbypass_io_WIRE_38) & _GEN_1
? 3'h7
: _wrbypass_io_WIRE_38 == 3'h0 & ~_GEN_1
? 3'h0
: _GEN_1
? 3'(_wrbypass_io_WIRE_38 + 3'h1)
: 3'(_wrbypass_io_WIRE_38 - 3'h1))
: (&_GEN_2) & _GEN_1
? 3'h7
: _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_2_0 =
(wrbypass_data_valid_4
? ~((&_wrbypass_io_WIRE_38) & _GEN_1 | _wrbypass_io_WIRE_38 == 3'h0 & ~_GEN_1)
: ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_47 =
(io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_5 =
(io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_2_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_2_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46
wire [2:0] per_bank_update_wdata_2_1_ctr =
_GEN_7
? (_GEN_5 ? 3'h4 : 3'h3)
: wrbypass_data_valid_5
? ((&_wrbypass_io_WIRE_47) & _GEN_5
? 3'h7
: _wrbypass_io_WIRE_47 == 3'h0 & ~_GEN_5
? 3'h0
: _GEN_5
? 3'(_wrbypass_io_WIRE_47 + 3'h1)
: 3'(_wrbypass_io_WIRE_47 - 3'h1))
: (&_GEN_6) & _GEN_5
? 3'h7
: _GEN_6 == 3'h0 & ~_GEN_5
? 3'h0
: _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_2_1 =
(wrbypass_data_valid_5
? ~((&_wrbypass_io_WIRE_47) & _GEN_5 | _wrbypass_io_WIRE_47 == 3'h0 & ~_GEN_5)
: ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_56 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_6 =
(~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_3_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_3_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46
wire [2:0] per_bank_update_wdata_3_0_ctr =
_GEN_4
? (_GEN_1 ? 3'h4 : 3'h3)
: wrbypass_data_valid_6
? ((&_wrbypass_io_WIRE_56) & _GEN_1
? 3'h7
: _wrbypass_io_WIRE_56 == 3'h0 & ~_GEN_1
? 3'h0
: _GEN_1
? 3'(_wrbypass_io_WIRE_56 + 3'h1)
: 3'(_wrbypass_io_WIRE_56 - 3'h1))
: (&_GEN_2) & _GEN_1
? 3'h7
: _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_3_0 =
(wrbypass_data_valid_6
? ~((&_wrbypass_io_WIRE_56) & _GEN_1 | _wrbypass_io_WIRE_56 == 3'h0 & ~_GEN_1)
: ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_65 =
(io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_7 =
(io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_3_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_3_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46
wire [2:0] per_bank_update_wdata_3_1_ctr =
_GEN_7
? (_GEN_5 ? 3'h4 : 3'h3)
: wrbypass_data_valid_7
? ((&_wrbypass_io_WIRE_65) & _GEN_5
? 3'h7
: _wrbypass_io_WIRE_65 == 3'h0 & ~_GEN_5
? 3'h0
: _GEN_5
? 3'(_wrbypass_io_WIRE_65 + 3'h1)
: 3'(_wrbypass_io_WIRE_65 - 3'h1))
: (&_GEN_6) & _GEN_5
? 3'h7
: _GEN_6 == 3'h0 & ~_GEN_5
? 3'h0
: _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_3_1 =
(wrbypass_data_valid_7
? ~((&_wrbypass_io_WIRE_65) & _GEN_5 | _wrbypass_io_WIRE_65 == 3'h0 & ~_GEN_5)
: ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
always @(posedge clock) begin
if (_s1_bank_req_1h_T) begin // src/main/scala/chisel3/util/Decoupled.scala:53:35
s1_unhashed_idx <= io_req_bits_pc[38:1]; // src/main/scala/xiangshan/frontend/Tage.scala:305:43, :330:34
s1_tag <= _GEN ^ {io_req_bits_folded_hist_hist_7_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :290:29, :291:{38,52}, :332:25
s1_bank_req_1h_0 <= s0_bank_req_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33
s1_bank_req_1h_1 <= s0_bank_req_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33
s1_bank_req_1h_2 <= s0_bank_req_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33
s1_bank_req_1h_3 <= &(_GEN[1:0]); // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :334:33
end
if (io_req_valid) begin // src/main/scala/xiangshan/frontend/Tage.scala:245:14
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49
s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49
s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49
end
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset)
powerOnResetState <= 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34
else
powerOnResetState <=
~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready
& _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready
& _table_banks_3_io_r_req_ready) & powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:310:18, :315:11, :399:34, :400:{26,79}, :402:23
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:3]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7
initial begin // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/Tage.scala:240:7
for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
_RANDOM[i[1:0]] = `RANDOM; // src/main/scala/xiangshan/frontend/Tage.scala:240:7
end // src/main/scala/xiangshan/frontend/Tage.scala:240:7
s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][5:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34
s1_tag = _RANDOM[2'h1][24:17]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34, :332:25
s1_bank_req_1h_0 = _RANDOM[2'h3][0]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33
s1_bank_req_1h_1 = _RANDOM[2'h3][1]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33
s1_bank_req_1h_2 = _RANDOM[2'h3][2]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33
s1_bank_req_1h_3 = _RANDOM[2'h3][3]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33
s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][4]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48
s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][5]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48
s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][6]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48
s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][7]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48
powerOnResetState = _RANDOM[2'h3][8]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :399:34
`endif // RANDOMIZE_REG_INIT
if (reset) // src/main/scala/xiangshan/frontend/Tage.scala:240:7
powerOnResetState = 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
FoldedSRAMTemplate us ( // src/main/scala/xiangshan/frontend/Tage.scala:310:18
.clock (clock),
.reset (reset),
.io_r_req_ready (_us_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T), // src/main/scala/chisel3/util/Decoupled.scala:53:35
.io_r_req_bits_setIdx ({io_req_bits_pc[11:9], _GEN}), // src/main/scala/xiangshan/frontend/Tage.scala:290:{29,38}
.io_r_resp_data_0 (_us_io_r_resp_data_0),
.io_r_resp_data_1 (_us_io_r_resp_data_1),
.io_w_req_valid (io_update_uMask_0 | io_update_uMask_1), // src/main/scala/xiangshan/frontend/Tage.scala:426:41
.io_w_req_bits_setIdx ({io_update_pc[11:9], _GEN_0}), // src/main/scala/xiangshan/frontend/Tage.scala:290:{29,38}
.io_w_req_bits_data_0
(~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :422:48
.io_w_req_bits_data_1
(io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43
.io_w_req_bits_waymask
({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1,
~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}), // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :415:{47,56}, :417:15, :418:7
.extra_reset (io_update_reset_u_0 | io_update_reset_u_1) // src/main/scala/xiangshan/frontend/Tage.scala:311:51
);
FoldedSRAMTemplate_1 table_banks_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_0_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52
.io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38
.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/Tage.scala:391:49
.io_w_req_bits_setIdx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38
.io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_waymask (per_bank_update_way_mask_0) // src/main/scala/xiangshan/frontend/Tage.scala:384:11
);
FoldedSRAMTemplate_1 table_banks_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_1_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52
.io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38
.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/Tage.scala:391:49
.io_w_req_bits_setIdx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38
.io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_waymask (per_bank_update_way_mask_1) // src/main/scala/xiangshan/frontend/Tage.scala:384:11
);
FoldedSRAMTemplate_1 table_banks_2 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_2_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52
.io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38
.io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2), // src/main/scala/xiangshan/frontend/Tage.scala:391:49
.io_w_req_bits_setIdx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38
.io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_waymask (per_bank_update_way_mask_2) // src/main/scala/xiangshan/frontend/Tage.scala:384:11
);
FoldedSRAMTemplate_1 table_banks_3 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_3_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & (&(_GEN[1:0]))), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :322:52
.io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38
.io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3), // src/main/scala/xiangshan/frontend/Tage.scala:391:49
.io_w_req_bits_setIdx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38
.io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_waymask (per_bank_update_way_mask_3) // src/main/scala/xiangshan/frontend/Tage.scala:384:11
);
WrBypass bank_wrbypasses_0_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_0), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45
.io_write_idx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_0_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_0_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_0), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45
.io_write_idx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_0_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_1_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_1), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45
.io_write_idx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_1_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_1_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_1), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45
.io_write_idx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_1_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_2_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_2), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45
.io_write_idx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_2_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_2_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_2), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45
.io_write_idx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_2_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_3_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & (&(_GEN_0[1:0]))), // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45
.io_write_idx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_3_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_3_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & (&(_GEN_0[1:0]))), // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45
.io_write_idx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_3_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits)
);
assign io_req_ready = ~powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :399:34, :407:19
assign io_resps_0_valid =
~(s1_unhashed_idx[0]) & _hit_selected_WIRE | s1_unhashed_idx[0]
& _hit_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34
assign io_resps_0_bits_ctr =
(s1_unhashed_idx[0] ? 3'h0 : _resp_selected_WIRE_1)
| (s1_unhashed_idx[0] ? _resp_selected_WIRE_5 : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34
assign io_resps_0_bits_u =
~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0]
& _us_io_r_resp_data_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :310:18, :330:34
assign io_resps_0_bits_unconf =
~(s1_unhashed_idx[0]) & _unconf_selected_WIRE | s1_unhashed_idx[0]
& _unconf_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34
assign io_resps_1_valid =
s1_unhashed_idx[0] & _hit_selected_WIRE | ~(s1_unhashed_idx[0])
& _hit_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34
assign io_resps_1_bits_ctr =
(s1_unhashed_idx[0] ? _resp_selected_WIRE_1 : 3'h0)
| (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_WIRE_5); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34
assign io_resps_1_bits_u =
s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0])
& _us_io_r_resp_data_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :310:18, :330:34
assign io_resps_1_bits_unconf =
s1_unhashed_idx[0] & _unconf_selected_WIRE | ~(s1_unhashed_idx[0])
& _unconf_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34
endmodule

765
src/TageSC/TageTable_1.sv Normal file
View File

@ -0,0 +1,765 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module TageTable_1( // src/main/scala/xiangshan/frontend/Tage.scala:240:7
input clock,
input reset,
output io_req_ready, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_req_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [6:0] io_req_bits_folded_hist_hist_15_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [7:0] io_req_bits_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [10:0] io_req_bits_folded_hist_hist_1_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output io_resps_0_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output [2:0] io_resps_0_bits_ctr, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output io_resps_0_bits_u, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output io_resps_0_bits_unconf, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output io_resps_1_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output [2:0] io_resps_1_bits_ctr, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output io_resps_1_bits_u, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output io_resps_1_bits_unconf, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [6:0] io_update_folded_hist_hist_15_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [7:0] io_update_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [10:0] io_update_folded_hist_hist_1_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_mask_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_mask_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_takens_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_takens_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_alloc_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_alloc_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [2:0] io_update_oldCtrs_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [2:0] io_update_oldCtrs_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_uMask_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_uMask_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_us_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_us_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_reset_u_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_reset_u_1 // src/main/scala/xiangshan/frontend/Tage.scala:245:14
);
wire per_bank_not_silent_update_3_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_3_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_2_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_2_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_1_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_1_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_0_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_0_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
reg powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:399:34
wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73
wire _bank_wrbypasses_3_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_3_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_3_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_3_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_2_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_2_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_2_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_2_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_1_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_1_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_1_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_1_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_0_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_0_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_0_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_0_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _table_banks_3_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_3_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_3_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_3_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_3_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_3_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_3_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_2_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_2_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_2_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_2_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_2_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_2_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_2_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_1_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_1_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_1_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_1_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_1_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_0_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_0_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_0_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_0_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_0_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _us_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:310:18
wire _us_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/Tage.scala:310:18
wire _us_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/Tage.scala:310:18
wire [10:0] s0_idx = io_req_bits_pc[11:1] ^ io_req_bits_folded_hist_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43
wire s0_bank_req_1h_0 = s0_idx[1:0] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}
wire s0_bank_req_1h_1 = s0_idx[1:0] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}
wire s0_bank_req_1h_2 = s0_idx[1:0] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}
wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid; // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:399:34, :407:19
reg [37:0] s1_unhashed_idx; // src/main/scala/xiangshan/frontend/Tage.scala:330:34
reg [7:0] s1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:332:25
reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:334:33
reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:334:33
reg s1_bank_req_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:334:33
reg s1_bank_req_1h_3; // src/main/scala/xiangshan/frontend/Tage.scala:334:33
reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/Tage.scala:335:48
reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/Tage.scala:335:48
reg s1_bank_has_write_on_this_req_2; // src/main/scala/xiangshan/frontend/Tage.scala:335:48
reg s1_bank_has_write_on_this_req_3; // src/main/scala/xiangshan/frontend/Tage.scala:335:48
wire [2:0] _resp_selected_WIRE_1 =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33
wire [2:0] _resp_selected_WIRE_5 =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33
wire _unconf_selected_WIRE =
s1_bank_req_1h_0
& (_table_banks_0_io_r_resp_data_0_ctr == 3'h4
| _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1
& (_table_banks_1_io_r_resp_data_0_ctr == 3'h4
| _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2
& (_table_banks_2_io_r_resp_data_0_ctr == 3'h4
| _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3
& (_table_banks_3_io_r_resp_data_0_ctr == 3'h4
| _table_banks_3_io_r_resp_data_0_ctr == 3'h3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14
wire _unconf_selected_WIRE_1 =
s1_bank_req_1h_0
& (_table_banks_0_io_r_resp_data_1_ctr == 3'h4
| _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1
& (_table_banks_1_io_r_resp_data_1_ctr == 3'h4
| _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2
& (_table_banks_2_io_r_resp_data_1_ctr == 3'h4
| _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3
& (_table_banks_3_io_r_resp_data_1_ctr == 3'h4
| _table_banks_3_io_r_resp_data_1_ctr == 3'h3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14
wire _hit_selected_WIRE =
s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag
& _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE
| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag
& _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE
| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag
& _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE
| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag
& _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82}
wire _hit_selected_WIRE_1 =
s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag
& _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE
| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag
& _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE
| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag
& _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE
| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag
& _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82}
assign _resp_invalid_by_write_WIRE =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2
| s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:334:33, :335:48
wire [10:0] update_idx = io_update_pc[11:1] ^ io_update_folded_hist_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43
wire [7:0] per_bank_update_wdata_3_1_tag =
io_update_pc[8:1] ^ io_update_folded_hist_hist_4_folded_hist
^ {io_update_folded_hist_hist_15_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :291:{29,38,52}, :305:43
wire update_req_bank_1h_0 = update_idx[1:0] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}
wire update_req_bank_1h_1 = update_idx[1:0] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}
wire update_req_bank_1h_2 = update_idx[1:0] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}
wire [1:0] per_bank_update_way_mask_0 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_0_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_0_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81
wire [1:0] per_bank_update_way_mask_1 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_1_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_1_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81
wire [1:0] per_bank_update_way_mask_2 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_2_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_2_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81
wire [1:0] per_bank_update_way_mask_3 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_3_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_3_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81
wire _s1_bank_has_write_on_this_req_WIRE_0 =
(|per_bank_update_way_mask_0) & update_req_bank_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49}
wire _s1_bank_has_write_on_this_req_WIRE_1 =
(|per_bank_update_way_mask_1) & update_req_bank_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49}
wire _s1_bank_has_write_on_this_req_WIRE_2 =
(|per_bank_update_way_mask_2) & update_req_bank_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49}
wire _s1_bank_has_write_on_this_req_WIRE_3 =
(|per_bank_update_way_mask_3) & (&(update_idx[1:0])); // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :384:11, :391:{45,49}
wire [2:0] _wrbypass_io_WIRE_2 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid =
(~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_0_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_0_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46
wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14
wire [2:0] _GEN_0 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43
wire _GEN_1 = (|_GEN_0) | _GEN; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :97:10, src/main/scala/xiangshan/frontend/Tage.scala:449:14
wire _GEN_2 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12
wire [2:0] per_bank_update_wdata_0_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid
? ((&_wrbypass_io_WIRE_2) & _GEN
? 3'h7
: _wrbypass_io_WIRE_2 == 3'h0 & ~_GEN
? 3'h0
: _GEN
? 3'(_wrbypass_io_WIRE_2 + 3'h1)
: 3'(_wrbypass_io_WIRE_2 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_0_0 =
(wrbypass_data_valid
? ~((&_wrbypass_io_WIRE_2) & _GEN | _wrbypass_io_WIRE_2 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_11 =
(io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_1 =
(io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_0_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_0_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46
wire _GEN_3 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14
wire [2:0] _GEN_4 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43
wire _GEN_5 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12
wire [2:0] per_bank_update_wdata_0_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_1
? ((&_wrbypass_io_WIRE_11) & _GEN_3
? 3'h7
: _wrbypass_io_WIRE_11 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3
? 3'(_wrbypass_io_WIRE_11 + 3'h1)
: 3'(_wrbypass_io_WIRE_11 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_0_1 =
(wrbypass_data_valid_1
? ~((&_wrbypass_io_WIRE_11) & _GEN_3 | _wrbypass_io_WIRE_11 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_20 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_2 =
(~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_1_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_1_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46
wire [2:0] per_bank_update_wdata_1_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_2
? ((&_wrbypass_io_WIRE_20) & _GEN
? 3'h7
: _wrbypass_io_WIRE_20 == 3'h0 & ~_GEN
? 3'h0
: _GEN
? 3'(_wrbypass_io_WIRE_20 + 3'h1)
: 3'(_wrbypass_io_WIRE_20 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_1_0 =
(wrbypass_data_valid_2
? ~((&_wrbypass_io_WIRE_20) & _GEN | _wrbypass_io_WIRE_20 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_29 =
(io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_3 =
(io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_1_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_1_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46
wire [2:0] per_bank_update_wdata_1_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_3
? ((&_wrbypass_io_WIRE_29) & _GEN_3
? 3'h7
: _wrbypass_io_WIRE_29 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3
? 3'(_wrbypass_io_WIRE_29 + 3'h1)
: 3'(_wrbypass_io_WIRE_29 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_1_1 =
(wrbypass_data_valid_3
? ~((&_wrbypass_io_WIRE_29) & _GEN_3 | _wrbypass_io_WIRE_29 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_38 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_4 =
(~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_2_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_2_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46
wire [2:0] per_bank_update_wdata_2_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_4
? ((&_wrbypass_io_WIRE_38) & _GEN
? 3'h7
: _wrbypass_io_WIRE_38 == 3'h0 & ~_GEN
? 3'h0
: _GEN
? 3'(_wrbypass_io_WIRE_38 + 3'h1)
: 3'(_wrbypass_io_WIRE_38 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_2_0 =
(wrbypass_data_valid_4
? ~((&_wrbypass_io_WIRE_38) & _GEN | _wrbypass_io_WIRE_38 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_47 =
(io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_5 =
(io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_2_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_2_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46
wire [2:0] per_bank_update_wdata_2_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_5
? ((&_wrbypass_io_WIRE_47) & _GEN_3
? 3'h7
: _wrbypass_io_WIRE_47 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3
? 3'(_wrbypass_io_WIRE_47 + 3'h1)
: 3'(_wrbypass_io_WIRE_47 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_2_1 =
(wrbypass_data_valid_5
? ~((&_wrbypass_io_WIRE_47) & _GEN_3 | _wrbypass_io_WIRE_47 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_56 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_6 =
(~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_3_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_3_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46
wire [2:0] per_bank_update_wdata_3_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_6
? ((&_wrbypass_io_WIRE_56) & _GEN
? 3'h7
: _wrbypass_io_WIRE_56 == 3'h0 & ~_GEN
? 3'h0
: _GEN
? 3'(_wrbypass_io_WIRE_56 + 3'h1)
: 3'(_wrbypass_io_WIRE_56 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_3_0 =
(wrbypass_data_valid_6
? ~((&_wrbypass_io_WIRE_56) & _GEN | _wrbypass_io_WIRE_56 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_65 =
(io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_7 =
(io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_3_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_3_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46
wire [2:0] per_bank_update_wdata_3_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_7
? ((&_wrbypass_io_WIRE_65) & _GEN_3
? 3'h7
: _wrbypass_io_WIRE_65 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3
? 3'(_wrbypass_io_WIRE_65 + 3'h1)
: 3'(_wrbypass_io_WIRE_65 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_3_1 =
(wrbypass_data_valid_7
? ~((&_wrbypass_io_WIRE_65) & _GEN_3 | _wrbypass_io_WIRE_65 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
always @(posedge clock) begin
if (_s1_bank_req_1h_T) begin // src/main/scala/chisel3/util/Decoupled.scala:53:35
s1_unhashed_idx <= io_req_bits_pc[38:1]; // src/main/scala/xiangshan/frontend/Tage.scala:305:43, :330:34
s1_tag <=
io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_4_folded_hist
^ {io_req_bits_folded_hist_hist_15_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :291:{29,38,52}, :305:43, :332:25
s1_bank_req_1h_0 <= s0_bank_req_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33
s1_bank_req_1h_1 <= s0_bank_req_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33
s1_bank_req_1h_2 <= s0_bank_req_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33
s1_bank_req_1h_3 <= &(s0_idx[1:0]); // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :334:33
end
if (io_req_valid) begin // src/main/scala/xiangshan/frontend/Tage.scala:245:14
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49
s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49
s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49
end
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset)
powerOnResetState <= 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34
else
powerOnResetState <=
~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready
& _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready
& _table_banks_3_io_r_req_ready) & powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:310:18, :315:11, :399:34, :400:{26,79}, :402:23
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:3]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7
initial begin // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/Tage.scala:240:7
for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
_RANDOM[i[1:0]] = `RANDOM; // src/main/scala/xiangshan/frontend/Tage.scala:240:7
end // src/main/scala/xiangshan/frontend/Tage.scala:240:7
s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][5:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34
s1_tag = _RANDOM[2'h1][24:17]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34, :332:25
s1_bank_req_1h_0 = _RANDOM[2'h3][0]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33
s1_bank_req_1h_1 = _RANDOM[2'h3][1]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33
s1_bank_req_1h_2 = _RANDOM[2'h3][2]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33
s1_bank_req_1h_3 = _RANDOM[2'h3][3]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33
s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][4]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48
s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][5]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48
s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][6]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48
s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][7]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48
powerOnResetState = _RANDOM[2'h3][8]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :399:34
`endif // RANDOMIZE_REG_INIT
if (reset) // src/main/scala/xiangshan/frontend/Tage.scala:240:7
powerOnResetState = 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
FoldedSRAMTemplate us ( // src/main/scala/xiangshan/frontend/Tage.scala:310:18
.clock (clock),
.reset (reset),
.io_r_req_ready (_us_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T), // src/main/scala/chisel3/util/Decoupled.scala:53:35
.io_r_req_bits_setIdx (s0_idx), // src/main/scala/xiangshan/frontend/Tage.scala:290:29
.io_r_resp_data_0 (_us_io_r_resp_data_0),
.io_r_resp_data_1 (_us_io_r_resp_data_1),
.io_w_req_valid (io_update_uMask_0 | io_update_uMask_1), // src/main/scala/xiangshan/frontend/Tage.scala:426:41
.io_w_req_bits_setIdx (update_idx), // src/main/scala/xiangshan/frontend/Tage.scala:290:29
.io_w_req_bits_data_0
(~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :422:48
.io_w_req_bits_data_1
(io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43
.io_w_req_bits_waymask
({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1,
~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}), // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :415:{47,56}, :417:15, :418:7
.extra_reset (io_update_reset_u_0 | io_update_reset_u_1) // src/main/scala/xiangshan/frontend/Tage.scala:311:51
);
FoldedSRAMTemplate_1 table_banks_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_0_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52
.io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/Tage.scala:391:49
.io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_waymask (per_bank_update_way_mask_0) // src/main/scala/xiangshan/frontend/Tage.scala:384:11
);
FoldedSRAMTemplate_1 table_banks_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_1_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52
.io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/Tage.scala:391:49
.io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_waymask (per_bank_update_way_mask_1) // src/main/scala/xiangshan/frontend/Tage.scala:384:11
);
FoldedSRAMTemplate_1 table_banks_2 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_2_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52
.io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2), // src/main/scala/xiangshan/frontend/Tage.scala:391:49
.io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_waymask (per_bank_update_way_mask_2) // src/main/scala/xiangshan/frontend/Tage.scala:384:11
);
FoldedSRAMTemplate_1 table_banks_3 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_3_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & (&(s0_idx[1:0]))), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :322:52
.io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3), // src/main/scala/xiangshan/frontend/Tage.scala:391:49
.io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_waymask (per_bank_update_way_mask_3) // src/main/scala/xiangshan/frontend/Tage.scala:384:11
);
WrBypass bank_wrbypasses_0_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_0), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45
.io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_0_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_0_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_0), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45
.io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_0_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_1_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_1), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45
.io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_1_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_1_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_1), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45
.io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_1_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_2_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_2), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45
.io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_2_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_2_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_2), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45
.io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_2_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_3_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & (&(update_idx[1:0]))), // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45
.io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_3_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_3_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & (&(update_idx[1:0]))), // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45
.io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_3_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits)
);
assign io_req_ready = ~powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :399:34, :407:19
assign io_resps_0_valid =
~(s1_unhashed_idx[0]) & _hit_selected_WIRE | s1_unhashed_idx[0]
& _hit_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34
assign io_resps_0_bits_ctr =
(s1_unhashed_idx[0] ? 3'h0 : _resp_selected_WIRE_1)
| (s1_unhashed_idx[0] ? _resp_selected_WIRE_5 : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34
assign io_resps_0_bits_u =
~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0]
& _us_io_r_resp_data_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :310:18, :330:34
assign io_resps_0_bits_unconf =
~(s1_unhashed_idx[0]) & _unconf_selected_WIRE | s1_unhashed_idx[0]
& _unconf_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34
assign io_resps_1_valid =
s1_unhashed_idx[0] & _hit_selected_WIRE | ~(s1_unhashed_idx[0])
& _hit_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34
assign io_resps_1_bits_ctr =
(s1_unhashed_idx[0] ? _resp_selected_WIRE_1 : 3'h0)
| (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_WIRE_5); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34
assign io_resps_1_bits_u =
s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0])
& _us_io_r_resp_data_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :310:18, :330:34
assign io_resps_1_bits_unconf =
s1_unhashed_idx[0] & _unconf_selected_WIRE | ~(s1_unhashed_idx[0])
& _unconf_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34
endmodule

765
src/TageSC/TageTable_2.sv Normal file
View File

@ -0,0 +1,765 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module TageTable_2( // src/main/scala/xiangshan/frontend/Tage.scala:240:7
input clock,
input reset,
output io_req_ready, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_req_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [10:0] io_req_bits_folded_hist_hist_17_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [6:0] io_req_bits_folded_hist_hist_9_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [7:0] io_req_bits_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output io_resps_0_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output [2:0] io_resps_0_bits_ctr, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output io_resps_0_bits_u, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output io_resps_0_bits_unconf, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output io_resps_1_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output [2:0] io_resps_1_bits_ctr, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output io_resps_1_bits_u, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output io_resps_1_bits_unconf, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [10:0] io_update_folded_hist_hist_17_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [6:0] io_update_folded_hist_hist_9_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [7:0] io_update_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_mask_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_mask_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_takens_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_takens_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_alloc_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_alloc_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [2:0] io_update_oldCtrs_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [2:0] io_update_oldCtrs_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_uMask_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_uMask_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_us_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_us_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_reset_u_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_reset_u_1 // src/main/scala/xiangshan/frontend/Tage.scala:245:14
);
wire per_bank_not_silent_update_3_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_3_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_2_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_2_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_1_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_1_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_0_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_0_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
reg powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:399:34
wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73
wire _bank_wrbypasses_3_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_3_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_3_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_3_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_2_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_2_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_2_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_2_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_1_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_1_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_1_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_1_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_0_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_0_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_0_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_0_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _table_banks_3_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_3_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_3_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_3_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_3_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_3_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_3_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_2_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_2_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_2_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_2_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_2_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_2_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_2_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_1_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_1_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_1_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_1_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_1_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_0_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_0_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_0_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_0_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_0_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _us_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:310:18
wire _us_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/Tage.scala:310:18
wire _us_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/Tage.scala:310:18
wire [10:0] s0_idx = io_req_bits_pc[11:1] ^ io_req_bits_folded_hist_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43
wire s0_bank_req_1h_0 = s0_idx[1:0] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}
wire s0_bank_req_1h_1 = s0_idx[1:0] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}
wire s0_bank_req_1h_2 = s0_idx[1:0] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}
wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid; // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:399:34, :407:19
reg [37:0] s1_unhashed_idx; // src/main/scala/xiangshan/frontend/Tage.scala:330:34
reg [7:0] s1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:332:25
reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:334:33
reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:334:33
reg s1_bank_req_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:334:33
reg s1_bank_req_1h_3; // src/main/scala/xiangshan/frontend/Tage.scala:334:33
reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/Tage.scala:335:48
reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/Tage.scala:335:48
reg s1_bank_has_write_on_this_req_2; // src/main/scala/xiangshan/frontend/Tage.scala:335:48
reg s1_bank_has_write_on_this_req_3; // src/main/scala/xiangshan/frontend/Tage.scala:335:48
wire [2:0] _resp_selected_WIRE_1 =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33
wire [2:0] _resp_selected_WIRE_5 =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33
wire _unconf_selected_WIRE =
s1_bank_req_1h_0
& (_table_banks_0_io_r_resp_data_0_ctr == 3'h4
| _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1
& (_table_banks_1_io_r_resp_data_0_ctr == 3'h4
| _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2
& (_table_banks_2_io_r_resp_data_0_ctr == 3'h4
| _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3
& (_table_banks_3_io_r_resp_data_0_ctr == 3'h4
| _table_banks_3_io_r_resp_data_0_ctr == 3'h3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14
wire _unconf_selected_WIRE_1 =
s1_bank_req_1h_0
& (_table_banks_0_io_r_resp_data_1_ctr == 3'h4
| _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1
& (_table_banks_1_io_r_resp_data_1_ctr == 3'h4
| _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2
& (_table_banks_2_io_r_resp_data_1_ctr == 3'h4
| _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3
& (_table_banks_3_io_r_resp_data_1_ctr == 3'h4
| _table_banks_3_io_r_resp_data_1_ctr == 3'h3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14
wire _hit_selected_WIRE =
s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag
& _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE
| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag
& _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE
| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag
& _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE
| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag
& _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82}
wire _hit_selected_WIRE_1 =
s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag
& _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE
| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag
& _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE
| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag
& _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE
| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag
& _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82}
assign _resp_invalid_by_write_WIRE =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2
| s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:334:33, :335:48
wire [10:0] update_idx = io_update_pc[11:1] ^ io_update_folded_hist_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43
wire [7:0] per_bank_update_wdata_3_1_tag =
io_update_pc[8:1] ^ io_update_folded_hist_hist_3_folded_hist
^ {io_update_folded_hist_hist_9_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :291:{29,38,52}, :305:43
wire update_req_bank_1h_0 = update_idx[1:0] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}
wire update_req_bank_1h_1 = update_idx[1:0] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}
wire update_req_bank_1h_2 = update_idx[1:0] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}
wire [1:0] per_bank_update_way_mask_0 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_0_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_0_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81
wire [1:0] per_bank_update_way_mask_1 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_1_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_1_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81
wire [1:0] per_bank_update_way_mask_2 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_2_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_2_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81
wire [1:0] per_bank_update_way_mask_3 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_3_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_3_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81
wire _s1_bank_has_write_on_this_req_WIRE_0 =
(|per_bank_update_way_mask_0) & update_req_bank_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49}
wire _s1_bank_has_write_on_this_req_WIRE_1 =
(|per_bank_update_way_mask_1) & update_req_bank_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49}
wire _s1_bank_has_write_on_this_req_WIRE_2 =
(|per_bank_update_way_mask_2) & update_req_bank_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49}
wire _s1_bank_has_write_on_this_req_WIRE_3 =
(|per_bank_update_way_mask_3) & (&(update_idx[1:0])); // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :384:11, :391:{45,49}
wire [2:0] _wrbypass_io_WIRE_2 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid =
(~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_0_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_0_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46
wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14
wire [2:0] _GEN_0 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43
wire _GEN_1 = (|_GEN_0) | _GEN; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :97:10, src/main/scala/xiangshan/frontend/Tage.scala:449:14
wire _GEN_2 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12
wire [2:0] per_bank_update_wdata_0_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid
? ((&_wrbypass_io_WIRE_2) & _GEN
? 3'h7
: _wrbypass_io_WIRE_2 == 3'h0 & ~_GEN
? 3'h0
: _GEN
? 3'(_wrbypass_io_WIRE_2 + 3'h1)
: 3'(_wrbypass_io_WIRE_2 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_0_0 =
(wrbypass_data_valid
? ~((&_wrbypass_io_WIRE_2) & _GEN | _wrbypass_io_WIRE_2 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_11 =
(io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_1 =
(io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_0_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_0_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46
wire _GEN_3 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14
wire [2:0] _GEN_4 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43
wire _GEN_5 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12
wire [2:0] per_bank_update_wdata_0_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_1
? ((&_wrbypass_io_WIRE_11) & _GEN_3
? 3'h7
: _wrbypass_io_WIRE_11 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3
? 3'(_wrbypass_io_WIRE_11 + 3'h1)
: 3'(_wrbypass_io_WIRE_11 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_0_1 =
(wrbypass_data_valid_1
? ~((&_wrbypass_io_WIRE_11) & _GEN_3 | _wrbypass_io_WIRE_11 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_20 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_2 =
(~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_1_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_1_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46
wire [2:0] per_bank_update_wdata_1_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_2
? ((&_wrbypass_io_WIRE_20) & _GEN
? 3'h7
: _wrbypass_io_WIRE_20 == 3'h0 & ~_GEN
? 3'h0
: _GEN
? 3'(_wrbypass_io_WIRE_20 + 3'h1)
: 3'(_wrbypass_io_WIRE_20 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_1_0 =
(wrbypass_data_valid_2
? ~((&_wrbypass_io_WIRE_20) & _GEN | _wrbypass_io_WIRE_20 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_29 =
(io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_3 =
(io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_1_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_1_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46
wire [2:0] per_bank_update_wdata_1_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_3
? ((&_wrbypass_io_WIRE_29) & _GEN_3
? 3'h7
: _wrbypass_io_WIRE_29 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3
? 3'(_wrbypass_io_WIRE_29 + 3'h1)
: 3'(_wrbypass_io_WIRE_29 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_1_1 =
(wrbypass_data_valid_3
? ~((&_wrbypass_io_WIRE_29) & _GEN_3 | _wrbypass_io_WIRE_29 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_38 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_4 =
(~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_2_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_2_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46
wire [2:0] per_bank_update_wdata_2_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_4
? ((&_wrbypass_io_WIRE_38) & _GEN
? 3'h7
: _wrbypass_io_WIRE_38 == 3'h0 & ~_GEN
? 3'h0
: _GEN
? 3'(_wrbypass_io_WIRE_38 + 3'h1)
: 3'(_wrbypass_io_WIRE_38 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_2_0 =
(wrbypass_data_valid_4
? ~((&_wrbypass_io_WIRE_38) & _GEN | _wrbypass_io_WIRE_38 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_47 =
(io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_5 =
(io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_2_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_2_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46
wire [2:0] per_bank_update_wdata_2_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_5
? ((&_wrbypass_io_WIRE_47) & _GEN_3
? 3'h7
: _wrbypass_io_WIRE_47 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3
? 3'(_wrbypass_io_WIRE_47 + 3'h1)
: 3'(_wrbypass_io_WIRE_47 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_2_1 =
(wrbypass_data_valid_5
? ~((&_wrbypass_io_WIRE_47) & _GEN_3 | _wrbypass_io_WIRE_47 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_56 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_6 =
(~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_3_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_3_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46
wire [2:0] per_bank_update_wdata_3_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_6
? ((&_wrbypass_io_WIRE_56) & _GEN
? 3'h7
: _wrbypass_io_WIRE_56 == 3'h0 & ~_GEN
? 3'h0
: _GEN
? 3'(_wrbypass_io_WIRE_56 + 3'h1)
: 3'(_wrbypass_io_WIRE_56 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_3_0 =
(wrbypass_data_valid_6
? ~((&_wrbypass_io_WIRE_56) & _GEN | _wrbypass_io_WIRE_56 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_65 =
(io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_7 =
(io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_3_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_3_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46
wire [2:0] per_bank_update_wdata_3_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_7
? ((&_wrbypass_io_WIRE_65) & _GEN_3
? 3'h7
: _wrbypass_io_WIRE_65 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3
? 3'(_wrbypass_io_WIRE_65 + 3'h1)
: 3'(_wrbypass_io_WIRE_65 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_3_1 =
(wrbypass_data_valid_7
? ~((&_wrbypass_io_WIRE_65) & _GEN_3 | _wrbypass_io_WIRE_65 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
always @(posedge clock) begin
if (_s1_bank_req_1h_T) begin // src/main/scala/chisel3/util/Decoupled.scala:53:35
s1_unhashed_idx <= io_req_bits_pc[38:1]; // src/main/scala/xiangshan/frontend/Tage.scala:305:43, :330:34
s1_tag <=
io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_3_folded_hist
^ {io_req_bits_folded_hist_hist_9_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :291:{29,38,52}, :305:43, :332:25
s1_bank_req_1h_0 <= s0_bank_req_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33
s1_bank_req_1h_1 <= s0_bank_req_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33
s1_bank_req_1h_2 <= s0_bank_req_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33
s1_bank_req_1h_3 <= &(s0_idx[1:0]); // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :334:33
end
if (io_req_valid) begin // src/main/scala/xiangshan/frontend/Tage.scala:245:14
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49
s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49
s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49
end
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset)
powerOnResetState <= 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34
else
powerOnResetState <=
~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready
& _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready
& _table_banks_3_io_r_req_ready) & powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:310:18, :315:11, :399:34, :400:{26,79}, :402:23
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:3]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7
initial begin // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/Tage.scala:240:7
for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
_RANDOM[i[1:0]] = `RANDOM; // src/main/scala/xiangshan/frontend/Tage.scala:240:7
end // src/main/scala/xiangshan/frontend/Tage.scala:240:7
s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][5:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34
s1_tag = _RANDOM[2'h1][24:17]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34, :332:25
s1_bank_req_1h_0 = _RANDOM[2'h3][0]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33
s1_bank_req_1h_1 = _RANDOM[2'h3][1]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33
s1_bank_req_1h_2 = _RANDOM[2'h3][2]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33
s1_bank_req_1h_3 = _RANDOM[2'h3][3]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33
s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][4]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48
s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][5]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48
s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][6]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48
s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][7]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48
powerOnResetState = _RANDOM[2'h3][8]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :399:34
`endif // RANDOMIZE_REG_INIT
if (reset) // src/main/scala/xiangshan/frontend/Tage.scala:240:7
powerOnResetState = 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
FoldedSRAMTemplate us ( // src/main/scala/xiangshan/frontend/Tage.scala:310:18
.clock (clock),
.reset (reset),
.io_r_req_ready (_us_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T), // src/main/scala/chisel3/util/Decoupled.scala:53:35
.io_r_req_bits_setIdx (s0_idx), // src/main/scala/xiangshan/frontend/Tage.scala:290:29
.io_r_resp_data_0 (_us_io_r_resp_data_0),
.io_r_resp_data_1 (_us_io_r_resp_data_1),
.io_w_req_valid (io_update_uMask_0 | io_update_uMask_1), // src/main/scala/xiangshan/frontend/Tage.scala:426:41
.io_w_req_bits_setIdx (update_idx), // src/main/scala/xiangshan/frontend/Tage.scala:290:29
.io_w_req_bits_data_0
(~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :422:48
.io_w_req_bits_data_1
(io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43
.io_w_req_bits_waymask
({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1,
~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}), // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :415:{47,56}, :417:15, :418:7
.extra_reset (io_update_reset_u_0 | io_update_reset_u_1) // src/main/scala/xiangshan/frontend/Tage.scala:311:51
);
FoldedSRAMTemplate_1 table_banks_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_0_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52
.io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/Tage.scala:391:49
.io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_waymask (per_bank_update_way_mask_0) // src/main/scala/xiangshan/frontend/Tage.scala:384:11
);
FoldedSRAMTemplate_1 table_banks_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_1_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52
.io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/Tage.scala:391:49
.io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_waymask (per_bank_update_way_mask_1) // src/main/scala/xiangshan/frontend/Tage.scala:384:11
);
FoldedSRAMTemplate_1 table_banks_2 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_2_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52
.io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2), // src/main/scala/xiangshan/frontend/Tage.scala:391:49
.io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_waymask (per_bank_update_way_mask_2) // src/main/scala/xiangshan/frontend/Tage.scala:384:11
);
FoldedSRAMTemplate_1 table_banks_3 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_3_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & (&(s0_idx[1:0]))), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :322:52
.io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3), // src/main/scala/xiangshan/frontend/Tage.scala:391:49
.io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_waymask (per_bank_update_way_mask_3) // src/main/scala/xiangshan/frontend/Tage.scala:384:11
);
WrBypass bank_wrbypasses_0_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_0), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45
.io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_0_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_0_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_0), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45
.io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_0_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_1_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_1), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45
.io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_1_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_1_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_1), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45
.io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_1_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_2_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_2), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45
.io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_2_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_2_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_2), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45
.io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_2_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_3_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & (&(update_idx[1:0]))), // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45
.io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_3_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_3_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & (&(update_idx[1:0]))), // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45
.io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_3_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits)
);
assign io_req_ready = ~powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :399:34, :407:19
assign io_resps_0_valid =
~(s1_unhashed_idx[0]) & _hit_selected_WIRE | s1_unhashed_idx[0]
& _hit_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34
assign io_resps_0_bits_ctr =
(s1_unhashed_idx[0] ? 3'h0 : _resp_selected_WIRE_1)
| (s1_unhashed_idx[0] ? _resp_selected_WIRE_5 : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34
assign io_resps_0_bits_u =
~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0]
& _us_io_r_resp_data_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :310:18, :330:34
assign io_resps_0_bits_unconf =
~(s1_unhashed_idx[0]) & _unconf_selected_WIRE | s1_unhashed_idx[0]
& _unconf_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34
assign io_resps_1_valid =
s1_unhashed_idx[0] & _hit_selected_WIRE | ~(s1_unhashed_idx[0])
& _hit_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34
assign io_resps_1_bits_ctr =
(s1_unhashed_idx[0] ? _resp_selected_WIRE_1 : 3'h0)
| (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_WIRE_5); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34
assign io_resps_1_bits_u =
s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0])
& _us_io_r_resp_data_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :310:18, :330:34
assign io_resps_1_bits_unconf =
s1_unhashed_idx[0] & _unconf_selected_WIRE | ~(s1_unhashed_idx[0])
& _unconf_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34
endmodule

765
src/TageSC/TageTable_3.sv Normal file
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@ -0,0 +1,765 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module TageTable_3( // src/main/scala/xiangshan/frontend/Tage.scala:240:7
input clock,
input reset,
output io_req_ready, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_req_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [10:0] io_req_bits_folded_hist_hist_16_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [7:0] io_req_bits_folded_hist_hist_8_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [6:0] io_req_bits_folded_hist_hist_5_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output io_resps_0_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output [2:0] io_resps_0_bits_ctr, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output io_resps_0_bits_u, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output io_resps_0_bits_unconf, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output io_resps_1_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output [2:0] io_resps_1_bits_ctr, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output io_resps_1_bits_u, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
output io_resps_1_bits_unconf, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [10:0] io_update_folded_hist_hist_16_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [7:0] io_update_folded_hist_hist_8_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [6:0] io_update_folded_hist_hist_5_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_mask_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_mask_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_takens_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_takens_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_alloc_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_alloc_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [2:0] io_update_oldCtrs_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input [2:0] io_update_oldCtrs_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_uMask_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_uMask_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_us_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_us_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_reset_u_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14
input io_update_reset_u_1 // src/main/scala/xiangshan/frontend/Tage.scala:245:14
);
wire per_bank_not_silent_update_3_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_3_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_2_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_2_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_1_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_1_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_0_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
wire per_bank_not_silent_update_0_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81
reg powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:399:34
wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73
wire _bank_wrbypasses_3_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_3_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_3_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_3_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_2_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_2_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_2_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_2_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_1_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_1_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_1_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_1_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_0_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_0_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_0_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _bank_wrbypasses_0_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11
wire _table_banks_3_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_3_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_3_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_3_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_3_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_3_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_3_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_2_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_2_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_2_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_2_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_2_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_2_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_2_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_1_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_1_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_1_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_1_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_1_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_0_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_0_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _table_banks_0_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [7:0] _table_banks_0_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire [2:0] _table_banks_0_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11
wire _us_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:310:18
wire _us_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/Tage.scala:310:18
wire _us_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/Tage.scala:310:18
wire [10:0] s0_idx = io_req_bits_pc[11:1] ^ io_req_bits_folded_hist_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43
wire s0_bank_req_1h_0 = s0_idx[1:0] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}
wire s0_bank_req_1h_1 = s0_idx[1:0] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}
wire s0_bank_req_1h_2 = s0_idx[1:0] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}
wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid; // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:399:34, :407:19
reg [37:0] s1_unhashed_idx; // src/main/scala/xiangshan/frontend/Tage.scala:330:34
reg [7:0] s1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:332:25
reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:334:33
reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:334:33
reg s1_bank_req_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:334:33
reg s1_bank_req_1h_3; // src/main/scala/xiangshan/frontend/Tage.scala:334:33
reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/Tage.scala:335:48
reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/Tage.scala:335:48
reg s1_bank_has_write_on_this_req_2; // src/main/scala/xiangshan/frontend/Tage.scala:335:48
reg s1_bank_has_write_on_this_req_3; // src/main/scala/xiangshan/frontend/Tage.scala:335:48
wire [2:0] _resp_selected_WIRE_1 =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33
wire [2:0] _resp_selected_WIRE_5 =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33
wire _unconf_selected_WIRE =
s1_bank_req_1h_0
& (_table_banks_0_io_r_resp_data_0_ctr == 3'h4
| _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1
& (_table_banks_1_io_r_resp_data_0_ctr == 3'h4
| _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2
& (_table_banks_2_io_r_resp_data_0_ctr == 3'h4
| _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3
& (_table_banks_3_io_r_resp_data_0_ctr == 3'h4
| _table_banks_3_io_r_resp_data_0_ctr == 3'h3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14
wire _unconf_selected_WIRE_1 =
s1_bank_req_1h_0
& (_table_banks_0_io_r_resp_data_1_ctr == 3'h4
| _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1
& (_table_banks_1_io_r_resp_data_1_ctr == 3'h4
| _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2
& (_table_banks_2_io_r_resp_data_1_ctr == 3'h4
| _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3
& (_table_banks_3_io_r_resp_data_1_ctr == 3'h4
| _table_banks_3_io_r_resp_data_1_ctr == 3'h3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14
wire _hit_selected_WIRE =
s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag
& _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE
| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag
& _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE
| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag
& _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE
| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag
& _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82}
wire _hit_selected_WIRE_1 =
s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag
& _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE
| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag
& _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE
| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag
& _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE
| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag
& _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82}
assign _resp_invalid_by_write_WIRE =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2
| s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:334:33, :335:48
wire [10:0] update_idx = io_update_pc[11:1] ^ io_update_folded_hist_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43
wire [7:0] per_bank_update_wdata_3_1_tag =
io_update_pc[8:1] ^ io_update_folded_hist_hist_8_folded_hist
^ {io_update_folded_hist_hist_5_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :291:{29,38,52}, :305:43
wire update_req_bank_1h_0 = update_idx[1:0] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}
wire update_req_bank_1h_1 = update_idx[1:0] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}
wire update_req_bank_1h_2 = update_idx[1:0] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38}
wire [1:0] per_bank_update_way_mask_0 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_0_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_0_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81
wire [1:0] per_bank_update_way_mask_1 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_1_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_1_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81
wire [1:0] per_bank_update_way_mask_2 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_2_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_2_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81
wire [1:0] per_bank_update_way_mask_3 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_3_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_3_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81
wire _s1_bank_has_write_on_this_req_WIRE_0 =
(|per_bank_update_way_mask_0) & update_req_bank_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49}
wire _s1_bank_has_write_on_this_req_WIRE_1 =
(|per_bank_update_way_mask_1) & update_req_bank_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49}
wire _s1_bank_has_write_on_this_req_WIRE_2 =
(|per_bank_update_way_mask_2) & update_req_bank_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49}
wire _s1_bank_has_write_on_this_req_WIRE_3 =
(|per_bank_update_way_mask_3) & (&(update_idx[1:0])); // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :384:11, :391:{45,49}
wire [2:0] _wrbypass_io_WIRE_2 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid =
(~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_0_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_0_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46
wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14
wire [2:0] _GEN_0 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43
wire _GEN_1 = (|_GEN_0) | _GEN; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :97:10, src/main/scala/xiangshan/frontend/Tage.scala:449:14
wire _GEN_2 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12
wire [2:0] per_bank_update_wdata_0_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid
? ((&_wrbypass_io_WIRE_2) & _GEN
? 3'h7
: _wrbypass_io_WIRE_2 == 3'h0 & ~_GEN
? 3'h0
: _GEN
? 3'(_wrbypass_io_WIRE_2 + 3'h1)
: 3'(_wrbypass_io_WIRE_2 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_0_0 =
(wrbypass_data_valid
? ~((&_wrbypass_io_WIRE_2) & _GEN | _wrbypass_io_WIRE_2 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_11 =
(io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_1 =
(io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_0_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_0_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46
wire _GEN_3 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14
wire [2:0] _GEN_4 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43
wire _GEN_5 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12
wire [2:0] per_bank_update_wdata_0_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_1
? ((&_wrbypass_io_WIRE_11) & _GEN_3
? 3'h7
: _wrbypass_io_WIRE_11 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3
? 3'(_wrbypass_io_WIRE_11 + 3'h1)
: 3'(_wrbypass_io_WIRE_11 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_0_1 =
(wrbypass_data_valid_1
? ~((&_wrbypass_io_WIRE_11) & _GEN_3 | _wrbypass_io_WIRE_11 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_20 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_2 =
(~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_1_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_1_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46
wire [2:0] per_bank_update_wdata_1_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_2
? ((&_wrbypass_io_WIRE_20) & _GEN
? 3'h7
: _wrbypass_io_WIRE_20 == 3'h0 & ~_GEN
? 3'h0
: _GEN
? 3'(_wrbypass_io_WIRE_20 + 3'h1)
: 3'(_wrbypass_io_WIRE_20 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_1_0 =
(wrbypass_data_valid_2
? ~((&_wrbypass_io_WIRE_20) & _GEN | _wrbypass_io_WIRE_20 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_29 =
(io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_3 =
(io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_1_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_1_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46
wire [2:0] per_bank_update_wdata_1_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_3
? ((&_wrbypass_io_WIRE_29) & _GEN_3
? 3'h7
: _wrbypass_io_WIRE_29 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3
? 3'(_wrbypass_io_WIRE_29 + 3'h1)
: 3'(_wrbypass_io_WIRE_29 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_1_1 =
(wrbypass_data_valid_3
? ~((&_wrbypass_io_WIRE_29) & _GEN_3 | _wrbypass_io_WIRE_29 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_38 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_4 =
(~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_2_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_2_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46
wire [2:0] per_bank_update_wdata_2_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_4
? ((&_wrbypass_io_WIRE_38) & _GEN
? 3'h7
: _wrbypass_io_WIRE_38 == 3'h0 & ~_GEN
? 3'h0
: _GEN
? 3'(_wrbypass_io_WIRE_38 + 3'h1)
: 3'(_wrbypass_io_WIRE_38 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_2_0 =
(wrbypass_data_valid_4
? ~((&_wrbypass_io_WIRE_38) & _GEN | _wrbypass_io_WIRE_38 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_47 =
(io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_5 =
(io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_2_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_2_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46
wire [2:0] per_bank_update_wdata_2_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_5
? ((&_wrbypass_io_WIRE_47) & _GEN_3
? 3'h7
: _wrbypass_io_WIRE_47 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3
? 3'(_wrbypass_io_WIRE_47 + 3'h1)
: 3'(_wrbypass_io_WIRE_47 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_2_1 =
(wrbypass_data_valid_5
? ~((&_wrbypass_io_WIRE_47) & _GEN_3 | _wrbypass_io_WIRE_47 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_56 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_6 =
(~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_3_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_3_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46
wire [2:0] per_bank_update_wdata_3_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_6
? ((&_wrbypass_io_WIRE_56) & _GEN
? 3'h7
: _wrbypass_io_WIRE_56 == 3'h0 & ~_GEN
? 3'h0
: _GEN
? 3'(_wrbypass_io_WIRE_56 + 3'h1)
: 3'(_wrbypass_io_WIRE_56 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_3_0 =
(wrbypass_data_valid_6
? ~((&_wrbypass_io_WIRE_56) & _GEN | _wrbypass_io_WIRE_56 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
wire [2:0] _wrbypass_io_WIRE_65 =
(io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11
wire wrbypass_data_valid_7 =
(io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_3_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_3_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46
wire [2:0] per_bank_update_wdata_3_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_7
? ((&_wrbypass_io_WIRE_65) & _GEN_3
? 3'h7
: _wrbypass_io_WIRE_65 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3
? 3'(_wrbypass_io_WIRE_65 + 3'h1)
: 3'(_wrbypass_io_WIRE_65 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14
assign per_bank_not_silent_update_3_1 =
(wrbypass_data_valid_7
? ~((&_wrbypass_io_WIRE_65) & _GEN_3 | _wrbypass_io_WIRE_65 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81}
always @(posedge clock) begin
if (_s1_bank_req_1h_T) begin // src/main/scala/chisel3/util/Decoupled.scala:53:35
s1_unhashed_idx <= io_req_bits_pc[38:1]; // src/main/scala/xiangshan/frontend/Tage.scala:305:43, :330:34
s1_tag <=
io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_8_folded_hist
^ {io_req_bits_folded_hist_hist_5_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :291:{29,38,52}, :305:43, :332:25
s1_bank_req_1h_0 <= s0_bank_req_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33
s1_bank_req_1h_1 <= s0_bank_req_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33
s1_bank_req_1h_2 <= s0_bank_req_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33
s1_bank_req_1h_3 <= &(s0_idx[1:0]); // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :334:33
end
if (io_req_valid) begin // src/main/scala/xiangshan/frontend/Tage.scala:245:14
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49
s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49
s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49
end
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset)
powerOnResetState <= 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34
else
powerOnResetState <=
~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready
& _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready
& _table_banks_3_io_r_req_ready) & powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:310:18, :315:11, :399:34, :400:{26,79}, :402:23
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:3]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7
initial begin // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/Tage.scala:240:7
for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
_RANDOM[i[1:0]] = `RANDOM; // src/main/scala/xiangshan/frontend/Tage.scala:240:7
end // src/main/scala/xiangshan/frontend/Tage.scala:240:7
s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][5:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34
s1_tag = _RANDOM[2'h1][24:17]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34, :332:25
s1_bank_req_1h_0 = _RANDOM[2'h3][0]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33
s1_bank_req_1h_1 = _RANDOM[2'h3][1]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33
s1_bank_req_1h_2 = _RANDOM[2'h3][2]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33
s1_bank_req_1h_3 = _RANDOM[2'h3][3]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33
s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][4]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48
s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][5]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48
s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][6]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48
s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][7]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48
powerOnResetState = _RANDOM[2'h3][8]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :399:34
`endif // RANDOMIZE_REG_INIT
if (reset) // src/main/scala/xiangshan/frontend/Tage.scala:240:7
powerOnResetState = 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
FoldedSRAMTemplate us ( // src/main/scala/xiangshan/frontend/Tage.scala:310:18
.clock (clock),
.reset (reset),
.io_r_req_ready (_us_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T), // src/main/scala/chisel3/util/Decoupled.scala:53:35
.io_r_req_bits_setIdx (s0_idx), // src/main/scala/xiangshan/frontend/Tage.scala:290:29
.io_r_resp_data_0 (_us_io_r_resp_data_0),
.io_r_resp_data_1 (_us_io_r_resp_data_1),
.io_w_req_valid (io_update_uMask_0 | io_update_uMask_1), // src/main/scala/xiangshan/frontend/Tage.scala:426:41
.io_w_req_bits_setIdx (update_idx), // src/main/scala/xiangshan/frontend/Tage.scala:290:29
.io_w_req_bits_data_0
(~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :422:48
.io_w_req_bits_data_1
(io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43
.io_w_req_bits_waymask
({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1,
~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}), // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :415:{47,56}, :417:15, :418:7
.extra_reset (io_update_reset_u_0 | io_update_reset_u_1) // src/main/scala/xiangshan/frontend/Tage.scala:311:51
);
FoldedSRAMTemplate_1 table_banks_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_0_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52
.io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/Tage.scala:391:49
.io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_waymask (per_bank_update_way_mask_0) // src/main/scala/xiangshan/frontend/Tage.scala:384:11
);
FoldedSRAMTemplate_1 table_banks_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_1_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52
.io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/Tage.scala:391:49
.io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_waymask (per_bank_update_way_mask_1) // src/main/scala/xiangshan/frontend/Tage.scala:384:11
);
FoldedSRAMTemplate_1 table_banks_2 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_2_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52
.io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2), // src/main/scala/xiangshan/frontend/Tage.scala:391:49
.io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_waymask (per_bank_update_way_mask_2) // src/main/scala/xiangshan/frontend/Tage.scala:384:11
);
FoldedSRAMTemplate_1 table_banks_3 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_3_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & (&(s0_idx[1:0]))), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :322:52
.io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3), // src/main/scala/xiangshan/frontend/Tage.scala:391:49
.io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12
.io_w_req_bits_waymask (per_bank_update_way_mask_3) // src/main/scala/xiangshan/frontend/Tage.scala:384:11
);
WrBypass bank_wrbypasses_0_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_0), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45
.io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_0_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_0_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_0), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45
.io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_0_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_1_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_1), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45
.io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_1_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_1_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_1), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45
.io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_1_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_2_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_2), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45
.io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_2_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_2_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_2), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45
.io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_2_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_3_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & (&(update_idx[1:0]))), // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45
.io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_3_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_3_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & (&(update_idx[1:0]))), // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45
.io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38}
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12
.io_hit (_bank_wrbypasses_3_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits)
);
assign io_req_ready = ~powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :399:34, :407:19
assign io_resps_0_valid =
~(s1_unhashed_idx[0]) & _hit_selected_WIRE | s1_unhashed_idx[0]
& _hit_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34
assign io_resps_0_bits_ctr =
(s1_unhashed_idx[0] ? 3'h0 : _resp_selected_WIRE_1)
| (s1_unhashed_idx[0] ? _resp_selected_WIRE_5 : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34
assign io_resps_0_bits_u =
~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0]
& _us_io_r_resp_data_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :310:18, :330:34
assign io_resps_0_bits_unconf =
~(s1_unhashed_idx[0]) & _unconf_selected_WIRE | s1_unhashed_idx[0]
& _unconf_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34
assign io_resps_1_valid =
s1_unhashed_idx[0] & _hit_selected_WIRE | ~(s1_unhashed_idx[0])
& _hit_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34
assign io_resps_1_bits_ctr =
(s1_unhashed_idx[0] ? _resp_selected_WIRE_1 : 3'h0)
| (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_WIRE_5); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34
assign io_resps_1_bits_u =
s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0])
& _us_io_r_resp_data_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :310:18, :330:34
assign io_resps_1_bits_unconf =
s1_unhashed_idx[0] & _unconf_selected_WIRE | ~(s1_unhashed_idx[0])
& _unconf_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34
endmodule

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// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module array_4( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
input [7:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [15:0] RW0_wdata,
output [15:0] RW0_rdata,
input [15:0] RW0_wmask
);
array_4_ext array_4_ext ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
);
endmodule

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// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module array_5( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
input [8:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [23:0] RW0_wdata,
output [23:0] RW0_rdata,
input [1:0] RW0_wmask
);
array_5_ext array_5_ext ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
);
endmodule

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// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module array_6( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
input [8:0] R0_addr,
input R0_en,
input R0_clk,
output [15:0] R0_data,
input [8:0] W0_addr,
input W0_en,
input W0_clk,
input [15:0] W0_data,
input [7:0] W0_mask
);
array_6_ext array_6_ext ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
);
endmodule

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// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module array_7( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
input [7:0] R0_addr,
input R0_en,
input R0_clk,
output [23:0] R0_data,
input [7:0] W0_addr,
input W0_en,
input W0_clk,
input [23:0] W0_data,
input [3:0] W0_mask
);
array_7_ext array_7_ext ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
);
endmodule

89
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// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
// VCS coverage exclude_file
module data_mem_0_8x3( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
input [2:0] R0_addr,
input R0_en,
input R0_clk,
output [2:0] R0_data,
input [2:0] W0_addr,
input W0_en,
input W0_clk,
input [2:0] W0_data
);
reg [2:0] Memory[0:7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
always @(posedge W0_clk) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
if (W0_en & 1'h1) // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
Memory[W0_addr] <= W0_data; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_ // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
reg [31:0] _RANDOM_MEM; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
`ifdef RANDOMIZE_MEM_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
for (logic [3:0] i = 4'h0; i < 4'h8; i += 4'h1) begin
_RANDOM_MEM = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
Memory[i[2:0]] = _RANDOM_MEM[2:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
end // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
`endif // RANDOMIZE_MEM_INIT
end // initial
`endif // ENABLE_INITIAL_MEM_
assign R0_data = R0_en ? Memory[R0_addr] : 3'bx; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
endmodule

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// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
// VCS coverage exclude_file
module data_mem_16x12( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
input [3:0] R0_addr,
input R0_en,
input R0_clk,
output [11:0] R0_data,
input [3:0] R1_addr,
input R1_en,
input R1_clk,
output [11:0] R1_data,
input [3:0] W0_addr,
input W0_en,
input W0_clk,
input [11:0] W0_data,
input [1:0] W0_mask
);
reg [11:0] Memory[0:15]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
always @(posedge W0_clk) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
if (W0_en & W0_mask[0]) // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
Memory[W0_addr][32'h0 +: 6] <= W0_data[5:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
if (W0_en & W0_mask[1]) // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
Memory[W0_addr][32'h6 +: 6] <= W0_data[11:6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_ // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
reg [31:0] _RANDOM_MEM; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
`ifdef RANDOMIZE_MEM_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
for (logic [4:0] i = 5'h0; i < 5'h10; i += 5'h1) begin
_RANDOM_MEM = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
Memory[i[3:0]] = _RANDOM_MEM[11:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
end // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
`endif // RANDOMIZE_MEM_INIT
end // initial
`endif // ENABLE_INITIAL_MEM_
assign R0_data = R0_en ? Memory[R0_addr] : 12'bx; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
assign R1_data = R1_en ? Memory[R1_addr] : 12'bx; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
endmodule

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// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
// VCS coverage exclude_file
module data_mem_8x4( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
input [2:0] R0_addr,
input R0_en,
input R0_clk,
output [3:0] R0_data,
input [2:0] R1_addr,
input R1_en,
input R1_clk,
output [3:0] R1_data,
input [2:0] W0_addr,
input W0_en,
input W0_clk,
input [3:0] W0_data,
input [1:0] W0_mask
);
reg [3:0] Memory[0:7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
always @(posedge W0_clk) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
if (W0_en & W0_mask[0]) // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
Memory[W0_addr][32'h0 +: 2] <= W0_data[1:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
if (W0_en & W0_mask[1]) // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
Memory[W0_addr][32'h2 +: 2] <= W0_data[3:2]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_ // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
reg [31:0] _RANDOM_MEM; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
`ifdef RANDOMIZE_MEM_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
for (logic [3:0] i = 4'h0; i < 4'h8; i += 4'h1) begin
_RANDOM_MEM = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
Memory[i[2:0]] = _RANDOM_MEM[3:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
end // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
`endif // RANDOMIZE_MEM_INIT
end // initial
`endif // ENABLE_INITIAL_MEM_
assign R0_data = R0_en ? Memory[R0_addr] : 4'bx; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
assign R1_data = R1_en ? Memory[R1_addr] : 4'bx; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
endmodule

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src/Tage_SC.txt Normal file
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./src/TageSC/CAMTemplate.sv
./src/TageSC/CAMTemplate_32.sv
./src/TageSC/CAMTemplate_33.sv
./src/TageSC/FoldedSRAMTemplate.sv
./src/TageSC/FoldedSRAMTemplate_1.sv
./src/TageSC/FoldedSRAMTemplate_20.sv
./src/TageSC/SCTable.sv
./src/TageSC/SCTable_1.sv
./src/TageSC/SCTable_2.sv
./src/TageSC/SCTable_3.sv
./src/TageSC/SRAMTemplate_10.sv
./src/TageSC/SRAMTemplate_11.sv
./src/TageSC/SRAMTemplate_30.sv
./src/TageSC/SRAMTemplate_31.sv
./src/TageSC/TageBTable.sv
./src/TageSC/TageTable.sv
./src/TageSC/TageTable_1.sv
./src/TageSC/TageTable_2.sv
./src/TageSC/TageTable_3.sv
#./src/TageSC/Tage_SC.sv
./src/TageSC/array_4.sv
./src/TageSC/array_5.sv
./src/TageSC/array_6.sv
./src/TageSC/array_7.sv
./src/TageSC/data_mem_0_8x3.sv
./src/TageSC/data_mem_16x12.sv
./src/TageSC/data_mem_8x4.sv
#
./src/WrBypass/WrBypass.sv
./src/WrBypass/WrBypass_32.sv
./src/WrBypass/WrBypass_33.sv
./src/common/ext_sram.v
./src/common/DelayN_2.sv

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// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module WrBypass( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
input clock,
input reset,
input io_wen, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
input [8:0] io_write_idx, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
input [2:0] io_write_data_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
output io_hit, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
output io_hit_data_0_valid, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
output [2:0] io_hit_data_0_bits // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
);
wire _idx_tag_cam_io_r_resp_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
reg valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_7_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
wire hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 & ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 & ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 & ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 & ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 & ever_written_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire [2:0] _hit_idx_T_2 =
{hits_oh_7, hits_oh_6, hits_oh_5} | {hits_oh_3, hits_oh_2, hits_oh_1}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83
wire [2:0] data_mem_io_hit_data_0_bits_MPORT_addr =
{|{hits_oh_7, hits_oh_6, hits_oh_5, hits_oh_4},
|(_hit_idx_T_2[2:1]),
_hit_idx_T_2[2] | _hit_idx_T_2[0]}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83
wire hit =
hits_oh_0 | hits_oh_1 | hits_oh_2 | hits_oh_3 | hits_oh_4 | hits_oh_5 | hits_oh_6
| hits_oh_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:61:83, :63:29
reg [6:0] state_reg; // rocket-chip/src/main/scala/util/Replacement.scala:168:72
wire [2:0] enq_idx =
{state_reg[6],
state_reg[6]
? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]}
: {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13
wire [2:0] state_reg_touch_way_sized =
hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37
wire _GEN = enq_idx == 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_0 = enq_idx == 3'h1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_1 = enq_idx == 3'h2; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_2 = enq_idx == 3'h3; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_3 = enq_idx == 3'h4; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_4 = enq_idx == 3'h5; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_5 = enq_idx == 3'h6; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
always @(posedge clock or posedge reset) begin
if (reset) begin
valids_0_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_1_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_2_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_3_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_4_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_5_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_6_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_7_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
ever_written_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_2 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_3 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_4 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_5 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_6 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_7 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
state_reg <= 7'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72
end
else begin
if (io_wen) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
if (hit) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29
valids_0_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h0 | valids_0_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30
valids_1_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h1 | valids_1_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30
valids_2_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h2 | valids_2_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30
valids_3_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h3 | valids_3_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30
valids_4_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h4 | valids_4_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30
valids_5_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h5 | valids_5_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30
valids_6_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h6 | valids_6_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30
valids_7_0 <= (&data_mem_io_hit_data_0_bits_MPORT_addr) | valids_7_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30
end
else begin // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29
valids_0_0 <= _GEN | ~_GEN & valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30
valids_1_0 <= _GEN_0 | ~_GEN_0 & valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30
valids_2_0 <= _GEN_1 | ~_GEN_1 & valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30
valids_3_0 <= _GEN_2 | ~_GEN_2 & valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30
valids_4_0 <= _GEN_3 | ~_GEN_3 & valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30
valids_5_0 <= _GEN_4 | ~_GEN_4 & valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30
valids_6_0 <= _GEN_5 | ~_GEN_5 & valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30
valids_7_0 <= (&enq_idx) | ~(&enq_idx) & valids_7_0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30
end
state_reg <=
{~(state_reg_touch_way_sized[2]),
state_reg_touch_way_sized[2]
? {~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1]
? ~(state_reg_touch_way_sized[0])
: state_reg[4],
state_reg_touch_way_sized[1]
? state_reg[3]
: ~(state_reg_touch_way_sized[0])}
: state_reg[5:3],
state_reg_touch_way_sized[2]
? state_reg[2:0]
: {~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1]
? ~(state_reg_touch_way_sized[0])
: state_reg[1],
state_reg_touch_way_sized[1]
? state_reg[0]
: ~(state_reg_touch_way_sized[0])}}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37
end
ever_written_0 <= io_wen & ~hit & _GEN | ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_1 <= io_wen & ~hit & _GEN_0 | ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_2 <= io_wen & ~hit & _GEN_1 | ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_3 <= io_wen & ~hit & _GEN_2 | ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_4 <= io_wen & ~hit & _GEN_3 | ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_5 <= io_wen & ~hit & _GEN_4 | ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_6 <= io_wen & ~hit & _GEN_5 | ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_7 <= io_wen & ~hit & (&enq_idx) | ever_written_7; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
valids_0_0 = _RANDOM[/*Zero width*/ 1'b0][0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_1_0 = _RANDOM[/*Zero width*/ 1'b0][1]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_2_0 = _RANDOM[/*Zero width*/ 1'b0][2]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_3_0 = _RANDOM[/*Zero width*/ 1'b0][3]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_4_0 = _RANDOM[/*Zero width*/ 1'b0][4]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_5_0 = _RANDOM[/*Zero width*/ 1'b0][5]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_6_0 = _RANDOM[/*Zero width*/ 1'b0][6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_7_0 = _RANDOM[/*Zero width*/ 1'b0][7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][8]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29
ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][9]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29
ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][10]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29
ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][11]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29
ever_written_4 = _RANDOM[/*Zero width*/ 1'b0][12]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29
ever_written_5 = _RANDOM[/*Zero width*/ 1'b0][13]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29
ever_written_6 = _RANDOM[/*Zero width*/ 1'b0][14]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29
ever_written_7 = _RANDOM[/*Zero width*/ 1'b0][15]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29
state_reg = _RANDOM[/*Zero width*/ 1'b0][22:16]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
`endif // RANDOMIZE_REG_INIT
if (reset) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
valids_0_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_1_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_2_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_3_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_4_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_5_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_6_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_7_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
ever_written_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_2 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_3 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_4 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_5 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_6 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_7 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
state_reg = 7'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
CAMTemplate idx_tag_cam ( // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
.clock (clock),
.io_r_req_0_idx (io_write_idx),
.io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0),
.io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1),
.io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2),
.io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3),
.io_r_resp_0_4 (_idx_tag_cam_io_r_resp_0_4),
.io_r_resp_0_5 (_idx_tag_cam_io_r_resp_0_5),
.io_r_resp_0_6 (_idx_tag_cam_io_r_resp_0_6),
.io_r_resp_0_7 (_idx_tag_cam_io_r_resp_0_7),
.io_w_valid (io_wen & ~hit), // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26}
.io_w_bits_data_idx (io_write_idx),
.io_w_bits_index (enq_idx) // rocket-chip/src/main/scala/util/Replacement.scala:249:12
);
data_mem_0_8x3 data_mem_0_ext ( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
.R0_addr (data_mem_io_hit_data_0_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10
.R0_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
.R0_clk (clock),
.R0_data (io_hit_data_0_bits),
.W0_addr (hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx), // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29
.W0_en (io_wen),
.W0_clk (clock),
.W0_data (io_write_data_0)
);
assign io_hit = hit; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29
assign io_hit_data_0_valid =
hits_oh_0 & valids_0_0 | hits_oh_1 & valids_1_0 | hits_oh_2 & valids_2_0 | hits_oh_3
& valids_3_0 | hits_oh_4 & valids_4_0 | hits_oh_5 & valids_5_0 | hits_oh_6
& valids_6_0 | hits_oh_7 & valids_7_0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :61:83
endmodule

358
src/WrBypass/WrBypass_32.sv Normal file
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@ -0,0 +1,358 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module WrBypass_32( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
input clock,
input reset,
input io_wen, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
input [10:0] io_write_idx, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
input [1:0] io_write_data_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
input [1:0] io_write_data_1, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
input io_write_way_mask_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
input io_write_way_mask_1, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
output io_hit, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
output io_hit_data_0_valid, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
output [1:0] io_hit_data_0_bits, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
output io_hit_data_1_valid, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
output [1:0] io_hit_data_1_bits // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
);
wire [3:0] _data_mem_ext_R0_data; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
wire [3:0] _data_mem_ext_R1_data; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
wire _idx_tag_cam_io_r_resp_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
reg valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_1_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_2_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_3_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_4_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_5_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_6_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_7_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_7_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
wire hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 & ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 & ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 & ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 & ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 & ever_written_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire [2:0] _hit_idx_T_2 =
{hits_oh_7, hits_oh_6, hits_oh_5} | {hits_oh_3, hits_oh_2, hits_oh_1}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83
wire [2:0] data_mem_io_hit_data_1_bits_MPORT_addr =
{|{hits_oh_7, hits_oh_6, hits_oh_5, hits_oh_4},
|(_hit_idx_T_2[2:1]),
_hit_idx_T_2[2] | _hit_idx_T_2[0]}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83
wire hit =
hits_oh_0 | hits_oh_1 | hits_oh_2 | hits_oh_3 | hits_oh_4 | hits_oh_5 | hits_oh_6
| hits_oh_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:61:83, :63:29
reg [6:0] state_reg; // rocket-chip/src/main/scala/util/Replacement.scala:168:72
wire [2:0] enq_idx =
{state_reg[6],
state_reg[6]
? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]}
: {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13
wire _GEN = data_mem_io_hit_data_1_bits_MPORT_addr == 3'h0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30
wire _GEN_0 = data_mem_io_hit_data_1_bits_MPORT_addr == 3'h1; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30
wire _GEN_1 = data_mem_io_hit_data_1_bits_MPORT_addr == 3'h2; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30
wire _GEN_2 = data_mem_io_hit_data_1_bits_MPORT_addr == 3'h3; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30
wire _GEN_3 = data_mem_io_hit_data_1_bits_MPORT_addr == 3'h4; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30
wire _GEN_4 = data_mem_io_hit_data_1_bits_MPORT_addr == 3'h5; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30
wire _GEN_5 = data_mem_io_hit_data_1_bits_MPORT_addr == 3'h6; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30
wire [2:0] state_reg_touch_way_sized =
hit ? data_mem_io_hit_data_1_bits_MPORT_addr : enq_idx; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37
wire _GEN_6 = enq_idx == 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_7 = enq_idx == 3'h1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_8 = enq_idx == 3'h2; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_9 = enq_idx == 3'h3; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_10 = enq_idx == 3'h4; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_11 = enq_idx == 3'h5; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_12 = enq_idx == 3'h6; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
always @(posedge clock or posedge reset) begin
if (reset) begin
valids_0_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_0_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_1_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_1_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_2_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_2_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_3_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_3_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_4_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_4_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_5_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_5_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_6_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_6_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_7_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_7_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
ever_written_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_2 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_3 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_4 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_5 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_6 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_7 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
state_reg <= 7'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72
end
else begin
if (io_wen) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
if (hit) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29
valids_0_0 <= io_write_way_mask_0 & _GEN | valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_0_1 <= io_write_way_mask_1 & _GEN | valids_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_1_0 <= io_write_way_mask_0 & _GEN_0 | valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_1_1 <= io_write_way_mask_1 & _GEN_0 | valids_1_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_2_0 <= io_write_way_mask_0 & _GEN_1 | valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_2_1 <= io_write_way_mask_1 & _GEN_1 | valids_2_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_3_0 <= io_write_way_mask_0 & _GEN_2 | valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_3_1 <= io_write_way_mask_1 & _GEN_2 | valids_3_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_4_0 <= io_write_way_mask_0 & _GEN_3 | valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_4_1 <= io_write_way_mask_1 & _GEN_3 | valids_4_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_5_0 <= io_write_way_mask_0 & _GEN_4 | valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_5_1 <= io_write_way_mask_1 & _GEN_4 | valids_5_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_6_0 <= io_write_way_mask_0 & _GEN_5 | valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_6_1 <= io_write_way_mask_1 & _GEN_5 | valids_6_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_7_0 <=
io_write_way_mask_0 & (&data_mem_io_hit_data_1_bits_MPORT_addr) | valids_7_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_7_1 <=
io_write_way_mask_1 & (&data_mem_io_hit_data_1_bits_MPORT_addr) | valids_7_1; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
end
else begin // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29
valids_0_0 <= io_write_way_mask_0 & _GEN_6 | ~_GEN_6 & valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_0_1 <= io_write_way_mask_1 & _GEN_6 | ~_GEN_6 & valids_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_1_0 <= io_write_way_mask_0 & _GEN_7 | ~_GEN_7 & valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_1_1 <= io_write_way_mask_1 & _GEN_7 | ~_GEN_7 & valids_1_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_2_0 <= io_write_way_mask_0 & _GEN_8 | ~_GEN_8 & valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_2_1 <= io_write_way_mask_1 & _GEN_8 | ~_GEN_8 & valids_2_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_3_0 <= io_write_way_mask_0 & _GEN_9 | ~_GEN_9 & valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_3_1 <= io_write_way_mask_1 & _GEN_9 | ~_GEN_9 & valids_3_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_4_0 <= io_write_way_mask_0 & _GEN_10 | ~_GEN_10 & valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_4_1 <= io_write_way_mask_1 & _GEN_10 | ~_GEN_10 & valids_4_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_5_0 <= io_write_way_mask_0 & _GEN_11 | ~_GEN_11 & valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_5_1 <= io_write_way_mask_1 & _GEN_11 | ~_GEN_11 & valids_5_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_6_0 <= io_write_way_mask_0 & _GEN_12 | ~_GEN_12 & valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_6_1 <= io_write_way_mask_1 & _GEN_12 | ~_GEN_12 & valids_6_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_7_0 <= io_write_way_mask_0 & (&enq_idx) | ~(&enq_idx) & valids_7_0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_7_1 <= io_write_way_mask_1 & (&enq_idx) | ~(&enq_idx) & valids_7_1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
end
state_reg <=
{~(state_reg_touch_way_sized[2]),
state_reg_touch_way_sized[2]
? {~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1]
? ~(state_reg_touch_way_sized[0])
: state_reg[4],
state_reg_touch_way_sized[1]
? state_reg[3]
: ~(state_reg_touch_way_sized[0])}
: state_reg[5:3],
state_reg_touch_way_sized[2]
? state_reg[2:0]
: {~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1]
? ~(state_reg_touch_way_sized[0])
: state_reg[1],
state_reg_touch_way_sized[1]
? state_reg[0]
: ~(state_reg_touch_way_sized[0])}}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37
end
ever_written_0 <= io_wen & ~hit & (_GEN_6 | io_wen & _GEN_6) | ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_1 <= io_wen & ~hit & (_GEN_7 | io_wen & _GEN_7) | ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_2 <= io_wen & ~hit & (_GEN_8 | io_wen & _GEN_8) | ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_3 <= io_wen & ~hit & (_GEN_9 | io_wen & _GEN_9) | ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_4 <= io_wen & ~hit & (_GEN_10 | io_wen & _GEN_10) | ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_5 <= io_wen & ~hit & (_GEN_11 | io_wen & _GEN_11) | ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_6 <= io_wen & ~hit & (_GEN_12 | io_wen & _GEN_12) | ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_7 <=
io_wen & ~hit & ((&enq_idx) | io_wen & (&enq_idx)) | ever_written_7; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
valids_0_0 = _RANDOM[/*Zero width*/ 1'b0][0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_0_1 = _RANDOM[/*Zero width*/ 1'b0][1]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_1_0 = _RANDOM[/*Zero width*/ 1'b0][2]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_1_1 = _RANDOM[/*Zero width*/ 1'b0][3]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_2_0 = _RANDOM[/*Zero width*/ 1'b0][4]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_2_1 = _RANDOM[/*Zero width*/ 1'b0][5]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_3_0 = _RANDOM[/*Zero width*/ 1'b0][6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_3_1 = _RANDOM[/*Zero width*/ 1'b0][7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_4_0 = _RANDOM[/*Zero width*/ 1'b0][8]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_4_1 = _RANDOM[/*Zero width*/ 1'b0][9]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_5_0 = _RANDOM[/*Zero width*/ 1'b0][10]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_5_1 = _RANDOM[/*Zero width*/ 1'b0][11]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_6_0 = _RANDOM[/*Zero width*/ 1'b0][12]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_6_1 = _RANDOM[/*Zero width*/ 1'b0][13]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_7_0 = _RANDOM[/*Zero width*/ 1'b0][14]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_7_1 = _RANDOM[/*Zero width*/ 1'b0][15]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][16]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29
ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][17]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29
ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][18]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29
ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][19]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29
ever_written_4 = _RANDOM[/*Zero width*/ 1'b0][20]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29
ever_written_5 = _RANDOM[/*Zero width*/ 1'b0][21]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29
ever_written_6 = _RANDOM[/*Zero width*/ 1'b0][22]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29
ever_written_7 = _RANDOM[/*Zero width*/ 1'b0][23]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29
state_reg = _RANDOM[/*Zero width*/ 1'b0][30:24]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
`endif // RANDOMIZE_REG_INIT
if (reset) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
valids_0_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_0_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_1_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_1_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_2_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_2_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_3_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_3_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_4_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_4_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_5_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_5_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_6_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_6_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_7_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_7_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
ever_written_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_2 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_3 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_4 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_5 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_6 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_7 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
state_reg = 7'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
CAMTemplate_32 idx_tag_cam ( // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
.clock (clock),
.io_r_req_0_idx (io_write_idx),
.io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0),
.io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1),
.io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2),
.io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3),
.io_r_resp_0_4 (_idx_tag_cam_io_r_resp_0_4),
.io_r_resp_0_5 (_idx_tag_cam_io_r_resp_0_5),
.io_r_resp_0_6 (_idx_tag_cam_io_r_resp_0_6),
.io_r_resp_0_7 (_idx_tag_cam_io_r_resp_0_7),
.io_w_valid (io_wen & ~hit), // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26}
.io_w_bits_data_idx (io_write_idx),
.io_w_bits_index (enq_idx) // rocket-chip/src/main/scala/util/Replacement.scala:249:12
);
data_mem_8x4 data_mem_ext ( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
.R0_addr (data_mem_io_hit_data_1_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10
.R0_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
.R0_clk (clock),
.R0_data (_data_mem_ext_R0_data),
.R1_addr (data_mem_io_hit_data_1_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10
.R1_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
.R1_clk (clock),
.R1_data (_data_mem_ext_R1_data),
.W0_addr (hit ? data_mem_io_hit_data_1_bits_MPORT_addr : enq_idx), // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29
.W0_en (io_wen),
.W0_clk (clock),
.W0_data ({io_write_data_1, io_write_data_0}), // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
.W0_mask ({io_write_way_mask_1, io_write_way_mask_0}) // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
);
assign io_hit = hit; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29
assign io_hit_data_0_valid =
hits_oh_0 & valids_0_0 | hits_oh_1 & valids_1_0 | hits_oh_2 & valids_2_0 | hits_oh_3
& valids_3_0 | hits_oh_4 & valids_4_0 | hits_oh_5 & valids_5_0 | hits_oh_6
& valids_6_0 | hits_oh_7 & valids_7_0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :61:83
assign io_hit_data_0_bits = _data_mem_ext_R1_data[1:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :54:21
assign io_hit_data_1_valid =
hits_oh_0 & valids_0_1 | hits_oh_1 & valids_1_1 | hits_oh_2 & valids_2_1 | hits_oh_3
& valids_3_1 | hits_oh_4 & valids_4_1 | hits_oh_5 & valids_5_1 | hits_oh_6
& valids_6_1 | hits_oh_7 & valids_7_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :61:83
assign io_hit_data_1_bits = _data_mem_ext_R0_data[3:2]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :54:21
endmodule

583
src/WrBypass/WrBypass_33.sv Normal file
View File

@ -0,0 +1,583 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module WrBypass_33( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
input clock,
input reset,
input io_wen, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
input [7:0] io_write_idx, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
input [5:0] io_write_data_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
input [5:0] io_write_data_1, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
input io_write_way_mask_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
input io_write_way_mask_1, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
output io_hit, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
output io_hit_data_0_valid, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
output [5:0] io_hit_data_0_bits, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
output io_hit_data_1_valid, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
output [5:0] io_hit_data_1_bits // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
);
wire [11:0] _data_mem_ext_R0_data; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
wire [11:0] _data_mem_ext_R1_data; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
wire _idx_tag_cam_io_r_resp_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_8; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_9; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_10; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_11; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_12; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_13; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_14; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_15; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
reg valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_1_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_2_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_3_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_4_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_5_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_6_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_7_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_7_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_8_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_8_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_9_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_9_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_10_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_10_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_11_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_11_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_12_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_12_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_13_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_13_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_14_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_14_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_15_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg valids_15_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
reg ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_8; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_9; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_10; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_11; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_12; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_13; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_14; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_15; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
wire hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 & ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 & ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 & ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 & ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 & ever_written_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_8 = _idx_tag_cam_io_r_resp_0_8 & ever_written_8; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_9 = _idx_tag_cam_io_r_resp_0_9 & ever_written_9; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_10 = _idx_tag_cam_io_r_resp_0_10 & ever_written_10; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_11 = _idx_tag_cam_io_r_resp_0_11 & ever_written_11; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_12 = _idx_tag_cam_io_r_resp_0_12 & ever_written_12; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_13 = _idx_tag_cam_io_r_resp_0_13 & ever_written_13; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_14 = _idx_tag_cam_io_r_resp_0_14 & ever_written_14; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_15 = _idx_tag_cam_io_r_resp_0_15 & ever_written_15; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire [6:0] _hit_idx_T_2 =
{hits_oh_15, hits_oh_14, hits_oh_13, hits_oh_12, hits_oh_11, hits_oh_10, hits_oh_9}
| {hits_oh_7, hits_oh_6, hits_oh_5, hits_oh_4, hits_oh_3, hits_oh_2, hits_oh_1}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83
wire [2:0] _hit_idx_T_4 = _hit_idx_T_2[6:4] | _hit_idx_T_2[2:0]; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28
wire [3:0] data_mem_io_hit_data_1_bits_MPORT_addr =
{|{hits_oh_15,
hits_oh_14,
hits_oh_13,
hits_oh_12,
hits_oh_11,
hits_oh_10,
hits_oh_9,
hits_oh_8},
|(_hit_idx_T_2[6:3]),
|(_hit_idx_T_4[2:1]),
_hit_idx_T_4[2] | _hit_idx_T_4[0]}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83
wire hit =
hits_oh_0 | hits_oh_1 | hits_oh_2 | hits_oh_3 | hits_oh_4 | hits_oh_5 | hits_oh_6
| hits_oh_7 | hits_oh_8 | hits_oh_9 | hits_oh_10 | hits_oh_11 | hits_oh_12
| hits_oh_13 | hits_oh_14 | hits_oh_15; // src/main/scala/xiangshan/frontend/WrBypass.scala:61:83, :63:29
reg [14:0] state_reg; // rocket-chip/src/main/scala/util/Replacement.scala:168:72
wire [3:0] enq_idx =
{state_reg[14],
state_reg[14]
? {state_reg[13],
state_reg[13]
? {state_reg[12], state_reg[12] ? state_reg[11] : state_reg[10]}
: {state_reg[9], state_reg[9] ? state_reg[8] : state_reg[7]}}
: {state_reg[6],
state_reg[6]
? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]}
: {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13
wire _GEN = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h0; // src/main/scala/chisel3/util/OneHot.scala:32:{10,14}, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30
wire _GEN_0 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h1; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30
wire _GEN_1 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h2; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30
wire _GEN_2 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h3; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30
wire _GEN_3 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h4; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30
wire _GEN_4 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h5; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30
wire _GEN_5 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h6; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30
wire _GEN_6 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h7; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30
wire _GEN_7 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h8; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30
wire _GEN_8 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h9; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30
wire _GEN_9 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'hA; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30
wire _GEN_10 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'hB; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30
wire _GEN_11 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'hC; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30
wire _GEN_12 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'hD; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30
wire _GEN_13 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'hE; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30
wire [3:0] state_reg_touch_way_sized =
hit ? data_mem_io_hit_data_1_bits_MPORT_addr : enq_idx; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37
wire _GEN_14 = enq_idx == 4'h0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:14, src/main/scala/xiangshan/frontend/WrBypass.scala:98:31
wire _GEN_15 = enq_idx == 4'h1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_16 = enq_idx == 4'h2; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_17 = enq_idx == 4'h3; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_18 = enq_idx == 4'h4; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_19 = enq_idx == 4'h5; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_20 = enq_idx == 4'h6; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_21 = enq_idx == 4'h7; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_22 = enq_idx == 4'h8; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_23 = enq_idx == 4'h9; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_24 = enq_idx == 4'hA; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_25 = enq_idx == 4'hB; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_26 = enq_idx == 4'hC; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_27 = enq_idx == 4'hD; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
wire _GEN_28 = enq_idx == 4'hE; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
always @(posedge clock or posedge reset) begin
if (reset) begin
valids_0_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_0_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_1_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_1_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_2_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_2_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_3_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_3_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_4_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_4_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_5_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_5_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_6_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_6_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_7_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_7_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_8_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_8_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_9_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_9_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_10_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_10_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_11_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_11_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_12_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_12_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_13_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_13_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_14_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_14_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_15_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_15_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
ever_written_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_2 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_3 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_4 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_5 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_6 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_7 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_8 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_9 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_10 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_11 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_12 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_13 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_14 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_15 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
state_reg <= 15'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72
end
else begin
if (io_wen) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
if (hit) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29
valids_0_0 <= io_write_way_mask_0 & _GEN | valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_0_1 <= io_write_way_mask_1 & _GEN | valids_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_1_0 <= io_write_way_mask_0 & _GEN_0 | valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_1_1 <= io_write_way_mask_1 & _GEN_0 | valids_1_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_2_0 <= io_write_way_mask_0 & _GEN_1 | valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_2_1 <= io_write_way_mask_1 & _GEN_1 | valids_2_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_3_0 <= io_write_way_mask_0 & _GEN_2 | valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_3_1 <= io_write_way_mask_1 & _GEN_2 | valids_3_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_4_0 <= io_write_way_mask_0 & _GEN_3 | valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_4_1 <= io_write_way_mask_1 & _GEN_3 | valids_4_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_5_0 <= io_write_way_mask_0 & _GEN_4 | valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_5_1 <= io_write_way_mask_1 & _GEN_4 | valids_5_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_6_0 <= io_write_way_mask_0 & _GEN_5 | valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_6_1 <= io_write_way_mask_1 & _GEN_5 | valids_6_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_7_0 <= io_write_way_mask_0 & _GEN_6 | valids_7_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_7_1 <= io_write_way_mask_1 & _GEN_6 | valids_7_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_8_0 <= io_write_way_mask_0 & _GEN_7 | valids_8_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_8_1 <= io_write_way_mask_1 & _GEN_7 | valids_8_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_9_0 <= io_write_way_mask_0 & _GEN_8 | valids_9_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_9_1 <= io_write_way_mask_1 & _GEN_8 | valids_9_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_10_0 <= io_write_way_mask_0 & _GEN_9 | valids_10_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_10_1 <= io_write_way_mask_1 & _GEN_9 | valids_10_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_11_0 <= io_write_way_mask_0 & _GEN_10 | valids_11_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_11_1 <= io_write_way_mask_1 & _GEN_10 | valids_11_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_12_0 <= io_write_way_mask_0 & _GEN_11 | valids_12_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_12_1 <= io_write_way_mask_1 & _GEN_11 | valids_12_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_13_0 <= io_write_way_mask_0 & _GEN_12 | valids_13_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_13_1 <= io_write_way_mask_1 & _GEN_12 | valids_13_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_14_0 <= io_write_way_mask_0 & _GEN_13 | valids_14_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_14_1 <= io_write_way_mask_1 & _GEN_13 | valids_14_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_15_0 <=
io_write_way_mask_0 & (&data_mem_io_hit_data_1_bits_MPORT_addr) | valids_15_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
valids_15_1 <=
io_write_way_mask_1 & (&data_mem_io_hit_data_1_bits_MPORT_addr) | valids_15_1; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30
end
else begin // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29
valids_0_0 <= io_write_way_mask_0 & _GEN_14 | ~_GEN_14 & valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_0_1 <= io_write_way_mask_1 & _GEN_14 | ~_GEN_14 & valids_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_1_0 <= io_write_way_mask_0 & _GEN_15 | ~_GEN_15 & valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_1_1 <= io_write_way_mask_1 & _GEN_15 | ~_GEN_15 & valids_1_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_2_0 <= io_write_way_mask_0 & _GEN_16 | ~_GEN_16 & valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_2_1 <= io_write_way_mask_1 & _GEN_16 | ~_GEN_16 & valids_2_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_3_0 <= io_write_way_mask_0 & _GEN_17 | ~_GEN_17 & valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_3_1 <= io_write_way_mask_1 & _GEN_17 | ~_GEN_17 & valids_3_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_4_0 <= io_write_way_mask_0 & _GEN_18 | ~_GEN_18 & valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_4_1 <= io_write_way_mask_1 & _GEN_18 | ~_GEN_18 & valids_4_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_5_0 <= io_write_way_mask_0 & _GEN_19 | ~_GEN_19 & valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_5_1 <= io_write_way_mask_1 & _GEN_19 | ~_GEN_19 & valids_5_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_6_0 <= io_write_way_mask_0 & _GEN_20 | ~_GEN_20 & valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_6_1 <= io_write_way_mask_1 & _GEN_20 | ~_GEN_20 & valids_6_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_7_0 <= io_write_way_mask_0 & _GEN_21 | ~_GEN_21 & valids_7_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_7_1 <= io_write_way_mask_1 & _GEN_21 | ~_GEN_21 & valids_7_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_8_0 <= io_write_way_mask_0 & _GEN_22 | ~_GEN_22 & valids_8_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_8_1 <= io_write_way_mask_1 & _GEN_22 | ~_GEN_22 & valids_8_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_9_0 <= io_write_way_mask_0 & _GEN_23 | ~_GEN_23 & valids_9_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_9_1 <= io_write_way_mask_1 & _GEN_23 | ~_GEN_23 & valids_9_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_10_0 <= io_write_way_mask_0 & _GEN_24 | ~_GEN_24 & valids_10_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_10_1 <= io_write_way_mask_1 & _GEN_24 | ~_GEN_24 & valids_10_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_11_0 <= io_write_way_mask_0 & _GEN_25 | ~_GEN_25 & valids_11_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_11_1 <= io_write_way_mask_1 & _GEN_25 | ~_GEN_25 & valids_11_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_12_0 <= io_write_way_mask_0 & _GEN_26 | ~_GEN_26 & valids_12_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_12_1 <= io_write_way_mask_1 & _GEN_26 | ~_GEN_26 & valids_12_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_13_0 <= io_write_way_mask_0 & _GEN_27 | ~_GEN_27 & valids_13_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_13_1 <= io_write_way_mask_1 & _GEN_27 | ~_GEN_27 & valids_13_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_14_0 <= io_write_way_mask_0 & _GEN_28 | ~_GEN_28 & valids_14_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_14_1 <= io_write_way_mask_1 & _GEN_28 | ~_GEN_28 & valids_14_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_15_0 <= io_write_way_mask_0 & (&enq_idx) | ~(&enq_idx) & valids_15_0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
valids_15_1 <= io_write_way_mask_1 & (&enq_idx) | ~(&enq_idx) & valids_15_1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30
end
state_reg <=
{~(state_reg_touch_way_sized[3]),
state_reg_touch_way_sized[3]
? {~(state_reg_touch_way_sized[2]),
state_reg_touch_way_sized[2]
? {~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1]
? ~(state_reg_touch_way_sized[0])
: state_reg[11],
state_reg_touch_way_sized[1]
? state_reg[10]
: ~(state_reg_touch_way_sized[0])}
: state_reg[12:10],
state_reg_touch_way_sized[2]
? state_reg[9:7]
: {~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1]
? ~(state_reg_touch_way_sized[0])
: state_reg[8],
state_reg_touch_way_sized[1]
? state_reg[7]
: ~(state_reg_touch_way_sized[0])}}
: state_reg[13:7],
state_reg_touch_way_sized[3]
? state_reg[6:0]
: {~(state_reg_touch_way_sized[2]),
state_reg_touch_way_sized[2]
? {~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1]
? ~(state_reg_touch_way_sized[0])
: state_reg[4],
state_reg_touch_way_sized[1]
? state_reg[3]
: ~(state_reg_touch_way_sized[0])}
: state_reg[5:3],
state_reg_touch_way_sized[2]
? state_reg[2:0]
: {~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1]
? ~(state_reg_touch_way_sized[0])
: state_reg[1],
state_reg_touch_way_sized[1]
? state_reg[0]
: ~(state_reg_touch_way_sized[0])}}}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37
end
ever_written_0 <= io_wen & ~hit & (_GEN_14 | io_wen & _GEN_14) | ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_1 <= io_wen & ~hit & (_GEN_15 | io_wen & _GEN_15) | ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_2 <= io_wen & ~hit & (_GEN_16 | io_wen & _GEN_16) | ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_3 <= io_wen & ~hit & (_GEN_17 | io_wen & _GEN_17) | ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_4 <= io_wen & ~hit & (_GEN_18 | io_wen & _GEN_18) | ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_5 <= io_wen & ~hit & (_GEN_19 | io_wen & _GEN_19) | ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_6 <= io_wen & ~hit & (_GEN_20 | io_wen & _GEN_20) | ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_7 <= io_wen & ~hit & (_GEN_21 | io_wen & _GEN_21) | ever_written_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_8 <= io_wen & ~hit & (_GEN_22 | io_wen & _GEN_22) | ever_written_8; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_9 <= io_wen & ~hit & (_GEN_23 | io_wen & _GEN_23) | ever_written_9; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_10 <= io_wen & ~hit & (_GEN_24 | io_wen & _GEN_24) | ever_written_10; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_11 <= io_wen & ~hit & (_GEN_25 | io_wen & _GEN_25) | ever_written_11; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_12 <= io_wen & ~hit & (_GEN_26 | io_wen & _GEN_26) | ever_written_12; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_13 <= io_wen & ~hit & (_GEN_27 | io_wen & _GEN_27) | ever_written_13; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_14 <= io_wen & ~hit & (_GEN_28 | io_wen & _GEN_28) | ever_written_14; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_15 <=
io_wen & ~hit & ((&enq_idx) | io_wen & (&enq_idx)) | ever_written_15; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:1]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
_RANDOM[i[0]] = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
end // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
valids_0_0 = _RANDOM[1'h0][0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_0_1 = _RANDOM[1'h0][1]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_1_0 = _RANDOM[1'h0][2]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_1_1 = _RANDOM[1'h0][3]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_2_0 = _RANDOM[1'h0][4]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_2_1 = _RANDOM[1'h0][5]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_3_0 = _RANDOM[1'h0][6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_3_1 = _RANDOM[1'h0][7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_4_0 = _RANDOM[1'h0][8]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_4_1 = _RANDOM[1'h0][9]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_5_0 = _RANDOM[1'h0][10]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_5_1 = _RANDOM[1'h0][11]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_6_0 = _RANDOM[1'h0][12]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_6_1 = _RANDOM[1'h0][13]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_7_0 = _RANDOM[1'h0][14]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_7_1 = _RANDOM[1'h0][15]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_8_0 = _RANDOM[1'h0][16]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_8_1 = _RANDOM[1'h0][17]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_9_0 = _RANDOM[1'h0][18]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_9_1 = _RANDOM[1'h0][19]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_10_0 = _RANDOM[1'h0][20]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_10_1 = _RANDOM[1'h0][21]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_11_0 = _RANDOM[1'h0][22]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_11_1 = _RANDOM[1'h0][23]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_12_0 = _RANDOM[1'h0][24]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_12_1 = _RANDOM[1'h0][25]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_13_0 = _RANDOM[1'h0][26]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_13_1 = _RANDOM[1'h0][27]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_14_0 = _RANDOM[1'h0][28]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_14_1 = _RANDOM[1'h0][29]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_15_0 = _RANDOM[1'h0][30]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_15_1 = _RANDOM[1'h0][31]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
ever_written_0 = _RANDOM[1'h1][0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_1 = _RANDOM[1'h1][1]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_2 = _RANDOM[1'h1][2]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_3 = _RANDOM[1'h1][3]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_4 = _RANDOM[1'h1][4]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_5 = _RANDOM[1'h1][5]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_6 = _RANDOM[1'h1][6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_7 = _RANDOM[1'h1][7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_8 = _RANDOM[1'h1][8]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_9 = _RANDOM[1'h1][9]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_10 = _RANDOM[1'h1][10]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_11 = _RANDOM[1'h1][11]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_12 = _RANDOM[1'h1][12]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_13 = _RANDOM[1'h1][13]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_14 = _RANDOM[1'h1][14]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_15 = _RANDOM[1'h1][15]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
state_reg = _RANDOM[1'h1][30:16]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
`endif // RANDOMIZE_REG_INIT
if (reset) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
valids_0_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_0_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_1_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_1_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_2_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_2_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_3_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_3_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_4_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_4_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_5_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_5_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_6_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_6_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_7_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_7_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_8_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_8_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_9_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_9_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_10_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_10_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_11_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_11_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_12_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_12_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_13_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_13_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_14_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_14_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_15_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
valids_15_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
ever_written_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_2 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_3 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_4 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_5 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_6 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_7 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_8 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_9 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_10 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_11 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_12 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_13 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_14 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_15 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
state_reg = 15'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
CAMTemplate_33 idx_tag_cam ( // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
.clock (clock),
.io_r_req_0_idx (io_write_idx),
.io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0),
.io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1),
.io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2),
.io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3),
.io_r_resp_0_4 (_idx_tag_cam_io_r_resp_0_4),
.io_r_resp_0_5 (_idx_tag_cam_io_r_resp_0_5),
.io_r_resp_0_6 (_idx_tag_cam_io_r_resp_0_6),
.io_r_resp_0_7 (_idx_tag_cam_io_r_resp_0_7),
.io_r_resp_0_8 (_idx_tag_cam_io_r_resp_0_8),
.io_r_resp_0_9 (_idx_tag_cam_io_r_resp_0_9),
.io_r_resp_0_10 (_idx_tag_cam_io_r_resp_0_10),
.io_r_resp_0_11 (_idx_tag_cam_io_r_resp_0_11),
.io_r_resp_0_12 (_idx_tag_cam_io_r_resp_0_12),
.io_r_resp_0_13 (_idx_tag_cam_io_r_resp_0_13),
.io_r_resp_0_14 (_idx_tag_cam_io_r_resp_0_14),
.io_r_resp_0_15 (_idx_tag_cam_io_r_resp_0_15),
.io_w_valid (io_wen & ~hit), // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26}
.io_w_bits_data_idx (io_write_idx),
.io_w_bits_index (enq_idx) // rocket-chip/src/main/scala/util/Replacement.scala:249:12
);
data_mem_16x12 data_mem_ext ( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
.R0_addr (data_mem_io_hit_data_1_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10
.R0_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
.R0_clk (clock),
.R0_data (_data_mem_ext_R0_data),
.R1_addr (data_mem_io_hit_data_1_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10
.R1_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
.R1_clk (clock),
.R1_data (_data_mem_ext_R1_data),
.W0_addr (hit ? data_mem_io_hit_data_1_bits_MPORT_addr : enq_idx), // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29
.W0_en (io_wen),
.W0_clk (clock),
.W0_data ({io_write_data_1, io_write_data_0}), // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
.W0_mask ({io_write_way_mask_1, io_write_way_mask_0}) // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
);
assign io_hit = hit; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29
assign io_hit_data_0_valid =
hits_oh_0 & valids_0_0 | hits_oh_1 & valids_1_0 | hits_oh_2 & valids_2_0 | hits_oh_3
& valids_3_0 | hits_oh_4 & valids_4_0 | hits_oh_5 & valids_5_0 | hits_oh_6
& valids_6_0 | hits_oh_7 & valids_7_0 | hits_oh_8 & valids_8_0 | hits_oh_9
& valids_9_0 | hits_oh_10 & valids_10_0 | hits_oh_11 & valids_11_0 | hits_oh_12
& valids_12_0 | hits_oh_13 & valids_13_0 | hits_oh_14 & valids_14_0 | hits_oh_15
& valids_15_0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :61:83
assign io_hit_data_0_bits = _data_mem_ext_R1_data[5:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :54:21
assign io_hit_data_1_valid =
hits_oh_0 & valids_0_1 | hits_oh_1 & valids_1_1 | hits_oh_2 & valids_2_1 | hits_oh_3
& valids_3_1 | hits_oh_4 & valids_4_1 | hits_oh_5 & valids_5_1 | hits_oh_6
& valids_6_1 | hits_oh_7 & valids_7_1 | hits_oh_8 & valids_8_1 | hits_oh_9
& valids_9_1 | hits_oh_10 & valids_10_1 | hits_oh_11 & valids_11_1 | hits_oh_12
& valids_12_1 | hits_oh_13 & valids_13_1 | hits_oh_14 & valids_14_1 | hits_oh_15
& valids_15_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :61:83
assign io_hit_data_1_bits = _data_mem_ext_R0_data[11:6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :54:21
endmodule

159
src/WrBypass/WrBypass_41.sv Normal file
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@ -0,0 +1,159 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module WrBypass_41( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
input clock,
input reset,
input io_wen, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
input [7:0] io_write_idx, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
input [1:0] io_write_data_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
output io_hit, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
output [1:0] io_hit_data_0_bits // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
);
wire _idx_tag_cam_io_r_resp_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
reg ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire [1:0] data_mem_io_hit_data_0_bits_MPORT_addr =
{|{hits_oh_3, hits_oh_2}, hits_oh_3 | hits_oh_1}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83
wire hit =
_idx_tag_cam_io_r_resp_0_0 & ever_written_0 | hits_oh_1 | hits_oh_2 | hits_oh_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83, :63:29
reg [2:0] state_reg; // rocket-chip/src/main/scala/util/Replacement.scala:168:72
wire [1:0] enq_idx = {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13
wire [1:0] state_reg_touch_way_sized =
hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37
always @(posedge clock or posedge reset) begin
if (reset) begin
ever_written_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_2 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_3 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
state_reg <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72
end
else begin
ever_written_0 <= io_wen & ~hit & enq_idx == 2'h0 | ever_written_0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:14, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_1 <= io_wen & ~hit & enq_idx == 2'h1 | ever_written_1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31
ever_written_2 <= io_wen & ~hit & enq_idx == 2'h2 | ever_written_2; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31
ever_written_3 <= io_wen & ~hit & (&enq_idx) | ever_written_3; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
if (io_wen) // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
state_reg <=
{~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[1],
state_reg_touch_way_sized[1] ? state_reg[0] : ~(state_reg_touch_way_sized[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][4]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][5]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
state_reg = _RANDOM[/*Zero width*/ 1'b0][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
`endif // RANDOMIZE_REG_INIT
if (reset) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
ever_written_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_2 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_3 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
state_reg = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
CAMTemplate_41 idx_tag_cam ( // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
.clock (clock),
.io_r_req_0_idx (io_write_idx),
.io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0),
.io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1),
.io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2),
.io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3),
.io_w_valid (io_wen & ~hit), // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26}
.io_w_bits_data_idx (io_write_idx),
.io_w_bits_index (enq_idx) // rocket-chip/src/main/scala/util/Replacement.scala:249:12
);
data_mem_0_4x2 data_mem_0_ext ( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
.R0_addr (data_mem_io_hit_data_0_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10
.R0_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
.R0_clk (clock),
.R0_data (io_hit_data_0_bits),
.W0_addr (hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx), // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29
.W0_en (io_wen),
.W0_clk (clock),
.W0_data (io_write_data_0)
);
assign io_hit = hit; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29
endmodule

159
src/WrBypass/WrBypass_43.sv Normal file
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@ -0,0 +1,159 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module WrBypass_43( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
input clock,
input reset,
input io_wen, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
input [8:0] io_write_idx, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
input [1:0] io_write_data_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
output io_hit, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
output [1:0] io_hit_data_0_bits // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
);
wire _idx_tag_cam_io_r_resp_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
reg ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire [1:0] data_mem_io_hit_data_0_bits_MPORT_addr =
{|{hits_oh_3, hits_oh_2}, hits_oh_3 | hits_oh_1}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83
wire hit =
_idx_tag_cam_io_r_resp_0_0 & ever_written_0 | hits_oh_1 | hits_oh_2 | hits_oh_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83, :63:29
reg [2:0] state_reg; // rocket-chip/src/main/scala/util/Replacement.scala:168:72
wire [1:0] enq_idx = {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13
wire [1:0] state_reg_touch_way_sized =
hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37
always @(posedge clock or posedge reset) begin
if (reset) begin
ever_written_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_2 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_3 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
state_reg <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72
end
else begin
ever_written_0 <= io_wen & ~hit & enq_idx == 2'h0 | ever_written_0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:14, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_1 <= io_wen & ~hit & enq_idx == 2'h1 | ever_written_1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31
ever_written_2 <= io_wen & ~hit & enq_idx == 2'h2 | ever_written_2; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31
ever_written_3 <= io_wen & ~hit & (&enq_idx) | ever_written_3; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
if (io_wen) // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
state_reg <=
{~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[1],
state_reg_touch_way_sized[1] ? state_reg[0] : ~(state_reg_touch_way_sized[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][4]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][5]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
state_reg = _RANDOM[/*Zero width*/ 1'b0][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
`endif // RANDOMIZE_REG_INIT
if (reset) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
ever_written_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_2 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_3 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
state_reg = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
CAMTemplate_43 idx_tag_cam ( // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
.clock (clock),
.io_r_req_0_idx (io_write_idx),
.io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0),
.io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1),
.io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2),
.io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3),
.io_w_valid (io_wen & ~hit), // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26}
.io_w_bits_data_idx (io_write_idx),
.io_w_bits_index (enq_idx) // rocket-chip/src/main/scala/util/Replacement.scala:249:12
);
data_mem_0_4x2 data_mem_0_ext ( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
.R0_addr (data_mem_io_hit_data_0_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10
.R0_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
.R0_clk (clock),
.R0_data (io_hit_data_0_bits),
.W0_addr (hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx), // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29
.W0_en (io_wen),
.W0_clk (clock),
.W0_data (io_write_data_0)
);
assign io_hit = hit; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29
endmodule

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// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module DelayN_2( // utility/src/main/scala/utility/Hold.scala:83:7
input clock,
input [35:0] io_in, // utility/src/main/scala/utility/Hold.scala:84:14
output [35:0] io_out // utility/src/main/scala/utility/Hold.scala:84:14
);
reg [35:0] REG; // utility/src/main/scala/utility/Hold.scala:90:18
reg [35:0] REG_1; // utility/src/main/scala/utility/Hold.scala:90:18
reg [35:0] REG_2; // utility/src/main/scala/utility/Hold.scala:90:18
reg [35:0] REG_3; // utility/src/main/scala/utility/Hold.scala:90:18
reg [35:0] REG_4; // utility/src/main/scala/utility/Hold.scala:90:18
always @(posedge clock) begin
REG <= io_in; // utility/src/main/scala/utility/Hold.scala:90:18
REG_1 <= REG; // utility/src/main/scala/utility/Hold.scala:90:18
REG_2 <= REG_1; // utility/src/main/scala/utility/Hold.scala:90:18
REG_3 <= REG_2; // utility/src/main/scala/utility/Hold.scala:90:18
REG_4 <= REG_3; // utility/src/main/scala/utility/Hold.scala:90:18
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/Hold.scala:83:7
`ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7
`FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:5]; // utility/src/main/scala/utility/Hold.scala:83:7
initial begin // utility/src/main/scala/utility/Hold.scala:83:7
`ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/Hold.scala:83:7
`INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/Hold.scala:83:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/Hold.scala:83:7
for (logic [2:0] i = 3'h0; i < 3'h6; i += 3'h1) begin
_RANDOM[i] = `RANDOM; // utility/src/main/scala/utility/Hold.scala:83:7
end // utility/src/main/scala/utility/Hold.scala:83:7
REG = {_RANDOM[3'h0], _RANDOM[3'h1][3:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_1 = {_RANDOM[3'h1][31:4], _RANDOM[3'h2][7:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_2 = {_RANDOM[3'h2][31:8], _RANDOM[3'h3][11:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_3 = {_RANDOM[3'h3][31:12], _RANDOM[3'h4][15:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_4 = {_RANDOM[3'h4][31:16], _RANDOM[3'h5][19:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7
`FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_out = REG_4; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
endmodule

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// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module DelayN_4( // utility/src/main/scala/utility/Hold.scala:83:7
input clock,
input [38:0] io_in, // utility/src/main/scala/utility/Hold.scala:84:14
output [38:0] io_out // utility/src/main/scala/utility/Hold.scala:84:14
);
reg [38:0] REG; // utility/src/main/scala/utility/Hold.scala:90:18
reg [38:0] REG_1; // utility/src/main/scala/utility/Hold.scala:90:18
always @(posedge clock) begin
REG <= io_in; // utility/src/main/scala/utility/Hold.scala:90:18
REG_1 <= REG; // utility/src/main/scala/utility/Hold.scala:90:18
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/Hold.scala:83:7
`ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7
`FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:2]; // utility/src/main/scala/utility/Hold.scala:83:7
initial begin // utility/src/main/scala/utility/Hold.scala:83:7
`ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/Hold.scala:83:7
`INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/Hold.scala:83:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/Hold.scala:83:7
for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin
_RANDOM[i] = `RANDOM; // utility/src/main/scala/utility/Hold.scala:83:7
end // utility/src/main/scala/utility/Hold.scala:83:7
REG = {_RANDOM[2'h0], _RANDOM[2'h1][6:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_1 = {_RANDOM[2'h1][31:7], _RANDOM[2'h2][13:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7
`FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_out = REG_1; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
endmodule

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// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module DelayN_5( // utility/src/main/scala/utility/Hold.scala:83:7
input clock,
input io_in_valid, // utility/src/main/scala/utility/Hold.scala:84:14
input [3:0] io_in_brSlots_0_offset, // utility/src/main/scala/utility/Hold.scala:84:14
input [11:0] io_in_brSlots_0_lower, // utility/src/main/scala/utility/Hold.scala:84:14
input [1:0] io_in_brSlots_0_tarStat, // utility/src/main/scala/utility/Hold.scala:84:14
input io_in_brSlots_0_sharing, // utility/src/main/scala/utility/Hold.scala:84:14
input io_in_brSlots_0_valid, // utility/src/main/scala/utility/Hold.scala:84:14
input [3:0] io_in_tailSlot_offset, // utility/src/main/scala/utility/Hold.scala:84:14
input [19:0] io_in_tailSlot_lower, // utility/src/main/scala/utility/Hold.scala:84:14
input [1:0] io_in_tailSlot_tarStat, // utility/src/main/scala/utility/Hold.scala:84:14
input io_in_tailSlot_sharing, // utility/src/main/scala/utility/Hold.scala:84:14
input io_in_tailSlot_valid, // utility/src/main/scala/utility/Hold.scala:84:14
input [3:0] io_in_pftAddr, // utility/src/main/scala/utility/Hold.scala:84:14
input io_in_carry, // utility/src/main/scala/utility/Hold.scala:84:14
input io_in_isCall, // utility/src/main/scala/utility/Hold.scala:84:14
input io_in_isRet, // utility/src/main/scala/utility/Hold.scala:84:14
input io_in_isJalr, // utility/src/main/scala/utility/Hold.scala:84:14
input io_in_last_may_be_rvi_call, // utility/src/main/scala/utility/Hold.scala:84:14
input io_in_always_taken_0, // utility/src/main/scala/utility/Hold.scala:84:14
input io_in_always_taken_1, // utility/src/main/scala/utility/Hold.scala:84:14
output io_out_valid, // utility/src/main/scala/utility/Hold.scala:84:14
output [3:0] io_out_brSlots_0_offset, // utility/src/main/scala/utility/Hold.scala:84:14
output [11:0] io_out_brSlots_0_lower, // utility/src/main/scala/utility/Hold.scala:84:14
output [1:0] io_out_brSlots_0_tarStat, // utility/src/main/scala/utility/Hold.scala:84:14
output io_out_brSlots_0_sharing, // utility/src/main/scala/utility/Hold.scala:84:14
output io_out_brSlots_0_valid, // utility/src/main/scala/utility/Hold.scala:84:14
output [3:0] io_out_tailSlot_offset, // utility/src/main/scala/utility/Hold.scala:84:14
output [19:0] io_out_tailSlot_lower, // utility/src/main/scala/utility/Hold.scala:84:14
output [1:0] io_out_tailSlot_tarStat, // utility/src/main/scala/utility/Hold.scala:84:14
output io_out_tailSlot_sharing, // utility/src/main/scala/utility/Hold.scala:84:14
output io_out_tailSlot_valid, // utility/src/main/scala/utility/Hold.scala:84:14
output [3:0] io_out_pftAddr, // utility/src/main/scala/utility/Hold.scala:84:14
output io_out_carry, // utility/src/main/scala/utility/Hold.scala:84:14
output io_out_isCall, // utility/src/main/scala/utility/Hold.scala:84:14
output io_out_isRet, // utility/src/main/scala/utility/Hold.scala:84:14
output io_out_isJalr, // utility/src/main/scala/utility/Hold.scala:84:14
output io_out_last_may_be_rvi_call, // utility/src/main/scala/utility/Hold.scala:84:14
output io_out_always_taken_0, // utility/src/main/scala/utility/Hold.scala:84:14
output io_out_always_taken_1 // utility/src/main/scala/utility/Hold.scala:84:14
);
reg REG_valid; // utility/src/main/scala/utility/Hold.scala:90:18
reg [3:0] REG_brSlots_0_offset; // utility/src/main/scala/utility/Hold.scala:90:18
reg [11:0] REG_brSlots_0_lower; // utility/src/main/scala/utility/Hold.scala:90:18
reg [1:0] REG_brSlots_0_tarStat; // utility/src/main/scala/utility/Hold.scala:90:18
reg REG_brSlots_0_sharing; // utility/src/main/scala/utility/Hold.scala:90:18
reg REG_brSlots_0_valid; // utility/src/main/scala/utility/Hold.scala:90:18
reg [3:0] REG_tailSlot_offset; // utility/src/main/scala/utility/Hold.scala:90:18
reg [19:0] REG_tailSlot_lower; // utility/src/main/scala/utility/Hold.scala:90:18
reg [1:0] REG_tailSlot_tarStat; // utility/src/main/scala/utility/Hold.scala:90:18
reg REG_tailSlot_sharing; // utility/src/main/scala/utility/Hold.scala:90:18
reg REG_tailSlot_valid; // utility/src/main/scala/utility/Hold.scala:90:18
reg [3:0] REG_pftAddr; // utility/src/main/scala/utility/Hold.scala:90:18
reg REG_carry; // utility/src/main/scala/utility/Hold.scala:90:18
reg REG_isCall; // utility/src/main/scala/utility/Hold.scala:90:18
reg REG_isRet; // utility/src/main/scala/utility/Hold.scala:90:18
reg REG_isJalr; // utility/src/main/scala/utility/Hold.scala:90:18
reg REG_last_may_be_rvi_call; // utility/src/main/scala/utility/Hold.scala:90:18
reg REG_always_taken_0; // utility/src/main/scala/utility/Hold.scala:90:18
reg REG_always_taken_1; // utility/src/main/scala/utility/Hold.scala:90:18
reg REG_1_valid; // utility/src/main/scala/utility/Hold.scala:90:18
reg [3:0] REG_1_brSlots_0_offset; // utility/src/main/scala/utility/Hold.scala:90:18
reg [11:0] REG_1_brSlots_0_lower; // utility/src/main/scala/utility/Hold.scala:90:18
reg [1:0] REG_1_brSlots_0_tarStat; // utility/src/main/scala/utility/Hold.scala:90:18
reg REG_1_brSlots_0_sharing; // utility/src/main/scala/utility/Hold.scala:90:18
reg REG_1_brSlots_0_valid; // utility/src/main/scala/utility/Hold.scala:90:18
reg [3:0] REG_1_tailSlot_offset; // utility/src/main/scala/utility/Hold.scala:90:18
reg [19:0] REG_1_tailSlot_lower; // utility/src/main/scala/utility/Hold.scala:90:18
reg [1:0] REG_1_tailSlot_tarStat; // utility/src/main/scala/utility/Hold.scala:90:18
reg REG_1_tailSlot_sharing; // utility/src/main/scala/utility/Hold.scala:90:18
reg REG_1_tailSlot_valid; // utility/src/main/scala/utility/Hold.scala:90:18
reg [3:0] REG_1_pftAddr; // utility/src/main/scala/utility/Hold.scala:90:18
reg REG_1_carry; // utility/src/main/scala/utility/Hold.scala:90:18
reg REG_1_isCall; // utility/src/main/scala/utility/Hold.scala:90:18
reg REG_1_isRet; // utility/src/main/scala/utility/Hold.scala:90:18
reg REG_1_isJalr; // utility/src/main/scala/utility/Hold.scala:90:18
reg REG_1_last_may_be_rvi_call; // utility/src/main/scala/utility/Hold.scala:90:18
reg REG_1_always_taken_0; // utility/src/main/scala/utility/Hold.scala:90:18
reg REG_1_always_taken_1; // utility/src/main/scala/utility/Hold.scala:90:18
always @(posedge clock) begin
REG_valid <= io_in_valid; // utility/src/main/scala/utility/Hold.scala:90:18
REG_brSlots_0_offset <= io_in_brSlots_0_offset; // utility/src/main/scala/utility/Hold.scala:90:18
REG_brSlots_0_lower <= io_in_brSlots_0_lower; // utility/src/main/scala/utility/Hold.scala:90:18
REG_brSlots_0_tarStat <= io_in_brSlots_0_tarStat; // utility/src/main/scala/utility/Hold.scala:90:18
REG_brSlots_0_sharing <= io_in_brSlots_0_sharing; // utility/src/main/scala/utility/Hold.scala:90:18
REG_brSlots_0_valid <= io_in_brSlots_0_valid; // utility/src/main/scala/utility/Hold.scala:90:18
REG_tailSlot_offset <= io_in_tailSlot_offset; // utility/src/main/scala/utility/Hold.scala:90:18
REG_tailSlot_lower <= io_in_tailSlot_lower; // utility/src/main/scala/utility/Hold.scala:90:18
REG_tailSlot_tarStat <= io_in_tailSlot_tarStat; // utility/src/main/scala/utility/Hold.scala:90:18
REG_tailSlot_sharing <= io_in_tailSlot_sharing; // utility/src/main/scala/utility/Hold.scala:90:18
REG_tailSlot_valid <= io_in_tailSlot_valid; // utility/src/main/scala/utility/Hold.scala:90:18
REG_pftAddr <= io_in_pftAddr; // utility/src/main/scala/utility/Hold.scala:90:18
REG_carry <= io_in_carry; // utility/src/main/scala/utility/Hold.scala:90:18
REG_isCall <= io_in_isCall; // utility/src/main/scala/utility/Hold.scala:90:18
REG_isRet <= io_in_isRet; // utility/src/main/scala/utility/Hold.scala:90:18
REG_isJalr <= io_in_isJalr; // utility/src/main/scala/utility/Hold.scala:90:18
REG_last_may_be_rvi_call <= io_in_last_may_be_rvi_call; // utility/src/main/scala/utility/Hold.scala:90:18
REG_always_taken_0 <= io_in_always_taken_0; // utility/src/main/scala/utility/Hold.scala:90:18
REG_always_taken_1 <= io_in_always_taken_1; // utility/src/main/scala/utility/Hold.scala:90:18
REG_1_valid <= REG_valid; // utility/src/main/scala/utility/Hold.scala:90:18
REG_1_brSlots_0_offset <= REG_brSlots_0_offset; // utility/src/main/scala/utility/Hold.scala:90:18
REG_1_brSlots_0_lower <= REG_brSlots_0_lower; // utility/src/main/scala/utility/Hold.scala:90:18
REG_1_brSlots_0_tarStat <= REG_brSlots_0_tarStat; // utility/src/main/scala/utility/Hold.scala:90:18
REG_1_brSlots_0_sharing <= REG_brSlots_0_sharing; // utility/src/main/scala/utility/Hold.scala:90:18
REG_1_brSlots_0_valid <= REG_brSlots_0_valid; // utility/src/main/scala/utility/Hold.scala:90:18
REG_1_tailSlot_offset <= REG_tailSlot_offset; // utility/src/main/scala/utility/Hold.scala:90:18
REG_1_tailSlot_lower <= REG_tailSlot_lower; // utility/src/main/scala/utility/Hold.scala:90:18
REG_1_tailSlot_tarStat <= REG_tailSlot_tarStat; // utility/src/main/scala/utility/Hold.scala:90:18
REG_1_tailSlot_sharing <= REG_tailSlot_sharing; // utility/src/main/scala/utility/Hold.scala:90:18
REG_1_tailSlot_valid <= REG_tailSlot_valid; // utility/src/main/scala/utility/Hold.scala:90:18
REG_1_pftAddr <= REG_pftAddr; // utility/src/main/scala/utility/Hold.scala:90:18
REG_1_carry <= REG_carry; // utility/src/main/scala/utility/Hold.scala:90:18
REG_1_isCall <= REG_isCall; // utility/src/main/scala/utility/Hold.scala:90:18
REG_1_isRet <= REG_isRet; // utility/src/main/scala/utility/Hold.scala:90:18
REG_1_isJalr <= REG_isJalr; // utility/src/main/scala/utility/Hold.scala:90:18
REG_1_last_may_be_rvi_call <= REG_last_may_be_rvi_call; // utility/src/main/scala/utility/Hold.scala:90:18
REG_1_always_taken_0 <= REG_always_taken_0; // utility/src/main/scala/utility/Hold.scala:90:18
REG_1_always_taken_1 <= REG_always_taken_1; // utility/src/main/scala/utility/Hold.scala:90:18
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/Hold.scala:83:7
`ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7
`FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:3]; // utility/src/main/scala/utility/Hold.scala:83:7
initial begin // utility/src/main/scala/utility/Hold.scala:83:7
`ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/Hold.scala:83:7
`INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/Hold.scala:83:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/Hold.scala:83:7
for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
_RANDOM[i[1:0]] = `RANDOM; // utility/src/main/scala/utility/Hold.scala:83:7
end // utility/src/main/scala/utility/Hold.scala:83:7
REG_valid = _RANDOM[2'h0][0]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_brSlots_0_offset = _RANDOM[2'h0][4:1]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_brSlots_0_lower = _RANDOM[2'h0][16:5]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_brSlots_0_tarStat = _RANDOM[2'h0][18:17]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_brSlots_0_sharing = _RANDOM[2'h0][19]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_brSlots_0_valid = _RANDOM[2'h0][20]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_tailSlot_offset = _RANDOM[2'h0][24:21]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_tailSlot_lower = {_RANDOM[2'h0][31:25], _RANDOM[2'h1][12:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_tailSlot_tarStat = _RANDOM[2'h1][14:13]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_tailSlot_sharing = _RANDOM[2'h1][15]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_tailSlot_valid = _RANDOM[2'h1][16]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_pftAddr = _RANDOM[2'h1][20:17]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_carry = _RANDOM[2'h1][21]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_isCall = _RANDOM[2'h1][22]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_isRet = _RANDOM[2'h1][23]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_isJalr = _RANDOM[2'h1][24]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_last_may_be_rvi_call = _RANDOM[2'h1][25]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_always_taken_0 = _RANDOM[2'h1][26]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_always_taken_1 = _RANDOM[2'h1][27]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_1_valid = _RANDOM[2'h1][28]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_1_brSlots_0_offset = {_RANDOM[2'h1][31:29], _RANDOM[2'h2][0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_1_brSlots_0_lower = _RANDOM[2'h2][12:1]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_1_brSlots_0_tarStat = _RANDOM[2'h2][14:13]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_1_brSlots_0_sharing = _RANDOM[2'h2][15]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_1_brSlots_0_valid = _RANDOM[2'h2][16]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_1_tailSlot_offset = _RANDOM[2'h2][20:17]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_1_tailSlot_lower = {_RANDOM[2'h2][31:21], _RANDOM[2'h3][8:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_1_tailSlot_tarStat = _RANDOM[2'h3][10:9]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_1_tailSlot_sharing = _RANDOM[2'h3][11]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_1_tailSlot_valid = _RANDOM[2'h3][12]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_1_pftAddr = _RANDOM[2'h3][16:13]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_1_carry = _RANDOM[2'h3][17]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_1_isCall = _RANDOM[2'h3][18]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_1_isRet = _RANDOM[2'h3][19]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_1_isJalr = _RANDOM[2'h3][20]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_1_last_may_be_rvi_call = _RANDOM[2'h3][21]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_1_always_taken_0 = _RANDOM[2'h3][22]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_1_always_taken_1 = _RANDOM[2'h3][23]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7
`FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_out_valid = REG_1_valid; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
assign io_out_brSlots_0_offset = REG_1_brSlots_0_offset; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
assign io_out_brSlots_0_lower = REG_1_brSlots_0_lower; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
assign io_out_brSlots_0_tarStat = REG_1_brSlots_0_tarStat; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
assign io_out_brSlots_0_sharing = REG_1_brSlots_0_sharing; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
assign io_out_brSlots_0_valid = REG_1_brSlots_0_valid; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
assign io_out_tailSlot_offset = REG_1_tailSlot_offset; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
assign io_out_tailSlot_lower = REG_1_tailSlot_lower; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
assign io_out_tailSlot_tarStat = REG_1_tailSlot_tarStat; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
assign io_out_tailSlot_sharing = REG_1_tailSlot_sharing; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
assign io_out_tailSlot_valid = REG_1_tailSlot_valid; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
assign io_out_pftAddr = REG_1_pftAddr; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
assign io_out_carry = REG_1_carry; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
assign io_out_isCall = REG_1_isCall; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
assign io_out_isRet = REG_1_isRet; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
assign io_out_isJalr = REG_1_isJalr; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
assign io_out_last_may_be_rvi_call = REG_1_last_may_be_rvi_call; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
assign io_out_always_taken_0 = REG_1_always_taken_0; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
assign io_out_always_taken_1 = REG_1_always_taken_1; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
endmodule

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// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module DelayN_6( // utility/src/main/scala/utility/Hold.scala:83:7
input clock,
input io_in, // utility/src/main/scala/utility/Hold.scala:84:14
output io_out // utility/src/main/scala/utility/Hold.scala:84:14
);
reg REG; // utility/src/main/scala/utility/Hold.scala:90:18
reg REG_1; // utility/src/main/scala/utility/Hold.scala:90:18
always @(posedge clock) begin
REG <= io_in; // utility/src/main/scala/utility/Hold.scala:90:18
REG_1 <= REG; // utility/src/main/scala/utility/Hold.scala:90:18
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/Hold.scala:83:7
`ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7
`FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0]; // utility/src/main/scala/utility/Hold.scala:83:7
initial begin // utility/src/main/scala/utility/Hold.scala:83:7
`ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/Hold.scala:83:7
`INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/Hold.scala:83:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/Hold.scala:83:7
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // utility/src/main/scala/utility/Hold.scala:83:7
REG = _RANDOM[/*Zero width*/ 1'b0][0]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
REG_1 = _RANDOM[/*Zero width*/ 1'b0][1]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7
`FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_out = REG_1; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
endmodule

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./src/uFTB/FauFTBWay.sv
./src/common/ext_sram.v
./src/common/DelayN_2.sv

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// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module FauFTBWay( // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7
input clock,
input reset,
input [15:0] io_req_tag, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
output [3:0] io_resp_brSlots_0_offset, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
output [11:0] io_resp_brSlots_0_lower, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
output [1:0] io_resp_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
output io_resp_brSlots_0_valid, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
output [3:0] io_resp_tailSlot_offset, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
output [19:0] io_resp_tailSlot_lower, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
output [1:0] io_resp_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
output io_resp_tailSlot_sharing, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
output io_resp_tailSlot_valid, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
output [3:0] io_resp_pftAddr, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
output io_resp_carry, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
output io_resp_always_taken_0, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
output io_resp_always_taken_1, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
output io_resp_hit, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
input [15:0] io_update_req_tag, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
output io_update_hit, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
input io_write_valid, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
input [3:0] io_write_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
input [11:0] io_write_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
input [1:0] io_write_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
input io_write_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
input [3:0] io_write_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
input [19:0] io_write_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
input [1:0] io_write_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
input io_write_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
input io_write_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
input [3:0] io_write_entry_pftAddr, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
input io_write_entry_carry, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
input io_write_entry_always_taken_0, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
input io_write_entry_always_taken_1, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
input [15:0] io_write_tag // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
);
reg [3:0] data_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
reg [11:0] data_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
reg [1:0] data_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
reg data_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
reg [3:0] data_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
reg [19:0] data_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
reg [1:0] data_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
reg data_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
reg data_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
reg [3:0] data_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
reg data_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
reg data_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
reg data_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
reg [15:0] tag; // src/main/scala/xiangshan/frontend/FauFTB.scala:58:16
reg valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:59:22
always @(posedge clock) begin
if (io_write_valid) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14
data_brSlots_0_offset <= io_write_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
data_brSlots_0_lower <= io_write_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
data_brSlots_0_tarStat <= io_write_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
data_brSlots_0_valid <= io_write_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
data_tailSlot_offset <= io_write_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
data_tailSlot_lower <= io_write_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
data_tailSlot_tarStat <= io_write_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
data_tailSlot_sharing <= io_write_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
data_tailSlot_valid <= io_write_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
data_pftAddr <= io_write_entry_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
data_carry <= io_write_entry_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
data_always_taken_0 <= io_write_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
data_always_taken_1 <= io_write_entry_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17
tag <= io_write_tag; // src/main/scala/xiangshan/frontend/FauFTB.scala:58:16
end
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset)
valid <= 1'h0; // src/main/scala/xiangshan/frontend/FauFTB.scala:59:22
else
valid <= io_write_valid & ~valid | valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:59:22, :68:25, :69:{11,19}, :70:13
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:2]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7
initial begin // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7
for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin
_RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7
end // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7
data_brSlots_0_offset = _RANDOM[2'h0][4:1]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
data_brSlots_0_lower = _RANDOM[2'h0][16:5]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
data_brSlots_0_tarStat = _RANDOM[2'h0][18:17]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
data_brSlots_0_valid = _RANDOM[2'h0][20]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
data_tailSlot_offset = _RANDOM[2'h0][24:21]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
data_tailSlot_lower = {_RANDOM[2'h0][31:25], _RANDOM[2'h1][12:0]}; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
data_tailSlot_tarStat = _RANDOM[2'h1][14:13]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
data_tailSlot_sharing = _RANDOM[2'h1][15]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
data_tailSlot_valid = _RANDOM[2'h1][16]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
data_pftAddr = _RANDOM[2'h1][20:17]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
data_carry = _RANDOM[2'h1][21]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
data_always_taken_0 = _RANDOM[2'h1][26]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
data_always_taken_1 = _RANDOM[2'h1][27]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
tag = {_RANDOM[2'h1][31:28], _RANDOM[2'h2][11:0]}; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17, :58:16
valid = _RANDOM[2'h2][12]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :58:16, :59:22
`endif // RANDOMIZE_REG_INIT
if (reset) // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7
valid = 1'h0; // src/main/scala/xiangshan/frontend/FauFTB.scala:59:22
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_resp_brSlots_0_offset = data_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
assign io_resp_brSlots_0_lower = data_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
assign io_resp_brSlots_0_tarStat = data_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
assign io_resp_brSlots_0_valid = data_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
assign io_resp_tailSlot_offset = data_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
assign io_resp_tailSlot_lower = data_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
assign io_resp_tailSlot_tarStat = data_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
assign io_resp_tailSlot_sharing = data_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
assign io_resp_tailSlot_valid = data_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
assign io_resp_pftAddr = data_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
assign io_resp_carry = data_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
assign io_resp_always_taken_0 = data_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
assign io_resp_always_taken_1 = data_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17
assign io_resp_hit = tag == io_req_tag & valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :58:16, :59:22, :62:{22,37}
assign io_update_hit =
tag == io_update_req_tag & valid | io_write_tag == io_update_req_tag & io_write_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :58:16, :59:22, :64:{26,49,59}, :65:{35,58}
endmodule